US20060035569A1 - Integrated system for processing semiconductor wafers - Google Patents

Integrated system for processing semiconductor wafers Download PDF

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US20060035569A1
US20060035569A1 US11249917 US24991705A US2006035569A1 US 20060035569 A1 US20060035569 A1 US 20060035569A1 US 11249917 US11249917 US 11249917 US 24991705 A US24991705 A US 24991705A US 2006035569 A1 US2006035569 A1 US 2006035569A1
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wafer
chamber
system
process
plurality
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US11249917
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Jalal Ashjaee
Homayoun Talieh
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ASM NuTool Inc
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ASM NuTool Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/6723Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one plating chamber

Abstract

An integrated system for processing a plurality of wafers, having a conductive front surface, is provided. The system includes a plurality of processing subsystems for depositing on or removing metal from the front surfaces of the wafers. Each processing subsystem includes a process chamber and a cleaning chamber. The system also has a wafer handling subsystem for transporting each of the wafers into or out of the appropriate one of the plurality of processing subsystems. The plurality of processing subsystems and wafer handling subsystem form an integrated system.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation application of co-pending U.S. patent application Ser. No. 09/795,687, filed on Feb. 27, 2001, which claims priority to U.S. Provisional Application Nos. 60/259,676, filed Jan. 5, 2001, and 60/261,263, filed on Jan. 16, 2001.
  • BACKGROUND
  • 1. Field of the Invention
  • The present invention generally relates to semiconductor processing technologies and, more particularly, to an integrated semiconductor wafer processing system.
  • 2. Description of the Related Art
  • In the semiconductor industry, various processes can be used to deposit and etch materials on the wafers. Deposition techniques include processes such as electrochemical deposition (ECD) and electrochemical mechanical deposition (ECMD). In both processes, a conductor is deposited on a semiconductor wafer or a work piece by having electrical current carried through an electrolyte that comes into contact with the surface of the wafer (cathode). The ECMD process is able to uniformly fill the holes and trenches on the surface of the wafer with the conductive material while maintaining the planarity of the surface. A more detailed description of the ECMD method and apparatus can be found in U.S. Pat. No. 6,176,992, entitled “Method and Apparatus For Electrochemical Mechanical Deposition,” commonly owned by the assignee of the present invention.
  • If a conventional plating process is performed to deposit the conductive material in a deposition chamber, the work piece may be transferred to another chamber in the cluster tool for polishing mechanically and chemically, e.g., chemical mechanical polishing (CMP). As is known, the material removal can also be carried out using electrochemical etching by making the wafer anodic (positive) with respect to an electrode after completing a ECD or ECMD process.
  • Regardless of which process is used, the work piece is next transferred to a rinsing/cleaning station after the deposition and/or polishing steps. During the rinsing/cleaning step, various residues generated by the deposition and/or polishing processes are rinsed off the wafer with a fluid such as water or the like, and subsequently wafer is dried.
  • Conventionally, processing chambers are designed in multiple processing stations or modules that are arranged in a cluster to form a cluster tool or system. Such cluster tools or systems are often used to process a multiple number of wafers at the same time. Generally, cluster tools are configured with multiple processing stations or modules and are designed for a specific operation. However in such conventional cluster tools, deposition and cleaning processing steps both typically require separate chambers. For this reason, in known cluster tools, for a wafer to be processed and cleaned, it must be moved to another station or system. Thus, such configured systems require picking wafers from a particular processing environment and placing into a cleaning environment. This may not be appropriate because during such transfer of the wafers, contaminants such as particles may attach themselves on the wafers. Additionally, such sequence of unloading, transporting, and reloading of the wafers may be costly and time consuming or require larger footprint.
  • To this end, there is a need for alternative integrated processing systems which reduce manufacturing cost and increase manufacturing efficiency.
  • SUMMARY
  • An integrated system for processing a plurality of wafers, having a conductive front surface, is provided. The system includes a plurality of processing subsystems for depositing on or removing metal from the front surfaces of the wafers. Each processing subsystem includes a process chamber and a cleaning chamber. The system also has a wafer handling subsystem for transporting each of the wafers into or out of the appropriate one of the plurality of processing subsystems. The plurality of processing subsystems and wafer handling subsystem form an integrated system.
  • These and other features, aspects and advantages of the present invention will become better understood with reference to the following drawings, description and claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objectives, features, and advantages of the present invention are further described in the detailed description which follows, with reference to the drawings by way of non-limiting exemplary embodiments of the present invention, wherein like reference numerals represent similar parts of the present invention throughout several views and wherein:
  • FIG. 1 illustrates a first embodiment of the present invention using a plurality of electrochemical deposition process stations;
  • FIG. 2 illustrates a second embodiment of the present invention using a plurality of electrochemical mechanical deposition process stations;
  • FIG. 3 illustrates a third embodiment of the present invention using a plurality of chemical mechanical processing process stations;
  • FIG. 4 illustrates a fourth embodiment of the present invention using a plurality of electrochemical polishing or etching process stations;
  • FIGS. 5 and 6 illustrate fifth and sixth embodiment of the present invention each using at least one plating process station and at least one conductor removal station;
  • FIG. 7 illustrates a seventh embodiment of the present invention using a plurality of different process stations; and
  • FIG. 8 illustrates an eighth embodiment of the present invention using a plurality of different process stations, including an anneal station.
  • DETAILED DESCRIPTION
  • The present invention provides a system for semiconductor device fabrication. The system comprises several process modules to perform process steps such as electrochemical mechanical deposition (ECMD), electrochemical deposition (ECD), chemical mechanical polishing (CMP) and electrochemical polishing (EC-polishing) integrated with other process steps such as cleaning, edge removal and drying. Additionally, an integrated tool of the present invention is designed to utilize these process modules to perform multiple processing steps related to electrochemical deposition, chemical mechanical polishing, and electrochemical polishing.
  • As mentioned above, following the ECD, ECMD, CMP or electrochemical polishing processes, the electrolyte residues need to be rinsed off the wafer, and subsequently wafer needs to be dried. Additionally, after such processes, it may be necessary to remove a portion of the metal that is deposited near the edge of the wafer surface. This process is often referred to as ‘bevel edge clean’ or ‘edge removal’ step. In the present invention, exemplary process chambers, i.e., ECD, ECMD, CMP or electrochemical polishing chambers, and their respective cleaning chambers are stacked vertically. In the prior art, however, the ECD process, electrochemical etching process, CMP process and cleaning process are carried at different chambers located horizontally with respect to each other. The edge removal step may be carried out in the cleaning chamber. In the context of this application, the cleaning chamber is the chamber where cleaning (using a fluid such as water or the like to remove residues therefrom) and drying and possibly edge removal process steps are performed.
  • Reference will now be made to the drawings wherein like numerals refer to like parts throughout. FIG. 1 illustrates an integrated tool 100 or system of the present invention which comprises a processing section 102 and a load/unload section 104 or a cassette section connected to the processing section through a buffer section 106. The processing section may comprise one or more process stations 108A-108D that may be clustered around the processing station 102, as in the manner shown in FIG. 1. In this embodiment, the process stations 108A-108D may preferably be vertically stacked chambers which may have a electrochemical deposition (ECD) chamber and a cleaning chamber (i.e., ECD/cleaning chamber). If so configured, the integrated tool 100 of the present invention is able to process wafers with different diameters. In one example, the process stations 108A and 108B can process 300 mm wafers while the process stations 108C, 108D are processing 200 mm wafers or vice versa. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention. In operation, wafers 110 or work pieces to be plated are delivered to the cassette section 104 in a cassette 112 and then each may be picked up and transferred to the buffer section 106 by a first robot 114. Each wafer 110 can then be transferred to one of the vertical chambers 108A-108D in the processing section 102 by a second robot 116. As mentioned above, the vertical chambers 108A-108D can be either adapted to process 200 or 300 millimeter wafers. After the electrochemical deposition and cleaning processes are complete, the above transport steps are performed in reverse order to remove each of the wafers from the integrated tool 100.
  • FIG. 2 illustrates another embodiment of an integrated tool 200 or system of the present invention which comprises a processing section 202 and a load/unload section 204 or a cassette section connected to the processing section through a buffer section 206. The processing section may comprise one or more process stations 208A-208D which may be clustered around the processing section 202, as in the manner shown in FIG. 2. In this embodiment, the process stations 208A-208D may preferably be vertically stacked chambers which may have a electrochemical mechanical deposition (ECMD) chamber and a cleaning chamber (i.e., ECMD/cleaning chamber), which can perform either plating or removal of a conductive material on a workpiece, as described in U.S. Pat. No. 6,176,992 mentioned above. If so configured, the integrated tool 200 of the present invention is able to process wafers with different diameters. In one example, the process stations 108A and 108B can process 300 mm wafers while the process stations 108C, 108D are processing 200 mm wafers or vice versa. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention.
  • In operation, wafers 210 or work pieces to be plated with a conductive material and/or have a previously deposited conductive material disposed thereon are picked up and delivered to the cassette section 204 in a cassette 212 and then each may be transferred to the buffer section 206 by a first robot 214. Each wafer 210 may then be transferred to one of the vertical chambers 208A-208D, in the processing section 202 by a second robot 216. As mentioned above, the vertical chambers 208A-208D can be either adapted to process 200 or 300 millimeter wafers. After the plating and/or removal and cleaning processes are complete, the above transport steps are performed in reverse order to remove each of the wafers 210 from the integrated tool 200. FIG. 3 illustrates another embodiment of an integrated tool 300 or system of the present invention which comprises a processing section 302 and a load/unload section 304 or a cassette section connected to the processing section through a buffer section 306. The processing section 302 may comprise one or more process stations 308A-308B which may be clustered around the processing section 302, as in the manner shown in FIG. 3. In this embodiment, the process stations 308A, 308D may preferably be vertically stacked chambers which may have a chemical mechanical polishing (CMP) chamber and a cleaning chamber (i.e., CMP/cleaning chamber). If so configured, the integrated tool 300 of the present invention is able to process wafers with different diameters. In one example, the process stations 308A and 308B can process 300 mm wafers while the process stations 308C, 308D are processing 200 mm wafers or vice versa. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention.
  • In operation, wafers 310 or work pieces to be polished are delivered to the cassette section 304 in a cassette 312 and then each may be picked up transferred to the buffer section 306 by a first robot 314. Each wafer 310 may then be picked up and transferred to one of the vertical chambers 308A-308D in the processing section 302 by a second robot 316. As mentioned above, the vertical chambers 308A-308D can be either adapted to process 200 or 300 millimeter wafers. After the chemical mechanical polishing and cleaning processes are complete, the above transport steps are performed in reverse order to remove each of the wafers 310 from the integrated tool 300 FIG. 4 illustrates another embodiment of an integrated tool 400 or system of the present invention which comprises a processing section 402 and a load/unload section 404 or a cassette section connected to the processing section through a buffer section 406. The processing section 402 may comprise one or more process stations 408A-408D which may be clustered around the processing section 402, as in the manner shown in FIG. 4. In this embodiment, the process stations 408A-408D may preferably be vertically stacked chambers which may have an electrochemical polishing or electrochemical etching chamber and a cleaning chamber (i.e., EC-polishing/cleaning chamber). If so configured, the integrated tool 400 of the present invention is able to process wafers with different diameters. In one example, the process stations 408A and 408B can process 300 mm wafers while the process stations 408C, 408D are processing 200 mm wafers or vice versa. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention.
  • In operation, wafers 410 or work pieces to be electrochemically polished are delivered to the cassette section 404 in a cassette 412 and then each may be transferred to the buffer section 406 by a first robot 414. Each wafer 410 may then be picked up and transferred to the vertical chambers 408A-408D in the processing section 402 by a second robot 416. As mentioned above, the vertical chambers 408A-408D can be either adapted to process 200 or 300 millimeter wafers. After the EC polishing and cleaning processes are complete, the above transport steps are performed in reverse order to remove each of the wafers 410 from the integrated tool 400.
  • While it is apparent from the above discussions that an advantage of the present invention is reducing contaminants as well as the time consumed, since the number of operations that can take place within the same vertical chamber therefore do not require the robots to handle the wafers as much, when vertical chambers which have different processing capabilities are made part of the integrated system, even further advantages are obtained in terms of overall throughput and reduced contamination. This is because within each of the different plating and removal chambers that are associated with a single processing section, there is also associated a cleaning chamber. Accordingly, the amount of time that would otherwise be needed to transfer wafers from one processing chamber, to a different cleaning chamber, and then again to a different processing chamber are eliminated, as will become more apparent hereinafter.
  • FIG. 5 illustrates another embodiment of an integrated tool 500 or system of the present invention which comprises a processing section 502 and a load/unload section 504 or a cassette section connected to the processing section through a buffer section 506. The processing section 502 may comprise one or more process stations 508A, 508B and 509A, 509B which may be clustered around the processing section 502, as in the manner shown in FIG. 5. In this embodiment, the process stations 508A, 508B and 509A, 509B may preferably be vertically stacked chambers. The vertically stacked chambers may be arranged as a set of ECD/cleaning chambers 508A, 508B and a set of CMP/cleaning chambers 509A, 509B. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention.
  • In operation, wafers 510 or work pieces to be plated and polished are delivered to the cassette section 504 in a cassette 512 and then each may be transferred to the buffer section 506 by a first robot 514. Each wafer 510 may then be picked up and transferred to one of the vertical chambers 508A, 508B and 509A, 509B by a second robot 516. In one example, the second robot 516 may initially transfers the wafers 510 to ECD/cleaning chamber 508A. Once the plating by deposition and an initial cleaning is over, the second robot 516 picks up the wafers and transfers them to the CMP/cleaning chamber 509A. After the chemical mechanical polishing and cleaning processes performed within the CMP/cleaning chamber 509A are complete, the second robot 516 and then the first robot 514 consecutively handle each wafer 510 to replace the wafer in the cassette 512 of the integrated tool 500. As mentioned above, the vertical chambers 508A, 508B or 509A, 509B can be either adapted to process 200 or 300 millimeter wafers.
  • FIG. 6 illustrates another embodiment of an integrated tool 600 or system of the present invention which comprises a processing section 602 and a load/unload section 604 or a cassette section connected to the processing section through a buffer section 606. The processing section 602 may comprise one or more process stations 608A, 608B and 609A, 609B which may be clustered around the processing section 602, as in the manner shown in FIG. 6. In this embodiment, the process stations 608A, 608B and 609A, 609B may preferably be vertically stacked chambers. The vertically stacked chambers may be arranged as a set of ECD/cleaning chambers 608A, 608B and a set of EC-polishing/cleaning chambers 609A, 609B. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention.
  • In operation, wafers 610 or work pieces to be plated and electrochemically polished and/or etched are delivered to the cassette section 604 in a cassette 612 and then each may be transferred to the buffer section 606 by a first robot 614. Each wafer 610 may then be picked up and transferred to one of the vertical chambers 608A, 608B and 609A, 609B by a second robot 616. In one example, the second robot 616 may initially transfer each of the wafers 610 to ECD/cleaning chamber 608A. Once the plating and subsequent initial cleaning take place within the ECD/cleaning chamber 608A, the second robot 616 picks up each of the wafer 610 and transfers it to the EC-polishing/cleaning chamber 609A. After the EC-polishing and cleaning processes performed within the EC-polishing/cleaning chamber 609A are complete, the second robot 516 and then the first robot 514 consecutively handle each wafer 610 to replace the wafer in the cassette 612 of the integrated tool 600. As mentioned above, the vertical chambers 608A, 608B or 609A, 609B can be either adapted to process 200 or 300 millimeter wafers.
  • FIG. 7 illustrates another embodiment of an integrated tool 700 or system of the present invention which comprises a processing section 702 and a load/unload section 704 or a cassette section connected to the processing section through a buffer section 706. The processing section 702 may comprise a first, second, third and fourth process station 708A, 708B, 708C and 708D which may be clustered around the processing section 702, as in the manner shown in FIG. 7. In this embodiment, the process stations 708A-708D may preferably be vertically stacked chambers. The first station 708A may be comprised of an ECD/cleaning vertical chamber. The second station 708B may be comprised of an ECMD/cleaning vertical chamber. The third station 708C may be comprised of a CMP/cleaning vertical chamber. The fourth chamber 708D may be comprised of an EC-polishing/cleaning vertical chamber. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of this invention.
  • In operation, wafers 710 or work pieces to be plated (with ECD and/or ECMD) and electrochemically polished or CMP polished are delivered to the cassette section 704 in a cassette 712 and then each may be transferred to the buffer section 706 by a first robot 714. Each wafer 710 may then be picked and transferred to one of the vertical chambers 708A-708D by a second robot 716.
  • In one example, the second robot 716 may initially transfer the wafer 710 to ECMD/cleaning chamber 708B. Once the plating and/or electropolishing, and then an initial cleaning is performed within the ECMD/cleaning chamber 708B the second robot 716 picks up the wafer 710 and transfers it to the CMP/cleaning chamber 708C or EC-polishing/cleaning chamber 708D. After either chemical mechanical polishing and cleaning, or EC-polishing and cleaning, performed by CMP/cleaning chamber 708C or EC-polishing/cleaning chamber 708D, respectively, is complete, are complete, the second robot 716 and then the first robot 714 consecutively handle each wafer 710 to replace the wafer in the cassette 712 of the integrated tool 700.
  • In a second example, the second robot 716 may initially transfer the wafer 710 to ECD/cleaning chamber 708A. Once the plating and initial cleaning is performed within the ECD/cleaning chamber 708A, the second robot 716 picks up the wafer 710 and transfers it to the CMP/cleaning chamber 708C or EC-polishing/cleaning chamber 708D. After the chemical mechanical polishing and cleaning or EC polishing and cleaning processes, performed by the CMP/cleaning chamber 708C or EC-polishing/cleaning chamber 708D, respectively are complete, the second robot 716 and then the first robot 714 consecutively handle each wafer 710 to replace the wafer in the cassette 712 the integrated tool 700.
  • As mentioned above, the vertical chambers 708A, 708B or 708C, 708D can be either adapted to process 200 or 300 millimeter wafers. Although the above embodiments exemplified with four process stations, it is understood that the use of more than four, for example six, process chambers is within the scope of this invention.
  • It is also within the scope of the present invention that the above systems may also comprise an annealing chamber to anneal the wafers. When an anneal chamber is included, it is preferable to have the anneal chamber located in proximity to the buffer area, and for the anneal chamber to include both a “hot” section capable of heating the wafer, and a “cool” section capable of cooling the wafer after annealing has been completed. Such an anneal chamber will typically have the ability to operate upon a single wafer at a time, and is well known. Thus, further description is not believed necessary. What is advantageous with respect to the present invention is the manner in which the anneal chamber is integrated with the other processing sections, in order to maximize efficiency and throughput.
  • Depending upon the construction of the system, it may be that only one of both of the robots can be constructed to place wafers into or take wafers out of the anneal chamber. If both robots can perform such operation, as described below, then if there are no further operations after annealing, as will be described hereinafter, the anneal chamber can act as a substitute buffer area.
  • FIG. 8 illustrates an embodiment of an integrated tool 800 or system of the present invention using an anneal chamber as described above which comprises a processing section 802 and a load/unload section 804 or a cassette section connected to the processing section through a buffer section 806. The processing section 802 may comprise a first, second, third, fourth and fifth process station 808A, 808B, 808C, 808D and 808E which may be clustered around the processing section 802, as in the manner shown in FIG. 8. The first station 808A may be comprised of an ECD/cleaning vertical chamber or an ECMD/cleaning vertical chamber (both may also be used in a larger system) capable of operating upon 200 mm wafers. The second station 808B may be comprised of an ECD/cleaning vertical chamber or an ECMD/cleaning vertical chamber (both may also be used in a larger system) capable of operating upon 300 mm wafers. The third station 808C may be comprised of a CMP/cleaning vertical chamber or an EC-polishing/cleaning vertical chamber (both may also be used in a larger system), capable of operating upon 200 mm wafers. The fourth station 808D may be comprised of a CMP/cleaning vertical chamber or an EC-polishing/cleaning vertical chamber (both may also be used in a larger system), capable of operating upon 300 mm wafers. As previously mentioned, one such exemplary vertical chamber design and operation is disclosed in co-pending U.S. application Ser. No. 09/466,014, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of this invention. The fifth chamber 808E may be comprised of an annealing chamber, as described above.
  • In operation, wafers 810 or work pieces to be plated (with ECD and/or ECMD) are delivered to the cassette section 804 in a cassette 812 and then each may be transferred to the buffer section 806 by a first robot 814. Each wafer 810 may then be picked up and transferred to one of the vertical chambers 808A-808E by a second robot 816.
  • In one example, the second robot 816 may initially transfer each wafer 810 to one of the ECMD/cleaning chambers 808A and 808B, depending upon the size of the wafer. Once the plating and/or removal of conductive material from the front surface of the wafer and an initial cleaning is performed within the ECMD/cleaning chamber 808A or 808B, the second robot 816 picks up the wafer 810 and transfers it to the annealing chamber 808E. Once annealed and chilled within the annealing chamber, the wafer 810 can then be picked up by the second robot 816 and transported to one of the CMP/cleaning chambers or EC-polishing/cleaning chambers 808C or 808D, depending upon the size of the wafer. Once conductive material is removed from the front face of the wafer using either the CMP/cleaning chamber or EC-polishing/cleaning chamber from 808C or 808D, and the subsequent cleaning within that same vertical chamber is completed, the second robot 816 and then first robot 814 can cooperate to transfer the wafer back to the cassette section 804. As another example, if after the anneal there is not need for further processing, the wafer can be picked up from the anneal chamber by the first robot 814 and transferred directly back to the cassette section 804.
  • In the various embodiments mentioned above, it has been noted that the present invention is capable of operating upon different sized wafers, which wafers are placed into a cassette section. The size of the wafer in each of the different cassette is known, such as through the use of a software tag that is used by a system controller. Further, the robot arms that lift the wafers are configured so that they can detect the center of each wafer, regardless of size, and properly pick the wafer up.
  • In addition, for each wafer, the system controller is also loaded with the process sequence, or recipe, that is needed for that wafer, with various portions of the process sequence performed by different processing stations. When sending a particular wafer to a particular processing station, that portion of the recipe can be sent in a command by the system controller to a processing station module, and that process can then take place, which then also allows tracking of the wafers that are being routed.
  • While in a production environment it is typical for each wafer to have the same process sequence, and that is contemplated by the present invention as well, in certain research settings, have more control over the processing of each wafer has been found beneficial. Thus, as each wafer is transported to the appropriate processing station, which can include processing stations of the same type which operate upon different sized wafers, the system controller will track the progress of the wafer through the system, so that coordination of the transport of the wafer from processing station to processing station can occur.
  • It should be understood, of course, that the foregoing relates to preferred embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims (20)

  1. 1. An integrated system for processing a plurality of wafers, each wafer including a conductive surface, the system comprising:
    a plurality of process stations, wherein the plurality comprises at least one material deposition chamber and at least one material removal chamber, wherein the at least one material deposition chamber is configured to deposit material onto the conductive surface of the wafer and the at least one material removal chamber is configured to remove material from the conductive surface of the wafer, each of the process stations including a cleaning chamber for removing residues that accumulate on the wafer during prior usage of the process station, wherein the material deposition chambers and the cleaning chambers are vertically stacked and the material removal chambers and cleaning chambers are vertically stacked; and
    a wafer-handling subsystem for transporting the wafer into or out of the plurality of process chambers and into or out of a wafer holding system.
  2. 2. The system of claim 1, wherein the material deposition chamber includes at least one of an electrochemical deposition chamber and an electrochemical mechanical deposition chamber.
  3. 3. The system of claim 1, wherein the material removal chamber includes at least one of an electrochemical polishing chamber and a chemical mechanical polishing chamber.
  4. 4. The system of claim 1, further comprising an anneal chamber.
  5. 5. The system of claim 1, wherein each of the process stations is disposed in a cluster arrangement adjacent the wafer-handling subsystem.
  6. 6. The system of claim 5, wherein the wafer-handling subsystem includes at least one wafer-handling robot.
  7. 7. The system of claim 1, wherein the wafer-handling subsystem includes first and second wafer-handling robots, wherein:
    the first wafer-handling robot is configured to remove each wafer from a cassette and place the wafer in a buffer, and subsequently remove each wafer from the buffer and replace the wafer in the cassette; and
    the second wafer-handling robot is configured to remove each wafer from the buffer and place the wafer in one of the plurality of process stations, and subsequently remove each wafer from the one of the plurality of process stations and replace the wafer in the buffer.
  8. 8. An integrated system for processing a plurality of wafers, wherein each wafer has a conductive front surface, the system comprising:
    a plurality of processing subsystems comprising at least one first processing subsystem and at least one second processing subsystem, wherein:
    the first processing subsystem comprises a first process chamber configured to deposit a conductor on the conductive front surface of each wafer and a first cleaning chamber disposed vertically with respect to the first process chamber, the cleaning chamber configured to remove residues that accumulate on the wafer during prior usage of the first process chamber; and
    the second processing subsystem comprises a second process chamber configured to remove a portion of the conductor on the conductive front surface of each wafer and a second cleaning chamber disposed vertically with respect to the second process chamber configured to remove residues that accumulate on the wafer during prior usage of the second process chamber; and
    a wafer handling subsystem configured to transport the wafer into or out of the plurality of processing subsystems and into or out of a wafer-holding system.
  9. 9. The system of claim 8, wherein the first processing subsystem includes an electrochemical deposition chamber and the second processing subsystem includes a chemical mechanical polishing chamber.
  10. 10. The system of claim 8, wherein the first processing subsystem includes an electrochemical deposition chamber and the second processing subsystem includes an electrochemical polishing chamber.
  11. 11. The system of claim 8, wherein the first processing subsystem includes an electrochemical mechanical deposition chamber and the second processing subsystem includes a chemical mechanical polishing chamber.
  12. 12. The system of claim 8, wherein the first processing subsystem includes an electrochemical mechanical deposition chamber and the second processing subsystem includes an electrochemical polishing chamber.
  13. 13. The system of claim 8, wherein each of the plurality of process subsystems is disposed in a cluster arrangement adjacent the wafer-handling subsystem.
  14. 14. The system according to claim 8, wherein the first cleaning chamber is configured to remove a portion of the conductor deposited near an edge of the wafer.
  15. 15. The system of claim 8, wherein the wafer-handling subsystem only handles wafers that are dry and includes first and second wafer-handling robots, wherein:
    the first wafer-handling robot is configured to remove each wafer from a cassette and place the wafer in a buffer, and subsequently remove each wafer from the buffer and replace the wafer in the cassette; and
    the second wafer-handling robot is configured to remove each wafer from the buffer and place the wafer in one of the plurality of process subsystems, and subsequently remove each wafer from the one of the plurality of process subsystems and replace the wafer in the buffer.
  16. 16. The system of claim 8, further comprising an anneal chamber.
  17. 17. An integrated system for processing a plurality of wafers, each wafer including a conductive surface, the system comprising:
    a plurality of deposition chambers and removal chambers, wherein the deposition chambers are configured to deposit material onto the conductive surface of the wafer and the removal chambers are configured to remove material from the conductive surface of the wafer, each of the deposition and removal chambers including a cleaning chamber for removing residues on the wafer, wherein each cleaning chamber and the corresponding deposition chamber or removal chamber are vertically stacked; and
    a wafer-handling subsystem for transporting the wafer into or out of the plurality of deposition and removal chambers and into or out of a wafer-holding system.
  18. 18. The system of claim 17, wherein each of the deposition chambers includes at least one of an electrochemical deposition chamber and an electrochemical mechanical deposition chamber.
  19. 19. The system of claim 17, wherein each of the removal chambers includes at least one of an electrochemical polishing chamber and a chemical mechanical polishing chamber.
  20. 20. The system of claim 17, further comprising an anneal chamber.
US11249917 2001-01-05 2005-10-11 Integrated system for processing semiconductor wafers Abandoned US20060035569A1 (en)

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US6953392B2 (en) 2005-10-11 grant
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US20020088543A1 (en) 2002-07-11 application
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