US20060035437A1 - Semiconductor device having dual-STI and manufacturing method thereof - Google Patents
Semiconductor device having dual-STI and manufacturing method thereof Download PDFInfo
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- US20060035437A1 US20060035437A1 US11/200,262 US20026205A US2006035437A1 US 20060035437 A1 US20060035437 A1 US 20060035437A1 US 20026205 A US20026205 A US 20026205A US 2006035437 A1 US2006035437 A1 US 2006035437A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000002955 isolation Methods 0.000 claims abstract description 213
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 105
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 105
- 239000010703 silicon Substances 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 55
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 99
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 99
- 230000002093 peripheral effect Effects 0.000 abstract description 90
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 62
- 229920005591 polysilicon Polymers 0.000 description 62
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 18
- 229910021342 tungsten silicide Inorganic materials 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000000034 method Methods 0.000 description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- -1 Phospho Chemical class 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
Definitions
- Dual-STI has normally been formed in the following manner. Initially, a shallow trench portion is formed in the memory cell area and the peripheral circuit area with the conventional method of manufacturing the STI. Thereafter, the memory cell area is covered with a resist. Using the resist and a silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form a deep trench portion within the shallow trench portion in the peripheral circuit area. After the resist is removed, the silicon oxide film is deposited on the entire surface. Extra silicon oxide film is removed by CMP, using the silicon nitride film as a stopper, so as to form Dual-STI having the shallow trench portion and the deep trench portion embedded with the silicon oxide film. After the Dual-STI is formed, the silicon oxide film, polysilicon, and the silicon nitride film formed on the silicon substrate are removed.
- a semiconductor device has a first area and a second area.
- the semiconductor device includes a silicon substrate, and an isolation structure implemented by a silicon insulating film formed on a surface of the silicon substrate.
- a depth of the isolation structure in the first area is smaller than that in the second area, and an isolation height of the isolation structure in the first area is substantially the same as that in the second area.
- FIGS. 2 to 8 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 16 is a cross-sectional view along the line XVI-XVI in FIG. 15 .
- FIG. 21 is a cross-sectional view along the line XXI-XXI in FIG. 15 .
- FIGS. 22 to 28 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the third embodiment of the present invention.
- FIG. 31 is an enlarged cross-sectional view of a state in which a silicide layer is formed in the semiconductor device when a silicon oxide film is not formed on a silicon nitride film.
- the method of manufacturing a semiconductor device having the memory cell area and the peripheral circuit area includes the following steps.
- Silicon oxide film 5 is formed on silicon substrate 1 .
- Trenches 15 a, 15 b are formed in silicon oxide film 5 and silicon substrate 1 in the memory cell area and the peripheral circuit area respectively.
- Resist 20 b is formed in trench 15 a formed in the memory cell area and on silicon oxide film 5 in the memory cell area.
- Silicon substrate 1 is etched, using resist 20 b and silicon oxide film 5 as a mask, so as to form trench 15 c in trench 15 b in the peripheral circuit area.
- Resist 20 b is removed.
- Second silicon oxide film 6 is formed on silicon oxide films 5 a, 5 b so as to bury trenches 15 a, 15 c.
- Silicon oxide films 5 a, 5 b and second silicon oxide film 6 on silicon substrate 1 are removed, so as to form isolation structures 6 a, 6 b in trenches 15 a, 15 c respectively.
- an isolation height h 4 of isolation structure 206 b becomes lower than an isolation height h 3 of isolation structure 206 a. More specifically, when depth d 3 of isolation structure 206 a is set to a value not smaller than 100 nm and less than 200 nm and depth d 4 of isolation structure 206 b is set to 200-400 nm, a difference of approximately 30 to 80 nm is produced between isolation height h 3 of isolation structure 206 a and isolation height h 4 of isolation structure 206 b. Moreover, if a gate oxide film in the peripheral circuit area is newly deposited, the difference is further increased.
- the height of the isolation structure in the present embodiment is preferably set to approximately 0 to 60 nm, and more preferably to approximately 20 to 40 nm.
- the active region at the boundary between the memory cell area and the peripheral circuit area serves as a dummy pattern.
- the dummy pattern is not necessary or can be made smaller, and therefore an element area can further be reduced.
- isolation structures having two types of depths that is, isolation structure 6 a having depth d 1 and isolation structure 6 b having depth d 2 , are formed, however, the present invention is not limited as such.
- isolation structures set to a plurality of depths may be formed.
- isolation structures having three or four types of depths may be formed.
- gate structures 132 , 133 of memory cell transistors are formed.
- floating gate electrodes implemented by a polysilicon film 108 (first conductive film) are formed on silicon substrate 101 , with a silicon oxide film 102 (first gate insulating film) being interposed.
- gate structures 134 , 135 of transistors for the peripheral circuit are formed.
- gate structures 134 , 135 of transistors gate electrodes implemented by polysilicon film 111 and tungsten silicide film 112 are formed on silicon substrate 101 with a silicon oxide film 110 (second gate insulating film) being interposed. Silicon oxide film 113 is formed on tungsten silicide film 112 .
- source/drain regions 116 , 117 of the transistor are formed on the surface of silicon substrate 101 .
- Sacrificial oxide film 102 is formed on a main surface of silicon substrate 101 , for example, using thermal oxidation or the like. Then, impurity ions are implanted into the prescribed area on the surface of silicon substrate 101 through sacrificial oxide film 102 , and heat treatment is performed so as to form P-type well 107 and embedded N-type well 106 . Thereafter, sacrificial oxide film 102 is removed, and the surface of silicon substrate 101 is subjected to oxidation. Then, silicon oxide film 102 is newly formed.
- a photoresist pattern (not shown) is formed on silicon oxide film 113 , and using this photoresist pattern as a mask, silicon oxide film 113 is anisotropically etched, whereby silicon oxide film 113 is patterned. Thereafter, the photoresist pattern is removed. Then, using patterned silicon oxide film 113 as a mask, tungsten silicide film 112 and polysilicon film 111 are anisotropically etched.
- the floating gate electrode implemented by polysilicon film 108 is formed on silicon oxide film 102 in the memory cell area.
- ONO film 109 and polysilicon film 108 implementing the dummy gate structure 131 are formed in the memory cell area around the boundary between the memory cell area and the peripheral circuit area.
- a prescribed ion implantation process is carried out, so as to form low-concentration impurity region 114 a serving as the drain region in an element forming area in the memory cell area.
- photoresist pattern 104 d is removed.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having Dual-STI (Shallow Trench Isolation) and a manufacturing method thereof.
- 2. Description of the Background Art
- In order to achieve smaller size or high speed of a semiconductor element, a distance between isolation structures should be narrowed. As a conventional method of forming an element isolation area, LOCOS (local oxidation of silicon) has commonly been employed, however, LOCOS cannot sufficiently meet such demand for a smaller size. Accordingly, STI has recently been employed instead of LOCOS.
- According to a conventional method of manufacturing an STI, initially, a silicon oxide film, polysilicon, and a silicon nitride film are stacked on a semiconductor substrate such as a silicon substrate. Thereafter, a resist having an opening for an element isolation area is formed by photolithography. Using this resist as a mask, the silicon oxide film, the polysilicon, the silicon nitride film, and the semiconductor substrate are anisotropically etched, so as to form a trench (groove). After the resist is removed, a silicon oxide film is deposited on an entire surface by using, for example, HDP (High density plasma)-CVD (Chemical Vapor Deposition). Extra silicon oxide film is removed by CMP (Chemical Mechanical Polishing) using the silicon nitride film as a stopper, and an STI having a trench embedded with the silicon oxide film is formed.
- In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a withstand voltage in isolation is different between a memory cell area and a peripheral circuit area. Specifically, as an applied voltage is lower in the memory cell area than in the peripheral circuit area, the withstand voltage in isolation required in the STI in the memory cell area is low. Therefore, the depth of the STI in the memory cell area is made smaller than that in the peripheral circuit area, so that an area occupied by the memory cell area is decreased. In this manner, a structure in which a depth of the STI is different between areas is referred to as Dual-STI.
- Conventionally, Dual-STI has normally been formed in the following manner. Initially, a shallow trench portion is formed in the memory cell area and the peripheral circuit area with the conventional method of manufacturing the STI. Thereafter, the memory cell area is covered with a resist. Using the resist and a silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form a deep trench portion within the shallow trench portion in the peripheral circuit area. After the resist is removed, the silicon oxide film is deposited on the entire surface. Extra silicon oxide film is removed by CMP, using the silicon nitride film as a stopper, so as to form Dual-STI having the shallow trench portion and the deep trench portion embedded with the silicon oxide film. After the Dual-STI is formed, the silicon oxide film, polysilicon, and the silicon nitride film formed on the silicon substrate are removed.
- Japanese Patent Laying-Open No. 05-121537 discloses a technique to form a shallow trench portion in a collector isolation area and to form a deep trench portion in an element isolation area. According to Japanese Patent Laying-Open No. 05-121537, a mask pattern having a width in the collector isolation area smaller than that in the element isolation area is formed, and the semiconductor substrate is etched utilizing a characteristic that etching progresses slowly in a narrow portion.
- In addition, Japanese Patent Laying-Open No. 2001-044273 discloses a method of forming an STI using a TEOS (Tetra Ethyl Ortho Silicate) film. According to Japanese Patent Laying-Open No. 2001-044273, a pad oxide film, a silicon nitride film, and a TEOS film are stacked on the silicon substrate. Using a resist formed on the TEOS film as a mask, the pad oxide film, the silicon nitride film, and the TEOS film are etched. After the resist is removed, the silicon substrate is etched using the TEOS film as a mask, so as to form a trench.
- Moreover, in Stephen N. Keeney, “A 130 nm Generation High Density Etox™ Flash Memory Technology,” page 11. [online]; <URL: ftp://download.intel.com/research/silicon/0.13micronflash_pres.pdf>, an example of a flash memory using Dual-STI is shown.
- As described above, according to the conventional method of forming Dual-STI, the memory cell area is covered with the resist. Using the resist and the silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form the deep trench portion in the peripheral circuit area. In forming the deep trench portion, the silicon nitride film formed in the memory cell area is covered with the resist. On the other hand, as the silicon nitride film formed in the peripheral circuit area serves as the mask during etching, it is not covered with the resist. Therefore, a part of the silicon nitride film formed in the peripheral circuit area is anisotropically etched, and a film thickness of the silicon nitride film in the peripheral circuit area becomes smaller than that in the memory cell area.
- When the film thickness of the silicon nitride film in the peripheral circuit area becomes smaller than that in the memory cell area, reliability of a semiconductor device is lowered. Such a disadvantage will be described in the following.
- When the film thickness of the silicon nitride film in the peripheral circuit area is smaller than that in the memory cell area, extra silicon oxide film remains particularly in a stepped portion at a boundary between the memory cell area and the peripheral circuit area in removing extra silicon oxide film on the silicon nitride film by using CMP. Thereafter, in removing the silicon nitride film or the like formed on the silicon substrate, remaining silicon oxide film serves as a mask, and the silicon nitride film or a polysilicon film under the silicon oxide film cannot be removed. Consequently, a defect such as generation of a foreign matter, short-circuiting, or defective shape is caused, resulting in lower reliability of a semiconductor device.
- In addition, as an isolation height of the STI is defined by the silicon nitride film serving as a stopper film at the time of CMP, the isolation height of the STI in the peripheral circuit area becomes lower than that in the memory cell area. If the isolation height of the STI in the peripheral circuit area is lower than that in the memory cell area, films to be etched on the STI stepped portion will have different thicknesses when a conductive film serving as an electrode for forming an element such as a transistor is subsequently formed. Therefore, when this film is patterned, the conductive film may remain at the STI stepped portion or an underlying layer may be removed, which results in lower reliability of a semiconductor device.
- According to the technique disclosed in Japanese Patent Laying-Open No. 05-121537, the depth is uniquely determined based on the width of the trench. Therefore, restriction in terms of layout is imposed on fabrication of the deep trench portion and the shallow trench portion. In addition, as this publication is silent about the isolation height, the problem as described above cannot be solved.
- In addition, the technique disclosed in Japanese Patent Laying-Open No. 2001-044273 is not directed to manufacturing of Dual-STI in which a deep trench portion and a shallow trench portion having depths different from each other are formed. Therefore, this publication cannot solve the problem as described above.
- Moreover, according to the technique disclosed in Stephen N. Keeney, “A 130 nm Generation High Density Etox™ Flash Memory Technology,” page 11. [online]; <URL: ftp://download.intel.com/research/silicon/0.13micronflash_pres.pdf>, the isolation structure height in the deep trench portion is smaller than that in-the shallow trench portion. Therefore, the problem as described above cannot be solved. This publication discloses no means for solving the problem of extra silicon oxide film remaining in the stepped portion at the boundary between the memory cell area and the peripheral circuit area.
- An object of the present invention is to provide a semiconductor device capable of achieving improvement in reliability, as well as a manufacturing method thereof
- A semiconductor device according to the present invention has a first area and a second area. The semiconductor device includes a silicon substrate, and an isolation structure implemented by a silicon insulating film formed on a surface of the silicon substrate. A depth of the isolation structure in the first area is smaller than that in the second area, and an isolation height of the isolation structure in the first area is substantially the same as that in the second area.
- A method of manufacturing a semiconductor device having a first area and a second area according to the present invention includes the steps of: forming a first silicon insulating film over a silicon substrate; forming a first trench in the first silicon insulating film and the silicon substrate in the first and second areas; forming a mask layer in the first trench formed in the first area and on the first silicon insulating film in the first area; etching the silicon substrate using the mask layer and the first silicon insulating film as a mask so as to form a second trench in the first trench in the second area; removing the mask layer; forming a second silicon insulating film on the first silicon nitride film so as to bury the first and second trenches; and removing the first and second silicon insulating films over the silicon substrate so as to form an isolation structure in the first and second trenches.
- The “isolation height of the isolation structure” herein refers to a height of an isolation structure from the surface of the silicon substrate to a highest position of the isolation structure. When a conductive film such as a gate electrode is normally formed on the isolation structure, in many cases, the height of the isolation structure does not decrease at that position in a process in a subsequent step. Meanwhile, the “depth of the isolation structure” refers to a depth of an isolation structure from the surface of the silicon substrate to a deepest position of the isolation structure.
- According to the semiconductor device and the manufacturing method of the present invention, the isolation height of the isolation structure in the first area is substantially the same as that in the second area. Therefore, reliability of the semiconductor device can be improved.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
-
FIG. 1 is a cross-sectional view of a structure of a semiconductor device in a first embodiment of the present invention. - FIGS. 2 to 8 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIGS. 9 to 11 are cross-sectional views sequentially showing the method of manufacturing a semiconductor device when a silicon oxide film is not formed on a silicon nitride film.
-
FIG. 12 is a perspective view of a state in which polysilicon remains at an end portion of an isolation structure in a memory cell area. -
FIG. 13 is a cross-sectional view of a structure of a semiconductor device in a second embodiment of the present invention. -
FIG. 14 is a cross-sectional view showing a step of manufacturing a semiconductor device in the second embodiment of the present invention. -
FIG. 15 is a plan view showing a structure around a boundary between a memory cell area and a peripheral circuit area in a flash memory in a third embodiment of the present invention. -
FIG. 16 is a cross-sectional view along the line XVI-XVI inFIG. 15 . -
FIG. 17 is a cross-sectional view along the line XVII-XVII inFIG. 15 . -
FIG. 18 is a cross-sectional view along the line XVIII-XVIII inFIG. 15 . -
FIG. 19 is a cross-sectional view along the line XIX-XIX inFIG. 15 . -
FIG. 20 is a cross-sectional view along the line XX-XX inFIG. 15 . -
FIG. 21 is a cross-sectional view along the line XXI-XXI inFIG. 15 . - FIGS. 22 to 28 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the third embodiment of the present invention.
-
FIG. 29 is a cross-sectional view of a semiconductor device when a silicon oxide film is not formed on a silicon nitride film. -
FIG. 30 is a perspective view of a semiconductor device when a silicon oxide film is not formed on a silicon nitride film. -
FIG. 31 is an enlarged cross-sectional view of a state in which a silicide layer is formed in the semiconductor device when a silicon oxide film is not formed on a silicon nitride film. -
FIG. 32 is an enlarged cross-sectional view of a state in which a silicide layer is formed in the semiconductor device in the third embodiment of the present invention. - An embodiment of the present invention will be described hereinafter with reference to the drawings.
- As shown in
FIG. 1 , a semiconductor device according to the present embodiment includes a memory cell area serving as a first area and a peripheral circuit area serving as a second area. The semiconductor device according to the present embodiment includes asilicon substrate 1 and a plurality ofisolation structures silicon substrate 1. A plurality ofisolation structures 6 a are formed on the surface ofsilicon substrate 1 in the memory cell area, while a plurality ofisolation structures 6 b are formed on the surface ofsilicon substrate 1 in the peripheral circuit area.Isolation structures isolation structure 6 a is smaller than a depth d2 ofisolation structure 6 b. That is, the semiconductor device according to the present embodiment has a Dual-STI structure. In the semiconductor device according to the present embodiment, an isolation height h1 ofisolation structure 6 a is substantially the same as an isolation height h2 ofisolation structure 6 b. When viewed two-dimensionally, a trench width ofisolation structure 6 a is smaller than that ofisolation structure 6 b. - For example,
gate electrodes 8 fortransistors 9 a to 9 g are formed onsilicon substrate 1, with agate insulating film 7 being interposed. Each oftransistors 9 a to 9 g is electrically isolated from each other by the plurality ofisolation structures transistors 9 a to 9 g are formed on the surface ofsilicon substrate 1 on opposing sides ofgate electrode 8 of eachtransistor 9 a to 9 g, respectively. In this manner, semiconductor elements such astransistors 9 a to 9 g are isolated by each of the plurality ofisolation structures interlayer insulating film 9 is formed to covergate electrode 8. In addition, a boundary between the memory cell area and the peripheral circuit area is present on an active region, which is formed to two-dimensionally surround the memory cell area as a dummy pattern. - A method of manufacturing the semiconductor device according to the present embodiment will now be described with reference to FIGS. 2 to 8.
- Initially, as shown in
FIG. 2 , anunderlying oxide film 2 implemented by the silicon oxide film is formed onsilicon substrate 1 to a thickness of approximately 5 to 30 nm, for example, by thermal oxidation. Then, apolysilicon film 3 is formed onunderlying oxide film 2 to a thickness of approximately 100 to 300 nm, for example, by CVD. In succession, asilicon nitride film 4 is formed onpolysilicon film 3, for example, by CVD. In addition, a silicon oxide film 5 (a first silicon oxide film) composed, for example, of TEOS is formed onsilicon nitride film 4. - Though the present embodiment shows an example in which
polysilicon film 3 is formed, an amorphous silicon film may be formed instead ofpolysilicon film 3, or alternativelypolysilicon film 3 may not be formed. In addition, though the present embodiment shows an example in whichsilicon oxide film 5 is implemented by TEOS, a silicon insulating film other than TEOS may be employed provided that a polished rate of the film in CMP is close to that of an isolation/insulating film such as a silicon oxide film embedding a trench which will be described later. - Thereafter, as shown in
FIG. 3 , a resist 20 a having a prescribed shape is formed onsilicon oxide film 5. Then, using resist 20 a as a mask,silicon oxide film 5,silicon nitride film 4,polysilicon film 3, andunderlying oxide film 2 are anisotropically etched, andsilicon substrate 1 is anisotropically etched to depth d1. Here, depth d1 is set, for example, to approximately 100 to 500 nm. In this manner, a plurality oftrenches silicon substrate 1. A plurality oftrenches 15 a are formed on the surface ofsilicon substrate 1 in the memory cell area, while a plurality oftrenches 15 b are formed on the surface ofsilicon substrate 1 in the peripheral circuit area. In addition,sidewall portions trenches silicon oxide film 5,silicon nitride film 4,polysilicon film 3, andunderlying oxide film 2. Thereafter, resist 20 a is removed. - Thereafter, as shown in
FIG. 4 , a resist 20 b is formed intrench 15 a formed in the memory cell area and onsilicon oxide film 5 in the memory cell area. Using resist 20 b andsilicon oxide film 5 as a mask,silicon substrate 1 is anisotropically etched. Then atrench 15 c having a depth d2 is formed intrench 15 b in the peripheral circuit area. Whensilicon substrate 1 is anisotropically etched, an optimal condition foretching silicon substrate 1 is employed, however,silicon oxide film 5 serving as the mask is etched to some extent. Consequently, a thickness t2 of asilicon oxide film 5 b in the peripheral circuit area becomes smaller than a thickness t1 of asilicon oxide film 5 a in the memory cell area. Thereafter, resist 20 b is removed. - Thereafter, as shown in
FIG. 5 , respective inner walls oftrenches silicon oxide film 6 is formed onsilicon oxide films trenches trenches polysilicon film 3 is oxidized from the side. Therefore, bird's beak of the isolation structure can be extended and isolation structure characteristic can be improved. - Though an example in which second
silicon oxide film 6 resulted from HDP is formed as the isolation/insulating film is shown in the present embodiment, a silicon oxide film obtained by applying NSG (Non-doped Silicate Glass) may be formed instead of the silicon oxide film resulted from HDP. In summary, a silicon oxide film should be formed. - Thereafter, as shown in
FIG. 6 ,silicon oxide film 5 and extra secondsilicon oxide film 6 onsilicon nitride film 4 are removed by CMP. Then,isolation structures trenches isolation structures 6 a are formed in the memory cell area, while a plurality ofisolation structures 6 b are formed in the peripheral circuit area. - Here, the polished speed of
silicon oxide films silicon oxide film 6. Therefore, even if thickness t2 ofsilicon oxide film 5 b is smaller than thickness t1 ofsilicon oxide film 5 a in the memory cell area, the polished speed in the memory cell area is substantially the same as that in the peripheral circuit area. In addition, as the polished speed of the silicon nitride film is approximately 1/300 of the polished speed ofsilicon oxide films silicon oxide film 6,silicon nitride film 4 serves as the etching stopper film in CMP. In this manner,silicon oxide films silicon oxide film 6 onsilicon nitride film 4 can completely be removed. Moreover, the surfaces ofisolation structures silicon nitride film 4 are substantially flush with each other, and flush with the surface ofsilicon nitride film 4. In other words, upper surfaces ofisolation structures silicon nitride film 4. - Thereafter, as shown in
FIG. 7 , respective surfaces ofisolation structures isolation structures isolation structures isolation structure 6 a is substantially the same as isolation height h2 ofisolation structure 6 b after wet-etching. That is, the upper surface ofisolation structure 6 a is flush with the upper surface ofisolation structure 6 b. In succession,silicon nitride film 4,polysilicon film 3, andunderlying oxide film 2 are removed by etching, so as to exposesilicon substrate 1. In this manner, a plurality ofisolation structures silicon substrate 1 are formed. - Thereafter, as shown in
FIG. 8 ,gate insulating film 7 is formed on the surface ofsilicon substrate 1 with thermal oxidation. Thereafter, apolysilicon film 8 is formed, for example, by CVD, so as to covergate insulating film 7 and each of the plurality ofisolation structures isolation structure 6 a is substantially the same as isolation height h2 ofisolation structure 6 b. Therefore, a thickness a1 ofpolysilicon film 8 in the vicinity ofisolation structure 6 a is substantially the same as a thickness b1 ofpolysilicon film 8 in the vicinity ofisolation structure 6 b. - Thereafter, as shown in
FIG. 1 ,polysilicon film 8 is etched to achieve a prescribed pattern, so as to formgate electrode 8 of each oftransistors 9 a to 9 g. As described previously, thickness a1 ofpolysilicon film 8 in the vicinity ofisolation structure 6 a is substantially the same as thickness b1 ofpolysilicon film 8 in the vicinity ofisolation structure 6 b. Therefore, during etching, etching of the silicon substrate as a result of etching throughgate insulating film 7 in the peripheral circuit area is avoided, orpolysilicon film 8 is not left in the memory cell area. Thereafter,interlayer insulating film 9 is formed so as to covergate electrode 8. The semiconductor device according to the present embodiment is completed through the above-described steps. - The semiconductor device according to the present embodiment has the memory cell area and the peripheral circuit area. The semiconductor device includes
silicon substrate 1 andisolation structures silicon oxide film 6 formed on the surface ofsilicon substrate 1. Depth d1 ofisolation structure 6 a in the memory cell area is smaller than depth d2 ofisolation structure 6 b in the peripheral circuit area, and isolation height h1 ofisolation structure 6 a in the memory cell area is substantially the same as isolation height h2 ofisolation structure 6 b in the peripheral circuit area. That is, the upper surface ofisolation structure 6 a is substantially flush with the upper surface ofisolation structure 6 b. - The method of manufacturing a semiconductor device having the memory cell area and the peripheral circuit area according to the present embodiment includes the following steps.
Silicon oxide film 5 is formed onsilicon substrate 1.Trenches silicon oxide film 5 andsilicon substrate 1 in the memory cell area and the peripheral circuit area respectively. Resist 20 b is formed intrench 15 a formed in the memory cell area and onsilicon oxide film 5 in the memory cell area.Silicon substrate 1 is etched, using resist 20 b andsilicon oxide film 5 as a mask, so as to formtrench 15 c intrench 15 b in the peripheral circuit area. Resist 20 b is removed. Secondsilicon oxide film 6 is formed onsilicon oxide films trenches Silicon oxide films silicon oxide film 6 onsilicon substrate 1 are removed, so as to formisolation structures trenches - According to the semiconductor device and the manufacturing method thereof according to the present embodiment, isolation height h1 of
isolation structure 6 a in the memory cell area is substantially the same as isolation height h2 ofisolation structure 6 b in the peripheral circuit area. Specifically, when depth d1 ofisolation structure 6 a is set to a value not smaller than 100 nm and less than 200 nm and depth d2 ofisolation structure 6 b is set to not smaller than 200 nm and not larger than 400 nm, a difference between isolation height h1 ofisolation structure 6 a and isolation height h2 ofisolation structure 6 b can be made to not larger than 20 nm. In addition, if a dummy pattern is used or a two-dimensional layout of the semiconductor device is designed to an appropriate shape, the difference between isolation height h1 ofisolation structure 6 a and isolation height h2 ofisolation structure 6 b can be made to not larger than 5 nm. In this manner, uniform thickness ofpolysilicon film 8 formed onisolation structures polysilicon film 8 can be improved, and consequently, reliability of the semiconductor device can be improved. - According to the method of manufacturing a semiconductor device in the present embodiment, in forming
trench 15 c,silicon oxide film 5 b instead ofsilicon nitride film 4 is used as a mask. As the polished speed ofsilicon oxide films silicon oxide film 6,silicon oxide films silicon oxide film 6 onsilicon nitride film 4 can completely be removed even if a step is produced betweensilicon oxide films silicon nitride film 4 has the uniform thickness, isolation height h1 ofisolation structure 6 a in the memory cell area can substantially be the same as isolation height h2 ofisolation structure 6 b in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. - Here, a problem that arises in a conventional example in which
silicon oxide film 5 is not formed onsilicon nitride film 4 will be described in detail with reference to FIGS. 9 to 11. - As shown in
FIG. 9 , ifsilicon oxide film 5 is not formed,silicon substrate 1 is anisotropically etched using resist 20 b and asilicon nitride film 204 b as a mask. Here,silicon nitride film 204 b in the peripheral circuit area is etched to some extent, and a thickness t4 ofsilicon nitride film 204 b becomes smaller than a thickness t3 of asilicon nitride film 204 a in the memory cell area. That is, a stepped portion is produced at the boundary between the memory cell area and the peripheral circuit area. More specifically, when a depth d3 of anisolation structure 206 a is set to a value not smaller than 100 nm and less than 200 nm and a depth d4 of anisolation structure 206 b is set to 200-400 nm, a difference of approximately 30 to 80 nm is produced between thickness t3 ofsilicon nitride film 204 a and thickness t4 ofsilicon nitride film 204 b. - As shown in
FIG. 10 , if there is a stepped portion at the boundary between the memory cell area and the peripheral circuit area, secondsilicon oxide film 6 present at the stepped portion is not removed by CMP but remains as extra secondsilicon oxide film 206. In addition, the surface ofisolation structure 206 b in the peripheral circuit area becomes lower than the surface ofisolation structure 206 a in the memory cell area. - Referring to
FIG. 11 , if extra secondsilicon oxide film 206 is left at the stepped portion, secondsilicon oxide film 206 serves as a mask. Then, underlyingsilicon nitride film 4,polysilicon film 3 or the like cannot be removed, and they are left as extrasilicon nitride film 204 andpolysilicon film 203. Consequently, a defect such as generation of a foreign matter, short-circuiting, or defective shape is caused, resulting in lower reliability of a semiconductor device. - In addition, if the surface of
isolation structure 206 b is lower than the surface ofisolation structure 206 a, an isolation height h4 ofisolation structure 206 b becomes lower than an isolation height h3 ofisolation structure 206 a. More specifically, when depth d3 ofisolation structure 206 a is set to a value not smaller than 100 nm and less than 200 nm and depth d4 ofisolation structure 206 b is set to 200-400 nm, a difference of approximately 30 to 80 nm is produced between isolation height h3 ofisolation structure 206 a and isolation height h4 ofisolation structure 206 b. Moreover, if a gate oxide film in the peripheral circuit area is newly deposited, the difference is further increased. - When
polysilicon film 8 is formed while isolation height h4 ofisolation structure 206 b is lower than isolation height h3 ofisolation structure 206 a, a thickness b2 ofpolysilicon film 8 in the vicinity ofisolation structure 206 b becomes smaller than a thickness a2 ofpolysilicon film 8 in the vicinity ofisolation structure 206 a. Then,polysilicon film 8 cannot uniformly be etched, in which case, the silicon substrate may be etched as a result of etching throughgate insulating film 7 in the peripheral circuit area, or apolysilicon film 208 may remain at an end portion ofisolation structure 206 a in the memory cell area, as shown inFIG. 12 . Consequently, reliability of a semiconductor device is lowered. If height h3 ofisolation structure 206 a in the memory cell area is set lower in order to avoid such a problem, the surface ofisolation structure 206 b in the peripheral circuit area becomes lower than the substrate surface. As a result, the gate electrode surrounds an end of an active region and a reverse narrow channel effect takes place, which results in lower threshold voltage. This may cause leakage current in a transistor. - According to the method of manufacturing a semiconductor device in the present embodiment, such a problem can be prevented and an isolation structure having an appropriate height can be formed. Therefore, reliability and performance of a semiconductor device can be improved.
- According to the semiconductor device in the present embodiment, when viewed two-dimensionally, a trench width of
isolation structure 6 a in the memory cell area is smaller than that in the peripheral circuit area. Therefore, if the trench width ofisolation structure 6 a in the memory cell area is made smaller in order to reduce the element in size, insufficient burying with the insulating film implementingisolation structure 6 a can be suppressed. - In the method of manufacturing a semiconductor device in the present embodiment,
silicon nitride film 4 is formed onsilicon substrate 1, and thereaftersilicon oxide film 5 is formed. Accordingly, flatsilicon nitride film 4 can serve as the etching stopper whensilicon oxide film 5 is removed. In addition,silicon nitride film 4 can define isolation heights h1, h2 ofisolation structures - The gate insulating films in the memory cell area and in the peripheral circuit area are simultaneously formed in the present embodiment. For example, however, in forming gate insulating films having different film thicknesses in the peripheral circuit area, the gate insulating films are once removed and again deposited. Then, the height of the isolation structure may be slightly lower by a thickness of removed gate insulating film (approximately less than 10-30 nm). In an element area such as a capacitive element where an insulating film formed simultaneously with the gate insulating film of a memory cell is used also in the peripheral circuit area, the height of the isolation structure is substantially the same.
- The height of the isolation structure in the present embodiment is preferably set to approximately 0 to 60 nm, and more preferably to approximately 20 to 40 nm.
- Referring to
FIG. 13 , in the semiconductor device according to the present embodiment, the boundary between the memory cell area and the peripheral circuit area is present on anisolation structure 6 c.Isolation structure 6 c has a portion in the memory cell area having depth d1 and a portion in the peripheral circuit area having depth d2, and there is a step at the boundary between the portion having depth d1 and the portion having depth d2. - Referring to
FIG. 14 , in the present embodiment, in forming resist 20 b, resist 20 b is formed also in a part oftrench 15 b formed at the boundary between the memory cell area and the peripheral circuit area. Using this resist 20 b as a mask, anisotropic etching is performed. Consequently, intrench 15 b formed at the boundary between the memory cell area and the peripheral circuit area, the portion where-resist 20 b is formed maintains depth d1, whiletrench 15 c having depth d2 is formed in the portion where resist 20 b is not formed.Trenches silicon oxide film 6, thereby obtaining the semiconductor device shown inFIG. 13 . - As a semiconductor device other than the above and a manufacturing method thereof are substantially similar to the semiconductor device and the manufacturing method in the first embodiment shown in FIGS. 1 to 8, the same components have the same reference characters allotted, and detailed description thereof will not be repeated.
- In the semiconductor device according to the present embodiment, the boundary between the memory cell area and the peripheral circuit area is present on
isolation structure 6 c. - According to the method of manufacturing the semiconductor device in the present embodiment, when resist 20 b is formed, resist 20 b is formed in a part of
trench 15 b. - According to the semiconductor device and the method of manufacturing the same in the present embodiment, an effect similar to that in the first embodiment can also be obtained. In addition, in the semiconductor device in the first embodiment, the active region at the boundary between the memory cell area and the peripheral circuit area serves as a dummy pattern. In the present embodiment, however, the dummy pattern is not necessary or can be made smaller, and therefore an element area can further be reduced.
- In the first and second embodiments, isolation structures having two types of depths, that is,
isolation structure 6 a having depth d1 andisolation structure 6 b having depth d2, are formed, however, the present invention is not limited as such. Alternatively, isolation structures set to a plurality of depths may be formed. Specifically, isolation structures having three or four types of depths may be formed. - In the present embodiment, an exemplary semiconductor device including a memory cell (flash memory) will be described.
- Initially, a structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. 15 to 21.
- Particularly referring to
FIGS. 16 and 17 , a prescribed P-type well 107 and an embedded N-type well 106 are formed on a surface of asilicon substrate 101. The surface ofsilicon substrate 101 is divided into the memory cell area and the peripheral circuit area by anisolation structure 105. When viewed two-dimensionally, the boundary between the memory cell area and the peripheral circuit area is present withinisolation structure 105. -
Isolation structure 105 has aportion 105 a in the memory cell area having depth d1 and aportion 105 b in the peripheral circuit area having depth d2. There is a step at the boundary betweenportion 105 a having depth d1 andportion 105 b having depth d2. In addition, an isolation height h101 (FIG. 18 ) ofisolation structure 105 a in the memory cell area is substantially the same as an isolation height h102 (FIG. 21 ) of anisolation structure 105 b in the peripheral circuit area. - In an element forming area S1 defined by
isolation structure 105 a in the memory cell area,gate structures gate structures silicon substrate 101, with a silicon oxide film 102 (first gate insulating film) being interposed. - A control gate electrode (upper electrode) implemented by a
polysilicon film 111 and a tungsten silicide film 112 (second conductive film) is formed on the floating gate electrode, with an ONO film 109 (insulating film) being interposed. Asilicon oxide film 113 is formed ontungsten silicide film 112. It is noted thatONO film 109 is a stacked-layer film in which a silicon oxide film is formed on a silicon oxide film with a silicon nitride film being interposed. In addition, on the surface ofsilicon substrate 101, a low-concentration impurity region 114 a and a high-concentration impurity region 114 b serving as a drain region of the memory cell transistor and asource region 115 are formed. - In an element forming area S2 defined by
isolation structure 105 b in the peripheral circuit area,gate structures gate structures polysilicon film 111 andtungsten silicide film 112 are formed onsilicon substrate 101 with a silicon oxide film 110 (second gate insulating film) being interposed.Silicon oxide film 113 is formed ontungsten silicide film 112. In addition, source/drain regions silicon substrate 101. - A dummy gate structure 131 (third gate structure) having a prescribed positional relation with the end portions of
isolation structure 105 is formed onisolation structure 105.Dummy gate structure 131 is formed astride the memory cell area and the peripheral circuit area. Indummy gate structure 131,polysilicon film 108 is formed onsilicon substrate 101 in the memory cell area, andONO film 109 is formed so as to cover an upper portion and a side portion ofpolysilicon film 108. In addition,polysilicon film 111 andtungsten silicide film 112 are formed so as to coverONO film 109.Polysilicon film 111 andtungsten silicide film 112 are formed astride the memory cell area and the peripheral circuit area.Silicon oxide film 113 is formed ontungsten silicide film 112. - A
sidewall oxide film 118 is formed on each side surface ofgate structures gate structures dummy gate structure 131. In addition, aninterlayer insulating film 119 is formed onsilicon substrate 101, so as to covergate structures gate structures dummy gate structure 131. - As shown in
FIG. 17 , ininterlayer insulating film 119, acontact 150 electrically connecting low-concentration impurity region 114 a and high-concentration impurity region 114 b in the memory cell area to an upper interconnection (not shown) and acontact 151 electrically connecting source/drain regions - In the semiconductor device according to the present embodiment, particularly as shown in
FIG. 15 , a trench width W1 ofisolation structure 105 a in the memory cell area is narrower than a trench width W2 ofisolation structure 105 b in the peripheral circuit area. - Particularly as shown in
FIGS. 16 and 17 ,dummy gate structure 131 andisolation structure 105 are formed such that a position of each end portion ofdummy gate structure 131 does not coincide with a position of each end portion ofisolation structure 105. - In addition, a film thickness of
polysilicon film 108 in the memory cell area is substantially the same as that indummy gate structure 131, each film thickness ofpolysilicon film 111 andtungsten silicide film 112 in the memory cell area, the peripheral circuit area anddummy gate structure 131 is substantially the same as that in the peripheral circuit area, and a film thickness ofsilicon oxide film 102 is different from a film thickness ofsilicon oxide film 110. - A method of manufacturing the semiconductor device according to the present embodiment will now be described with reference to FIGS. 22 to 28. FIGS. 22 to 28 are cross-sectional views corresponding to
FIG. 17 . - Initially, as shown in
FIG. 22 , with the method similar to that in the first and second embodiments,isolation structure 105 is formed in a prescribed area on the surface ofsilicon substrate 101. Detailed method of formingisolation structure 105 will not be repeated. -
Sacrificial oxide film 102 is formed on a main surface ofsilicon substrate 101, for example, using thermal oxidation or the like. Then, impurity ions are implanted into the prescribed area on the surface ofsilicon substrate 101 throughsacrificial oxide film 102, and heat treatment is performed so as to form P-type well 107 and embedded N-type well 106. Thereafter,sacrificial oxide film 102 is removed, and the surface ofsilicon substrate 101 is subjected to oxidation. Then,silicon oxide film 102 is newly formed. - Thereafter,
polysilicon film 108 is formed onsilicon oxide film 102, for example, by CVD. Then, afterpolysilicon film 108 is etched away so as to remain on the active region of the memory cell (not shown),polysilicon film 108 is subjected to oxidation to form a silicon oxide film on the surface ofpolysilicon film 108. Then, a silicon oxide film is formed on the silicon oxide film with a silicon nitride film being interposed, thereby formingONO film 109. - Thereafter, as shown in
FIG. 23 , aphotoresist pattern 104 c is formed onONO film 109 in the memory cell area. Then,ONO film 109 andpolysilicon film 108 are anisotropically etched, usingphotoresist pattern 104 c as a mask. In this manner,ONO film 109 andpolysilicon film 108 are formed solely in the memory cell area. In addition, exposedsilicon oxide film 102 is removed. In this manner, the surface ofsilicon substrate 101 is exposed in the peripheral circuit area, andgate insulating film 102 is formed solely in the memory cell area. Thereafter,photoresist pattern 104 c is removed. - Thereafter, as shown in
FIG. 24 , the surface ofsilicon substrate 101 is subjected to oxidation so as to formsilicon oxide film 110 on the surface ofsilicon substrate 101 in the peripheral circuit area. Then,polysilicon film 111 is formed onONO film 109 andsilicon oxide film 110 astride the memory cell area and the peripheral circuit area, for example, by using CVD. Thereafter,tungsten silicide film 112 is formed onpolysilicon film 111, andsilicon oxide film 113 is formed ontungsten silicide film 112. - Thereafter, as shown in
FIG. 25 , a photoresist pattern (not shown) is formed onsilicon oxide film 113, and using this photoresist pattern as a mask,silicon oxide film 113 is anisotropically etched, wherebysilicon oxide film 113 is patterned. Thereafter, the photoresist pattern is removed. Then, using patternedsilicon oxide film 113 as a mask,tungsten silicide film 112 andpolysilicon film 111 are anisotropically etched. - As a result of anisotropic etching, the control gate electrode implemented by
polysilicon film 111 andtungsten silicide film 112 is formed onONO film 109 in the memory cell area. In addition, the gate electrode implemented bypolysilicon film 111 andtungsten silicide film 112 is formed onsilicon oxide film 110 in the peripheral circuit area. Moreover,polysilicon film 111 andtungsten silicide film 112 implementingdummy gate structure 131 are formed on the boundary between the memory cell area and the peripheral circuit area. Thereafter, a prescribed ion implantation process is carried out, so as to form low-concentration N-type source/drain region 116 (seeFIG. 26 ) in the peripheral area. - Thereafter, as shown in
FIG. 26 , aphotoresist pattern 104 d is formed. Usingphotoresist pattern 104 d and patternedsilicon oxide film 113 as a mask,ONO film 109 andpolysilicon film 108 are anisotropically etched. - As a result of anisotropic etching, the floating gate electrode implemented by
polysilicon film 108 is formed onsilicon oxide film 102 in the memory cell area. In addition,ONO film 109 andpolysilicon film 108 implementing thedummy gate structure 131 are formed in the memory cell area around the boundary between the memory cell area and the peripheral circuit area. Thereafter, a prescribed ion implantation process is carried out, so as to form low-concentration impurity region 114 a serving as the drain region in an element forming area in the memory cell area. Thereafter,photoresist pattern 104 d is removed. - Thereafter, as shown in
FIG. 27 , aphotoresist pattern 104 e is formed. Usingphotoresist pattern 104 e as a mask, exposedsilicon substrate 101 is etched. Thereafter, the surface ofsilicon substrate 101 is subjected to a prescribed ion implantation process, so as to formsource region 115 in the memory cell area. Thereafter,photoresist pattern 104 e is removed. - In this manner,
gate structures gate structures dummy gate structure 131 is formed onisolation structure 105, astride the memory cell area and the peripheral circuit area. - Thereafter, as shown in
FIG. 28 , a TEOS film (not shown) is formed so as to cover each ofgate structures gate structures dummy gate structure 131. The TEOS film is subjected to dry etching process, so as to form eachsidewall oxide film 118. Then, aphotoresist pattern 104 f is formed. Usingphotoresist pattern 104 f andsidewall oxide film 118 as a mask, the surface ofsilicon substrate 101 is subjected to a prescribed ion implantation process. In this manner, high-concentration N-type source/drain region 117 is formed in the peripheral circuit area. Thereafter,photoresist pattern 104 f is removed. In addition, usingsidewall oxide film 118 as a mask, the surface ofsilicon substrate 101 is subjected to a prescribed ion implantation process in the memory cell area. Then, high-concentration impurity region 114 b is formed in the memory cell area (FIG. 17 ). - Thereafter, referring to
FIG. 17 ,interlayer insulating film 119 including the TEOS film and a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate glass) film is formed to cover each ofgate structures gate structures dummy gate structure 131. Thereafter, contact 150 connecting low-concentration impurity region 114 a and high-concentration impurity region 114 b in the memory cell area and contact 151 connecting source/drain regions FIG. 17 is thus completed. - According to the semiconductor device and the manufacturing method in the present embodiment, in addition to the effect described in the first and second embodiments, the following effect can be achieved.
- Specifically, as shown in
FIG. 25 ,dummy gate structure 131 is provided on the boundary between the memory cell area and the peripheral circuit area, and a memory cell area side ofdummy gate structure 131 has such a structure thatpolysilicon film 108 implementing the floating gate electrode andpolysilicon film 111 andtungsten silicide film 112 implementing the control gate electrode are stacked.Polysilicon film 111 andtungsten silicide film 112 are formed to cover the end portion ofpolysilicon film 108. - With such a structure, the control gate electrode portion formed to cover the end portion of the floating gate electrode (polysilicon film 108) does not need to be etched. That is, it is not necessary to etch a large thickness portion as shown with a3 in
FIG. 25 . Therefore, whenpolysilicon film 111 andtungsten silicide film 112 serving as the control gate electrode in the memory cell area and the gate electrode in the peripheral circuit area are etched, residue ofpolysilicon film 111 andtungsten silicide film 112 at the end portion of the floating gate electrode can be prevented. - In addition, as shown in
FIG. 26 , when solely the peripheral circuit area is covered withphotoresist pattern 104 d as well, abnormal shape ofsilicon substrate 101 or ofisolation structure 105 due to unnecessary over-etching can be prevented, by arranging the boundary between the memory cell area and the peripheral circuit area ondummy gate structure 131. - Moreover, as the boundary between the shallow trench of
isolation structure 105 a and the deep trench ofisolation structure 105 b may cause a defect such as current leakage due to crystal defect originating from the step on the bottom of the trench, such an area is not suitable for element formation. Accordingly, the boundary between the shallow trench and the deep trench is arranged in a manner superposed ondummy gate structure 131, so that areas not suitable for element formation are superposed. An element can thus be reduced in size. - The boundary between the memory cell area and the peripheral circuit area may be arranged on a dummy active region (an active region where
transistors 9 a to 9 g are not formed inFIG. 1 ) as in the first embodiment. Meanwhile, in the present embodiment, the boundary between the memory cell area and the peripheral circuit area is arranged onisolation structure 105, so that the end portion of the floating gate electrode (polysilicon film 108) is located onisolation structure 105, as shown inFIG. 23 . Then, scrape-out ofsilicon substrate 101 due to over-etching during etching of the floating gate can be prevented. That is, when the boundary is superposed on the dummy active region, the boundary should be arranged distant from the end portion of the floating gate electrode, in order to prevent scrape-out ofsilicon substrate 101. In such a case, an element area is increased. Therefore, in order to reduce the element in size, it is preferable to arrange the boundary on the isolation structure. - Furthermore,
gate structures silicon substrate 101, withgate insulating film 102 being interposed. Therefore, stress of the gate electrode tends to be applied to the memory cell area or the like, and crystal defect is likely in the memory cell area or the like. - In the present embodiment, the end portion of
dummy gate structure 131 on the memory cell area side is located more distant from the boundary (on the element forming area within the memory cell area) than the corresponding end portion ofisolation structure 105 a, and the end portion thereof on the peripheral circuit area side is located closer to the memory cell area side (on isolation structure 105) than the corresponding end portion ofisolation structure 105 a. - In particular, as a result of forming
dummy gate structure 131 in the above-described manner, crystal defect that occurs in a portion ofsilicon substrate 101 located in the vicinity ofisolation structure 105 can significantly be suppressed as compared with the conventional semiconductor device. - In the present embodiment, the end portions of
dummy gate structure 131 are both displaced toward the memory cell side, however, they may be displaced toward the peripheral circuit area side. A similar effect can be obtained, so long as the end portion of the dummy gate structure or the end portion of the element isolation area is displaced toward either side. - In the present embodiment, as the depth of the isolation structure in the memory cell area is made smaller than that in the peripheral circuit area, insufficient burying of the isolation structure is less likely. In addition, as shown in
FIG. 20 , assource region 115 formed by removing the isolation structure can be formed to have a small depth, a problem that desired implantation cannot be achieved due to an influence of shadowing at the time of ion implantation can be avoided, and a resistance ofsource region 115 can be lowered. - Here, as in the first embodiment, a problem that arises in a conventional example in which the silicon oxide film is not formed on the silicon nitride film will be described in detail with reference to FIGS. 29 to 32. It is noted that
FIG. 29 corresponds toFIG. 18 in the present embodiment. - According to the conventional method, there is a great difference in the height of the isolation structure between the memory cell area and the peripheral circuit area. As such, the height of the isolation structure in the peripheral circuit area is set so as not to be lower than the silicon substrate. Then, as shown in
FIGS. 29 and 30 , the height of anisolation structure 305 a in the memory cell area becomes extremely high. If the height ofisolation structure 305 a is extremely high, in formingsidewall oxide film 118, asidewall oxide film 301 is formed also on the side surface ofisolation structure 305 a that protrudes fromsilicon substrate 101. Consequently, a contact area betweencontact 150 andsilicon substrate 101 is made smaller due to presence ofsidewall oxide film 301, and contact resistance betweencontact 150 andsilicon substrate 101 becomes higher. In the semiconductor device according to the present embodiment, as the height of the isolation structure in the memory cell area is substantially the same as that in the peripheral circuit area, such a problem is not caused. Therefore, reliability and performance of a semiconductor device can be improved. - When a high-speed logic circuit or the like is formed in the peripheral circuit area, the substrate surface may be silicided so as to achieve low resistance. In such a case, as shown in
FIG. 31 , usingsidewall oxide film 301 as a mask, high-concentration impurity region 114 b is formed within low-concentration impurity region 114 a, and thereafter, the silicon substrate surface in an area wheresidewall oxide film 301 slightly retreated as a result of a cleaning process or the like is silicided, to form asilicide layer 30. Here, a problem of occurrence of leakage due to contact betweensilicide layer 30 and low-concentration impurity region 114 a is caused. In the present embodiment, however, as shown inFIG. 32 , as the sidewall oxide film is not formed on the side surface ofisolation structure 105, such a problem does not occur in spite of formation ofsilicide layer 30. - Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims (11)
1. A semiconductor device having a first area and a second area, comprising:
a silicon substrate; and
an isolation structure implemented by a silicon insulating film formed on a surface of said silicon substrate; wherein
a depth of said isolation structure in said first area is smaller than a depth of said isolation structure in said second area, and
an isolation height of said isolation structure in said first area is substantially equal to an isolation height of said isolation structure in said second area.
2. The semiconductor device according to claim 1 , wherein
a trench width of said isolation structure in said first area is smaller than a trench width of said isolation structure in said second area.
3. The semiconductor device according to claim 1 , further comprising:
a first gate structure formed in an element area defined by said isolation structure in said first area;
a second gate structure formed in an element area defined by said isolation structure in said second area; and
a third gate structure formed astride said first area and said second area.
4. The semiconductor device according to claim 3 , wherein
said first gate structure includes a first gate insulating film formed over said silicon substrate, a lower electrode formed over said first gate insulating film and including a first conductive film, an insulating film formed over said lower electrode, and an upper electrode formed over said insulating film and including a second conductive film,
said second gate structure includes a second gate insulating film formed over said silicon substrate and a gate electrode formed over said second gate insulating film and including said second conductive film, and
said third gate structure includes said first conductive film and said insulating film formed in said first area and said second conductive film formed astride said first area and said second area so as to cover said first conductive film and said insulating film.
5. The semiconductor device according to claim 4 , wherein
a film thickness of said first gate insulating film is different from a film thickness of said second gate insulating film.
6. The semiconductor device according to claim 1 , wherein
a boundary between said first area and said second area is present in said isolation structure.
7. A method of manufacturing a semiconductor device having a first area and a second area, comprising the steps of:
forming a first silicon insulating film over a silicon substrate;
forming a first trench in said first silicon insulating film and said silicon substrate in said first and said second areas;
forming a mask layer in said first trench formed in said first area and over said first silicon insulating film in said first area;
etching said silicon substrate using said mask layer and said first silicon insulating film as a mask, so as to form a second trench in said first trench in said second area;
removing said mask layer;
forming a second silicon insulating film over said first silicon insulating film so as to bury said first and said second trenches; and
removing said first and said second silicon insulating films over said silicon substrate so as to form an isolation structure in said first and said second trenches.
8. The method of manufacturing a semiconductor device according to claim 7 , further comprising the steps of:
forming a first gate insulating film over said silicon substrate in said first area;
forming a first conductive film over said first gate insulating film;
forming an insulating film over said first conductive film;
forming a second gate insulating film over said silicon substrate in said second area;
forming a second conductive film over said insulating film and said second gate insulating film;
etching said second conductive film to leave at least said second conductive film present at a boundary between said first area and said second area, so as to form an upper electrode on said insulating film in said first area, to form a gate electrode on said second gate insulating film in said second area, and to form said second conductive film implementing a gate structure at the boundary between said first area and said second area; and
etching said insulating film and said first conductive film, so as to form a lower electrode over said first gate insulating film and to form said insulating film and said first conductive film implementing the gate structure in said first area around said boundary.
9. The method of manufacturing a semiconductor device according to claim 7 , wherein
said step of forming a mask layer includes the step of forming said mask layer in a part of said first trench.
10. The method of manufacturing a semiconductor device according to claim 7 , further comprising the step of forming a silicon nitride film over said silicon substrate prior to the step of forming said first silicon insulating film.
11. A semiconductor device having a first area and a second area, comprising:
a silicon substrate;
an isolation structure implemented by a silicon insulating film formed on a surface of said silicon substrate; wherein
a depth of said isolation structure in said first area is smaller than a depth of said isolation structure in said second area, and
a trench width of said isolation structure in said first area is smaller than a trench width of said isolation structure in said second area.
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US12/946,311 US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
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JP2004-235434(P). | 2004-08-12 | ||
JP2004235434 | 2004-08-12 | ||
JP2005214776A JP4947931B2 (en) | 2004-08-12 | 2005-07-25 | Semiconductor device |
JP2005-214776(P). | 2005-07-25 |
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US12/946,311 Expired - Fee Related US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
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US12/946,311 Expired - Fee Related US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
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Also Published As
Publication number | Publication date |
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KR101166268B1 (en) | 2012-07-17 |
JP4947931B2 (en) | 2012-06-06 |
KR20060050398A (en) | 2006-05-19 |
TW200614418A (en) | 2006-05-01 |
US8294236B2 (en) | 2012-10-23 |
US7858490B2 (en) | 2010-12-28 |
JP2006080492A (en) | 2006-03-23 |
US20110057287A1 (en) | 2011-03-10 |
TWI390665B (en) | 2013-03-21 |
US20080213971A1 (en) | 2008-09-04 |
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