US20060026372A1 - Page replacement method using page information - Google Patents

Page replacement method using page information Download PDF

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Publication number
US20060026372A1
US20060026372A1 US11/191,074 US19107405A US2006026372A1 US 20060026372 A1 US20060026372 A1 US 20060026372A1 US 19107405 A US19107405 A US 19107405A US 2006026372 A1 US2006026372 A1 US 2006026372A1
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Prior art keywords
page
pages
list
listed
main memory
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US7366855B2 (en
Inventor
Jin-Kyu Kim
Kwang-yoon Lee
Jin-soo Kim
Sun-Young Park
Chan-ik Park
Jeong-uk Kang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to KR10-2004-0059384 priority Critical
Priority to KR1020040059384A priority patent/KR100577384B1/en
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, JEONG-UK, KIM, JIN-KYU, KIM, JIN-SOO, LEE, KWANG-YOON, PARK, CHAN-IK, PARK, SUN-YOUNG
Publication of US20060026372A1 publication Critical patent/US20060026372A1/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/123Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/202Non-volatile memory
    • G06F2212/2022Flash memory
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/13Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production or to increase battery life

Abstract

A page replacement method is provided. The page replacement method includes (a) establishing a first page list in which a plurality of pages in a main memory are listed in an order that they have been used, (b) establishing a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that they have been used, and (c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims priority from Korean Patent Application No. 10-2004-0059384 filed on Jul. 28, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a page replacement method performed in a system that uses a flash memory as a storage medium, and more particularly, to a page replacement method that can minimize the number of write operations performed on a flash memory and can enhance a memory hit rate.
  • 2. Description of the Related Art
  • FIG. 1 is a schematic block diagram illustrating a conventional system 100 that uses a flash memory 150 as a storage medium.
  • Referring to FIG. 1, the system 100 includes a CPU 110, a main memory 120, and the flash memory 150. An operating system 130 is loaded in a portion of the main memory 120. The storage capacity of the main memory 120 is managed by a memory management module 140 included in the operating system 130. In other words, the memory management module 140 manages used pages and free pages of the main memory 120. Here, a page is a unit in which data is written to a memory at one time.
  • The memory management module 140 allocates a page of the main memory 120 yet to be used for predetermined data stored in the flash memory 150 and reads the predetermined data from the flash memory 150 in order to transfer the predetermined data from the flash memory 150 to the main memory 120.
  • However, if there are no free pages in the main memory 120, one of the pages of the main memory 120 that have already been used is selected, and the predetermined data read from the flash memory 150 is written to the selected page of the main memory 120. An algorithm that reuses used pages of a memory as new pages is called a page replacement algorithm. Meanwhile, if the selected page of the main memory 120 has already been modified, data stored in the selected page of the main memory 120 is written to the flash memory 150, and the new data is extracted from the flash memory 150. This means that write operations are performed on the flash memory 150.
  • However, if the selected page of the main memory 120 has not been modified, the flash memory 150 still has an image of the selected page of the main memory 120. Thus, a write operation does not need to be carried out on the flash memory 150, and the selected page of the main memory 120 is removed. Here, the image of the selected page of the main memory 120 is a relative concept. In a case where data stored in an arbitrary page of the main memory 120 is also stored in the flash memory 150, the flash memory 150 is considered having an image of the arbitrary page of the main memory 120. Likewise, in a case where data stored in an arbitrary page of the flash memory 150 is also stored in the main memory 120, the main memory 120 is considered to have an image of the arbitrary page of the flash memory 150.
  • There are a variety of conventional page replacement algorithms.
  • Examples of the conventional page replacement algorithms include a first in first out (FIFO) algorithm that replaces a page that has been used first, a least recently used (LRU) algorithm that replaces a page that has been least recently used, a least frequently used (LFU) algorithm that replaces a page that has been least frequently used, and a not recently used (NRU) algorithm that replaces a page that has not been used recently.
  • FIG. 2 is a diagram illustrating an LRU algorithm that selects a page of the main memory 120 of FIG. 1 that has not been read or written to recently as a page to be replaced. The LRU algorithm is also applicable to a cache memory.
  • The LRU algorithm is based on the principle of temporal locality, which means that a page that has not been accessed for a long time is not likely to be accessed in the near future.
  • In the LRU algorithm, a list of a plurality of pages of the main memory 120 is managed so that one of the pages of the main memory 120 that has been most recently accessed tops the corresponding page list.
  • Referring to FIG. 2, PAGEa (210) is located at the head of a page list because it has been most recently accessed. When Paged (240) is accessed, it is transferred to the head of the page list so that it is followed by page a (210). A page at the tail of the page list, i.e., Pagee (250), is used as a page to be replaced.
  • FIG. 3 is a diagram illustrating an NRU algorithm.
  • Referring to FIG. 3, the locations of a plurality of pages, i.e., pages a through e (310 through 350), in a page list, are fixed, and each of pages a through e (310 through 350) has page information represented by 2 bits, i.e., a reference bit 360 and a modified bit 370.
  • The reference bit 360 is initially set to a value of ‘0’ and is switched to a value of ‘1’ when a corresponding page is used. The modified bit 370 is initially set to a value of ‘0’ and is switched to a value of ‘1’ when the corresponding page is modified. The reference bit 360 is periodically reset to a value of 0 because the corresponding page becomes less likely to be referenced over time.
  • A pointer 380 points to a page to be replaced. The pointer 380 examines the reference bit 360 and the modified bit 370 of each of pages PAGEa (310), PAGEb (320), PAGEc (330), PAGEd (340), and PAGEe (350) while sequentially moving from PAGEa (310) to PAGEb (320), from PAGEb (320) to PAGEc (330), from PAGEc (330) to PAGEd (340), and from PAGEd (340) to PAGEe (350), and then selects one of PAGEa through PAGEe (310 through 350) as the page to be replaced based on the examination results. When the pointer 380 arrives at the tail of the page list, it moves back to the head of the page list and then performs the above-described operation again.
  • Here, the pointer 380 selects one of pages a through e (310 through 350) as the page to be replaced according to a set of rules. Specifically, the pointer 380 selects a page, if any, whose reference bit 360 and modified bit 370 are all set to a value of ‘0’ as the page to be replaced. If none of the pages in the page list have the reference bit 360 and the modified bit 370 all set to a value of ‘0’, the pointer 380 selects a page, if any, whose reference bit 360 is set to a value of ‘1’ and whose modified bit 370 is set to a value of ‘0’ as the page to be replaced. If none of the pages in the page list have the reference bit 360 set to a value of ‘1’ and has the modified bit 370 set to a value of ‘0’, the pointer 380 selects a page in the page list whose reference bit 360 and modified bit 370 are all set to a value of ‘1’ as the page to be replaced.
  • If one of PAGEa through PAGEe (310 through 350) selected as the page to be replaced has already been modified, a write operation is performed on the flash memory 150. However, a delay time required for performing a write operation on the flash memory 150 is generally greater than a delay time required for performing a read operation on the flash memory 150. Thus, the higher the number of write operations performed on the flash memory 150, the greater the delay time.
  • It is possible to reduce delay time regarding the operation of the flash memory 150 by reducing the number of write operations performed on the flash memory. The LRU algorithm selects a page of the main memory 120 located at the tail of a page list as a page to be replaced regardless of whether the page has been modified. Therefore, when the LRU algorithm is applied to the conventional system 100 of FIG. 1, the performance of the conventional system 100 of FIG. 1 may deteriorate because of frequent write operations performed on the flash memory 150.
  • In addition, the NRU algorithm does not consider memory hit rate regarding non-modified pages of the main memory 120. Here, the memory hit rate indicates the number of times that the CPU 110 shown in FIG. 1 has successfully obtained meaningful data from the main memory 120 by accessing the main memory 120. In other words, pages of the main memory 120 whose reference bits 360 have the same value and whose modified bits 370 have a value of ‘0’ have the same priority level in terms of page replacement regardless of the memory hit rate.
  • Therefore, there is a need for development of a page replacement algorithm that minimizes the number of write operations performed on a flash memory while ensuring a memory hit rate.
  • SUMMARY OF THE INVENTION
  • The present invention provides a page replacement algorithm which can reduce delay time regarding the inputting/outputting of data to/from a flash memory and can enhance memory hit rate by minimizing the number of write operations performed on the flash memory.
  • The above stated object as well as other objects of the present invention will become clear to those skilled in the art upon review of the following description.
  • According to an aspect of the present invention, there is provided a page replacement method including (a) making a first page list in which a plurality of pages in a main memory are listed in an order that they have been used, (b) making a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that they have been used, and (c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.
  • According to another aspect of the present invention, there is provided a page replacement method including (a) making a first page list in which a plurality of pages in a main memory are listed in an order that they have been used, (b) making a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that they have been used, (c) making a third page list in which some of the pages in the main memory whose images are not stored in the storage medium are listed in an order that they have been used, and (d) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list, if the second page list is not empty, and storing data downloaded from the storage medium in the pages included in the third page list in an order opposite to the order that the corresponding pages are listed in the third page list, if the second page list is empty.
  • According to still another aspect of the present invention, there is provided a page replacement method including (a) making a first page list in which a plurality of pages in a main memory are listed in an order that they have been used, (b) making a second page list in which some of the pages in the main memory whose images are not stored in a storage medium are listed in an order that they have been used, and (c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
  • FIG. 1 is a schematic block diagram illustrating a conventional system that uses a flash memory as a storage medium;
  • FIG. 2 is a diagram illustrating a least recently used (LRU) algorithm;
  • FIG. 3 is a diagram illustrating a not recently used (NRU) algorithm;
  • FIG. 4 is a diagram illustrating the structure of a clean first LRU (CFLRU) algorithm according to an exemplary embodiment of the present invention;
  • FIG. 5 is a flowchart illustrating a page replacement method using a CFLRU algorithm according to an exemplary embodiment of the present invention;
  • FIG. 6 is a diagram illustrating a CFLRU-dirty related (CFLRU-D) algorithm according to an exemplary embodiment of the present invention;
  • FIG. 7 is a diagram illustrating page information of a page included in a CFLRU-D list of FIG. 6; and
  • FIG. 8 is a flowchart illustrating a page replacement method using a CFLRU-D list according to an exemplary embodiment of the present invention.
  • DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE PRESENT INVENTION
  • Aspects of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of exemplary embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
  • The present invention is described hereinafter with reference to flowchart illustrations of a page replacement method according to exemplary embodiments of the invention. It will be understood that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks.
  • These computer program instructions may also be stored in a computer usable or computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer usable or computer-readable memory produce an article of manufacture including instruction means that implement the function specified in the flowchart block or blocks.
  • The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.
  • And each block of the flowchart illustrations may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • For a better understanding of the present invention, the terms used in this disclosure will now be described in detail.
  • Clean Page
  • A clean page is a page of a main memory whose image exists in a flash memory and is represented by ‘C’ in the drawings.
  • Dirty Page
  • A dirty page is a page of the main memory whose image does not exist in the flash memory and is represented by ‘D’ in the drawings.
  • Page Cache
  • A page cache is a memory zone managed by a memory management module in an operating system.
  • Clean First Least Recently Used (CFLRU) List
  • A CFLRU list is a clean page list in which a clean page that has been the most recently used is listed first and a clean page that has been least recently used is listed last.
  • CFLRU-Dirty Related (CFLRU-D) List
  • A CFLRU-D list is a dirty page list in which a dirty page that has been the most recently used is listed first and a dirty page that has been least recently used is listed last.
  • For the convenience of explanation, it is assumed that a page replacement method according to an exemplary embodiment of the present invention will now be described with reference to the structure of the conventional system 100 of FIG. 1 and will now be assumed to be performed by the memory management module 140 included in the conventional system 100 of FIG. 1.
  • FIG. 4 is a diagram illustrating a CFLRU algorithm according to an exemplary embodiment of the present invention.
  • Referring to FIGS. 1 and 4, the memory management module 140, which is part of the operating system 130, stores predetermined data in a portion of the main memory 120 and thus enables the predetermined data to be quickly accessed by the operating system 130 or a processor. The portion of the main memory 120 managed by the memory management module 140 is referred to as a page cache 400, as described above. The page cache 400 is comprised of a plurality of pages having the same size.
  • If no free space is left in the page cache 400, the memory management module 140 can make a free space in the page cache 400 by transferring data stored in a portion of the page cache 400 to a slow storage device, such as a disc. For this, a memory replacement algorithm may be used to select one of the pages of the page cache 400 and to store data stored in the selected page to the slow storage device.
  • The CFLRU algorithm suggested in the present embodiment is applicable to a NAND flash memory. In addition, a modified version of a typical LRU algorithm is also applicable to a NAND flash memory.
  • The page cache 400 is comprised of a plurality of pages, i.e., PAGEa (410) through PAGEe (450). Referring to FIG. 4, pages represented by ‘C’ are clean pages, and pages represented by ‘D’ are dirty pages.
  • Pages PAGEa through PAGEe (410 through 450) are managed using an LRU list 460 and a CFLRU list 470. The LRU list 460 lists all of the pages of the page cache 400, i.e., pages PAGEa through PAGEe (410 through 450), and the CFLRU list 470 lists only clean pages of the page cache 400, i.e., pages PAGEa, PAGEb, and PAGEd (410, 420, and 440).
  • A page that has been most recently used is located at the head of the LRU list 460, and a page that has been least recently used is located at the tail of the LRU list 460, as described above, regardless of whether the pages are clean pages or dirty pages. A clean page that has been most recently used is located at the head of the CFLRU list 470, and a clean page that has been least recently used in located at the tail of the CFLRU list 470.
  • If a clean page is selected as a page to be replaced through a memory replacement algorithm, data stored in the clean page does not need to be written to the flash memory 150 because an image of the clean page exists in the flash memory 150. However, if a dirty page is selected as the page to be replaced through the memory replacement algorithm, data stored in the dirty page needs to be written to the flash memory 150 because an image of the dirty page does not exist in the flash memory 150.
  • FIG. 5 is a flowchart illustrating a page replacement method using a CFLRU algorithm according to an exemplary embodiment of the present invention.
  • Referring to FIGS. 1, 4, and 5, in operation S510, the CFLRU list 470 is accessed in order to determine which of the pages of the main memory 120 is to be replaced. The CFLRU list 470 includes only clean pages, i.e., PAGEa (410), PAGEb (420), and PAGEd (440).
  • In operation S530, if the CFLRU list 470 is not empty, a page located at the tail of the CFLRU list 470, i.e., PAGEd (440), is selected as a page to be replaced. In operation S560, data downloaded from the flash memory 150 is stored in PAGEd (440). Since an image of PAGEd (440) is stored in the flash memory 150, data written on PAGEd (440) does not need to be written to the flash memory 150. In operation S570, a pointer pointing to the heads of the LRU list 460 and the CFLRU list 470 points to PAGEd (440) because PAGEd (440) has been most recently used and is a clean page. If the data written on PAGEd (440) is modified afterwards, PAGEd (440) is removed from the CFLRU list 470.
  • If the CFLRU list 470 is empty, it appears that the main memory 120 has no clean pages. Thus, in operation S540, the memory management module 140 accesses the LRU list 460. In operation S550, the memory management module 140 selects a dirty page located at the tail of the LRU list 460, i.e., PAGEe (450). In operation S560, the memory management module 140 stores the data downloaded from the flash memory 150 in PAGEe (450). Since an image of PAGEe (450) is not stored in the flash memory 150, data stored in PAGEe (450) needs to be written to the flash memory 150. In operation S570, the pointer pointing to the heads of the LRU list 460 and the CFLRU list 470 points to PAGEe (450). If the data stored in PAGEe (450) is modified afterwards, PAGEe (450) is removed from the CFLRU list 470.
  • However, if a clean image at the tail of the CFLRU list 470 is indiscriminately selected as a page to be replaced, memory hit rate may considerably decrease. Therefore, in the present invention, it is also considered how much the clean image located at the tail of the CFLRU list 470 is apart from the tail of the LRU list 460. Referring to FIG. 4, four pages, i.e., PAGEe (450), PAGEd (440), PAGEc (430), and PAGEb (420), are within a distance 480, in which case, the distance 480 is 4.
  • Accordingly, in the present embodiment, if there is a clean page within the distance 440, the clean page is selected as a page to be replaced. Otherwise, a dirty page located at the tail of the LRU list 460 is chosen as the page to be replaced.
  • For example, in the present embodiment, page d (440), PAGEb (420), PAGEe (450), and PAGEc (430) may be sequentially chosen as the page to be replaced, and a write operation is not performed on the flash memory 150 for PAGEd and PAGEb (420 and 410). Even though PAGEa (410) is a clean page included in the CFLRU list 470, it is not chosen as the page to be replaced because it is not within the distance 480.
  • In order to determine the distance 480, the number of times NIN that a NAND flash memory, e.g., the flash memory 150, has been read and the number of times NOUT that the flash memory 150 has been written are measured at intervals of a predetermined amount of time (e.g., at intervals of several seconds) or whenever a predetermined condition is met (for example, slightly after each process begins or slightly before each process is complete). Thereafter, a predetermined variable TCFLRU is calculated by substituting the measurement results, i.e., NIN and NOUT, into Equation (1):
    T CLFLRU =N OUT ×T OUT +N IN ×T IN  (1)
    where TOUT is a constant indicating the amount of delay time regarding the reading of data from the flash memory 150, and TIN is a constant indicating the amount of delay time regarding the writing of data from a page cache to the flash memory 150.
  • The distance 480 is initially set to a value of 0 and then increases by ( memory size 1 N )
    (where memory size indicates the number of pages included in the LRU list 460 and N is an arbitrary integer that may be determined in advance or may be dynamically determined later) at intervals of the predetermined amount of time or whenever the predetermined condition is met.
  • If the sum of NOUT and NIN obtained in a current iteration is larger than a threshold value and a value of TCFLRU obtained in the current iteration is larger than a value of TCFLRU obtained in a previous iteration, the distance 480 may increase or decrease by ( memory size 1 N )
    depending on whether it has decreased or increased in the previous iteration.
  • In other words, if the distance 480 has decreased in the previous iteration, it increases by ( memory size 1 N )
    in the current iteration.
  • However, if the distance 480 has increased in the previous iteration, it decreases by ( memory size 1 N )
    in the current iteration.
  • However, if the value of TCFLRU obtained in the current iteration is smaller than the value of TCFLRU obtained in a previous iteration and the distance 480 has increased in the previous iteration, the distance 480 further increases by ( memory size 1 N ) .
  • On the other hand, if the value of TCFLRU obtained in the current iteration is smaller than the value of TCFLRU obtained in a previous iteration and the distance 480 has decreased in the previous iteration, the distance 480 further decreases by ( memory size 1 N ) .
  • For example, if memory size is 30 and N is 6, the distance 480 may increase or decrease by 5.
  • The cycle of measuring NOUT or NIN and the threshold value may be varied based on system load, then those can be set by a system manager.
  • In operation S530, one of the clean pages included in the CFLRU list 470 that has been least recently used may be chosen first as a page to be replaced. However, the present invention is not restricted to it. In other words, a clean page following the clean page that has been least recently used may be chosen first as the page to be replaced. In addition, the pages included in the CFLRU list 470 may be sequentially chosen as the page to be replaced in a random order, rather than in the order from the page at the tail of the CFLRU list 470 to the page at the head of the CFLRU list 470.
  • FIG. 6 is a diagram illustrating a CFLRU-D algorithm according to an exemplary embodiment of the present invention.
  • Referring to FIG. 6, a plurality of pages of a page cache 600 managed by the CFLRU-D algorithm has page information 700 of FIG. 7.
  • Referring to FIGS. 1 and 7, ‘Image on Storage Device’ of the page information 700 specifies whether the flash memory 150 has an image of data stored in a corresponding page of the main memory 120, i.e., whether the corresponding page of the main memory 120 is a clean page or a dirty page.
  • If ‘Image on Storage Device’ is set to ‘C’, the corresponding page of the main memory 120 is a clean page. If ‘Image on Storage Device’ is set to ‘D’, the corresponding page of the main memory 120 is a dirty page.
  • ‘The Number of Memory-outs’ indicates the number of times that the corresponding page of the main memory 120 has been chosen as a page to be replaced through the CFLRU-D algorithm. Specifically, ‘The Number of Memory-outs’ indicates the sum of the number of times that the corresponding page of the main memory 120 has been abandoned as a clean page and the number of times that data stored in the corresponding page of the main memory 120 has been written to the flash memory 150 as a dirty page.
  • ‘The Number of Clean-outs’ indicates the number of times that the corresponding page of the main memory 120, as a clean page, has been abandoned through page replacement.
  • ‘Page Data’ serves as an address or a pointer designating the data stored in the corresponding page of the main memory 120.
  • Referring to FIG. 6, in the CFLRU-D algorithm, the pages of the page cache 600 are managed using a LRU list 640, a CFLRU list 650, and a CFLRU-D list 660. The LRU list 640 and CFLRU list 650 are the same as their respective counterparts of FIG. 4. The CFLRU-D list 660 sequentially lists the pages of the page cache 600 so that a dirty page that has been the most recently used is listed first and a dirty page that has been least recently used is listed last. The CFLRU-D list 660 lists only some of a plurality of dirty pages included in the page cache 600 that satisfy a predetermined condition.
  • Specifically, a dirty page whose ‘The Number of Memory-outs’ is set to M or higher and whose ‘The Number of Clean-outs’ is set to N or higher may be listed in the CFLRU-D list 660. In other words, a page that has been replaced M or more times and has been abandoned as a clean page N or more times may be listed in the CFLRU-D list 660.
  • A distance 670 is the same as the distance 480 of FIG. 4. In the CFLRU-D algorithm, ‘The Number of Memory-outs’ and ‘The Number of Clean-outs’ of each of the pages in the page cache 600 may be set in advance based on an initial system workload or may be dynamically set, like the distance 670, by the memory management module 140.
  • FIG. 8 is a flowchart illustrating a page replacement method using a CFLRU-D list according to an exemplary embodiment of the present invention.
  • Referring to FIGS. 1, 6, and 8, in operation S805, the CFLRU list 650 is accessed in order to select one of a plurality of pages of the main memory 120 as a page to be replaced. The CFLRU list 650 includes three clean pages, i.e., PAGEa (605), PAGEc (615), and PAGEf (630).
  • In operation S815, if the CFLRU list 650 is not empty, PAGEf (630) located at the tail of the CFLRU list 650 is chosen as the page to be replaced. In operation S845, data downloaded from the flash memory 150 is stored in PAGEf (630). Since PAGEf (630) is a clean page whose image is stored in the flash memory 150, data stored in PAGEf (630) does not need to be written to the flash memory 150.
  • In operation S850, a pointer pointing to the heads of the LRU list 640 and the CFLRU list 650 now points to PAGEf (630). In other words, since PAGEf (630) is a page that has been most recently used and the image of PAGEf (630) is stored in the flash memory 150, PAGEf (630) is located both at the head of the LRU list 640 and at the head of the CFLRU list 650. If PAGEf (630) is modified afterwards, it is removed from the CFLRU list 650, in which case, if ‘The Number of Memory-outs’ and ‘The Number of Cleanouts’ in the page information 700 of PAGEf (630) satisfy a predetermined condition, PAGEf (630) may be included in the CFLRU-D list (660) so that it is located at the head of the CFLRU-D list (660).
  • In operation S820, if the CFLRU list 650 is empty, the memory management module 140 accesses the CFLRU-D list 660.
  • In operation S830, if the CFLRU-D list 660 is not empty, one of a plurality of dirty pages included in the CFLRU-D list 660, particularly, a dirty page located at the tail of the CFLRU-D list 660, is chosen as the page to be replaced. In operation S845, the data downloaded from the flash memory 150 is stored in the dirty page chosen in operation S830. Since the flash memory 150 does not have an image of the dirty page chosen in operation S830, data stored in the dirty page chosen in operation S830 needs to be written to the flash memory 150. In operation S850, the pointer pointing to the heads of the LRU list 640 and the CFLRU list 650 now points to the dirty page chosen in operation S830. If the data stored in the dirty page chosen in operation S830 is modified afterwards, the dirty page chosen in operation S830 is removed from the CFLRU list 650, in which case, if ‘The Number of Memory-outs’ and ‘The Number of Clean-outs’ in the page information 700 of the dirty page chosen in operation S830 satisfy the predetermined condition, the dirty page chosen in operation S830 may be included in the CFLRU-D list (660) so that it is located at the head of the CFLRU-D list (660).
  • In operation S835, if the CFLRU list 650 and the CFLRU-D list 660 are empty, the memory management module 140 accesses the LRU list 640. In operation S840, a dirty page located at the tail of the LRU list 640 is chosen as the page to be replaced. In operation S845, the data downloaded from the flash memory 150 is stored in the dirty page chosen in operation S840. Since the flash memory 150 does not have an image of the dirty page chosen in operation S840, data stored in the dirty page chosen in operation S840 needs to be written to the flash memory 150. In operation S850, the pointer pointing to the heads of the LRU list 640 and the CFLRU list 650 now points to the dirty page chosen in operation S840. If the data stored in the dirty page chosen in operation S840 is modified afterwards, the dirty page chosen in operation S840 is removed from the CFLRU list 650, in which case, if ‘The Number of Memory-outs’ and ‘The Number of Clean-outs’ in the page information 700 of the dirty page chosen in operation S840 satisfy the predetermined condition, the dirty page chosen in operation S840 may be included in the CFLRU-D list (660) so that it is located at the head of the CFLRU-D list (660).
  • For example, referring to FIG. 6, PAGEf (630), PAGEc (615), PAGEe (625), PAGEd (620), and PAGEg (635) are sequentially replaced and then transferred to the flash memory 150 through the CFLRU-D algorithm. A write operation is not performed on the flash memory 150 for PAGEf (630) and PAGEc (615). Page PAGEa (605) and PAGEb (610) are not within the distance 670 and thus are not even considered as candidates for the page to be replaced.
  • In operation S830, one of the dirty pages included in the CFLRU-D list 660 that has been least recently used may be chosen first as a page to be replaced. However, the present invention is not restricted to it. In other words, a dirty page following the dirty page that has been least recently used may be chosen first as the page to be replaced. In addition, the dirty pages included in the CFLRU-D list 660 may be sequentially chosen as the page to be replaced in a random order, rather than in the order from the dirty page at the tail of the CFLRU-D list 660 to the dirty page at the head of the CFLRU-D list 660.
  • As described above, the page replacement method according to the present invention can reduce data input or output delay and can enhance a memory hit rate by minimizing the number of write operations performed on a flash memory.
  • In addition, the page replacement method according to an exemplary embodiment of the present invention can reduce the power consumption of a system including a flash memory by reducing the number of read operations or write operations performed on the flash memory.
  • Although the present invention has been described in connection with the exemplary embodiments of the present invention, it will be apparent to those skilled in the art that various modifications and changes may be made thereto without departing from the scope and spirit of the invention. Therefore, it should be understood that the above exemplary embodiments are not limiting, but are illustrative in all aspects.

Claims (22)

1. A page replacement method comprising:
(a) establishing a first page list in which a plurality of pages in a main memory are listed in an order that they have been used;
(b) establishing a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that said some of the pages have been used; and
(c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.
2. The page replacement method of claim 1, wherein the storage medium comprises a flash memory.
3. The page replacement method of claim 1, wherein the first page list sequentially lists the pages in the main memory so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last.
4. The page replacement method of claim 1, wherein the second page list sequentially lists the pages whose images are stored in the storage medium so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last.
5. The page replacement method of claim 1, further comprising (d) listing the pages in which the data downloaded from the storage medium is stored, in the second page list.
6. The page replacement method of claim 1, wherein the pages in which the data downloaded from the storage medium is stored, are within a preset distance from the tail of the second page list.
7. A page replacement method comprising:
(a) establishing a first page list in which a plurality of pages in a main memory are listed in an order that they have been used;
(b) establishing a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that said some of the pages have been used;
(c) establishing a third page list in which some other of the pages in the main memory whose images are not stored in the storage medium are listed in an order that said at least one other of the pages have been used;
(d) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list, if the second page list is not empty, and
(e) storing data downloaded from the storage medium in the pages included in the third page list in an order opposite to the order that the corresponding pages are listed in the third page list, if the second page list is empty.
8. The page replacement method of claim 7, wherein the storage medium comprises a flash memory.
9. The page replacement method of claim 7, wherein the first page list sequentially lists the pages in the main memory so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last.
10. The page replacement method of claim 7, wherein the second page list sequentially lists the pages whose images are stored in the storage medium so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last.
11. The page replacement method of claim 7, wherein the third page list sequentially lists the pages whose images are not stored in the storage medium so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last according to a predetermined condition.
12. The page replacement method of claim 7, further comprising listing the pages having data downloaded from the storage medium stored therein in the second page list.
13. The page replacement method of claim 7, wherein the pages in which the data downloaded from the storage medium is stored are within a preset distance from the tail of the second page list.
14. The page replacement method of claim 7, wherein the third page list lists the pages that are referenced from the main memory, according to the number of times greater than a preset value that the main memory is referenced.
15. The page replacement method of claim 7, wherein when the pages are referenced from the main memory, the third page list lists the pages that are not stored in the storage medium by the number of times greater than a preset value that the main memory is referenced.
16. A page replacement method comprising:
(a) establishing a first page list in which a plurality of pages in a main memory are listed in an order that they have been used;
(b) establishing a second page list in which some of the pages in the main memory whose images are not stored in a storage medium are listed in an order that said some of the pages have been used; and
(c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.
17. The page replacement method of claim 16, wherein the storage medium comprises a flash memory.
18. The page replacement method of claim 16, wherein the first page list sequentially lists the pages in the main memory so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last.
19. The page replacement method of claim 16, wherein the second page list sequentially lists the pages whose images are not stored in the storage medium so that a page that has been the most recently used is listed first and a page that has been least recently used is listed last according to a predetermined condition.
20. The page replacement method of claim 16, wherein the pages in which the data downloaded from the storage medium is stored are within a preset distance from the tail of the second page list.
21. The page replacement method of claim 16, wherein the second page list lists the pages that are referenced from the main memory, according to the number of times greater than a preset value that the main memory is referenced.
22. The page replacement method of claim 16, wherein when the pages are referenced from the main memory, the second page list lists the pages that are not stored in the storage medium according to the number of times greater than a preset value that the main memory is referenced.
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070118695A1 (en) * 2005-11-18 2007-05-24 International Business Machines Corporation Decoupling storage controller cache read replacement from write retirement
US20090063753A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Method for utilizing data access patterns to determine a data migration order
US20090063752A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Utilizing data access patterns to determine a data migration order
US20090064136A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Utilizing system configuration information to determine a data migration order
US20090063749A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Tracking data updates during memory migration
US20090063751A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Method for migrating contents of a memory on a virtual machine
US20090063750A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Migrating contents of a memory on a virtual machine
US20090100244A1 (en) * 2007-10-15 2009-04-16 Li-Pin Chang Adaptive hybrid density memory storage device and control method thereof
US20120084511A1 (en) * 2010-10-04 2012-04-05 International Business Machines Corporation Ineffective prefetch determination and latency optimization
US20120254575A1 (en) * 2011-03-28 2012-10-04 Seung-Woo Ryu Method and portable device for managing memory in a data stream management system
US20130205113A1 (en) * 2012-02-06 2013-08-08 Vmware, Inc. Method of allocating referenced memory pages from a free list
US20160170659A1 (en) * 2014-12-10 2016-06-16 Plexistor Ltd. Method and apparatus for adaptively managing data in a memory based file system
US20160188217A1 (en) * 2014-12-31 2016-06-30 Plexistor Ltd. Method for data placement in a memory based file system
US9478274B1 (en) * 2014-05-28 2016-10-25 Emc Corporation Methods and apparatus for multiple memory maps and multiple page caches in tiered memory
KR20170054268A (en) * 2015-10-29 2017-05-17 에이취지에스티 네덜란드 비.브이. Reducing write-backs to memory by controlling the age of cache lines in lower level cache
US9678670B2 (en) 2014-06-29 2017-06-13 Plexistor Ltd. Method for compute element state replication

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787856B1 (en) * 2006-11-29 2007-12-27 한양대학교 산학협력단 Method for changing page in flash memory storage
JP5083757B2 (en) * 2007-04-19 2012-11-28 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Data caching technology
KR100941382B1 (en) * 2008-07-10 2010-02-10 한양대학교 산학협력단 Apparatus and method for managing page buffer linked with flash memory and apparatus and method for changing page of flash memory
KR101056460B1 (en) * 2009-06-05 2011-08-11 세종대학교산학협력단 How to Replace Cache Controllers and Cache Blocks
CN102156753B (en) * 2011-04-29 2012-11-14 中国人民解放军国防科学技术大学 Data page caching method for file system of solid-state hard disc
US8880806B2 (en) 2012-07-27 2014-11-04 International Business Machines Corporation Randomized page weights for optimizing buffer pool page reuse
KR101481633B1 (en) * 2013-07-03 2015-01-15 아주대학교산학협력단 Buffer Management Apparatus And Method having three states based on Flash Memory
KR101653092B1 (en) 2015-02-06 2016-09-01 한국과학기술원 Bio-inspired Algorithm based P2P Content Caching Method for Wireless Mesh Networks and System thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734861A (en) * 1995-12-12 1998-03-31 International Business Machines Corporation Log-structured disk array with garbage collection regrouping of tracks to preserve seek affinity
US20010001873A1 (en) * 1998-07-31 2001-05-24 Hewlett-Packard Company Method and apparatus for replacing cache lines in a cache memory
US6389513B1 (en) * 1998-05-13 2002-05-14 International Business Machines Corporation Disk block cache management for a distributed shared memory computer system
US20020152361A1 (en) * 2001-02-05 2002-10-17 International Business Machines Corporation Directed least recently used cache replacement method
US6968351B2 (en) * 2000-08-19 2005-11-22 International Business Machines Corporation Free space collection in information storage systems

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3104270B2 (en) 1991-02-12 2000-10-30 富士ゼロックス株式会社 Page replacement control device
JP3437852B2 (en) * 1992-10-07 2003-08-18 富士通株式会社 Data processing apparatus having a paging function
KR100389867B1 (en) * 2001-06-04 2003-07-04 삼성전자주식회사 Flash memory management method
US6678785B2 (en) 2001-09-28 2004-01-13 M-Systems Flash Disk Pioneers Ltd. Flash management system using only sequential write
JP2003131946A (en) 2001-10-19 2003-05-09 Nec Corp Method and device for controlling cache memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734861A (en) * 1995-12-12 1998-03-31 International Business Machines Corporation Log-structured disk array with garbage collection regrouping of tracks to preserve seek affinity
US6389513B1 (en) * 1998-05-13 2002-05-14 International Business Machines Corporation Disk block cache management for a distributed shared memory computer system
US20010001873A1 (en) * 1998-07-31 2001-05-24 Hewlett-Packard Company Method and apparatus for replacing cache lines in a cache memory
US6968351B2 (en) * 2000-08-19 2005-11-22 International Business Machines Corporation Free space collection in information storage systems
US20020152361A1 (en) * 2001-02-05 2002-10-17 International Business Machines Corporation Directed least recently used cache replacement method

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070118695A1 (en) * 2005-11-18 2007-05-24 International Business Machines Corporation Decoupling storage controller cache read replacement from write retirement
US8671256B2 (en) 2007-08-27 2014-03-11 International Business Machines Corporation Migrating contents of a memory on a virtual machine
US20090063752A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Utilizing data access patterns to determine a data migration order
US20090064136A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Utilizing system configuration information to determine a data migration order
US20090063749A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Tracking data updates during memory migration
US20090063751A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Method for migrating contents of a memory on a virtual machine
US20090063750A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Migrating contents of a memory on a virtual machine
US8694990B2 (en) 2007-08-27 2014-04-08 International Business Machines Corporation Utilizing system configuration information to determine a data migration order
US8661211B2 (en) 2007-08-27 2014-02-25 International Business Machines Corporation Method for migrating contents of a memory on a virtual machine
US9274949B2 (en) * 2007-08-27 2016-03-01 International Business Machines Corporation Tracking data updates during memory migration
US20090063753A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Method for utilizing data access patterns to determine a data migration order
US8171207B2 (en) * 2007-10-15 2012-05-01 A-Data Technology Co., Ltd. Adaptive hybrid density memory storage device and control method thereof
KR101521958B1 (en) * 2007-10-15 2015-05-20 에이-데이타 테크놀로지 캄파니 리미티드 Hybrid density Memory storage device
US20090100244A1 (en) * 2007-10-15 2009-04-16 Li-Pin Chang Adaptive hybrid density memory storage device and control method thereof
US20120084511A1 (en) * 2010-10-04 2012-04-05 International Business Machines Corporation Ineffective prefetch determination and latency optimization
US8949579B2 (en) * 2010-10-04 2015-02-03 International Business Machines Corporation Ineffective prefetch determination and latency optimization
US9298644B2 (en) * 2011-03-28 2016-03-29 Samsung Electronics Co., Ltd. Method and portable device for managing memory in a data stream management system using priority information
US20120254575A1 (en) * 2011-03-28 2012-10-04 Seung-Woo Ryu Method and portable device for managing memory in a data stream management system
US20150301931A1 (en) * 2012-02-06 2015-10-22 Vmware, Inc. Method of allocating referenced memory pages from a free list
US20130205113A1 (en) * 2012-02-06 2013-08-08 Vmware, Inc. Method of allocating referenced memory pages from a free list
US9361218B2 (en) * 2012-02-06 2016-06-07 Vmware, Inc. Method of allocating referenced memory pages from a free list
US9092318B2 (en) * 2012-02-06 2015-07-28 Vmware, Inc. Method of allocating referenced memory pages from a free list
US10509731B1 (en) 2014-05-28 2019-12-17 EMC IP Holding Company LLC Methods and apparatus for memory tier page cache coloring hints
US10235291B1 (en) * 2014-05-28 2019-03-19 Emc Corporation Methods and apparatus for multiple memory maps and multiple page caches in tiered memory
US9478274B1 (en) * 2014-05-28 2016-10-25 Emc Corporation Methods and apparatus for multiple memory maps and multiple page caches in tiered memory
US10049046B1 (en) 2014-05-28 2018-08-14 EMC IP Holding Company LLC Methods and apparatus for memory tier page cache with zero file
US9678670B2 (en) 2014-06-29 2017-06-13 Plexistor Ltd. Method for compute element state replication
US10140029B2 (en) * 2014-12-10 2018-11-27 Netapp, Inc. Method and apparatus for adaptively managing data in a memory based file system
US20160170659A1 (en) * 2014-12-10 2016-06-16 Plexistor Ltd. Method and apparatus for adaptively managing data in a memory based file system
US20160188217A1 (en) * 2014-12-31 2016-06-30 Plexistor Ltd. Method for data placement in a memory based file system
US9851919B2 (en) * 2014-12-31 2017-12-26 Netapp, Inc. Method for data placement in a memory based file system
US9952973B2 (en) * 2015-10-29 2018-04-24 Western Digital Technologies, Inc. Reducing write-backs to memory by controlling the age of cache lines in lower level cache
KR101875844B1 (en) * 2015-10-29 2018-08-02 에이취지에스티 네덜란드 비.브이. Reducing write-backs to memory by controlling the age of cache lines in lower level cache
JP2017117437A (en) * 2015-10-29 2017-06-29 エイチジーエスティーネザーランドビーブイ Reducing write-backs to memory by controlling age of cache lines in lower level cache
KR20170054268A (en) * 2015-10-29 2017-05-17 에이취지에스티 네덜란드 비.브이. Reducing write-backs to memory by controlling the age of cache lines in lower level cache

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