US20060013243A1 - Video processor with programmable input/output stages to enhance system design configurability and improve channel routing - Google Patents
Video processor with programmable input/output stages to enhance system design configurability and improve channel routing Download PDFInfo
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- US20060013243A1 US20060013243A1 US11/182,101 US18210105A US2006013243A1 US 20060013243 A1 US20060013243 A1 US 20060013243A1 US 18210105 A US18210105 A US 18210105A US 2006013243 A1 US2006013243 A1 US 2006013243A1
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Definitions
- the present invention relates to integrated circuits (ICs), and more particularly to video processor ICs in which programmable input and output stages are disposed to provide design flexibility and enhance ease of use.
- ICs integrated circuits
- video processor ICs in which programmable input and output stages are disposed to provide design flexibility and enhance ease of use.
- FIG. 1 is a schematic block diagram of an input stage 10 of a video processor (not shown) and coupled to video buses CH 1 [7:0], CH 2 [7:0] and CH 3 [7:0], each of which is an 8-bit bus and thus carries 8 video signal lines.
- Input stage 10 is shown as including, in part, three formatters, namely a 24-bit input formatter 12 , a 16-bit input formatter 14 , and an 8-bit input formatter 16 . As is seen in FIG.
- input formatter 12 is hardwired to video buses CH 1 [7:0], CH 2 [7:0] and CH 3 [7:0]
- input formatter 14 is hardwired to video buses CH 2 [7:0] and CH 3 [7:0]
- input formatter 16 is hardwire to video buses CH 3 [7:0]. Because the input formatters are hardwired to the buses carrying the input signals, there is no flexibility in reallocating the channel sources supplying the input signals to the input formatters.
- FIGS. 2A, 2B , and 2 C are high-level schematic block diagrams of a video processor 50 , as known in the prior art.
- Video processor 50 is shown as including a 24-bit input formatter 52 , a 16-bit input formatter 54 , and an 8-bit input formatter 56 .
- FIG. 2A video processor 50 is shown as receiving data form an 8-bit source 60 . Accordingly, source 60 is connected directly to 8-bit input formatter 56 .
- FIG. 2B video processor 50 is shown as receiving data form a 16-bit source 65 . Accordingly, source 65 is connected directly to 16-bit input formatter 54 .
- FIG. 2C video processor 50 is shown as receiving data from a 24-bit source 70 .
- source 70 is connected directly to 24-bit input formatter 52 . Therefore, as seen from the above Figures, in prior art video processors, depending on the type and the number of bits carried by each source, a direct connection is made between the source and one of the input-formatters disposed in the video processor at any given time. Because the input formatters are hardwired to the source supplying the input signals, there is no flexibility in reallocating the various sources to the input formatters.
- the video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor, such as a video processor used in high definition televisions.
- a video signal processor such as a video processor used in high definition televisions.
- Each bus carries a number of signal lines.
- the input stage includes a multiplexing stage which receives the buses and selectively supplies one or more of the buses for delivery to each of the input formatters disposed in the video signal processor.
- a second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order.
- Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters.
- the reordering of the bus lines makes it easier to, for example, route the bus lines in a printed circuit board (PCB) without cross-over.
- the software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- the video signals generated by one or more output formatters disposed in the output stage of the video signal processor are selectively delivered to the output terminals of the video processor.
- the output stage includes a multiplexing stage which receives the generated signals and selectively supplies one or more of such signals both in the original as well as in a changed order for delivery to the output terminals of the video signal processor.
- a second multiplexing stage also disposed in the output stage receives the original and the reordered bus lines delivered by the first multiplexing stage.
- Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the output terminals of the video signal processor.
- the software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- FIG. 1 is a simplified high-level diagram of an input stage of a video signal processor, as known in the prior art.
- FIGS. 2A, 2B , and 2 C are high-level schematic block diagrams of a video processor connected directly to sources of video data supplying 8-bit, 16-bit and 24-bit signals, as known in the prior art.
- FIGS. 3A, 3B , and 3 C are high-level schematic block diagrams of a video processor, in accordance with one exemplary embodiment of the present invention, connected to receive data from various sources.
- FIG. 4 is a simplified high-level diagram of an input stage of a video signal processor, in accordance with one embodiment of the present invention.
- FIG. 5 is a simplified high-level diagram of an output stage of a video signal processor, in accordance with one embodiment of the present invention.
- the video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor, such as a video processor used in high definition televisions.
- a video signal processor such as a video processor used in high definition televisions.
- Each bus carries a number of signal lines.
- the input stage includes a multiplexing stage which receives the buses and selectively supplies one or more of the buses for delivery to each of the input formatters disposed in the video signal processor.
- a second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order.
- Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters.
- the software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- the video signals generated by one or more output formatters disposed in the output stage of the video signal processor are selectively delivered to the output terminals of the video processor.
- the output stage includes a multiplexing stage which receives the generated signals and selectively supplies one or more of such signals both in the original as well as in a changed order for delivery to the output terminals of the video signal processor.
- a second multiplexing stage also disposed in the output stage receives the original and the reordered bus lines delivered by the first multiplexing stage.
- Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the output terminals of the video signal processor.
- the software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- FIGS. 3A, 3B , and 3 C are high-level schematic block diagrams of a video processor 80 , in accordance with a few exemplary configurations of the present invention.
- Video processor 80 is shown as including, in part, an input stage 85 .
- Input stage 85 includes, a multiplexing stage 88 , a 24-bit input formatter 82 , a 16-bit input formatter 84 , and an 8-bit input formatter 86 .
- video processor 80 is shown as receiving data from three 8-bit sources 90 , 92 , and 94 via multiplexing stage 88 disposed in input stage 85 .
- Multiplexing stage 88 is configured to deliver data from one of the 8-bit sources 90 , 92 , and 94 to 8-bit input formatter 86 .
- FIG. 3B video processor 80 is shown as receiving data from one 16-bit source 90 and one 8-bit source 96 via multiplexing stage 88 disposed in input stage 85 .
- Multiplexing stage 88 is configured to deliver data from the 16-bit source 90 to 16-bit input formatter 84 .
- Multiplexing stage 88 is also configured to deliver data from the 8-bit source 96 to 8-bit input formatter 86 .
- video processor 80 is shown as receiving data from one 24-bit sources 98 via multiplexing stage 88 disposed in input stage 85 .
- Multiplexing stage 88 is configured to deliver data from the 24-bit sources 98 to 24-bit input formatter 82 .
- the input stage of the video processor in accordance with the present invention is configurable, any of the video sources may be selectively routed to any of the input formatters, thereby providing enhanced system design configurability and improved channel source routing in systems and applications, such as PCB layout.
- source 60 is connected directly to 8-bit input formatter 56 .
- video processor 50 is shown as receiving data form a 16-bit source 65 . Accordingly, source 65 is connected directly to 16-bit input formatter 54 .
- video processor 50 is shown as receiving data form a 24-bit source 70 . Accordingly, source 70 is connected directly to 24-bit input formatter 52 . Therefore, as seen from the above Figures, in prior art video processors, depending on the type and the number of bits carried by each source, a direct connection is made between the source and one of the input-formatters disposed in the video processor at any given time. Because the input formatters are hardwired to the source supplying the input signals, there is no flexibility in reallocating the various sources to the input formatters.
- FIG. 4 is a high-level block diagram of an exemplary input stage 200 of a video signal processor (not shown), in accordance with one exemplary embodiment of the present invention.
- Input stage 200 is shown as including first and second multiplexing stages 210 , and 220 . It is understood, however, that more multiplexing stages may be disposed in input stage 200 .
- Input stage 200 is also shown as including a 24-bit formatter 202 , a 16-bit formatter 204 , and an 8-bit formatter 206 . It is understood, however, that more formatters with other bits may be disposed in input stage 200 .
- Each of the formatters 202 , 204 , and 206 is configured to handle data having certain timing and other characteristics.
- the 8-bit formatter 206 is configured to handle higher clock frequency and an encoding scheme with timing synchronization embedded therein.
- Video buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0], each of which is an 8-bit bus, are received by input terminals of the video processor (not shown) in which input stage 200 is disposed.
- Each of multiplexing stages 210 , and 220 includes a multitude of multiplexers.
- multiplexing stage 210 is shown as including multiplexers 210 a , 210 b , 210 c , and 210 d .
- multiplexing stage 220 is shown as including multiplexers 220 a , 220 b , 220 c , and 220 d .
- Video bus VIDI_CH 0 [7:0] is applied to input terminal I 0 of each of multiplexers 210 a , 210 b , 210 c , 210 d ;
- Video bus VIDI_CH 1 [7:0] is applied to input terminal I 1 of each of multiplexers 210 a , 210 b , 210 c , 210 d ;
- video bus VIDI_CH 2 [7:0] is applied to input terminal I 2 of each of multiplexers 210 a , 210 b , 210 c , 210 d .
- Select terminal S 0 and S 1 of multiplexer 210 a respectively receive bits b 0 and b 1 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 a .
- Select terminal S 0 and S 1 of multiplexer 210 b respectively receive bits b 2 and b 3 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 b .
- Select terminal S 0 and S 1 of multiplexer 210 c respectively receive bits b 4 and b 5 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 c .
- Select terminal S 0 and S 1 of multiplexer 210 d respectively receive bits b 6 and b 7 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 d.
- the signals carried by one of the video buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], VIDI_CH 2 [7:0] are supplies by output terminal O 0 , shown as bus B[7:0].
- the other output terminal O 1 supplies signal B[0:7] whose bits are reversed with respect to bus B[7:0].
- the signals carried by one of the video buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] are supplies by output terminal O 0 , shown as bus C[7:0].
- the other output terminal O 1 supplies signal C[0:7] whose bits are reversed with respect to bus C[7:0].
- the signals carried by one of the video buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] are supplies by output terminal O 0 , shown as bus D[7:0].
- the other output terminal O 1 supplies signal D[0:7] whose bits are reversed with respect to bus D[7:0].
- Buses A[0:7] and A[7:0] are respectively received by input terminals I 0 and I 1 of multiplexer 220 a disposed in multiplexing stage 220 .
- Multiplexer 220 b disposed in multiplexing stage 220 is configured to receive buses B[7:0] and B[0:7] at its respective input terminals I 0 , I 1 .
- Multiplexer 220 c disposed in multiplexing stage 220 is configured to receive buses C[7:0] and C[0:7] at its respective input terminals I 0 , I 1 .
- Multiplexer 220 d disposed in multiplexing stage 220 is configured to receive buses D[7:0] and D[0:7] at its respective input terminals I 0 , I 1 .
- the signals carried by one of the buses A[7:0] and A[0:7] is applied to input terminal I 0 of 24-bit input formatter 202 .
- the signals carried by one of the buses B[7:0] and B[0:7] is applied to input terminal I 1 of 24-bit input formatter 202 .
- the signals carried by one of the buses C[7:0] and C[0:7] is applied to input terminal I 2 of 24-bit input formatter 202 .
- Input terminals I 0 , I 1 of input formatter 202 are respectively coupled to input terminals I 0 , I 1 of input formatter 204 .
- the signals carried by one of the buses D[7:0] and D[0:7] is supplied to input terminal I of multiplexer 206 .
- any one of the buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] may be delivered to any one of the input terminals I 0 , I 1 , and I 2 of input formatter 202 , in response to the signals applied to the select terminals of the multiplexers disposed in multiplexing stages 210 , and 220 .
- the 8-bits of bus VIDI_CH 0 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 0 of input formatter 202 ; the 8 bits of bus VIDI_CH 2 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 1 of input formatter 202 , and the 8-bits of bus VIDI_CH 1 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 2 of input formatter 202 .
- the 8-bits of bus VIDI_CH 2 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 0 of input formatter 202 ; the 8 bits of bus VIDI_CH 0 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 1 of input formatter 202 , and the 8-bits of bus VIDI_CH 1 [7:0], either in their original form or in a reverse order, may be delivered to input terminal I 0 of input formatter 202 .
- any of the buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] may be received by input terminal I of input formatter 206 .
- each of the buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] may be generated by a different source of video signal.
- the 8 bits of bus VIDI_CH 0 [7:0] may be supplied by a television
- the 8 bits of bus VIDI_CH 1 [7:0] may be supplied by a personal computer
- the 8 bits of bus VIDI_CH 2 [7:0] may be supplied by a high definition video source.
- buses VIDI_CH 0 [7:0], VIDI_CH 1 [7:0], and VIDI_CH 2 [7:0] may carry the red, green and blue components associated with the same video signal. Therefore, signal AA[7:0], supplied by multiplexer 220 a , may be the Y or the green component of a video source, signal BB[7:0], supplied by multiplexer 220 b , may be the U or the blue component of a video source, and signal CC[7:0], supplied by multiplexer 220 c may be the V or the red component of a video source.
- the 16-bit input formatter 204 is adapted to receive the Y component on one of its input terminals (e.g., I 0 ) and the UV component on the other one of its input terminals (e.g., I 1 ). If time multiplexed YUV 4:2:2 components, such as ITU656, are used, 8-bit input formatter 206 is typically adapted to receive the video data on its input terminals.
- FIG. 5 is a high-level block diagram of an exemplary output stage 300 of a video signal processor, in accordance with one embodiment of the present invention.
- Output stage 300 is shown as including first and second multiplexing stages 310 , and 320 . It is understood, however, that more multiplexing stages may be disposed in output stage 300 .
- Output stage 300 is configured to receive buses Y/G[7:0], U/B[7:0] V/R[7:0] and supply signals on output buses VIDO_CH 0 [7:0], VIDO_CH 1 [7:0], and VIDO_CH 2 [7:0], as example of 8-bit bus structure in one instance
- Each of multiplexing stages 310 , and 320 includes a multitude of multiplexers.
- multiplexing stage 310 is shown as including multiplexers 310 a , 310 b , and 310 c .
- multiplexing stage 320 is shown as including multiplexers 320 a , 320 b , and 320 c .
- Video bus Y/G[7:0] is applied to input terminal I 0 of each of multiplexers 310 a , 310 b , and 310 c ;
- Video bus U/B[7:0] is applied to input terminal I 1 of each of multiplexers 310 a , 310 b , and 310 c ;
- video bus V/R[7:0] is applied to input terminal I 2 of each of multiplexers 310 a , 310 b , and 310 c.
- Select terminal S 0 and S 1 of multiplexer 310 a respectively receive bits d 0 and d 1 of a software controlled register configured to select from among one of the input signals applied to multiplexer 310 a .
- Select terminal S 0 and S 1 of multiplexer 310 b respectively receive bits d 2 and d 3 of a software controlled register configured to select from among one of the input signals applied to multiplexer 310 b .
- Select terminal S 0 and S 1 of multiplexer 310 c respectively receive bits d 4 and d 5 of a software controlled register configured to select from among one of the input signals applied to multiplexer 310 c.
- the signals carried by one of the buses Y/G[7:0], U/B[7:0], V/R[7:0] are supplied as output signals O[7:0] by output terminal O 0 of multiplexer 310 a .
- the other output terminal O 1 of multiplexer 310 a supplies signal O[0:7] whose bits are reversed with respect to bus O[7:0].
- Buses O[7:0] and 0 [0:7] are respectively received by input terminals I 0 and I 1 of multiplexer 320 a disposed in multiplexing stage 320 .
- Multiplexer 320 b disposed in multiplexing stage 320 is configured to receive buses P[7:0] and P[0:7] at its respective input terminals I 0 , I 1 .
- Multiplexer 230 c disposed in multiplexing stage 230 is configured to receive buses Q[7:0] and Q[0:7] at its respective input terminals I 0 , I 1 .
- the signals carried by one of the input terminals of multiplexer 320 a is supplied as output signal VIDO_CH 0 [7:0] via output terminal O multiplexer 320 a .
- the signals carried by one of the input terminals of multiplexer 320 b is supplied as output signal VIDO_CH 1 [7:0] via output terminal O multiplexer 320 b .
- any one of the buses Y/G[7:0], U/B[7:0], V/R[7:0] may be delivered to the output terminal of any one of the multiplexers 320 a , 320 b , and 320 c .
- the 8-bits of bus Y/G[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of multiplexer 320 a ; the 8 bits of bus U/B[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of input formatter 320 b , and the 8-bits of bus V/R[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of multiplexer 320 c .
- the 8-bits of bus U/B[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of multiplexer 320 a ; the 8 bits of bus V/R[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of input formatter 320 b , and the 8-bits of bus Y/G[7:0], either in their original form or in a reverse order, may be delivered to output terminal O of multiplexer 320 c.
- bus Y/G[7:0] may carry either the Y or the green component of a video source
- bus U/B[7:0] may carry either the U or the blue component of a video source
- bus V/R[7:0] may carry either V or the red component of a video source.
- the above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible.
- the invention is not limited by the number of multiplexing stages disposed in either the input or output stages of the video processor.
- the invention is not limited by the number of bus lines or the number of signals lines disposed in each bus line.
- the invention is not limited by the number of channel supplying video signal to the video processor.
- the invention is not limited by the number of input formatters disposed in the video processor.
- the invention is not limited by the type of integrated circuit in which the present disclosure may be disposed.
- the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure.
- Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Abstract
The video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor. The input stage includes a multiplexing stage which receives the buses and selectively supplies one ore more of the buses for delivery to each of the input formatters disposed in the video signal processor. A second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
Description
- The present application claims benefit under 35 USC 119(e) of U.S. provisional Application No. 60/588,647, filed Jul. 16, 2004, entitled “System And Method For Use In Video Processing Including A Programmable Input Device, A Pixel Clock Generator, And A Dual Scaler Architecture,” the contents of which is incorporated herein by reference in its entirety.
- NOT APPLICABLE
- NOT APPLICABLE
- The present invention relates to integrated circuits (ICs), and more particularly to video processor ICs in which programmable input and output stages are disposed to provide design flexibility and enhance ease of use.
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FIG. 1 is a schematic block diagram of aninput stage 10 of a video processor (not shown) and coupled to video buses CH1[7:0], CH2[7:0] and CH3[7:0], each of which is an 8-bit bus and thus carries 8 video signal lines.Input stage 10 is shown as including, in part, three formatters, namely a 24-bit input formatter 12, a 16-bit input formatter 14, and an 8-bit input formatter 16. As is seen inFIG. 1 ,input formatter 12 is hardwired to video buses CH1[7:0], CH2[7:0] and CH3[7:0], input formatter 14 is hardwired to video buses CH2[7:0] and CH3[7:0], andinput formatter 16 is hardwire to video buses CH3[7:0]. Because the input formatters are hardwired to the buses carrying the input signals, there is no flexibility in reallocating the channel sources supplying the input signals to the input formatters. -
FIGS. 2A, 2B , and 2C are high-level schematic block diagrams of avideo processor 50, as known in the prior art.Video processor 50 is shown as including a 24-bit input formatter 52, a 16-bit input formatter 54, and an 8-bit input formatter 56. InFIG. 2A ,video processor 50 is shown as receiving data form an 8-bit source 60. Accordingly,source 60 is connected directly to 8-bit input formatter 56. InFIG. 2B ,video processor 50 is shown as receiving data form a 16-bit source 65. Accordingly,source 65 is connected directly to 16-bit input formatter 54. InFIG. 2C ,video processor 50 is shown as receiving data from a 24-bit source 70. Accordingly,source 70 is connected directly to 24-bit input formatter 52. Therefore, as seen from the above Figures, in prior art video processors, depending on the type and the number of bits carried by each source, a direct connection is made between the source and one of the input-formatters disposed in the video processor at any given time. Because the input formatters are hardwired to the source supplying the input signals, there is no flexibility in reallocating the various sources to the input formatters. - In accordance with one embodiment of the present invention, the video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor, such as a video processor used in high definition televisions. Each bus carries a number of signal lines. The input stage includes a multiplexing stage which receives the buses and selectively supplies one or more of the buses for delivery to each of the input formatters disposed in the video signal processor. A second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters. The reordering of the bus lines makes it easier to, for example, route the bus lines in a printed circuit board (PCB) without cross-over. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- In some embodiments, the video signals generated by one or more output formatters disposed in the output stage of the video signal processor are selectively delivered to the output terminals of the video processor. The output stage includes a multiplexing stage which receives the generated signals and selectively supplies one or more of such signals both in the original as well as in a changed order for delivery to the output terminals of the video signal processor. A second multiplexing stage also disposed in the output stage receives the original and the reordered bus lines delivered by the first multiplexing stage. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the output terminals of the video signal processor. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
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FIG. 1 is a simplified high-level diagram of an input stage of a video signal processor, as known in the prior art. -
FIGS. 2A, 2B , and 2C are high-level schematic block diagrams of a video processor connected directly to sources of video data supplying 8-bit, 16-bit and 24-bit signals, as known in the prior art. -
FIGS. 3A, 3B , and 3C are high-level schematic block diagrams of a video processor, in accordance with one exemplary embodiment of the present invention, connected to receive data from various sources. -
FIG. 4 is a simplified high-level diagram of an input stage of a video signal processor, in accordance with one embodiment of the present invention. -
FIG. 5 is a simplified high-level diagram of an output stage of a video signal processor, in accordance with one embodiment of the present invention. - In accordance with one embodiment of the present invention, the video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor, such as a video processor used in high definition televisions. Each bus carries a number of signal lines. The input stage includes a multiplexing stage which receives the buses and selectively supplies one or more of the buses for delivery to each of the input formatters disposed in the video signal processor. A second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
- In some embodiments, the video signals generated by one or more output formatters disposed in the output stage of the video signal processor are selectively delivered to the output terminals of the video processor. The output stage includes a multiplexing stage which receives the generated signals and selectively supplies one or more of such signals both in the original as well as in a changed order for delivery to the output terminals of the video signal processor. A second multiplexing stage also disposed in the output stage receives the original and the reordered bus lines delivered by the first multiplexing stage. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the output terminals of the video signal processor. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.
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FIGS. 3A, 3B , and 3C are high-level schematic block diagrams of avideo processor 80, in accordance with a few exemplary configurations of the present invention.Video processor 80 is shown as including, in part, aninput stage 85.Input stage 85, in part, includes, amultiplexing stage 88, a 24-bit input formatter 82, a 16-bit input formatter 84, and an 8-bit input formatter 86. - In
FIG. 3A ,video processor 80 is shown as receiving data from three 8-bit sources multiplexing stage 88 disposed ininput stage 85. Multiplexingstage 88 is configured to deliver data from one of the 8-bit sources bit input formatter 86. InFIG. 3B ,video processor 80 is shown as receiving data from one 16-bit source 90 and one 8-bit source 96 via multiplexingstage 88 disposed ininput stage 85. Multiplexingstage 88 is configured to deliver data from the 16-bit source 90 to 16-bit input formatter 84. Multiplexingstage 88 is also configured to deliver data from the 8-bit source 96 to 8-bit input formatter 86. InFIG. 3C ,video processor 80 is shown as receiving data from one 24-bit sources 98 via multiplexingstage 88 disposed ininput stage 85. Multiplexingstage 88 is configured to deliver data from the 24-bit sources 98 to 24-bit input formatter 82. As is seen from the above exemplary configurations, at any given time more than two sources may supply video data tovideo processor 80. Furthermore, because the input stage of the video processor, in accordance with the present invention is configurable, any of the video sources may be selectively routed to any of the input formatters, thereby providing enhanced system design configurability and improved channel source routing in systems and applications, such as PCB layout. - Referring to
FIG. 2A , accordingly,source 60 is connected directly to 8-bit input formatter 56. InFIG. 2B ,video processor 50 is shown as receiving data form a 16-bit source 65. Accordingly,source 65 is connected directly to 16-bit input formatter 54. InFIG. 2C ,video processor 50 is shown as receiving data form a 24-bit source 70. Accordingly,source 70 is connected directly to 24-bit input formatter 52. Therefore, as seen from the above Figures, in prior art video processors, depending on the type and the number of bits carried by each source, a direct connection is made between the source and one of the input-formatters disposed in the video processor at any given time. Because the input formatters are hardwired to the source supplying the input signals, there is no flexibility in reallocating the various sources to the input formatters. -
FIG. 4 is a high-level block diagram of anexemplary input stage 200 of a video signal processor (not shown), in accordance with one exemplary embodiment of the present invention.Input stage 200 is shown as including first and second multiplexing stages 210, and 220. It is understood, however, that more multiplexing stages may be disposed ininput stage 200.Input stage 200 is also shown as including a 24-bit formatter 202, a 16-bit formatter 204, and an 8-bit formatter 206. It is understood, however, that more formatters with other bits may be disposed ininput stage 200. Each of theformatters bit formatter 206 is configured to handle higher clock frequency and an encoding scheme with timing synchronization embedded therein. Video buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0], each of which is an 8-bit bus, are received by input terminals of the video processor (not shown) in whichinput stage 200 is disposed. - Each of multiplexing
stages stage 210 is shown as includingmultiplexers stage 220 is shown as includingmultiplexers multiplexers multiplexers multiplexers multiplexer 210 a respectively receive bits b0 and b1 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 a. Select terminal S0 and S1 ofmultiplexer 210 b respectively receive bits b2 and b3 of a software controlled register configured to select from among one of the input signals applied tomultiplexer 210 b. Select terminal S0 and S1 ofmultiplexer 210 c respectively receive bits b4 and b5 of a software controlled register configured to select from among one of the input signals applied tomultiplexer 210 c. Select terminal S0 and S1 ofmultiplexer 210 d respectively receive bits b6 and b7 of a software controlled register configured to select from among one of the input signals applied to multiplexer 210 d. - In response to the signals applied to select terminals S0, S1 of
multiplexer 210 a, the signals carried by one of the buses VIDI_CH0[7:0], VIDI_CH1[7:0], VIDI_CH2[7:0] are supplied by output terminal O0, shown as bus A[7:0]. The other output terminal O1 supplies signal A[0:7] whose bits are reversed with respect to bus A[0:7]. In response to the signals applied to select terminals S0, S1 ofmultiplexer 210 b, the signals carried by one of the video buses VIDI_CH0[7:0], VIDI_CH1[7:0], VIDI_CH2[7:0] are supplies by output terminal O0, shown as bus B[7:0]. The other output terminal O1 supplies signal B[0:7] whose bits are reversed with respect to bus B[7:0]. In response to the signals applied to select terminals S0, S1 ofmultiplexer 210 c, the signals carried by one of the video buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] are supplies by output terminal O0, shown as bus C[7:0]. The other output terminal O1 supplies signal C[0:7] whose bits are reversed with respect to bus C[7:0]. In response to the signals applied to select terminals S0, S1 ofmultiplexer 210 d, the signals carried by one of the video buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] are supplies by output terminal O0, shown as bus D[7:0]. The other output terminal O1 supplies signal D[0:7] whose bits are reversed with respect to bus D[7:0]. - Buses A[0:7] and A[7:0] are respectively received by input terminals I0 and I1 of
multiplexer 220 a disposed in multiplexingstage 220.Multiplexer 220 b disposed in multiplexingstage 220 is configured to receive buses B[7:0] and B[0:7] at its respective input terminals I0, I1.Multiplexer 220 c disposed in multiplexingstage 220 is configured to receive buses C[7:0] and C[0:7] at its respective input terminals I0, I1.Multiplexer 220 d disposed in multiplexingstage 220 is configured to receive buses D[7:0] and D[0:7] at its respective input terminals I0, I1. - In response to the signal b8 applied to select terminal S of
multiplexer 220 a, the signals carried by one of the buses A[7:0] and A[0:7] is applied to input terminal I0 of 24-bit input formatter 202. In response to the signal b9 applied to select terminal S ofmultiplexer 220 b, the signals carried by one of the buses B[7:0] and B[0:7] is applied to input terminal I1 of 24-bit input formatter 202. In response to the signal b10 applied to select terminal S ofmultiplexer 220 c, the signals carried by one of the buses C[7:0] and C[0:7] is applied to input terminal I2 of 24-bit input formatter 202. Input terminals I0, I1 ofinput formatter 202 are respectively coupled to input terminals I0, I1 ofinput formatter 204. In response to the signal b11, the signals carried by one of the buses D[7:0] and D[0:7] is supplied to input terminal I ofmultiplexer 206. - In accordance with the present invention, as shown in the exemplary embodiment of
input stage 200, any one of the buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] may be delivered to any one of the input terminals I0, I1, and I2 ofinput formatter 202, in response to the signals applied to the select terminals of the multiplexers disposed in multiplexingstages input formatter 202; the 8 bits of bus VIDI_CH2[7:0], either in their original form or in a reverse order, may be delivered to input terminal I1 ofinput formatter 202, and the 8-bits of bus VIDI_CH1[7:0], either in their original form or in a reverse order, may be delivered to input terminal I2 ofinput formatter 202. Similarly, for example, the 8-bits of bus VIDI_CH2[7:0], either in their original form or in a reverse order, may be delivered to input terminal I0 ofinput formatter 202; the 8 bits of bus VIDI_CH0[7:0], either in their original form or in a reverse order, may be delivered to input terminal I1 ofinput formatter 202, and the 8-bits of bus VIDI_CH1[7:0], either in their original form or in a reverse order, may be delivered to input terminal I0 ofinput formatter 202. Similarly, any of the buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] may be received by input terminal I ofinput formatter 206. - In some embodiments, each of the buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] may be generated by a different source of video signal. For example, the 8 bits of bus VIDI_CH0[7:0] may be supplied by a television, the 8 bits of bus VIDI_CH1[7:0] may be supplied by a personal computer, and the 8 bits of bus VIDI_CH2[7:0] may be supplied by a high definition video source. In other embodiments, buses VIDI_CH0[7:0], VIDI_CH1[7:0], and VIDI_CH2[7:0] may carry the red, green and blue components associated with the same video signal. Therefore, signal AA[7:0], supplied by
multiplexer 220 a, may be the Y or the green component of a video source, signal BB[7:0], supplied bymultiplexer 220 b, may be the U or the blue component of a video source, and signal CC[7:0], supplied bymultiplexer 220 c may be the V or the red component of a video source. If YUV 4:2:2 components are used, the 16-bit input formatter 204 is adapted to receive the Y component on one of its input terminals (e.g., I0) and the UV component on the other one of its input terminals (e.g., I1). If time multiplexed YUV 4:2:2 components, such as ITU656, are used, 8-bit input formatter 206 is typically adapted to receive the video data on its input terminals. -
FIG. 5 is a high-level block diagram of anexemplary output stage 300 of a video signal processor, in accordance with one embodiment of the present invention.Output stage 300 is shown as including first and second multiplexing stages 310, and 320. It is understood, however, that more multiplexing stages may be disposed inoutput stage 300.Output stage 300 is configured to receive buses Y/G[7:0], U/B[7:0] V/R[7:0] and supply signals on output buses VIDO_CH0[7:0], VIDO_CH1[7:0], and VIDO_CH2[7:0], as example of 8-bit bus structure in one instance - Each of multiplexing
stages stage 310 is shown as includingmultiplexers stage 320 is shown as includingmultiplexers multiplexers multiplexers multiplexers - Select terminal S0 and S1 of
multiplexer 310 a respectively receive bits d0 and d1 of a software controlled register configured to select from among one of the input signals applied to multiplexer 310 a. Select terminal S0 and S1 ofmultiplexer 310 b respectively receive bits d2 and d3 of a software controlled register configured to select from among one of the input signals applied tomultiplexer 310 b. Select terminal S0 and S1 ofmultiplexer 310 c respectively receive bits d4 and d5 of a software controlled register configured to select from among one of the input signals applied tomultiplexer 310 c. - In response to the signals applied to select terminals S0, S1 of
multiplexer 310 a, the signals carried by one of the buses Y/G[7:0], U/B[7:0], V/R[7:0] are supplied as output signals O[7:0] by output terminal O0 ofmultiplexer 310 a. The other output terminal O1 ofmultiplexer 310 a supplies signal O[0:7] whose bits are reversed with respect to bus O[7:0]. In response to the signals applied to select terminals S0, S1 ofmultiplexer 310 b, the signals carried by one of the video buses Y/G[7:0], U/B[7:0], V/R[7:0] as output signals P[7:0] by output terminal O0 ofmultiplexer 310 b. The other output terminal O1 supplies signal P[0:7] whose bits are reversed with respect to bus P[7:0]. In response to the signals applied to select terminals S0, S1 ofmultiplexer 310 c, the signals carried by one of the buses Y/G[7:0], U/B[7:0], V/R[7:0] are supplied as output signals Q[7:0] by output terminal O0 ofmultiplexer 310 c. The other output terminal O1 supplies signal Q[0:7] whose bits are reversed with respect to bus Q[7:0]. - Buses O[7:0] and 0[0:7] are respectively received by input terminals I0 and I1 of
multiplexer 320 a disposed in multiplexingstage 320.Multiplexer 320 b disposed in multiplexingstage 320 is configured to receive buses P[7:0] and P[0:7] at its respective input terminals I0, I1. Multiplexer 230 c disposed in multiplexing stage 230 is configured to receive buses Q[7:0] and Q[0:7] at its respective input terminals I0, I1. - In response to the signal d6 applied to select terminal S of
multiplexer 320 a, the signals carried by one of the input terminals ofmultiplexer 320 a is supplied as output signal VIDO_CH0[7:0] via outputterminal O multiplexer 320 a. In response to the signal d7 applied to select terminal S ofmultiplexer 320 b, the signals carried by one of the input terminals ofmultiplexer 320 b is supplied as output signal VIDO_CH1[7:0] via outputterminal O multiplexer 320 b. In response to the signal d8 applied to select terminal S ofmultiplexer 320 c, the signals carried by one of the input terminals ofmultiplexer 320 c is supplied as output signal VIDO_CH2[7:0] via outputterminal O multiplexer 320 c. - In accordance with the present invention, as shown in the exemplary embodiment of
output stage 300, any one of the buses Y/G[7:0], U/B[7:0], V/R[7:0] may be delivered to the output terminal of any one of themultiplexers multiplexer 320 a; the 8 bits of bus U/B[7:0], either in their original form or in a reverse order, may be delivered to output terminal O ofinput formatter 320 b, and the 8-bits of bus V/R[7:0], either in their original form or in a reverse order, may be delivered to output terminal O ofmultiplexer 320 c. Similarly, for example, the 8-bits of bus U/B[7:0], either in their original form or in a reverse order, may be delivered to output terminal O ofmultiplexer 320 a; the 8 bits of bus V/R[7:0], either in their original form or in a reverse order, may be delivered to output terminal O ofinput formatter 320 b, and the 8-bits of bus Y/G[7:0], either in their original form or in a reverse order, may be delivered to output terminal O ofmultiplexer 320 c. - In some embodiments, bus Y/G[7:0] may carry either the Y or the green component of a video source, bus U/B[7:0] may carry either the U or the blue component of a video source, and bus V/R[7:0] may carry either V or the red component of a video source.
- The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the number of multiplexing stages disposed in either the input or output stages of the video processor. The invention is not limited by the number of bus lines or the number of signals lines disposed in each bus line. The invention is not limited by the number of channel supplying video signal to the video processor. Nor is the invention limited by the number of input formatters disposed in the video processor. The invention is not limited by the type of integrated circuit in which the present disclosure may be disposed. Nor is the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Claims (35)
1. A video processing integrated circuit comprising an input stage, said input stage further comprising:
first and second input formatters; and
a first multiplexing stage configured to receive N buses each carrying M bits of video signals, wherein said multiplexing stage is further configured to selectively deliver the M bits of at least one of the N bus lines to one of U input terminals of the first input formatter and to one of the V input terminals of the second input formatter.
2. The video processing integrated circuit of claim 1 wherein each of the N buses is generated by a different video source.
3. The video processing integrated circuit of claim 1 wherein each of the N buses is associated with a different RGB component of a same video source.
4. The video processing integrated circuit of claim 1 wherein each of the N buses is associated with a different YUV component of a same video source.
5. The video processing integrated circuit of claim 1 further comprising:
a second multiplexing stage configured to receive output signals supplied by the first multiplexing stage and deliver a selected ones of the received signals to first and second input formatters.
6. The video processing integrated circuit of claim 5 wherein said first multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
7. The video processing integrated circuit of claim 6 wherein said second multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
8. The video processing integrated circuit of claim 7 wherein N is three and W is four, wherein each of the multiplexers in the first multiplexing stage is configured to receive each of the buses and deliver a selected one of the buses on its first output terminals, and an associated order modified bits of the selected bus on its second output terminal
9. The video processing integrated circuit of claim 8 wherein each of the multiplexers in the second multiplexing stage is configured to receive a different one of the selected buses delivered by the multiplexers of the first multiplexing stage as well as receive the associated order modified bits of the selected bus and deliver one of the received buses to its associated output terminal.
10. The video processing integrated circuit of claim 9 wherein an output terminal of at least three of the multiplexers disposed in the second multiplexing stage are coupled to input terminals of the first input formatter.
11. A method of operating a video processor, the method comprising:
receiving N buses each carrying M bits; and
selectively delivering the M bits of at least one of the N bus lines to one of U input terminals of a first input formatter disposed in the video processor and to one of V input terminals of a second input formatter disposed in the video processor.
12. The method of claim 11 wherein each of the N buses is generated by a different video source.
13. The method of claim 11 wherein each of the N buses is associated with a different RGB or YUV component of a same video source.
14. The method of claim 11 further comprising:
receiving output signals supplied by the first multiplexing stage; and
delivering a selected ones of the received signals to first and second input formatters.
15. The method of claim 14 wherein said first multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
16. The method of claim 15 wherein said second multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
17. The method of claim 16 wherein N is three and W is four, the method further comprising:
configuring each of the multiplexers in the first multiplexing to receive each of the buses and deliver a selected one of the buses on its first output terminals, and an associated order modified bits of the selected bus on its second output terminal.
18. The method of claim 17 wherein N is three and W is four, the method further comprising:
configuring each of the multiplexers in the second multiplexing stage to receive a different one of the selected buses delivered by the multiplexers of the first multiplexing stage as well as to receive the associated order modified bits of the selected bus and deliver one of the received buses to its associated output terminal.
19. The method of claim 18 wherein an output terminal of at least three of the multiplexers disposed in the second multiplexing stage are coupled to input terminals of the first input formatter.
20. A video processing integrated circuit comprising an output stage, said output stage further comprising:
first multiplexing stage configured to receive N buses generated by the video processing integrated circuit, each bus carrying M bits of video signals, wherein said multiplexing stage is further configured to selectively deliver the M bits of at least one of the N bus lines to one of U output terminals of the video processing integrated circuit.
21. The video processing integrated circuit of claim 20 wherein each of the N buses carries a different component of an RGB video signal.
22. The video processing integrated circuit of claim 20 wherein each of the N buses carries a different component of an YUV video signal.
23. The video processing integrated circuit of claim 20 further comprising:
a second multiplexing stage configured to receive output signals supplied by the first multiplexing stage and deliver a selected ones of the received signals to output terminals of the video processing integrated circuit.
24. The video processing integrated circuit of claim 23 wherein said first multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
25. The video processing integrated circuit of claim 24 wherein said second multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
26. The video processing integrated circuit of claim 25 wherein N is three and W is three, wherein each of the multiplexers in the first multiplexing stage is configured to receive each of the N buses and deliver a selected one of the buses on its first output terminals, and an associated order modified bits of the selected bus on its second output terminal.
27. The video processing integrated circuit of claim 26 wherein each of the multiplexers in the second multiplexing stage is configured to receive a different one of the selected buses delivered by the multiplexers of the first multiplexing stage as well as receive the associated order modified bits of the selected bus and deliver one of the received buses to its associated output terminal.
28. A method of operating a video processor, the method comprising:
receiving N buses generated by the video processing integrated circuit, each bus carrying M bits of video signals;
selectively delivering the M bits of at least one of the N bus lines as output signals of a first multiplexing stage.
29. The method of claim 28 wherein each of the N buses carries a different component of an RGB video signal.
30. The method of claim 28 wherein each of the N buses carries a different component of an YUV video signal.
31. The method of claim 28 further comprising:
receiving output signals supplied by the first stage;
delivering a selected ones of the received output signals of the first stage to output terminals of the video processing integrated circuit.
32. The method of claim 31 wherein said first multiplexing stage includes W multiplexers each having select terminals controlled by a software controlled register.
33. The method of claim 32 wherein said delivering a selected ones of the received output signals of the first stage to output terminals of the video processing integrated circuit is carried out via a second multiplexing stage that includes W multiplexers each having select terminals controlled by a software controlled register.
34. The method of claim 33 wherein N is three and W is three, wherein each of the multiplexers in the first multiplexing stage is configured to receive each of the N buses and deliver a selected one of the buses on its first output terminals, and an associated order modified bits of the selected bus on its second output terminal.
35. The method of claim 34 wherein each of the multiplexers in the second multiplexing stage is configured to receive a different one of the selected buses delivered by the multiplexers of the first multiplexing stage as well as receive the associated order modified bits of the selected bus and deliver one of the received buses to its associated output terminal.
Priority Applications (1)
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US11/182,101 US20060013243A1 (en) | 2004-07-16 | 2005-07-14 | Video processor with programmable input/output stages to enhance system design configurability and improve channel routing |
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US11/182,101 US20060013243A1 (en) | 2004-07-16 | 2005-07-14 | Video processor with programmable input/output stages to enhance system design configurability and improve channel routing |
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US11/182,102 Expired - Fee Related US7253842B2 (en) | 2004-07-16 | 2005-07-14 | Locking display pixel clock to input frame rate |
US11/182,101 Abandoned US20060013243A1 (en) | 2004-07-16 | 2005-07-14 | Video processor with programmable input/output stages to enhance system design configurability and improve channel routing |
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US11/182,102 Expired - Fee Related US7253842B2 (en) | 2004-07-16 | 2005-07-14 | Locking display pixel clock to input frame rate |
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WO2006019865A3 (en) | 2007-12-06 |
WO2006019865A2 (en) | 2006-02-23 |
US20060012714A1 (en) | 2006-01-19 |
WO2006010157A2 (en) | 2006-01-26 |
WO2006019867A3 (en) | 2006-06-08 |
US20060012712A1 (en) | 2006-01-19 |
CN1998139A (en) | 2007-07-11 |
US7253842B2 (en) | 2007-08-07 |
WO2006019867A2 (en) | 2006-02-23 |
WO2006010157A3 (en) | 2007-02-15 |
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