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US20050269669A1 - Capacitor constructions and methods of forming - Google Patents

Capacitor constructions and methods of forming Download PDF

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US20050269669A1
US20050269669A1 US11185468 US18546805A US2005269669A1 US 20050269669 A1 US20050269669 A1 US 20050269669A1 US 11185468 US11185468 US 11185468 US 18546805 A US18546805 A US 18546805A US 2005269669 A1 US2005269669 A1 US 2005269669A1
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layer
capacitor
conductive
electrode
silicon
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US11185468
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Brent McClure
Casey Kurth
Shenlin Chen
Debra Gould
Lyle Breiner
Er-Xuan Ping
Fred Fishburn
Hongmei Wang
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Mcclure Brent A
Kurth Casey R
Shenlin Chen
Gould Debra K
Breiner Lyle D
Er-Xuan Ping
Fishburn Fred D
Hongmei Wang
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805Capacitors only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10861Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor being in a substrate trench
    • H01L27/10867Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor being in a substrate trench with at least one step of making a connection between transistor and capacitor, e.g. buried strap
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10873Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

Description

    TECHNICAL FIELD
  • [0001]
    The invention pertains to capacitor constructions and methods of forming capacitor constructions. The invention also pertains to memory devices including such capacitor constructions and to computer systems including such memory devices.
  • BACKGROUND OF THE INVENTION
  • [0002]
    The RC (resistance and capacitance) time constant of a capacitor is indicative of the time it takes to charge or discharge the capacitor. For a given resistance, increasing capacitance will accordingly increase charging/discharging time. However, high cell capacitance becomes more desirable as devices become smaller. The increased RC time constant of high cell capacitance parts may prevent such parts from passing write time sensitive tests, resulting in decreased process margin. Also, tests designed to guardband write speed to the capacitor are limited when high cell capacitance parts are used.
  • [0003]
    As may be appreciated, improved capacitor constructions and methods of forming them are desired to decrease the RC time constant.
  • SUMMARY OF THE INVENTION
  • [0004]
    According to one aspect of the invention, a capacitor construction includes a first electrode, a nitride layer between the first electrode and a surface supporting the capacitor construction, a capacitor dielectric over the first electrode, and a second electrode over the capacitor dielectric. By way of example, the nitride layer may be conductive. The first electrode may be in conductive contact with the nitride layer. Accordingly, the capacitor construction may exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the conductive nitride layer. Instead, the nitride layer may be insulative. Either way, the first electrode may contain Si and the nitride layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. Alternatively, the capacitor construction may further include an undoped rough silicon layer between the first electrode and the nitride layer. The nitride layer may limit Si of the rough silicon layer from contributing to formation of metal silicide material between the rough silicon layer and the supporting surface. Exemplary materials for the nitride layer include TiN and silicon nitride, as well as other materials in keeping with the principles of the inventions described herein. The silicon nitride may contain Si3N4.
  • [0005]
    According to another aspect of the invention, a capacitor construction includes a storage node in a substrate, a composite first electrode, a capacitor dielectric over the first electrode, and a second electrode over the capacitor dielectric. The first electrode includes a first conductive layer over and in conductive contact with the storage node and includes a conductive polysilicon layer over and in conductive contact with the first conductive layer. The first conductive layer exhibits a first conductivity greater than a second conductivity of the polysilicon layer. By way of example, the first conductive layer may contain a nitride. The capacitor construction may exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the first conductive layer. The first conductive layer may limit Si of the polysilicon layer from contributing to formation of metal silicide material between the polysilicon layer and the storage node.
  • [0006]
    According to a further aspect of the invention, a capacitor construction may include a metal-containing storage node in a substrate, a barrier layer over the substrate, and a polysilicon layer over the barrier layer, the polysilicon layer not physically contacting the storage node. The capacitor construction includes an opening through the polysilicon layer and barrier layer to the storage node, and a first conductive layer over the polysilicon layer and in conductive contact with the storage node through the opening. The first conductive layer is comprised by a first electrode. A capacitor dielectric is over the first electrode and a second electrode is over the capacitor dielectric. By way of example, the barrier layer may include a nitride. The barrier layer may be insulative. The barrier layer may limit Si of the polysilicon layer from contributing to formation of metal silicide material between the polysilicon layer and the metal-containing storage node.
  • [0007]
    Still further aspects of the invention include methods for forming the capacitor constructions described herein. Also, included among aspects of the invention are memory devices having a plurality of memory cells that contain the capacitor constructions described herein. Such memory devices may be part of a computer system that also includes a microprocessor. The memory devices may be dynamic random access memory (DRAM).
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • [0009]
    FIG. 1 is a partial sectional view of a capacitor construction formed on a substrate according one aspect of the invention.
  • [0010]
    FIG. 2 is a partial sectional view of a capacitor construction formed on a substrate according to another aspect of the invention.
  • [0011]
    FIGS. 3-6 are partial sectional views at sequential process stages leading to formation of the capacitor construction of FIG. 6 formed on a substrate according to a further aspect of the invention.
  • [0012]
    FIGS. 7-12 are partial sectional views at sequential process stages leading to formation of the capacitor construction of FIG. 12 formed on a substrate according to a still further aspect of the invention.
  • [0013]
    FIG. 13 is a diagrammatic view of a computer illustrating an exemplary application of the present invention.
  • [0014]
    FIG. 14 is a block diagram showing particular features of the motherboard of the FIG. 14 computer.
  • [0015]
    FIG. 15 is a high level block diagram of an electronic system according to an exemplary aspect of the present invention.
  • [0016]
    FIG. 16 is a simplified block diagram of an exemplary memory device according to an aspect of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0017]
    A storage node is typically electrically connected to the lower electrode of a capacitor. Exemplary storage nodes include a conductive polysilicon plug, a tungsten plug, and other structures and materials known to those skilled in the art. However, often the electrical connection between the storage node and lower electrode does not provide an equidistant path to all points within the lower electrode. Accordingly, the resistance of the lower electrode along the various conductive paths might not be uniform across the capacitor. The conductive path length within the lower electrode multiplied by the resistivity of the lower electrode yields increasing resistance for points of increasing distance from the storage node.
  • [0018]
    The net effect of the varying resistance can be modeled as several smaller sub-capacitors in parallel. The resistance of the modeled sub-capacitors' lower electrodes increases as the distance from the storage node increases. The sub-capacitors with a higher resistance in the lower electrode increase the RC time constant and the charge or discharge time for the overall combination of sub-capacitors (the actual capacitor). Reducing the electrode resistance is thus useful in reducing the RC time constant of high cell capacitance parts and allowing such parts to pass write time sensitive tests, resulting in improved process margin.
  • [0019]
    In addition, one of the conventional structures used to provide increased capacitance involves forming the capacitor dielectric on a lower electrode having a rough surface, enhancing surface area per unit area. Hemispherical grain (HSG) silicon is a common candidate for materials providing the desired rough surface. However, in the present context, a surface may be considered rough even though it comprises grains that are not considered hemispherical. Typically, smooth polysilicon is first deposited and then converted to rough silicon. Unfortunately, Si of the smooth polysilicon or rough silicon can react with the material of the storage node, especially tungsten, to create undesirable layers between the rough silicon and storage node. Such unwanted layers may include, for example, a metal silicide such as tungsten silicide. Accordingly, limiting the formation of performance degrading layers between the storage node and lower electrode is also useful.
  • [0020]
    It has been discovered that the problems described above of high RC time constant and/or undesirable material forming between the lower electrode and storage node can be resolved by forming a properly selected material under the lower electrode. Such a solution as described herein in the context of various aspects of the invention is particularly suitable where a capacitor construction is formed over a semiconductive substrate. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. However, the aspects of the invention might also be suitable in other contexts.
  • [0021]
    In the context of the present document, the term “capacitor construction” refers to a structure suitable for comprising part or all of a completed capacitor. The most basic components of a completed capacitor include two electrodes separated by a dielectric. A capacitor construction may include one or more of the basic components. Those of ordinary skill will recognize that a completed capacitor may include additional components to form a functioning device. The capacitor constructions described herein may be considered completed capacitors or may be combined with any other components known to those of ordinary skill that may be useful in forming a functioning completed capacitor.
  • [0022]
    FIG. 1 shows a sectional view of a capacitor construction 10 formed on substrate 12. Substrate 12 provides a supporting surface for capacitor construction 10 and may be a semiconductive substrate. Substrate 12 may include a storage node (not shown) of any structure and material known to those of ordinary skill. The storage node may be formed in an insulative material, such as silicon dioxide containing material. One example includes borophosphosilicate glass (BPSG). FIG. 1 also shows an underlayer 14 on substrate 12, a first electrode 16 on underlayer 14, a dielectric 18 on first electrode 16, and a second electrode 20 on dielectric 18. The structure and composition of underlayer 14 may be selected to afford the advantages described herein after considering the structure and materials of substrate 12, a storage node, and first electrode 16 as well as potentially other considerations. For example, underlayer 14 may be conductive or insulative. Underlayer 14 may have a thickness of from about 50 to about 250 Angstroms. When insulative, underlayer 14 preferably has a thickness of from about 100 to about 200 Angstroms. When conductive, an underlayer 14 thickness can largely depend on the particular configuration of the capacitor. A thicker underlayer 14 might prompt a less thick first electrode 16 and thus decrease capacitance. A conductive underlayer 14 might be selected to address the problem of high RC time constant as well as the problem of undesired material forming under first electrode 16, such as between first electrode 16 and a storage node. An insulative underlayer 14 may be selected to resolve the problem of undesired material forming under first electrode 16.
  • [0023]
    According to one aspect of the invention, a capacitor construction includes a first electrode, a nitride layer between the first electrode and a surface supporting the capacitor construction, a capacitor dielectric over the first electrode, and a second electrode over the capacitor dielectric. The nitride layer may be conductive or insulative. The first electrode may be in conductive contact with or formed on the nitride layer. Additionally, the capacitor construction may exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking a conductive nitride layer. For example, the nitride layer may exhibit a first resistance less than a second resistance of the first electrode. The nitride layer may thus reduce the effective resistance of the lower electrode by about 25% to 35% or more.
  • [0024]
    A capacitor construction lacking the conductive nitride layer exhibits a RC time constant reflective of the resistance that occurs along conductive paths to points that are not equidistant from a storage node or other conductive connection to the first electrode. The conductive nitride layer can provide conductive pathways to such non-equidistant points at least a portion of which exhibit a lower resistance. The lower resistance thus provides a lower RC time constant and decreases the time for the capacitor construction to charge or discharge.
  • [0025]
    The nitride layer may comprise a variety of materials, including TiN, TiSiN, silicon nitride, TaN, TaSiN, and WN. Usually, TiN provides a conductive nitride layer and silicon nitride provides an insulative nitride layer. TiN and/or TaN may be preferred for conductive nitrides. When the first electrode comprises TiN or other metal-containing conductive material, it may be referred to as a metallized electrode. Regardless of nitride layer conductivity, the first electrode may include Si and the nitride layer can limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. One example of the first electrode including Si is a first electrode that is a conductive rough silicon layer. The rough silicon may comprise HSG. Combo HSG (CHSG) is one particularly suitable type of HSG silicon layer. CHSG formation involves a single deposition of smooth polysilicon having an outermost region that is doped for seed formation while an innermost region is not doped for seed formation (i.e., lower dopant concentration). In situ heat processing, such as annealing, can yield a seed layer that may be further heat processed to produce HSG silicon. CHSG formation may be contrasted with conventional methods that involve depositing undoped smooth polysilicon, cleaning the undoped layer, depositing doped smooth polysilicon, and heat processing to form HSG silicon.
  • [0026]
    In the case where the nitride layer is conductive, the first electrode may include the conductive rough silicon and the nitride layer. In the case where the nitride layer is insulative, a preferred first electrode further includes another conductive layer over the conductive rough silicon layer. The another conductive layer may be used in the case where the nitride layer is conductive, but it is less preferable. The another conductive layer can include TiN, as well as other materials.
  • [0027]
    FIG. 2 shows a partial sectional view of a capacitor construction 22 formed on substrate 12. Capacitor construction 22 includes a conductive layer 24 formed on substrate 12, a HSG silicon layer 26 formed on conductive layer 24, dielectric 18 formed on HSG silicon layer 26, and second electrode 20 formed on dielectric 18. An HSG silicon layer such as layer 26 may have a thickness of from about 300 to about 1000 Angstroms and may provide enhance surface area by a factor of from about 1.25 to about 2.2, preferably from about 1.5 to about 1.8, or alternatively about 2.
  • [0028]
    Attempts to improve the RC time constant of a capacitor have included forming a conductive layer similar to conductive layer 24, but between HSG silicon layer 26 and dielectric 18. One problem with such an approach includes the difficulty encountered with integrating such an intermediate conductive layer with existing processes for thereafter completing formation of the capacitor. As one example, forming dielectric 18 often involves wet gate processing of a cell nitride, such as in an oxide-nitride-oxide (ONO) composite dielectric, to reduce porosity of the nitride. However, wet gate processing may oxidize an underlying conductive layer between HSG silicon layer 26 and dielectric 18. With conductive layer 24 formed beneath HSG silicon layer 26 as in FIG. 2, such integration problems are largely resolved. Some advantage may exist to forming a conductive layer instead between HSG silicon layer 26 and dielectric 18 since it may alleviate depletion effects within HSG silicon layer 26, but resolving the integration problems is viewed as more significant.
  • [0029]
    “Depletion effects” refers to the well known phenomenon wherein charge carriers within conductive silicon migrate to the dielectric interface and deplete inner portions of the conductive silicon of the charge carriers. Since silicon is intrinsically semiconductive and is rendered conductive by addition of charge carriers, significant migration potentially creates an inner semiconductive, or even poorly semiconductive, region that in essence functions as a sort of internal dielectric. Accordingly, depletion effects can degrade capacitor performance. Conceivably, a conductive layer could be formed both below HSG silicon layer 26 and between HSG silicon layer 26 and dielectric 18. However, even though such structure may address depletion effects, it may introduce process integration problems and is thus less preferred, as indicated above. It is an advantage of aspects of the invention described herein that a conductive layer below HSG silicon layer 26 can enhance RC time constant without prompting a change in conventional process flows for dielectric 18 and later formed structures.
  • [0030]
    Notably, a capacitor construction without rough silicon as the first electrode may nevertheless include an undoped rough silicon layer between the first electrode and the nitride layer. In the present context, “undoped” silicon refers to a material having a concentration of conductivity enhancing impurities less than about 1020 atoms/centimeter3 or, alternatively, less than about 1012 atomsicentimeter3. This is because the processes of forming rough silicon may include introducing phosphorous or other dopants on the surface of polysilicon to provide “seeds” for growing grains. The doping may be sufficient to produce the structural change of roughening the silicon without producing a significant electrical change of increasing conductivity by 5% or more. Accordingly, roughened silicon may be considered undoped even though it actually contains dopants in the concentration ranges described above.
  • [0031]
    One purpose for providing the undoped rough silicon layer is to provide area enhancement of a thin electrode formed on the rough surface of the undoped rough silicon layer. Such an electrode may have a thickness of from about 20 to about 500 Angstroms, preferably from about 100 to about 200 Angstroms, or more preferably about 100 Angstroms. TiN is a suitable thin electrode material, as well as other metal-containing conductive materials, that may thus be used to provide an area enhanced, metal-insulator-metal (MIM) capacitor. MIM capacitors have become particularly desirable in memory devices such as DRAM.
  • [0032]
    A layer consisting of undoped rough silicon without enough other constituents sufficient to impart conductivity is typically considered semiconductive. As semiconductive material, the undoped rough silicon layer does not form part of the first electrode. However, the nitride layer may still function to limit Si of the undoped rough silicon layer from contributing to formation of metal silicide material between the rough silicon layer and the supporting surface.
  • [0033]
    According to another aspect of the invention, a capacitor construction includes a rough silicon layer, a nitride layer under the rough silicon layer, a capacitor dielectric over the rough silicon layer, and an electrode over the capacitor dielectric. FIG. 2 provides one example of such a capacitor construction in the case where conductive layer 24 is a nitride layer. When the rough silicon layer and nitride layer are conductive, the nitride layer and the rough silicon layer may form another electrode under the capacitor dielectric. Thus, the capacitor construction may exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the conductive nitride layer. Whether conductive or insulative, the nitride layer may limit Si of the rough silicon layer from contributing to formation of metal silicide material under the rough silicon layer.
  • [0034]
    In a further aspect of the invention, a capacitor construction includes a conductive rough silicon layer over a support surface and a nitride layer between the rough silicon layer and the support surface. The capacitor construction includes a first electrode containing the rough silicon layer, a capacitor dielectric over the first electrode, and a second electrode over the capacitor dielectric. FIG. 2 shows one example of such a capacitor construction for the case where conductive layer 24 is a nitride layer and HSG silicon layer 26 is conductive.
  • [0035]
    FIGS. 1 and 2 provide simplified examples of capacitor constructions incorporating the principles described herein as addressing the problems of high RC time constant and/or undesirable material forming under a lower electrode. Because FIGS. 1 and 2 are highly simplified, those of ordinary skill will readily recognize that capacitor construction 10 and capacitor construction 22 can be readily incorporated into a variety of capacitor designs known in the art by modifying such designs in keeping with the aspects of the invention described herein. FIGS. 3-6 and FIGS. 7-12 show partial sectional views at sequential process stages used in forming the respective capacitor constructions of FIG. 6 and FIG. 12 revealing additional structural details of possible capacitor constructions.
  • [0036]
    For example, in one aspect of the invention, a capacitor construction includes a storage node in a substrate, a composite first electrode, a capacitor dielectric over the first electrode, and a second electrode over the capacitor dielectric. The composite first electrode includes a first conductive layer over and in conductive contact with the storage node and includes a conductive polysilicon layer over and in conductive contact with the first conductive layer. The first conductive layer exhibits a first conductivity greater than a second conductivity of the polysilicon layer.
  • [0037]
    By way of example, the first conductive layer may contain a nitride. The capacitor construction may exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the first conductive layer. Also, the first conductive layer may limit Si of the polysilicon layer from contributing to formation of metal silicide material between the polysilicon layer and the storage node. Accordingly, preferably the first conductive layer does not substantially comprise silicon. Otherwise, a risk may exist for the first conductive layer to contribute to formation of metal silicide.
  • [0038]
    Further, the polysilicon layer may contain HSG silicon. The polysilicon layer may be on the first conductive layer, rather than other materials or layers being intermediate the polysilicon layer and first conductive layer with some sort of conductive contact therebetween. Typically, forming the polysilicon layer on the first conductive layer provides an adequate conductive contact.
  • [0039]
    In a further aspect of the invention, a capacitor construction includes a metal-containing storage node in a substrate, a barrier layer over the substrate, and a polysilicon layer over the barrier layer. The polysilicon layer does not physically contact the storage node. An opening is provided through the polysilicon layer and the barrier layer and to the storage node. A first conductive layer is over the polysilicon layer and in conductive contact with the storage node through the opening. The first conductive layer is comprised by a first electrode, a capacitor dielectric is over the electrode, and a second electrode is over the capacitor dielectric.
  • [0040]
    The barrier layer may include a nitride. The barrier layer may be insulative. The barrier layer may limit Si of the polysilicon layer and metal of the metal-containing storage node from contributing to formation of metal silicide. One example of a storage node metal includes tungsten. The barrier layer may thus limit formation of tungsten silicide. Notably, the first electrode may further include the polysilicon layer in addition to including the first conductive layer. The first conductive may be on the polysilicon layer. The polysilicon layer may instead be undoped or not otherwise comprised by the first electrode.
  • [0041]
    FIGS. 3-6 show sectional views at sequential process stages in forming a capacitor construction 28 of FIG. 6 that is one example of the just described aspect of the invention. FIG. 3 shows insulative layer 32 formed over substrate 12 and storage node 30 within substrate 12. Polysilicon layer 34 is formed over insulative layer 32. Insulative layer 32 may be a barrier layer. FIG. 4 shows a sectional view at a subsequent process stage after removing a portion of polysilicon layer 34 from over storage node 30 and converting remaining polysilicon layer 34 to a HSG silicon layer 36. Thus, a first opening 38 is formed through HSG silicon layer 36 to insulative layer 32. When insulative layer 32 is a barrier layer, it may limit Si of polysilicon layer 34 and HSG silicon layer 52 from contributing to formation of metal silicide material between such layers and storage node 30.
  • [0042]
    FIG. 5 shows a sectional view at a subsequent process stage after removing insulative layer 32 from over storage node 30, forming opening 40 through insulative layer 32 to storage node 30. FIG. 6 shows a sectional view at a subsequent process stage where a conductive layer 42 is formed on HSG silicon layer 36 and in conductive contact with storage node 30 through opening 38 and opening 40. A dielectric 44 is formed on conductive layer 42 and a second electrode 46 is formed on dielectric 44. In the case where HSG silicon layer 36 is conductive, conductive layer 42 and HSG silicon layer 36 together form a first electrode. In the case where HSG silicon layer 36 is undoped and otherwise not conductive, conductive layer 42 alone forms a first electrode. As may be appreciated from FIG. 6, insulative layer 32 functioning as a barrier layer may limit Si of polysilicon layer 32 and/or HSG silicon layer 36 from contributing to formation of metal silicide material between such layers and storage node 30.
  • [0043]
    Turning to FIGS. 7-12, sectional views at sequential process stages are shown to form a capacitor construction 48 of FIG. 12. Noticeably, at least a part of capacitor construction 48 is formed within a container 50. Any size and shape of container known to those skilled in the art may be used. FIG. 7 shows insulative layer 32 formed over substrate 12 and storage node 30, including within container 50 formed as an opening within substrate 12. Polysilicon layer 34 is formed on insulative layer 32. FIG. 8 shows a subsequent sectional view after performing a spacer etch of polysilicon layer 34, such that polysilicon layer 34 remains only over sidewalls of container 50, and after converting remaining polysilicon layer 34 to HSG silicon layer 52. Opening 38 is thus formed through HSG silicon layer 52 to insulative layer 32.
  • [0044]
    The spacer etch of polysilicon layer 34 may include providing a halogen gas, a fluorine containing gas, and an inert gas while applying RF source and bias power under low pressure conditions. The halogen gas may comprise the majority of the gases. The halogen gas may be Cl2 flowed at about 45 standard cubic centimeters per minute (sccm), the fluorine containing gas may be NF3 flowed at about 15 sccm, and the inert gas may be He used for added uniformity. A source power of about 350 watts (W), a bias power of about 200 W, and a pressure of about 10 milliTorr are suitable.
  • [0045]
    FIG. 9 shows a sectional view at a process stage subsequent to that shown in FIG. 8. After etching, insulative layer 32 is removed from over substrate 12 where exposed following the spacer etch of polysilicon layer 34. Removal of exposed insulative layer 32 may include similar conditions to those described above for the spacer etch with the substitution of a fluorinated, carbon-containing gas instead of the halogen and fluorinated gases. CF4, CHF3, or a combination thereof may be used.
  • [0046]
    FIG. 10 shows a sectional view at a subsequent process stage where conductive layer 42 is formed on HSG silicon layer 52 and within container 50 on exposed portions of substrate 12 and storage node 30. The structure of FIG. 10 results after formation of conductive layer 42 followed by chemical mechanical polishing to remove conductive layer 42 and HSG silicon layer 52 outside of container 50.
  • [0047]
    In FIG. 11, dielectric 44 is shown formed on conductive layer 42 and second electrode 46 is shown formed on dielectric 44. When HSG silicon layer 52 is undoped or otherwise not conductive, conductive layer 42 forms a first electrode. When HSG silicon layer 52 is conductive, both HSG silicon layer 52 and conductive layer 42 together form a first electrode. In FIG. 12, dielectric 44 and second electrode 46 are shown after etching to remove excess portions.
  • [0048]
    FIG. 13 illustrates generally, by way of example, but not by way of limitation, an embodiment of a computer system 400 according to an aspect of the present invention. Computer system 400 includes a monitor 401 or other communication output device, a keyboard 402 or other communication input device, and a motherboard 404. Motherboard 404 can carry a microprocessor 406 or other data processing unit, and at least one memory device 408. Memory device 408 can comprise various aspects of the invention described above. Memory device 408 can comprise an array of memory cells, and such array can be coupled with addressing circuitry for accessing individual memory cells in the array. Further, the memory cell array can be coupled to a read circuit for reading data from the memory cells. The addressing and read circuitry can be utilized for conveying information between memory device 408 and processor 406. Such is illustrated in the block diagram of the motherboard 404 shown in FIG. 14. In such block diagram, the addressing circuitry is illustrated as 410 and the read circuitry is illustrated as 412.
  • [0049]
    In particular aspects of the invention, memory device 408 can correspond to a memory module. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation which utilize the teachings of the present invention. The memory device can be incorporated into any of a variety of designs which provide different methods of reading from and writing to memory cells of the device. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed.
  • [0050]
    An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on a memory bus. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flash memories.
  • [0051]
    FIG. 15 illustrates a simplified block diagram of a high-level organization of various embodiments of an exemplary electronic system 700 of the present invention. System 700 can correspond to, for example, a computer system, a process control system, or any other system that employs a processor and associated memory. Electronic system 700 has functional elements, including a processor or arithmetic/logic unit (ALU) 702, a control unit 704, a memory device unit 706 and an input/output (I/O) device 708. Generally, electronic system 700 will have a native set of instructions that specify operations to be performed on data by the processor 702 and other interactions between the processor 702, the memory device unit 706 and the I/O devices 708. The control unit 704 coordinates all operations of the processor 702, the memory device 706 and the I/O devices 708 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 706 and executed. In various embodiments, the memory device 706 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that any of the illustrated electrical components are capable of being fabricated to include DRAM cells in accordance with various aspects of the present invention.
  • [0052]
    FIG. 16 is a simplified block diagram of a high-level organization of various embodiments of an exemplary electronic system 800. The system 800 includes a memory device 802 that has an array of memory cells 804, address decoder 806, row access circuitry 808, column access circuitry 810, read/write control circuitry 812 for controlling operations, and input/output circuitry 814. The memory device 802 further includes power circuitry 816, and sensors 820, such as current sensors for determining whether a memory cell is in a low-threshold conducting state or in a high-threshold non-conducting state. The illustrated power circuitry 816 includes power supply circuitry 880, circuitry 882 for providing a reference voltage, circuitry 884 for providing the first wordline with pulses, circuitry 886 for providing the second wordline with pulses, and circuitry 888 for providing the bitline with pulses. The system 800 also includes a processor 822, or memory controller for memory accessing.
  • [0053]
    The memory device 802 receives control signals 824 from the processor 822 over wiring or metallization lines. The memory device 802 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 802 has been simplified to help focus on the invention. At least one of the processor 822 or memory device 802 can include a capacitor construction in a memory device of the type described previously herein.
  • [0054]
    The various illustrated systems of this disclosure are intended to provide a general understanding of various applications for the circuitry and structures of the present invention, and are not intended to serve as a complete description of all the elements and features of an electronic system using memory cells in accordance with aspects of the present invention. One of the ordinary skill in the art will understand that the various electronic systems can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device(s).
  • [0055]
    Applications for memory cells can include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
  • [0056]
    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (20)

  1. 1-41. (canceled)
  2. 42. A capacitor construction comprising:
    a metal-containing storage node in a substrate;
    a barrier layer over the substrate;
    a polysilicon layer over the barrier layer, the polysilicon layer not physically contacting the storage node;
    an opening through the polysilicon layer and barrier layer to the storage node;
    a first conductive layer over the polysilicon layer and in conductive contact with the storage node through the opening, the first conductive layer being comprised by a first electrode;
    a capacitor dielectric over the first electrode; and
    a second electrode over the capacitor dielectric.
  3. 43. The capacitor construction of claim 42 wherein the barrier layer comprises a nitride.
  4. 44. The capacitor construction of claim 42 wherein the barrier layer is insulative.
  5. 45. The capacitor construction of claim 42 wherein the barrier layer limits Si of the polysilicon layer from contributing to formation of metal silicide material between the polysilicon layer and the metal-containing storage node.
  6. 46. The capacitor construction of claim 42 wherein the storage node comprises tungsten.
  7. 47. The capacitor construction of claim 42 wherein the first conductive layer comprises TiN.
  8. 48. The capacitor construction of claim 42 wherein the polysilicon layer comprises HSG silicon.
  9. 49. The capacitor construction of claim 42 wherein the first conductive layer is on the polysilicon layer.
  10. 50. The capacitor construction of claim 42 wherein the first electrode further comprises the polysilicon layer.
  11. 51. The capacitor construction of claim 42 wherein the polysilicon layer is undoped.
  12. 52-63. (canceled)
  13. 64. A capacitor construction forming method comprising:
    forming a metal-containing storage node in a substrate;
    forming a barrier layer at least over the storage node;
    forming a polysilicon layer at least over the storage node and barrier layer, the polysilicon layer not physically contacting the storage node;
    forming an opening through the polysilicon layer and barrier layer to the storage node;
    forming a first conductive layer over the polysilicon layer and in conductive contact with the storage node through the opening, the first conductive layer being comprised by a first electrode;
    forming a capacitor dielectric over the first electrode; and
    forming a second electrode over the capacitor dielectric.
  14. 65. The method of claim 64 wherein the barrier layer comprises a nitride.
  15. 66. The method of claim 64 wherein the barrier layer is insulative.
  16. 67. The method of claim 64 wherein the barrier layer limits Si of the polysilicon layer from contributing to formation of metal silicide material between the polysilicon layer and the metal-containing storage node.
  17. 68. The method of claim 64 wherein the storage node comprises tungsten.
  18. 69. The method of claim 64 wherein the first conductive layer is formed on the polysilicon layer.
  19. 70. The method of claim 64 wherein the forming an opening comprises:
    forming a first opening through the polysilicon layer to the barrier layer;
    transforming the polysilicon layer to comprise HSG silicon; and
    after the transforming, forming a second opening through the barrier layer to the storage node.
  20. 71-78. (canceled)
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217615B1 (en) * 2000-08-31 2007-05-15 Micron Technology, Inc. Capacitor fabrication methods including forming a conductive layer
US7112503B1 (en) * 2000-08-31 2006-09-26 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US6420230B1 (en) * 2000-08-31 2002-07-16 Micron Technology, Inc. Capacitor fabrication methods and capacitor constructions
US7557015B2 (en) 2005-03-18 2009-07-07 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7544563B2 (en) 2005-05-18 2009-06-09 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7902081B2 (en) 2006-10-11 2011-03-08 Micron Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US7682924B2 (en) 2007-08-13 2010-03-23 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8388851B2 (en) 2008-01-08 2013-03-05 Micron Technology, Inc. Capacitor forming methods
US8274777B2 (en) 2008-04-08 2012-09-25 Micron Technology, Inc. High aspect ratio openings
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US8946043B2 (en) 2011-12-21 2015-02-03 Micron Technology, Inc. Methods of forming capacitors
US8652926B1 (en) 2012-07-26 2014-02-18 Micron Technology, Inc. Methods of forming capacitors

Citations (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291289B1 (en) *
US5006956A (en) * 1988-11-07 1991-04-09 Matsushita Electric Industrial Co., Ltd. Dielectric ceramic composition
US5126283A (en) * 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device
US5187637A (en) * 1992-02-14 1993-02-16 At&T Bell Laboratories Monolithic high-voltage capacitor
US5316982A (en) * 1991-10-18 1994-05-31 Sharp Kabushiki Kaisha Semiconductor device and method for preparing the same
US5432732A (en) * 1991-01-01 1995-07-11 Ohmi; Tadahiro Dynamic semiconductor memory
US5444013A (en) * 1994-11-02 1995-08-22 Micron Technology, Inc. Method of forming a capacitor
US5452178A (en) * 1993-09-22 1995-09-19 Northern Telecom Limited Structure and method of making a capacitor for an intergrated circuit
US5625233A (en) * 1995-01-13 1997-04-29 Ibm Corporation Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide
US5641984A (en) * 1994-08-19 1997-06-24 General Electric Company Hermetically sealed radiation imager
US5774327A (en) * 1995-11-29 1998-06-30 Samsung Electronics Co., Ltd. High dielectric capacitors
US5811344A (en) * 1997-01-27 1998-09-22 Mosel Vitelic Incorporated Method of forming a capacitor of a dram cell
US5885882A (en) * 1995-07-18 1999-03-23 Micron Technology, Inc. Method for making polysilicon electrode with increased surface area making same
US5899725A (en) * 1995-11-15 1999-05-04 Micron Technology, Inc. Method of forming a hemispherical grained silicon on refractory metal nitride
US5905280A (en) * 1997-02-11 1999-05-18 Micron Technology, Inc. Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures
US5908947A (en) * 1996-02-09 1999-06-01 Micron Technology, Inc. Difunctional amino precursors for the deposition of films comprising metals
US5972769A (en) * 1996-12-20 1999-10-26 Texas Instruments Incoporated Self-aligned multiple crown storage capacitor and method of formation
US6033967A (en) * 1997-07-21 2000-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for increasing capacitance in DRAM capacitors and devices formed
US6069053A (en) * 1997-02-28 2000-05-30 Micron Technology, Inc. Formation of conductive rugged silicon
US6097052A (en) * 1992-11-27 2000-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing thereof
US6124158A (en) * 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6144060A (en) * 1997-07-31 2000-11-07 Samsung Electronics Co., Ltd. Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature
US6156606A (en) * 1998-11-17 2000-12-05 Siemens Aktiengesellschaft Method of forming a trench capacitor using a rutile dielectric material
US6174770B1 (en) * 1999-10-14 2001-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a crown capacitor having HSG for DRAM memory
US6180481B1 (en) * 1998-01-09 2001-01-30 Micron Technology, Inc. Barrier layer fabrication methods
US6180447B1 (en) * 1997-02-27 2001-01-30 Samsung Electronics Co., Ltd. Methods for fabricating integrated circuit capacitors including barrier layers having grain boundary filling material
US6204049B1 (en) * 1996-02-09 2001-03-20 The United States Of America As Represented By The Secretary Of Agriculture Fungal compositions for bioremediation
US6204172B1 (en) * 1998-09-03 2001-03-20 Micron Technology, Inc. Low temperature deposition of barrier layers
US6204070B1 (en) * 1997-12-27 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method for manufacturing ferroelectric capacitor
US6207561B1 (en) * 1998-09-29 2001-03-27 Texas Instruments Incorporated Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication
US6207487B1 (en) * 1998-10-13 2001-03-27 Samsung Electronics Co., Ltd. Method for forming dielectric film of capacitor having different thicknesses partly
US6218260B1 (en) * 1997-04-22 2001-04-17 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby
US6218256B1 (en) * 1999-04-13 2001-04-17 Micron Technology, Inc. Electrode and capacitor structure for a semiconductor device and associated methods of manufacture
US6222722B1 (en) * 1998-04-02 2001-04-24 Kabushiki Kaisha Toshiba Storage capacitor having undulated lower electrode for a semiconductor device
US6242299B1 (en) * 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
US6249056B1 (en) * 1997-08-16 2001-06-19 Samsung Electronics Co., Ltd. Low resistance interconnect for a semiconductor device and method of fabricating the same
US6262469B1 (en) * 1998-03-25 2001-07-17 Advanced Micro Devices, Inc. Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor
US6270572B1 (en) * 1998-08-07 2001-08-07 Samsung Electronics Co., Ltd. Method for manufacturing thin film using atomic layer deposition
US6274428B1 (en) * 1999-04-22 2001-08-14 Acer Semiconductor Manufacturing Inc. Method for forming a ragged polysilicon crown-shaped capacitor for a memory cell
US6281142B1 (en) * 1999-06-04 2001-08-28 Micron Technology, Inc. Dielectric cure for reducing oxygen vacancies
US6281543B1 (en) * 1999-08-31 2001-08-28 Micron Technology, Inc. Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same
US6291850B1 (en) * 1998-12-23 2001-09-18 Hyundai Electric Industries Co., Ltd. Structure of cylindrical capacitor electrode with layer of hemispherical grain silicon
US6291289B2 (en) * 1999-06-25 2001-09-18 Micron Technology, Inc. Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon
US20010024387A1 (en) * 1999-12-03 2001-09-27 Ivo Raaijmakers Conformal thin films over textured capacitor electrodes
US6307730B1 (en) * 1999-01-21 2001-10-23 Nec Corporation Capacitor formed by lower electrode having inner and outer uneven surfaces
US6309923B1 (en) * 2000-07-20 2001-10-30 Vanguard International Semiconductor Corporation Method of forming the capacitor in DRAM
US20010038116A1 (en) * 1997-03-14 2001-11-08 Figura Thomas A. Doped silicon structure with impression image on opposing roughened surfaces
US6335240B1 (en) * 1998-01-06 2002-01-01 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device and method for forming the same
US6355519B1 (en) * 1998-12-30 2002-03-12 Hyundai Electronics Industries Co., Ltd. Method for fabricating capacitor of semiconductor device
US6359295B2 (en) * 1997-09-29 2002-03-19 Samsung Electronics Co., Ltd. Ferroelectric memory devices including patterned conductive layers
US6363691B1 (en) * 1999-09-23 2002-04-02 Brown & Williamson Tobacco Corporation Method of wrapping a package having a corona treated tear tape
US6391803B1 (en) * 2001-06-20 2002-05-21 Samsung Electronics Co., Ltd. Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
US20020064915A1 (en) * 1998-12-17 2002-05-30 Hiroyuki Kitamura Semiconductor device and method of forming the same
US6403156B2 (en) * 2000-06-28 2002-06-11 Hyundai Electronics Industries Co., Ltd. Method of forming an A1203 film in a semiconductor device
US6420230B1 (en) * 2000-08-31 2002-07-16 Micron Technology, Inc. Capacitor fabrication methods and capacitor constructions
US20020094632A1 (en) * 2000-08-31 2002-07-18 Agarwal Vishnu K. Capacitor fabrication methods and capacitor constructions
US20020109198A1 (en) * 2000-01-18 2002-08-15 Micron Technology, Inc. Metal oxynitride capacitor barrier layer
US6451650B1 (en) * 2001-04-20 2002-09-17 Taiwan Semiconductor Manufacturing Company Low thermal budget method for forming MIM capacitor
US6458416B1 (en) * 2000-07-19 2002-10-01 Micron Technology, Inc. Deposition methods
US20020142488A1 (en) * 2001-03-28 2002-10-03 Suk-Kyoung Hong FeRAM (ferroelectric random access memory ) and method for forming the same
US20020153579A1 (en) * 2001-04-19 2002-10-24 Nec Corporation Semiconductor device with thin film having high permittivity and uniform thickness
US6486022B2 (en) * 2001-04-30 2002-11-26 Hynix Semiconductor Inc. Method of fabricating capacitors
US20020175329A1 (en) * 2001-05-10 2002-11-28 Tomoyuki Hirano Semiconductor apparatus and method of making same
US20020182820A1 (en) * 2001-05-29 2002-12-05 Samsung Electronics Co. Method of forming a capacitor of an integrated circuit device
US20020197744A1 (en) * 2001-06-21 2002-12-26 Kyu-Mann Lee Ferroelectric memory devices using a ferroelectric planarization layer and fabrication methods
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US6583022B1 (en) * 1998-08-27 2003-06-24 Micron Technology, Inc. Methods of forming roughened layers of platinum and methods of forming capacitors
US6583441B2 (en) * 2000-08-30 2003-06-24 Micron Technology, Inc. Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer
US6596583B2 (en) * 2000-06-08 2003-07-22 Micron Technology, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6596602B2 (en) * 2001-01-29 2003-07-22 Nec Corporation Method of fabricating a high dielectric constant metal oxide capacity insulator film using atomic layer CVD
US6627462B1 (en) * 1999-06-28 2003-09-30 Hyundai Electronics Industries Co., Ltd. Semiconductor device having a capacitor and method for the manufacture thereof
US20030215960A1 (en) * 2002-05-20 2003-11-20 Toshiro Mitsuhashi Method of fabricating ferroelectric capacitor
US6664186B1 (en) * 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US20040018747A1 (en) * 2002-07-20 2004-01-29 Lee Jung-Hyun Deposition method of a dielectric layer
US6709919B2 (en) * 2002-05-15 2004-03-23 Taiwan Semiconductor Manufacturing Company Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin
US6730163B2 (en) * 2002-03-14 2004-05-04 Micron Technology, Inc. Aluminum-containing material and atomic layer deposition methods
US6746930B2 (en) * 2001-07-11 2004-06-08 Micron Technology, Inc. Oxygen barrier for cell container process
US20040125541A1 (en) * 2002-12-30 2004-07-01 Hyun-Jin Chung Capacitor having oxygen diffusion barrier and method for fabricating the same
US6800892B2 (en) * 2003-02-10 2004-10-05 Micron Technology, Inc. Memory devices, and electronic systems comprising memory devices
US6809212B2 (en) * 2002-06-12 2004-10-26 Praxair Technology, Inc. Method for producing organometallic compounds
US6824816B2 (en) * 2002-01-29 2004-11-30 Asm International N.V. Process for producing metal thin films by ALD
US6849505B2 (en) * 2001-09-14 2005-02-01 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
US6881260B2 (en) * 2002-06-25 2005-04-19 Micron Technology, Inc. Process for direct deposition of ALD RhO2
US20050082593A1 (en) * 2003-08-18 2005-04-21 Samsung Electronics Co., Ltd. Capacitor, method of manufacturing the same and memory device including the same
US6946342B2 (en) * 2002-08-16 2005-09-20 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US7018469B2 (en) * 2003-09-23 2006-03-28 Micron Technology, Inc. Atomic layer deposition methods of forming silicon dioxide comprising layers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US109198A (en) * 1870-11-15 Improvement in gates
US664186A (en) * 1900-08-10 1900-12-18 Christain Strobel Cooler.
US6104049A (en) 1997-03-03 2000-08-15 Symetrix Corporation Ferroelectric memory with ferroelectric thin film having thickness of 90 nanometers or less, and method of making same
KR100384851B1 (en) 2000-12-14 2003-05-22 주식회사 하이닉스반도체 Method for fabricating capacitor by Atomic Layer Deposition

Patent Citations (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291289B1 (en) *
US6180481B2 (en) *
US5006956A (en) * 1988-11-07 1991-04-09 Matsushita Electric Industrial Co., Ltd. Dielectric ceramic composition
US5126283A (en) * 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device
US5432732A (en) * 1991-01-01 1995-07-11 Ohmi; Tadahiro Dynamic semiconductor memory
US5316982A (en) * 1991-10-18 1994-05-31 Sharp Kabushiki Kaisha Semiconductor device and method for preparing the same
US5187637A (en) * 1992-02-14 1993-02-16 At&T Bell Laboratories Monolithic high-voltage capacitor
US6097052A (en) * 1992-11-27 2000-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing thereof
US5452178A (en) * 1993-09-22 1995-09-19 Northern Telecom Limited Structure and method of making a capacitor for an intergrated circuit
US5641984A (en) * 1994-08-19 1997-06-24 General Electric Company Hermetically sealed radiation imager
US5444013A (en) * 1994-11-02 1995-08-22 Micron Technology, Inc. Method of forming a capacitor
US5625233A (en) * 1995-01-13 1997-04-29 Ibm Corporation Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide
US5885882A (en) * 1995-07-18 1999-03-23 Micron Technology, Inc. Method for making polysilicon electrode with increased surface area making same
US5899725A (en) * 1995-11-15 1999-05-04 Micron Technology, Inc. Method of forming a hemispherical grained silicon on refractory metal nitride
US5774327A (en) * 1995-11-29 1998-06-30 Samsung Electronics Co., Ltd. High dielectric capacitors
US6204049B1 (en) * 1996-02-09 2001-03-20 The United States Of America As Represented By The Secretary Of Agriculture Fungal compositions for bioremediation
US5908947A (en) * 1996-02-09 1999-06-01 Micron Technology, Inc. Difunctional amino precursors for the deposition of films comprising metals
US5972769A (en) * 1996-12-20 1999-10-26 Texas Instruments Incoporated Self-aligned multiple crown storage capacitor and method of formation
US5811344A (en) * 1997-01-27 1998-09-22 Mosel Vitelic Incorporated Method of forming a capacitor of a dram cell
US5905280A (en) * 1997-02-11 1999-05-18 Micron Technology, Inc. Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures
US6180447B1 (en) * 1997-02-27 2001-01-30 Samsung Electronics Co., Ltd. Methods for fabricating integrated circuit capacitors including barrier layers having grain boundary filling material
US6069053A (en) * 1997-02-28 2000-05-30 Micron Technology, Inc. Formation of conductive rugged silicon
US20010038116A1 (en) * 1997-03-14 2001-11-08 Figura Thomas A. Doped silicon structure with impression image on opposing roughened surfaces
US6218260B1 (en) * 1997-04-22 2001-04-17 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby
US6033967A (en) * 1997-07-21 2000-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for increasing capacitance in DRAM capacitors and devices formed
US6144060A (en) * 1997-07-31 2000-11-07 Samsung Electronics Co., Ltd. Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature
US6249056B1 (en) * 1997-08-16 2001-06-19 Samsung Electronics Co., Ltd. Low resistance interconnect for a semiconductor device and method of fabricating the same
US6359295B2 (en) * 1997-09-29 2002-03-19 Samsung Electronics Co., Ltd. Ferroelectric memory devices including patterned conductive layers
US6204070B1 (en) * 1997-12-27 2001-03-20 Hyundai Electronics Industries Co., Ltd. Method for manufacturing ferroelectric capacitor
US6335240B1 (en) * 1998-01-06 2002-01-01 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device and method for forming the same
US6180481B1 (en) * 1998-01-09 2001-01-30 Micron Technology, Inc. Barrier layer fabrication methods
US6262469B1 (en) * 1998-03-25 2001-07-17 Advanced Micro Devices, Inc. Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor
US6222722B1 (en) * 1998-04-02 2001-04-24 Kabushiki Kaisha Toshiba Storage capacitor having undulated lower electrode for a semiconductor device
US20010023110A1 (en) * 1998-04-02 2001-09-20 Yoshiaki Fukuzumi Storage capacitor having undulated lower electrode for a semiconductor device
US6270572B1 (en) * 1998-08-07 2001-08-07 Samsung Electronics Co., Ltd. Method for manufacturing thin film using atomic layer deposition
US6583022B1 (en) * 1998-08-27 2003-06-24 Micron Technology, Inc. Methods of forming roughened layers of platinum and methods of forming capacitors
US6204172B1 (en) * 1998-09-03 2001-03-20 Micron Technology, Inc. Low temperature deposition of barrier layers
US6207561B1 (en) * 1998-09-29 2001-03-27 Texas Instruments Incorporated Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication
US6207487B1 (en) * 1998-10-13 2001-03-27 Samsung Electronics Co., Ltd. Method for forming dielectric film of capacitor having different thicknesses partly
US6156606A (en) * 1998-11-17 2000-12-05 Siemens Aktiengesellschaft Method of forming a trench capacitor using a rutile dielectric material
US20020064915A1 (en) * 1998-12-17 2002-05-30 Hiroyuki Kitamura Semiconductor device and method of forming the same
US6291850B1 (en) * 1998-12-23 2001-09-18 Hyundai Electric Industries Co., Ltd. Structure of cylindrical capacitor electrode with layer of hemispherical grain silicon
US6355519B1 (en) * 1998-12-30 2002-03-12 Hyundai Electronics Industries Co., Ltd. Method for fabricating capacitor of semiconductor device
US6307730B1 (en) * 1999-01-21 2001-10-23 Nec Corporation Capacitor formed by lower electrode having inner and outer uneven surfaces
US6242299B1 (en) * 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
US6218256B1 (en) * 1999-04-13 2001-04-17 Micron Technology, Inc. Electrode and capacitor structure for a semiconductor device and associated methods of manufacture
US6274428B1 (en) * 1999-04-22 2001-08-14 Acer Semiconductor Manufacturing Inc. Method for forming a ragged polysilicon crown-shaped capacitor for a memory cell
US6281142B1 (en) * 1999-06-04 2001-08-28 Micron Technology, Inc. Dielectric cure for reducing oxygen vacancies
US6124158A (en) * 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6291289B2 (en) * 1999-06-25 2001-09-18 Micron Technology, Inc. Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon
US6627462B1 (en) * 1999-06-28 2003-09-30 Hyundai Electronics Industries Co., Ltd. Semiconductor device having a capacitor and method for the manufacture thereof
US6281543B1 (en) * 1999-08-31 2001-08-28 Micron Technology, Inc. Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same
US6363691B1 (en) * 1999-09-23 2002-04-02 Brown & Williamson Tobacco Corporation Method of wrapping a package having a corona treated tear tape
US6174770B1 (en) * 1999-10-14 2001-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a crown capacitor having HSG for DRAM memory
US6780704B1 (en) * 1999-12-03 2004-08-24 Asm International Nv Conformal thin films over textured capacitor electrodes
US20010024387A1 (en) * 1999-12-03 2001-09-27 Ivo Raaijmakers Conformal thin films over textured capacitor electrodes
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US20020109198A1 (en) * 2000-01-18 2002-08-15 Micron Technology, Inc. Metal oxynitride capacitor barrier layer
US6596583B2 (en) * 2000-06-08 2003-07-22 Micron Technology, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6403156B2 (en) * 2000-06-28 2002-06-11 Hyundai Electronics Industries Co., Ltd. Method of forming an A1203 film in a semiconductor device
US6458416B1 (en) * 2000-07-19 2002-10-01 Micron Technology, Inc. Deposition methods
US6309923B1 (en) * 2000-07-20 2001-10-30 Vanguard International Semiconductor Corporation Method of forming the capacitor in DRAM
US6583441B2 (en) * 2000-08-30 2003-06-24 Micron Technology, Inc. Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer
US20020094632A1 (en) * 2000-08-31 2002-07-18 Agarwal Vishnu K. Capacitor fabrication methods and capacitor constructions
US6420230B1 (en) * 2000-08-31 2002-07-16 Micron Technology, Inc. Capacitor fabrication methods and capacitor constructions
US6664186B1 (en) * 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US6596602B2 (en) * 2001-01-29 2003-07-22 Nec Corporation Method of fabricating a high dielectric constant metal oxide capacity insulator film using atomic layer CVD
US20020142488A1 (en) * 2001-03-28 2002-10-03 Suk-Kyoung Hong FeRAM (ferroelectric random access memory ) and method for forming the same
US20020153579A1 (en) * 2001-04-19 2002-10-24 Nec Corporation Semiconductor device with thin film having high permittivity and uniform thickness
US6451650B1 (en) * 2001-04-20 2002-09-17 Taiwan Semiconductor Manufacturing Company Low thermal budget method for forming MIM capacitor
US6486022B2 (en) * 2001-04-30 2002-11-26 Hynix Semiconductor Inc. Method of fabricating capacitors
US20020175329A1 (en) * 2001-05-10 2002-11-28 Tomoyuki Hirano Semiconductor apparatus and method of making same
US20020182820A1 (en) * 2001-05-29 2002-12-05 Samsung Electronics Co. Method of forming a capacitor of an integrated circuit device
US6391803B1 (en) * 2001-06-20 2002-05-21 Samsung Electronics Co., Ltd. Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
US20020197744A1 (en) * 2001-06-21 2002-12-26 Kyu-Mann Lee Ferroelectric memory devices using a ferroelectric planarization layer and fabrication methods
US6746930B2 (en) * 2001-07-11 2004-06-08 Micron Technology, Inc. Oxygen barrier for cell container process
US6849505B2 (en) * 2001-09-14 2005-02-01 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
US6824816B2 (en) * 2002-01-29 2004-11-30 Asm International N.V. Process for producing metal thin films by ALD
US6730163B2 (en) * 2002-03-14 2004-05-04 Micron Technology, Inc. Aluminum-containing material and atomic layer deposition methods
US6709919B2 (en) * 2002-05-15 2004-03-23 Taiwan Semiconductor Manufacturing Company Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin
US20030215960A1 (en) * 2002-05-20 2003-11-20 Toshiro Mitsuhashi Method of fabricating ferroelectric capacitor
US6809212B2 (en) * 2002-06-12 2004-10-26 Praxair Technology, Inc. Method for producing organometallic compounds
US6881260B2 (en) * 2002-06-25 2005-04-19 Micron Technology, Inc. Process for direct deposition of ALD RhO2
US20040018747A1 (en) * 2002-07-20 2004-01-29 Lee Jung-Hyun Deposition method of a dielectric layer
US6946342B2 (en) * 2002-08-16 2005-09-20 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20040125541A1 (en) * 2002-12-30 2004-07-01 Hyun-Jin Chung Capacitor having oxygen diffusion barrier and method for fabricating the same
US6800892B2 (en) * 2003-02-10 2004-10-05 Micron Technology, Inc. Memory devices, and electronic systems comprising memory devices
US20050082593A1 (en) * 2003-08-18 2005-04-21 Samsung Electronics Co., Ltd. Capacitor, method of manufacturing the same and memory device including the same
US7018469B2 (en) * 2003-09-23 2006-03-28 Micron Technology, Inc. Atomic layer deposition methods of forming silicon dioxide comprising layers

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