US20050242845A1 - Efficient current monitoring for DC-DC converters - Google Patents

Efficient current monitoring for DC-DC converters Download PDF

Info

Publication number
US20050242845A1
US20050242845A1 US10/838,099 US83809904A US2005242845A1 US 20050242845 A1 US20050242845 A1 US 20050242845A1 US 83809904 A US83809904 A US 83809904A US 2005242845 A1 US2005242845 A1 US 2005242845A1
Authority
US
United States
Prior art keywords
latch
comparator
stage
preamplifier
specified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/838,099
Inventor
Dolly Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US10/838,099 priority Critical patent/US20050242845A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WU, DOLLY Y.
Publication of US20050242845A1 publication Critical patent/US20050242845A1/en
Priority to US11/470,130 priority patent/US7372307B1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G01R19/16552Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies in I.C. power supplies
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16571Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing AC or DC current with one threshold, e.g. load current, over-current, surge current or fault current

Definitions

  • the present invention is generally related to DC-DC switching converters, and more particularly to current monitoring of these converters.
  • a switching transistor In a conventional DC-DC converter, a switching transistor (switcher) is turned ON to pass a noisy input voltage to the output as a quiet, well regulated output voltage that is sourcing a large current. This current may be monitored a number of ways.
  • a typical current monitor circuit has a current sensing element which provides an associated voltage signal that is sent to a comparator stage to decide whether the voltage signal is higher than some reference (voltage) value that is representative of an over-current threshold. The comparison is often made only after a certain time interval that allows signals to settle, known as the blanking time interval.
  • FIG. 1 shows a typical timing diagram for the blanking time and a pulse (PH) which controls a conventional DC-DC switcher, turning it on and off to pass or restrict current to the load.
  • PH pulse
  • FIG. 1A with a long PH (switcher ON) time interval case allows the current limit circuit much time after the blanking period, to operate and make a decision.
  • cases 1 B and 1 C give the current limiting circuit very little time to operate and make a decision. This circumstance occurs when the switching cycle is very fast, and the switcher is ON only briefly.
  • FIG. 2 a shows a prior art example of a “continuous time” high speed comparator that may be used as part of a current limiting circuit, similar to those used in many Texas Instruments DC-DC converter products.
  • FIG. 2 b shows a discrete time current comparator, such as described in U.S. Pat. No. 6,147,518, that switches currents. The decision is made on the edge of an enable control signal.
  • FIG. 3 shows a block diagram of a conventional “track and latch” comparator architecture adapted to be used in data converters.
  • a preamplifier is selectively enabled by a clock signal, and its output “tracks” the input while the second latch stage is simultaneous disabled and is controlled by the same clock signal.
  • the latch stage is enabled and regeneratively amplifies the output of the preamplifier with essentially infinite gain, producing and holding the output logic decision.
  • the present invention achieves technical advantages as a current monitoring circuit for DC-DC switching converters, including a track and latch comparator circuit having a preamplifier that is controllable independently of a latch circuit.
  • the preamplifier circuit can be disabled when the latch stage is making its decision, such as to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature also speeds up the signal processing of the overall comparator, and allows it to work in parallel with other circuits.
  • the latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.
  • the preamplifier need not be disabled while the latch is enabled, depending on the system algorithm used to detect over-current conditions. In some situations, it may be better to not disengage the preamplifier stage when the latch stage regenerates and makes its decision. For example, the transistors in the preamplifier may be selectively biased to increase the gain of the preamplifier.
  • the preamplifier includes transistors that may be configured as cascades, but which also may be selectively deactivated. When operating as cascades, the transistors reduce the Miller capacitance seen at the inputs of the comparator and also reduce the current kick back to the inputs from switching transistors, thereby improving the processing speed and sensitivity of the comparator.
  • current in the preamplifier stage may be mirrored, the mirrored current pre-loading the latch stage transistors with current, saving time so that when the rising edge of the latch enabling signal occurs, the latch stage already has started towards making a decision.
  • the present invention has fewer switching devices at the input of the circuit where it is critical to have quiet circuitry to avoid degrading the input signals.
  • the comparator of the present invention utilizes a technique novel to and optimized for current trip monitoring providing a faster decision circuit, allowing a reduction of the size of an inductor needed at the output of the DC-DC converter and allowing larger input-to-output voltage conversion ratio, when when the PH pulse becomes very narrow in width.
  • the present invention is smaller than conventional current limiting circuits with fewer switches and control signals, and has virtually infinite gain and very high sensitivity, even for small differential input voltage over drives.
  • FIG. 1A-1C are timing diagrams of a blanking time and pulse (PH) signal which control a conventional DC-DC switcher under different conditions;
  • FIG. 2A shows a prior art example of a continuous time high speed comparator
  • FIG. 2B shows a prior art conventional discreet time current comparator (U.S. Pat. No. 6,147,518);
  • FIG. 3 shows a block diagram of a conventional track and latch architecture adapted to be used in data converters
  • FIG. 4 is a detailed electrical schematic diagram of one preferred embodiment of the present invention comprising a track and latch decision circuit having an individually controllable preamplifier and latch stage;
  • FIG. 5 is a timing diagram for controlling the comparator of the present invention using multiple clock signals.
  • the present invention comprises an improved “track and latch” decision circuit providing over-current monitoring, whereby the preamplifier and the latch stage are advantageously independently controlled, with one preferred embodiment of the invention shown as a comparator circuit 30 in FIG. 4 .
  • Comparator 30 has two voltage inputs, inp and inn, input to the comparator's preamplifier stage 32 operating as a first stage.
  • One input is formed from the current sensing element, and the other input represents the reference current trip point threshold voltage.
  • a differential current mirror OTA comprising transistors Q 1 -Q 8 along with a current source bias, is used in the preamplifier stage 32 of a comparator 30 to magnify the difference between the inputs inn and inp.
  • Diode connected load transistors Q 5 , Q 6 are in saturation and keep the node voltage at the drain of the input transistors, Q 1 and Q 2 , of the first stage 32 fairly stationary, allowing high speed operation to the second latch stage 34 .
  • Parallel to the load transistors, Q 5 and Q 6 are another set of transistors, Q 5 a and Q 6 a , which may be used to selectively disable the preamplifier 32 if transistors Q 5 a and Q 6 a are turned ON starting on the rising edge of clock T 1 .
  • the advantage of selectively disabling the first stage 32 when the second latch stage 34 is making its decision is to avoid noise and input disturbances from affecting the latch stage 34 . Also, this selective disabling feature speeds up the signal processing of the latch stage 34 and allows the overall comparator 30 to work in parallel with other circuits.
  • the latch stage 34 can make its decision later, regardless of any further activity at the inputs of the comparator 30 .
  • the preamplifier 32 need not be disabled, and transistors Q 5 a and Q 6 a need not be used as switches. This depends on the system algorithm used to detect over current conditions, and whether it is better to disengage the first stage 32 when the latch stage 34 regenerates and makes its decision. If not used as switches, transistors Q 5 a and Q 6 a may advantageously be biased to increase the gain of the preamplifier 32 by sourcing additional current from the supply AVDD.
  • Two optional transistors Q 3 and Q 4 are provided in the first stage 32 which may be used as cascodes, or deactivated by tying their gates HI via input line bias 1 .
  • these transistors reduce the Miller capacitance seen at the inputs and also the kickback to the inputs from the switching transistors Q 5 a and Q 6 a , thereby improving the processing speed and sensitivity of comparator 30 .
  • the cascode transistors may limit the common mode input voltage range, but a large common mode range is generally not an issue in over current monitoring; so, it's typically better to have the cascode transistors.
  • the legs transistors Q 9 and Q 10 , of the latch stage 34 are used simultaneously as pull downs for the mirror opamp transistors Q 7 and Q 8 , and also as part of the regenerative latch stage 34 itself. These legs are pre-loaded with currents from the transistors Q 7 and Q 8 of the preamplifier stage, again saving time, so that when the rising edges of the clocks T 2 and T 3 occur, the latch stage 34 already has started towards making a decision.
  • both the upper transistor Q 11 is ON, and the left and right inverter pairs of the latch are released and no longer shorted together by Q 11 , then the latch stage 34 can flip and make a decision.
  • the rising edge of the clock T 2 activates the release of the latch stage 34 and essentially determines the decision time point.
  • the decision output of this latch stage 34 can then be buffered or sampled onto the next stage 40 or next circuit via output line 38 .
  • the optimal timing for when the various clock edges T 1 , T 2 , T 3 occur depends on the type of switching regulator, the system algorithm used for over current monitoring, and also on the power saving needs or over-drive sensitivity needs of the comparator 30 .
  • the clock edges may be the initial/trailing edge of the PH control pulse, the end of the blanking time, or some subsequent time, as shown in FIG. 1A-1C .
  • clock T 1 should precede clocks T 2 and T 3 , if the algorithm calls for disabling the preamp stage 32 .
  • clock T 1 may be the same as clock T 2 . See FIG. 5 for one embodiment of the various timing diagrams for clocks T 1 , T 2 , and T 3 .
  • the present invention is a track and latch (“discrete” time) circuit instead of the continuous time method usually used. It is also different from the discrete time approach shown in FIG. 2 b which takes in current directly, rather than voltage and has many switches and multiple timing controls. In many applications, the current to be sensed is too large to be processed by small circuit elements without destroying them, it is easier to take in voltage signals rather than currents.
  • the present invention avoids clock kickback issues, and has fewer switching devices at the input of the circuit where it is critical to have “quiet” circuitry to avoid degrading the input signals.
  • the gain improvement transistors Q 5 A and Q 6 A, and cascode transistors Q 3 and Q 4 technique help improve sensitivity over prior art of FIG. 2B .
  • the over current trip circuit part of a switching voltage regulator is generally the circuit which limits the speed at which the regulator can operate. This occurs when the PH pulse is very narrow, when the flat portion of PH is ON for only a short time duration. For example, it a DC-DC converter is made to switch faster to reduce the inductor size and cost. Or if the switching regulator is operated to allow for a large input-to-output conversion ratio. The time interval during which the over current monitoring is engaged becomes nearly non-existent due to circuit ringing and settling time issues.
  • the track and latch comparator circuit 30 of the present invention, along with being fast and yet maintaining high gain is edge triggered and able to overcome the short time interval limitation problems.
  • the comparator 30 for over-current is also quite small, saving die area and cost and has virtually infinite gain and very high sensitivity, good even for small differential input voltage overdrives. Furthermore, the circuit is small enough for two of them to exist, to enhance the system algorithm to monitor over current problems, or even to open up possibilities to new system algorithms.
  • the comparator 30 is differential and thus very balanced from input to output; so, it won't have much of an offset due to an imbalanced architecture. For example, if folded-cascoded amplifiers are instead used for comparators like in some of the present products, making such architectures fully differential consumes die area; however, if they are not fully differential, offsets occur. Offsets that vary with input voltage or temperature disadvantageously lead to a varying comparator trip point.

Abstract

The present invention achieves technical advantages as a current monitoring circuit for DC-DC switching converters, including a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). Advantageously, the comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.

Description

    FIELD OF THE INVENTION
  • The present invention is generally related to DC-DC switching converters, and more particularly to current monitoring of these converters.
  • BACKGROUND OF THE INVENTION
  • Current monitoring and overcurrent trip circuits are typically used in high current voltage regulation IC's, including DC-DC switching converters. These circuits protect the IC, and/or the other circuits to which the regulator is supplying current, in applications such as computers, communications, and industrial machinery. Without over current monitoring, both the switching regulator itself and the circuits powered by the regulator may overheat and collapse when there is too much current being supplied to the load.
  • In a conventional DC-DC converter, a switching transistor (switcher) is turned ON to pass a noisy input voltage to the output as a quiet, well regulated output voltage that is sourcing a large current. This current may be monitored a number of ways. A typical current monitor circuit has a current sensing element which provides an associated voltage signal that is sent to a comparator stage to decide whether the voltage signal is higher than some reference (voltage) value that is representative of an over-current threshold. The comparison is often made only after a certain time interval that allows signals to settle, known as the blanking time interval.
  • FIG. 1 shows a typical timing diagram for the blanking time and a pulse (PH) which controls a conventional DC-DC switcher, turning it on and off to pass or restrict current to the load. There are several cases, 1A-1C. FIG. 1A with a long PH (switcher ON) time interval case allows the current limit circuit much time after the blanking period, to operate and make a decision. However, cases 1B and 1C give the current limiting circuit very little time to operate and make a decision. This circumstance occurs when the switching cycle is very fast, and the switcher is ON only briefly.
  • FIG. 2 a shows a prior art example of a “continuous time” high speed comparator that may be used as part of a current limiting circuit, similar to those used in many Texas Instruments DC-DC converter products.
  • FIG. 2 b shows a discrete time current comparator, such as described in U.S. Pat. No. 6,147,518, that switches currents. The decision is made on the edge of an enable control signal.
  • FIG. 3 shows a block diagram of a conventional “track and latch” comparator architecture adapted to be used in data converters. A preamplifier is selectively enabled by a clock signal, and its output “tracks” the input while the second latch stage is simultaneous disabled and is controlled by the same clock signal. During the latch mode, starting at the rising edge of the clock signal, the latch stage is enabled and regeneratively amplifies the output of the preamplifier with essentially infinite gain, producing and holding the output logic decision.
  • SUMMARY OF THE INVENTION
  • The present invention achieves technical advantages as a current monitoring circuit for DC-DC switching converters, including a track and latch comparator circuit having a preamplifier that is controllable independently of a latch circuit. Advantageously, the preamplifier circuit can be disabled when the latch stage is making its decision, such as to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature also speeds up the signal processing of the overall comparator, and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.
  • Alternatively, the preamplifier need not be disabled while the latch is enabled, depending on the system algorithm used to detect over-current conditions. In some situations, it may be better to not disengage the preamplifier stage when the latch stage regenerates and makes its decision. For example, the transistors in the preamplifier may be selectively biased to increase the gain of the preamplifier.
  • The preamplifier includes transistors that may be configured as cascades, but which also may be selectively deactivated. When operating as cascades, the transistors reduce the Miller capacitance seen at the inputs of the comparator and also reduce the current kick back to the inputs from switching transistors, thereby improving the processing speed and sensitivity of the comparator.
  • Advantageously, current in the preamplifier stage may be mirrored, the mirrored current pre-loading the latch stage transistors with current, saving time so that when the rising edge of the latch enabling signal occurs, the latch stage already has started towards making a decision.
  • The present invention has fewer switching devices at the input of the circuit where it is critical to have quiet circuitry to avoid degrading the input signals. The comparator of the present invention utilizes a technique novel to and optimized for current trip monitoring providing a faster decision circuit, allowing a reduction of the size of an inductor needed at the output of the DC-DC converter and allowing larger input-to-output voltage conversion ratio, when when the PH pulse becomes very narrow in width. The present invention is smaller than conventional current limiting circuits with fewer switches and control signals, and has virtually infinite gain and very high sensitivity, even for small differential input voltage over drives.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A-1C are timing diagrams of a blanking time and pulse (PH) signal which control a conventional DC-DC switcher under different conditions;
  • FIG. 2A shows a prior art example of a continuous time high speed comparator;
  • FIG. 2B shows a prior art conventional discreet time current comparator (U.S. Pat. No. 6,147,518);
  • FIG. 3 shows a block diagram of a conventional track and latch architecture adapted to be used in data converters;
  • FIG. 4 is a detailed electrical schematic diagram of one preferred embodiment of the present invention comprising a track and latch decision circuit having an individually controllable preamplifier and latch stage; and
  • FIG. 5 is a timing diagram for controlling the comparator of the present invention using multiple clock signals.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The present invention comprises an improved “track and latch” decision circuit providing over-current monitoring, whereby the preamplifier and the latch stage are advantageously independently controlled, with one preferred embodiment of the invention shown as a comparator circuit 30 in FIG. 4.
  • Comparator 30 has two voltage inputs, inp and inn, input to the comparator's preamplifier stage 32 operating as a first stage. One input is formed from the current sensing element, and the other input represents the reference current trip point threshold voltage. A differential current mirror OTA, comprising transistors Q1-Q8 along with a current source bias, is used in the preamplifier stage 32 of a comparator 30 to magnify the difference between the inputs inn and inp. Diode connected load transistors Q5, Q6 are in saturation and keep the node voltage at the drain of the input transistors, Q1 and Q2, of the first stage 32 fairly stationary, allowing high speed operation to the second latch stage 34.
  • Parallel to the load transistors, Q5 and Q6, are another set of transistors, Q5 a and Q6 a, which may be used to selectively disable the preamplifier 32 if transistors Q5 a and Q6 a are turned ON starting on the rising edge of clock T1. The advantage of selectively disabling the first stage 32 when the second latch stage 34 is making its decision is to avoid noise and input disturbances from affecting the latch stage 34. Also, this selective disabling feature speeds up the signal processing of the latch stage 34 and allows the overall comparator 30 to work in parallel with other circuits. The latch stage 34 can make its decision later, regardless of any further activity at the inputs of the comparator 30.
  • Alternatively, the preamplifier 32 need not be disabled, and transistors Q5 a and Q6 a need not be used as switches. This depends on the system algorithm used to detect over current conditions, and whether it is better to disengage the first stage 32 when the latch stage 34 regenerates and makes its decision. If not used as switches, transistors Q5 a and Q6 a may advantageously be biased to increase the gain of the preamplifier 32 by sourcing additional current from the supply AVDD.
  • Two optional transistors Q3 and Q4 are provided in the first stage 32 which may be used as cascodes, or deactivated by tying their gates HI via input line bias 1. As cascodes, these transistors reduce the Miller capacitance seen at the inputs and also the kickback to the inputs from the switching transistors Q5 a and Q6 a, thereby improving the processing speed and sensitivity of comparator 30. The cascode transistors may limit the common mode input voltage range, but a large common mode range is generally not an issue in over current monitoring; so, it's typically better to have the cascode transistors.
  • The legs transistors Q9 and Q10, of the latch stage 34, are used simultaneously as pull downs for the mirror opamp transistors Q7 and Q8, and also as part of the regenerative latch stage 34 itself. These legs are pre-loaded with currents from the transistors Q7 and Q8 of the preamplifier stage, again saving time, so that when the rising edges of the clocks T2 and T3 occur, the latch stage 34 already has started towards making a decision. When both the upper transistor Q11 is ON, and the left and right inverter pairs of the latch are released and no longer shorted together by Q11, then the latch stage 34 can flip and make a decision. The rising edge of the clock T2 activates the release of the latch stage 34 and essentially determines the decision time point. The decision output of this latch stage 34 can then be buffered or sampled onto the next stage 40 or next circuit via output line 38.
  • The optimal timing for when the various clock edges T1, T2, T3 occur depends on the type of switching regulator, the system algorithm used for over current monitoring, and also on the power saving needs or over-drive sensitivity needs of the comparator 30. For example, the clock edges may be the initial/trailing edge of the PH control pulse, the end of the blanking time, or some subsequent time, as shown in FIG. 1A-1C. When implemented, clock T1 should precede clocks T2 and T3, if the algorithm calls for disabling the preamp stage 32. For simplicity, clock T1 may be the same as clock T2. See FIG. 5 for one embodiment of the various timing diagrams for clocks T1, T2, and T3.
  • Advantageously, the present invention is a track and latch (“discrete” time) circuit instead of the continuous time method usually used. It is also different from the discrete time approach shown in FIG. 2 b which takes in current directly, rather than voltage and has many switches and multiple timing controls. In many applications, the current to be sensed is too large to be processed by small circuit elements without destroying them, it is easier to take in voltage signals rather than currents. The present invention avoids clock kickback issues, and has fewer switching devices at the input of the circuit where it is critical to have “quiet” circuitry to avoid degrading the input signals. The gain improvement transistors Q5A and Q6A, and cascode transistors Q3 and Q4, technique help improve sensitivity over prior art of FIG. 2B.
  • The over current trip circuit part of a switching voltage regulator (DC-DC converter) is generally the circuit which limits the speed at which the regulator can operate. This occurs when the PH pulse is very narrow, when the flat portion of PH is ON for only a short time duration. For example, it a DC-DC converter is made to switch faster to reduce the inductor size and cost. Or if the switching regulator is operated to allow for a large input-to-output conversion ratio. The time interval during which the over current monitoring is engaged becomes nearly non-existent due to circuit ringing and settling time issues. The track and latch comparator circuit 30 of the present invention, along with being fast and yet maintaining high gain is edge triggered and able to overcome the short time interval limitation problems.
  • The comparator 30 for over-current is also quite small, saving die area and cost and has virtually infinite gain and very high sensitivity, good even for small differential input voltage overdrives. Furthermore, the circuit is small enough for two of them to exist, to enhance the system algorithm to monitor over current problems, or even to open up possibilities to new system algorithms.
  • The comparator 30 is differential and thus very balanced from input to output; so, it won't have much of an offset due to an imbalanced architecture. For example, if folded-cascoded amplifiers are instead used for comparators like in some of the present products, making such architectures fully differential consumes die area; however, if they are not fully differential, offsets occur. Offsets that vary with input voltage or temperature disadvantageously lead to a varying comparator trip point.
  • First, monitoring the average value of the current for the purpose of aiding voltage regulation, instead of overcurrent checking, or second, normalizing the over current trip point are additional possibilities with two comparators of the present invention. For the second application, normally, it is very difficult to set an accurate trip point, one that is fairly constant. Two such small and fast comparators, may be used to calibrate/normalize the trip point.
  • All of these attributes of the present invention greatly enhances overall performance.
  • Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.
  • One skilled in the art will recognize that the presented embodiments can be readily changed to use another polarity for example. Instead of N-type transistor inputs, P-type transistors may be used, and the subsequent polarity and timing control of the other transistors revised accordingly, pull-up transistors instead of pull-down, and so on. Also, instead of CMOS, bipolar or biCMOS processes may be used.

Claims (17)

1. A comparator adapted to provide over-current monitoring, comprising:
a preamplifier stage having a first input adapted to receive and track a current sensing parameter, a second input adapted to receive a reference current trip point threshold parameter, and generating an output tracking the current sensing parameter as a function of a first control signal; and
a latch stage receiving the output and adapted to be selectively enabled by a second control signal.
2. The comparator as specified in claim 1 wherein the latch stage is adapted to selectively latch the preamplifier stage output.
3. The comparator as specified in claim 2 wherein the latch stage has nearly an infinite gain when the latch stage is regenerating.
4. The comparator as specified in claim 1 wherein the preamplifier stage is adapted to be selectively disabled.
5. The comparator as specified in claim 4 wherein the preamplifier stage is adapted to be selectively disabled when the latch stage is enabled.
6. The comparator as specified in claim 4 wherein the preamplifier stage further comprises transistors adapted to be selectively enabled to source additional current when enabled.
7. The comparator as specified in claim 1 wherein the preamplifier further comprises transistors mirroring current to the latch stage.
8. The comparator as specified in claim 7 wherein the latch stage further includes receiving transistors coupled to the current mirroring transistors of the preamplifier stage.
9. The comparator as specified in claim 8 wherein the receiving transistors are pre-charged with current from the preamplifier stage.
10. The comparator as specified in claim 9 wherein the latch stage is a regenerative latch.
11. A method of operating a current sensing comparator having a preamplifier and a latch responsively coupled to the preamplifier, comprising the steps of:
selectively disabling the latch independently of the preamplifier receiving and tracking a parameter indicative of a sensed current.
12. The method as specified in claim 11 further comprising the step of selectively disabling the preamplifier independently of the latch.
13. The method as specified in claim 11 further comprising the step of selectively pre-charging the latch prior to enabling the latch.
14. The method as specified in claim 11 further comprising the step of mirroring current of the preamplifier to the latch.
15. The method as specified in claim 14 wherein the latch has current receiving transistors coupled to the mirrored current.
16. The method as specified in claim 11 wherein the latch is a regenerative latch.
17. The method as specified in claim 11 wherein the latch is selectively disabled as a function of a blacking time interval.
US10/838,099 2004-05-03 2004-05-03 Efficient current monitoring for DC-DC converters Abandoned US20050242845A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/838,099 US20050242845A1 (en) 2004-05-03 2004-05-03 Efficient current monitoring for DC-DC converters
US11/470,130 US7372307B1 (en) 2004-05-03 2006-09-05 Efficient current monitoring for DC-DC converters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/838,099 US20050242845A1 (en) 2004-05-03 2004-05-03 Efficient current monitoring for DC-DC converters

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/470,130 Continuation US7372307B1 (en) 2004-05-03 2006-09-05 Efficient current monitoring for DC-DC converters

Publications (1)

Publication Number Publication Date
US20050242845A1 true US20050242845A1 (en) 2005-11-03

Family

ID=35186449

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/838,099 Abandoned US20050242845A1 (en) 2004-05-03 2004-05-03 Efficient current monitoring for DC-DC converters
US11/470,130 Active US7372307B1 (en) 2004-05-03 2006-09-05 Efficient current monitoring for DC-DC converters

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/470,130 Active US7372307B1 (en) 2004-05-03 2006-09-05 Efficient current monitoring for DC-DC converters

Country Status (1)

Country Link
US (2) US20050242845A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120133395A1 (en) * 2010-11-30 2012-05-31 Ipgoal Microelectronics (Sichuan) Co., Ltd. High speed dynamic comparative latch
US20150280561A1 (en) * 2014-03-31 2015-10-01 Michael T. Berens Comparator for synchronous rectification and method of operation
CN109905105A (en) * 2019-02-18 2019-06-18 长沙理工大学 Low latency low-voltage current comparator and circuit module

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4342548B2 (en) * 2006-12-15 2009-10-14 Okiセミコンダクタ株式会社 Preamplifier latch comparator
TWI427301B (en) * 2010-10-19 2014-02-21 Himax Analogic Inc Dc-to-dc converter having test circuit
US8471749B2 (en) * 2011-07-18 2013-06-25 Freescale Semiconductor, Inc. Comparator
US11405030B1 (en) * 2021-08-19 2022-08-02 Texas Instruments Incorporated Cascode bias for comparator

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245223A (en) * 1992-03-17 1993-09-14 Hewlett-Packard Company CMOS latching comparator
US6008673A (en) * 1997-09-30 1999-12-28 Intel Corporation High speed, low power, current mode comparator
US6046612A (en) * 1998-07-27 2000-04-04 National Semiconductor Corporation Self-resetting comparator circuit and method
US6124732A (en) * 1998-07-15 2000-09-26 Lucent Technologies, Inc. Signaling voltage range discriminator
US6147518A (en) * 1997-10-01 2000-11-14 U.S. Philips Corporation Current comparator
US6396329B1 (en) * 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US6847234B2 (en) * 2000-12-07 2005-01-25 Hynix Semiconductor Inc. Comparison apparatus operated at a low voltage

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066944A (en) * 1999-02-18 2000-05-23 National Semiconductor Corporation High speed current mirror circuit and method
JP4075777B2 (en) * 2003-11-19 2008-04-16 沖電気工業株式会社 Comparator circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245223A (en) * 1992-03-17 1993-09-14 Hewlett-Packard Company CMOS latching comparator
US6008673A (en) * 1997-09-30 1999-12-28 Intel Corporation High speed, low power, current mode comparator
US6147518A (en) * 1997-10-01 2000-11-14 U.S. Philips Corporation Current comparator
US6124732A (en) * 1998-07-15 2000-09-26 Lucent Technologies, Inc. Signaling voltage range discriminator
US6046612A (en) * 1998-07-27 2000-04-04 National Semiconductor Corporation Self-resetting comparator circuit and method
US6396329B1 (en) * 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US6847234B2 (en) * 2000-12-07 2005-01-25 Hynix Semiconductor Inc. Comparison apparatus operated at a low voltage

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120133395A1 (en) * 2010-11-30 2012-05-31 Ipgoal Microelectronics (Sichuan) Co., Ltd. High speed dynamic comparative latch
US8339158B2 (en) * 2010-11-30 2012-12-25 Ipgoal Microelectronics (Sichuan) Co., Ltd. High speed dynamic comparative latch
US20150280561A1 (en) * 2014-03-31 2015-10-01 Michael T. Berens Comparator for synchronous rectification and method of operation
US9312768B2 (en) * 2014-03-31 2016-04-12 Freescale Semiconductor, Inc. Comparator for synchronous rectification and method of operation
CN109905105A (en) * 2019-02-18 2019-06-18 长沙理工大学 Low latency low-voltage current comparator and circuit module

Also Published As

Publication number Publication date
US7372307B1 (en) 2008-05-13

Similar Documents

Publication Publication Date Title
US7372307B1 (en) Efficient current monitoring for DC-DC converters
US7911237B2 (en) High speed comparator
US8284953B2 (en) Circuit and method of reducing pop-up noise in a digital amplifier
US7642852B2 (en) Resistor self-trim circuit for increased performance
US7319365B2 (en) Signal determining apparatus including amplifier circuit with variable response speed
EP0594305A1 (en) Comparator circuit
US20090273874A1 (en) Power switch circuit exhibiting over current and short circuit protection and method for limiting the output current thereof
US9501080B2 (en) Multiple output offset comparator
KR100725677B1 (en) Input-buffer of an integrated semiconductor-circuit
JP2000306385A (en) Complementary differential input buffer for semiconductor memory
US20090091388A1 (en) Apparatus for slew rate enhancement of an operational amplifier
US8044717B2 (en) Amplifier circuit and method therefor
US6522199B2 (en) Reconfigurable dual-mode multiple stage operational amplifiers
JP2004072700A (en) Slew rate increasing apparatus
US8395437B2 (en) Charge pump circuit and semiconductor integrated circuit
US7446606B2 (en) Methods and apparatus to provide slew enhancement for low power amplifiers
JP2003046347A (en) High output amplifier
JP2005027392A (en) High speed comparator and dc/dc converter using it
US7274218B2 (en) Integrated circuit
US7053681B2 (en) Comparator and method for amplifying an input signal
JP4189283B2 (en) Comparator that operates stably at low voltage
JPH1065274A (en) Driver for light-emitting element
JP2804678B2 (en) Photodetector
US7002392B2 (en) Converting signals from a low voltage domain to a high voltage domain
JP3381528B2 (en) Power amplifier

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WU, DOLLY Y.;REEL/FRAME:016042/0082

Effective date: 20040429

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION