US20050178741A1 - Method of etching porous dielectric - Google Patents

Method of etching porous dielectric Download PDF

Info

Publication number
US20050178741A1
US20050178741A1 US10/836,618 US83661804A US2005178741A1 US 20050178741 A1 US20050178741 A1 US 20050178741A1 US 83661804 A US83661804 A US 83661804A US 2005178741 A1 US2005178741 A1 US 2005178741A1
Authority
US
United States
Prior art keywords
method
etch
cf
film
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/836,618
Inventor
Joon Yeoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aviza Europe Ltd
Original Assignee
Aviza Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB0310238 priority Critical
Priority to GB0310238.1 priority
Priority to US46826303P priority
Application filed by Aviza Technology Inc filed Critical Aviza Technology Inc
Priority to US10/836,618 priority patent/US20050178741A1/en
Assigned to TRIKON TECHNOLOGIES LIMITED reassignment TRIKON TECHNOLOGIES LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YEOH, JOON CHAI
Publication of US20050178741A1 publication Critical patent/US20050178741A1/en
Assigned to AVIZA TECHNOLOGY LIMITED reassignment AVIZA TECHNOLOGY LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: TRIKON TECHNOLOGIES LIMITED
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Abstract

The present invention relates to methods of etching a porous dielectric. The method includes etching the film in a plasma etch chamber with CF4, H2 and a noble gas, wherein the CF4 to H2 gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • A claim of priority is made to U.S. provisional application Ser. No. 60/468,263, filed May 7, 2003, and to British patent application no. 0310238.1, filed May 3, 2003.
  • BACKGROUND OF THE INVENTION
  • The present invention relates to methods of etching a porous dielectric layer that forms part of an interconnect structure on a substrate such as a wafer or multi chip module. In particular, but not exclusively, it relates to a method of etching a porous dielectric layer forming part of a dual damascene structure. More particularly it relates to a method of etching the upper part of a dual damascene structure.
  • To reduce the RC product in interconnect layers there is a requirement to reduce the capacitive coupling between adjoining conductors. Low dielectric constant (k) materials are therefore desirable and it is known that a vacuum gap has the lowest k value of 1. A known method of reducing bulk insulators' k values is to introduce porosity such that there is a matrix material and voids, thereby reducing the k value to less than that of the matrix.
  • Such porous materials present numerous problems for integration into practical devices and an additional complexity is introduced by the requirement to make ever smaller structures. As yet no porous dielectrics have been successfully integrated into state of the art devices in volume manufacturing for public sale.
  • At e.g. the 65 nm technology node there is a potential integration scheme whereby the total thickness of the dual damascene dielectric is deposited without an etch stop layer within it. The trench is then etched for a timed period into the dielectric and the etching terminated part way through the thickness of the dielectric. Over and above all the well known desirable aspects of anisotropic etching there is an additional requirement that the base of the etched trench is smooth. If the dielectric is porous (i.e. containing voids) then this is clearly a challenge. If the voids are very small then stopping in the voided dielectric may be acceptable though some degree of ‘healing’ of these voids is also desirable.
  • The Applicants have developed a porous dielectric known as Orion™ as is described in various patent applications in the name of the Applicants, e.g. WO/03/009364. This material has a k value in the range of 1.8 to 2.6 and is under evaluation at this time for integration into 65 nm (and below 65 nm) design rule logic devices at a k value of 2.2 to 2.5. It is this material that has been etched in this invention, though the invention also relates to any porous carbon doped silicon dioxide low-k dielectric e.g. a SiCOH type material. Typically such carbon doped oxides have methyl groups contained within them. Carbon (and thereby hydrogen) concentrations may be varied, higher concentrations leading to porosity under certain circumstances.
  • It should be made clear that this application is not related to the etched sidewalls. It is well known that to achieve anisotropic (directional) etching polymer is deposited on sidewalls to protect them from chemical attack whilst bombardment of the etch front (base of trench) removes this protective layer enabling downward etching. After etching the photoresist and any remaining polymer is then removed.
  • It should also be understood that in almost all cases layers of material forming interconnect layers are completely etched through such that the etch process stops on an ‘etch stop’ layer or some other layer that etches more slowly in the etchant than the layer being etched. It is somewhat unusual to terminate an etch part way through a layer but elimination of a device etch-stop layer is highly desirable as it reduces the effective k value of the structure and reduces the number of interfaces between layers. The Applicants have found (in unpublished work) that, perhaps not surprisingly, when such a partial etch is performed on a porous dielectric then a rough trench base is formed. This can be seen in FIGS. 1 (a) and 1 (b).
  • FIG. 1 (a) and (b) show rough etch front on SEM images after partial etch using CF4 and CH2F2 gases, at 1250 W helicon source plasma power, 400 W platen (wafer) bias power, 2 mTorr, with wafer helium back pressure of 15 Torr (giving a wafer surface temperature of approximately 90-100° C. as indicated by temperature sensitive labels) in a MORI™ process chamber, as supplied by the Applicants.
  • FIG. 1 (a) shows a dual damascene structure. The etched porous oxide surface is at 1.
  • There is therefore a need for an improved etch process to provide a smooth base to an etched feature formed within a carbon doped silicon oxide type porous dielectric layer.
  • SUMMARY OF THE INVENTION
  • From one aspect the invention consists in a method of etching a porous carbon-doped silicon dioxide type dielectric film including plasma etching the film in a plasma etch chamber with CF4H2 and a noble gas, wherein the CF4 to H2 gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.
  • From another aspect the invention provides a method of plasma etching a porous dielectric layer of carbon doped silicon oxide material such as a SiCOH material with the following desirable characteristics: Characteristic Target result Etch depth 40-70% of film thickness Etch rate 200-500 nm/min Selectivity to photoresist Greater than 5:1 ARDE percentage less than 5% (Aspect Ratio Dependent Etch rate: the difference in etch rate in features of different aspect ratio) Side wall angle 90 degrees Micro-trenching none visible in an electron micrograph Roughness none visible in an electron micrograph when surface viewed in plan view or at 45° degree glancing angle (at minimum magnification of 20,000)
  • Although the invention has been defined above it includes any inventive combination of the features set out above or in the following description.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention may be performed in various ways and specific embodiments will now be described with reference to the accompanying drawings:
  • FIGS. 1(a) and (b), are SEM images of an etch front and partial etch using CF4 and CH2F2 gases;
  • FIGS. 2(a), (b) and (c) illustrate similar etch fronts using CF4 and H2 with increasing amounts of argon present;
  • FIG. 3(a)a shows the etch front resulting from a non optimised process, whilst FIG. 3(b) illustrates the effect of a partial oxygen based resist step on the material of 3 (a);
  • FIGS. 4(a), (b) and (c) illustrate the effect of reducing amounts of backside cooling whilst FIGS. 5(a) and 5(b) are similar SEM's for a specified set of process conditions;
  • FIGS. 6(a) and (b) illustrate the results of the process using reduced cooling for particular process conditions and can be compared with FIG. 7 where the same process was run, but with increased cooling; and
  • FIGS. 8(a) and (b) show the etch front surfaces before and after resist etch has taken place.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Whilst a rough etch front 1(a) and (b) exhibited in FIG. 5 might be thought of as an obvious consequence of the film's porosity, it was observed that the surface roughness was greater than the mean pore size of 1-4 nm. This therefore suggested that the roughness of the etch front was not simply the result of exposure of pores and it was therefore postulated that an improved etch process could yield a smoother etch front/base of trench.
  • Initially the Applicants determined that noble gas additions, such as argon improved the smoothness of the etch front as illustrated in FIGS. 2, a, b and c.
  • Each of the processes illustrated in FIG. 2 was carried out in the MORI™ chamber referred to above with the chamber pressure being 110 mT, the plasma power 700 w applied to the wafer platen only and wafer helium backside pressure of 15 T (i.e. the water temperature was approximately 90-100° C.).
  • The gas flow rates, in seem, for the samples illustrated in FIGS. 2(a), (b) and (c) respectively were as follows: CF4 80 60 60 H2 30 30 30 Ar 0 90 120
  • At 1 can be seen the etch front/base surface of the porous oxide where a) is no argon additions, b) has argon added, and c) has the most argon added to a reactive ion etch process of CF4+H2. It will be seen that the addition of argon results in a smoother etch front 1, with that of 2(c) being the smoothest. This is contrary to expectation, as it would be anticipated that increasing the physical sputter etch component by adding a heavy noble gas would increase roughness of etch front of a material of non-uniform density.
  • The process of FIG. 2 c is still not acceptable and shows for example pronounced microtrenching at 2.
  • It will be noted that in all cases the Applicants had selected a CF4 and H2 mix, rather than the more usual CF4/O2 for the etch gas for the following reasons.
  • CF4 is a well known and readily available fluorine source and can etch with lower wafer bias power levels than other well known fluorine containing etch gasses because of its low polymer generation. Whilst silicon dioxide films are generally etched in a CF4+Oxygen gas mix it was determined that oxygen should be excluded from the etch process, because the Applicants anticipated that there may be methyl groups formed in the film, which would be stripped from the film by O2.
  • Hydrogen was then selected as an additional process gas on the basis of its ability to scavenge fluorine and increase selectivity by depressing the etch rate of silicon compared to silicon dioxide or carbide. Hydrogen plasma is known to cure or treat low-k materials from Applicants GB-A-0020 509. Increasing levels of hydrogen are known to have only a limited effect on silicon dioxide etch rate and to increase polymerization. Therefore the plasma would provide hydrogen radicals from hydrogen gas directly, rather than from CH2F2 gas.
  • Argon was selected as a heavy noble gas (others may have been selected, such as krypton or xenon) because of its ability to increase ionization efficiency.
  • Considerable DOE (Design of Experiment) experimentation was then performed yielding the conclusions that a CF4:H2 ratio of 2:1 was the best for this application, and a range of CF4 to H2 gas flow ratios of between 1.33:1 and 2.7:1 were acceptable.
  • This is an unusually high hydrogen concentration. It is generally held that in a CF4+Hydrogen gas mix, the etch rate of both silicon dioxide and silicon falls to about zero at about 40% hydrogen in the CF4+H2 gas mix due to the level of polymerization.
  • It was further discovered that for the CF4 and H2 flows rates being used, the argon flow should be at least 90 sccm and preferably about 77 percent of total gas flow. In a process of 80 sccm CF4 and 40 sccm of hydrogen, then argon gas flow was preferably 400 sccm and at least 90 sccm.
  • A further non-optimized process is shown at FIG. 3 a. At 1 the etch front can be seen and shows some surface roughness e.g. at 4 and micro trenching e.g. at 2 after etch completion into approximately 80 percent of Orion porous SICOH material with a k value of 2.2. ARDE is less than 2% (0.25 nanometres /1.25 micron structures), selectivity to photoresist 3 is greater than 6:1 and the etch rate is greater than 300 nm/min. The same structure as at FIG. 3 a was then subjected to a partial oxygen based resist strip and the results are shown at FIG. 3 b. As can be seen there is severe roughening of the etched base of the trench.
  • It has been discovered that to further improve etch results stopping within the thickness of the porous carbon-doped oxide then two further variations are necessary. Firstly, the porous SICOH material should have small pores with tightly controlled distribution. A material with average pore sizes in the range 1-4 nm etches more smoothly that a porous dielectric with a larger average pore size e.g. 4-5 nm and pores ranging in size from 2 nm-12 nm. It has also been found that the wafer temperature during etching has an effect on the surface roughness of the etch front.
  • Higher wafer temperatures yield smoother etch fronts. However, the maximum temperature is limited by photoresist reticulation.
  • It is notoriously difficult to specify the temperature of a film during an etch (or deposition) process as it is practically impossible to measure. Attempts at estimation may be made using temperature indicating stickers or ‘Sensarray™’ wafers with embedded thermocouples, but these are only approximations. It has however been noted that reducing the pressure of helium to the backside of the electrostatically clamped wafer (thereby reducing the thermal coupling of the wafer to the chilled electrostatic chuck) improved etch front smoothness as illustrated in FIGS. 4 a and b. These are submicron structures etched to 86% of the Orion film thickness both with the electrostatic chuck coolant set to −15° C. At FIG. 4 a is the etch result with 15 torr of helium pressure (sufficient to thermally couple the wafer to the chuck with a small thermal gradient) and in the case of FIG. 4 b the helium pressure is 2 torr. As can be seen the etch front 1 at FIG. 4 b is smoother than at FIG. 4 a.
  • Temperature sensing stickers on the face of a wafer indicate a wafer surface temperature of 93-99° C. for 15 torr pressure, −15° C. coolant temperature, and 143-149° C. for 2 torr helium backpressure and −15° C. coolant temperature.
  • An acceptable wafer surface temperature for the process of this invention is therefore estimated as above 100° C., preferably within the range 130° C. to 220° C., more preferably between 130-170° C. and most preferably about 150° C. (the upper temperature limited by the photoresist, higher temperatures being otherwise at least potentially equally preferable).
  • Minimum preferred pressure for the process is 80 mTorr. FIG. 5 (a) and (b) show the onset of etch front 1 surface roughness 4, for gas flows of 70 sccm CF4, 30 sccm H2, 90 sccm Ar, 700 W, with a wafer helium back pressure of 15 T (wafer ‘cold’).
  • FIG. 6 (a) and (b) show smooth etch front 1 after etching at higher wafer surface temperature (130° to 170° C.). This is achieved by reducing the Helium back pressure to 2 Torr, thereby lowering the thermal coupling of platen to wafer. The process conditions where otherwise revise CF4—84 sccm; H2—42 sccm; Ar—400 sccm; pressure 200 ml and power 1000 W.
  • FIG. 7 shows rougher etch fronts after processing at lower wafer surface temperature (−10 to +99° C.), when Helium back pressure is 15 Torr. Here the process conditions where essentially identical to those for FIG. 6 with slight variations in the CF4 and H2 flow rates being 82.55 sccm and 37.5 sccm respectively.
  • In order to prove that smooth etch front surface of the invention is not due to polymer residues covering the etch front/base, a N2+H2 plasma strip was used to remove the photoresist post-etch. FIG. 8 (a) shows the smooth etch front 1 and photoresist 3 in place after hot etch. Figure 8 (b) shows the equally smooth etch front surface 1 after N2+H2 plasma strip to remove the photoresist. There is no visible polymer residue remaining.
  • The first order major responses of each individual factor can thus be summarized below. etch front increasing smoothness μ-trenching ARDE side wall angle CF4/H2 Ar Flow pressure power temperature
  • Best known process conditions to partially etch a porous SICOH type dielectric to leave a smooth etch front are therefore: Etch gasses: 80 sccm CF4, 40 sccm H2, 400 sccm Ar, 5% variation in CF4 and H2 would yield similar result, so long as the CF4:H2 ratio is kept at about 2:1. Etch process pressure: 200 mTorr, Plasma power:1000 W: 13.56 MHz applied to the wafer plate (RIE) (Power needs to be increased as pressure increases to avoid “wafer lens effect”) wafer surface temp.: 100 to 170° C. (e.g. by adjusting platen temperature and/or Helium wafer back pressure thermal coupling)

Claims (11)

1. A method of etching a porous carbon-doped silicon dioxide type dielectric film including plasma etching the film in a plasma etch chamber with CF4, H2 and a noble gas, wherein the CF4 to H2 gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.
2. A method as claimed in claim 1 wherein the CF4:H2 ratio is about 2:1.
3. A method as claimed in claim 1 wherein the noble gas is argon.
4. A method as claimed in claim 3 wherein argon is present at up to about 77% of the total gas flow to the plasma etch chamber.
5. A method as claimed in claim 1 wherein film temperature is in the range of 100° C. and 170° C.
6. A method as claimed in claim 1 wherein the chamber pressure is in the range 90 mT to 300 mT.
7. A method as claimed in claim 1 wherein the power supplied to the plasma is between 700 and 1000 Watts.
8. A method as claimed in claim 1 wherein the etch is terminated within the film.
9. A method as claimed in claim 8 wherein the film is within an interconnect structure.
10. A method as claimed in claim 1 wherein the plasma etch is forming an interconnect structure or other relevant structure in the film.
11. A device incorporating a film as etched by the method of claim 1.
US10/836,618 2003-05-03 2004-05-03 Method of etching porous dielectric Abandoned US20050178741A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0310238 2003-05-03
GB0310238.1 2003-05-03
US46826303P true 2003-05-07 2003-05-07
US10/836,618 US20050178741A1 (en) 2003-05-03 2004-05-03 Method of etching porous dielectric

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/836,618 US20050178741A1 (en) 2003-05-03 2004-05-03 Method of etching porous dielectric

Publications (1)

Publication Number Publication Date
US20050178741A1 true US20050178741A1 (en) 2005-08-18

Family

ID=34841429

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/836,618 Abandoned US20050178741A1 (en) 2003-05-03 2004-05-03 Method of etching porous dielectric

Country Status (1)

Country Link
US (1) US20050178741A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2148360A1 (en) * 2007-05-14 2010-01-27 Ulvac, Inc. Dry etching method
US20120205814A1 (en) * 2011-02-16 2012-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric protection layer as a chemical-mechanical polishing stop layer
US9330989B2 (en) 2012-09-28 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for chemical-mechanical planarization of a metal layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411923B1 (en) * 1998-04-30 2002-06-25 Fisher-Rosemount Systems, Inc. Topology analysis tool for use in analyzing a process control network design
US6511923B1 (en) * 2000-05-19 2003-01-28 Applied Materials, Inc. Deposition of stable dielectric films
US20030232504A1 (en) * 2002-06-14 2003-12-18 Aaron Eppler Process for etching dielectric films with improved resist and/or etch profile characteristics
US20040121586A1 (en) * 2002-12-23 2004-06-24 Abell Thomas Joseph Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411923B1 (en) * 1998-04-30 2002-06-25 Fisher-Rosemount Systems, Inc. Topology analysis tool for use in analyzing a process control network design
US6511923B1 (en) * 2000-05-19 2003-01-28 Applied Materials, Inc. Deposition of stable dielectric films
US20030232504A1 (en) * 2002-06-14 2003-12-18 Aaron Eppler Process for etching dielectric films with improved resist and/or etch profile characteristics
US20040121586A1 (en) * 2002-12-23 2004-06-24 Abell Thomas Joseph Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2148360A1 (en) * 2007-05-14 2010-01-27 Ulvac, Inc. Dry etching method
US20100133233A1 (en) * 2007-05-14 2010-06-03 Yasuhiro Morikawa Dry etching method
EP2148360A4 (en) * 2007-05-14 2010-07-21 Ulvac Inc Dry etching method
US20120205814A1 (en) * 2011-02-16 2012-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric protection layer as a chemical-mechanical polishing stop layer
US8889544B2 (en) * 2011-02-16 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric protection layer as a chemical-mechanical polishing stop layer
US9330989B2 (en) 2012-09-28 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for chemical-mechanical planarization of a metal layer

Similar Documents

Publication Publication Date Title
KR100887911B1 (en) Use of ammonia for etching organic low-k dielectrics
US6794290B1 (en) Method of chemical modification of structure topography
US10186428B2 (en) Removal methods for high aspect ratio structures
KR101191699B1 (en) Dual doped polysilicon and silicon germanium etch
US6617257B2 (en) Method of plasma etching organic antireflective coating
US6362109B1 (en) Oxide/nitride etching having high selectivity to photoresist
US6207583B1 (en) Photoresist ashing process for organic and inorganic polymer dielectric materials
EP1042796B1 (en) Improved techniques for etching an oxide layer
EP0880799B1 (en) Methods for etching semiconductor wafers
Armacost et al. Plasma-etching processes for ULSI semiconductor circuits
US6867125B2 (en) Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
US6620733B2 (en) Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics
EP0908936B1 (en) Formation of a bottle shaped trench
US6440863B1 (en) Plasma etch method for forming patterned oxygen containing plasma etchable layer
JP4579611B2 (en) Dry etching method
US5256245A (en) Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
CN1524287B (en) Unique process chemistry for etching organic low-K materials
US20050051864A1 (en) Control of air gap position in a dielectric layer
US6284666B1 (en) Method of reducing RIE lag for deep trench silicon etching
JP3574680B2 (en) Plasma etching using xenon
JP5019748B2 (en) How to improve plasma etching performance
US5888309A (en) Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6090717A (en) High density plasma etching of metallization layer using chlorine and nitrogen
TWI352387B (en) Etch methods to form anisotropic features for high
US20020177322A1 (en) Method of plasma etching of silicon carbide

Legal Events

Date Code Title Description
AS Assignment

Owner name: TRIKON TECHNOLOGIES LIMITED, UNITED KINGDOM

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YEOH, JOON CHAI;REEL/FRAME:015742/0447

Effective date: 20040329

AS Assignment

Owner name: AVIZA TECHNOLOGY LIMITED, UNITED KINGDOM

Free format text: CHANGE OF NAME;ASSIGNOR:TRIKON TECHNOLOGIES LIMITED;REEL/FRAME:018972/0945

Effective date: 20051202

Owner name: AVIZA TECHNOLOGY LIMITED,UNITED KINGDOM

Free format text: CHANGE OF NAME;ASSIGNOR:TRIKON TECHNOLOGIES LIMITED;REEL/FRAME:018972/0945

Effective date: 20051202

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION