US20050140688A1 - Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems - Google Patents

Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems Download PDF

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US20050140688A1
US20050140688A1 US10747966 US74796603A US2005140688A1 US 20050140688 A1 US20050140688 A1 US 20050140688A1 US 10747966 US10747966 US 10747966 US 74796603 A US74796603 A US 74796603A US 2005140688 A1 US2005140688 A1 US 2005140688A1
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texture
plurality
register
registers
data
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Kim Pallister
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Intel Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/005General purpose rendering architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/04Texture mapping

Abstract

A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The embodiments of the invention relate to computer graphics. More specifically, embodiments of the invention relate to processing of texture map data.
  • 2. Background
  • Graphics applications, and particularly three dimensionally (3D) graphic applications have long been one of the most processing intensive activities performed by personal computers. To improve graphic processing capabilities, graphics co-processors have proliferated and are widely available on most modern day personal computers. Graphic coprocessors are specialized integrated circuits designed to quickly perform processing intensive tasks required by graphic applications.
  • The transformation of scene information (source data) into 3D images (display output) requires a number of operations. These operations in aggregate are referred to as a 3D graphics rendering pipeline. The operations performed by the pipeline can be grouped into certain fundamental functionalities. One of these functionalities is texture mapping. Texture mapping is a process in which the one, two or three dimensional image representing an object surface properties (such as appearance, reflectivity, or other such properties) is applied to a three dimensional mesh representing the object in a final rendering. While a two dimensional image is most commonly used, other dimensionalities are possible.
  • It is frequently the case when a texture image is applied to an object in a final rendering, there is disparity between a number of sample texture elements (texels) and the source texture image and the number of picture elements (pixels) to which the image is mapped. When the number of texels in a given range is less than the number of pixels, then the texture is required to be upsampled. When upsampling a texture, a scheme must be used to fill intermediate values. This scheme is referred to herein as “texture filtering” and has largely been performed by a fixed function state machine. Most current graphic coprocessor support four types of texture filtering; point sampling, bilinear filtering, trilinear filtering and anisotropic filtering. As the filtering methods become increasingly complex, the state machine required to perform them becomes increasingly complex and requires increased real estate within the graphics coprocessor. This coupled with the fact that uses for texture data continues to expand, for example, texture data is being used for lighting and other surface properties in addition to color, renders the commonly employed linear interpolation inefficient or even insufficient.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
  • FIG. 1A is a block diagram of a system of one embodiment of the invention.
  • FIG. 1B is a diagram of texture sampling in one embodiment of the invention.
  • FIG. 2 is a flow diagram of the setup of the textured filtering module in one embodiment of the invention.
  • FIG. 3 is a flow diagram of texture filtering in one embodiment of the invention.
  • DETAILED DESCRIPTION
  • FIG. 1A is a block diagram of a system of one embodiment of the invention. A host processor 100 is coupled by a bus 102 to a memory 104. A graphics coprocessor 106 is also coupled to the bus 102. Additionally, graphics coprocessor 106 may be coupled to memory 104 by an accelerated graphics port (AGP) 112. The AGP may adhere to Accelerated Graphics Port AGP V3.0 Interface Specification Rev. 1.0 published September 2002 (hereinafter the AGP Specification). AGP 112 allows rapid access to graphics data residing in memory 104. Also coupled to the bus are framebuffer 108 and display 110. In some embodiments, framebuffer 108 may be contained within memory 104. Graphics coprocessor 106 includes pixel processing pipeline 120. Within the pixel processing pipeline 120 is a vertex processing module 122, primitive assembly module 124, a fragment processing module 126 and a framebuffer processing module 128. Vertex processing module 122 in operation receives vertex data, which may include, for example, 3D positional information, color information and other similar information related to vertices in the graphic image. In one embodiment, vertex data is of the form V=X, Y, Z, Tu, Tv, RGB. In this expression, X, Y, Z are the three dimensional Cartesian coordinates of the vertex, Tu and Tv are the two dimensional coordinate of the corresponding texel in the texture map and RGB are the red, green and blue color values at the vertex. Other forms and contents of vertex data are also contemplated.
  • Vertex processing module does three-dimensional transformations on 3D positional data conveyed, and may, for example, applies lighting. The processed vertices are passed to the primitive assembly module, which receives connectivity data. The connectivity data may include indices to permit assembly of primitives, typically triangles, based on the vertices and indices received.
  • The primitives are passed to the fragment processing module 126 which processes the primitives to identify fragments and apply texture data to build an output. As used herein, “fragment” refers to a pixel or group of contiguous pixels that are to be consistently processed to generate the output. The fragment processing exchanges data relating to texture mapping the fragments with a texture filter module 130.
  • The texture filter module 130 communicates with fragment processing module 126 to supply texels for application to the pixels. In one embodiment, texture filter module 130 is programmable. In this context, programmable is deemed to mean capable of executing a software program consisting of one or more instructions from a defined instruction set. One example of an instruction set is set forth below in Table 1.
    TABLE 1
    Instruction Description
    ADD A, B Adds A and B operands
    SUB A, B Subtracts B from A
    MUL A, B Multiples A by B
    RCP A, B Makes A the reciprocal of B
    CMP A, B, X Compares A, B according to immediate X,
    places result in A
    MIN A, B Compares A, B leaves minimum of two values in A
    MAX A, B Compares A, B leaves maximum of two values in A
    MOV A, B Moves B into A
  • Alternative instruction sets, either shorter or longer, may be employed in various embodiments of the invention.
  • In one embodiment, texture filter module 130 includes a plurality of texture processing cores (TPCs) 132 (16 TPC are shown in FIG. 1). Other embodiments may have more or fewer TPCs. In one embodiment, a single TPC exists. In one embodiment, each TPC 132 is capable of processing a pixel in parallel with each of the other TPC 132. Each core 132 may be provided with a register set 134 which may include various types of registers such as control registers, source registers, temporary registers and an output register.
  • In one embodiment, the control registers include a sampling register, a status register, an address register, an offset register, and a plurality of fraction registers. In one embodiment, the sampling register has one bit corresponding to each source registers indicating whether the source register should be sampled or not. For example, if there are sixteen source registers, the sampling register may be a sixteen bit register with one bit corresponding to each of the sixteen source registers. In one embodiment, the status register is used to indicate the status of the TPC after certain conditions, such as overflow, divide by zero, etc. In one embodiment, the address register may be a 32 bit register containing the address of the texture map data. In one embodiment, this register may be accessible only by an application programming interface (API) rather than providing direct access to a programmer. The offset register may be used to provide an offset into the texture data corresponding to the nearest texel coordinate. Fraction registers may be used to hold the fractional coordinate between the texel samples in each dimensionality. In one embodiment, these would be provided by the fragment processing module 126. In one embodiment above, where V=X, Y, Z, Tu, Tv, RGB; Tu and Tv correspond to a pixel to be texture mapped would be provided to the texture filtering module. As one example, an eight pixel one dimensional texture coordinate of 0.175 would fall between the second (0.125) and third (0.25) texel. It would equate to a fraction of 0.2. The fraction in this embodiment is found as (0.175−0.125)/0.125 or more generally, the coordinate less the closest lower increment divided by the increment value.
  • FIG. 1B is a diagram of texture sampling in one embodiment of the invention. In one embodiment, sixteen source registers are provided. With each register corresponding to one texel in a 4×4 grid surrounding the TuTv sampling location of the texture sample point and would correspond to pixels addressed in such a fashion. While TuTv mapps to a location between texels 5 and 6 and texels 9 and 10, the contribution of the sixteen texels in the patch to the texture value assigned to TuTv may be defined by the texture filtering program. In some embodiments, only texels 5, 6, 9 and 10 provide a contribution. In other embodiments, all sixteen texels may contribute. In still other embodiments, all diagonal prixels in the group may contribute. As illustrated, the programmable nature of the texture filtering module permits robust and flexible texture filtering options.
  • Temporary registers may be provided for optional use by a programmer performing intermediate calculations on sample data. An output register is provided to store the output once the filtering operation is complete. In one embodiment, a 32 bit register is provided to receive the final result. Larger registers may be employed, however, in some embodiments a 32 bit ARGB (alpha red green blue) value is deemed sufficient.
  • The actual filtering may be performed by the texture filtering module 130 by loading a desired filtering program into a textured processing core. The filtering program corresponds to a fragment to be processed. Within a region of an image, it may be desirable to apply various effects to the texture data accordingly. Thus, for a particular graphic image, there may be numerous filtering programs employed. For example, the filter program applied to a shiny part of a leather jacket on an image would likely to be different than the filter program applied to a scuffed part of a leather jacket. By using different programs in e texture filter module, the different effect can be accommodated. The usage of several filter programs during the course of rendering a given scene image is analogous to how, under the current-day fixed-function schemes, the rendering of a given scene may involve switching between the different fixed-function filtering states for different parts of the scene.
  • The program employed will influence which of the e.g. 16 texels are actually sampled to perform the texture filtering. In one embodiment, texture data may be arranged in memory to optimize access to the texels likely to be sampled. For example, if the sampling register indicates every fourth texel value is active, the texture data may be stored so that points 1, 5, 9 and 13 are contiguous in memory, points 2, 6, 10, etc. are contiguous. As another example, where every second texel is active, 1, 3, 5, 7, etc. are contiguous and 2, 4, 8, etc. are contiguous. This arrangement in memory may be performed by the host processor 100 or the graphic coprocessor 106.
  • Arranging memory requires a certain amount of processor resources, in one embodiment, a determination is made when the likely use of the texture data exceeds a threshold cost required to rearrange it. Thus, where the usage of the textured data justifies the cost to rearrange it, in one embodiment, the textured data is rearranged in memory to facilitate access. The threshold may be selected based on objective guidelines such as number of texels to be processed with a given program.
  • Once texture filtering is complete and the output generated, the output value may then be passed back to fragment processing module 126 to permit the output fragment to be built. The output built by the fragment processing module 126 is passed to framebuffer processing module 128. Framebuffer processing module 128 combines the pixels received with the existing framebuffer for output to display 110.
  • FIG. 2 is a flow diagram of the setup of the textured filtering module in one embodiment of the invention. At functional block 202, a texture filter program is loaded into a texture processing core of the texture filtering module. At functional block 204, the sampling register is initialized to indicate the texels surrounding a sample point that will be sampled as part of the filtering process. At decision block 206, a determination is made if the texels to be sampled in conjunction with the number of samplings required justify reorganization of the texture data in memory. If so, the texture data is reordered for efficient access at functional block 208. After reordering, or if no reordering is required, the address register is initialized at functional block 210.
  • FIG. 3 is a flow diagram of texture filtering in one embodiment of the invention. At functional block 302, the texture filter fetches the coordinate data for pixels to be rendered from the vertex pipeline. In one embodiment, these will be fetched from the fragment processing module. At functional block 304, texel values identified from the sampling register are fetched from memory. At functional block 306, fraction registers are loaded with the coordinate data. The texture processing cores are used to execute a filter program at functional block 308. At decision block 310, a determination is made if the execution of the filter program necessitates setting of a status flag. If the execution requires the status flag such as a divide by zero or overflow, the status register is loaded with an appropriate value at functional block 312. If no status flag is required, or after the status register has been loaded, the output value is loaded into the output register and the output is signaled to be available at functional block 314. At decision block 316, a determination is made if there are more pixels to be rendered using the existing filter program. If so, a flow continues. If not, it ends.
  • Although the above flow diagrams are arranged in a particular order, it should be understood that some of the operations may be performed in parallel or in a different order than depicted. Accordingly, such parallization or rearrangement is within the scope and contemplation of the embodiments of the invention. It should also be noted that while in only one embodiment, a single texture processing core may be present in the texture filter module, embodiments with multiple texture processing cores, pixels may be processed in parallel with each core following the flow depicted in FIG. 3.
  • In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (22)

1. A method comprising:
fetching coordinate data for a pixel to be rendered;
fetching texel values corresponding to the pixel;
filtering the texel values through a programmable filter; and
outputting a filtered texture value for the pixel.
2. The method of claim 1 wherein filtering texel values comprises:
reading a control register; and
using at least one location specified in the control register as a source location.
3. The method of claim 1 wherein fetching coordinate data comprises:
retrieving X, Y, Z coordinate data from a vertex pipeline.
4. The method of claim 1 further comprising:
writing coordinate fraction data to a plurality of registers.
5. The method of claim 1 wherein outputting comprises:
writing the filtered texture value to a register; and
signaling a processor that the filtered texture value is available.
6. An apparatus comprising:
a fragment processing module;
a programmable texture filtering module in communication with the fragment processing module to programmably filter texture data corresponding to at least one pixel; and
a frame buffer processing module to combine filtered texture data with an existing frame buffer.
7. The apparatus of claim 6 wherein the programmable texture filtering module comprises:
a plurality of control registers;
a plurality of source registers;
a plurality of temporary registers; and
at least one output register.
8. The apparatus of Clam 7 wherein the source registers are read only.
9. The apparatus of claim 7 wherein the plurality of control registers comprises:
a status register;
an address register;
an offset register; and
a plurality of fraction registers.
10. The apparatus of claim 7 where the plurality of the control registers comprise:
at least one sampling register have a bit corresponding to each of the source registers to indicate if sampling of a corresponding source register is required.
11. The apparatus of claim 6 wherein the programmable texture filtering module comprises:
a plurality of processing cores to execute an instruction set.
12. The apparatus of claim 6 wherein a subset of the plurality of cores are to execute a filtering program on at least one pixel in parallel.
13. A system comprising:
a memory,
a plurality of texture processing cores (TPC) coupled to the memory to programmably filter texture data;
a fragment processing module to apply the filtered texture data to at least one fragment; and
a display to display an image created using the at least one fragment.
14. The system of claim 13 wherein the plurality of TPC and the fragment processing module are integrated with a host processor.
15. The system of claim 13 wherein the plurality of TPCS and the fragment processing module reside in a graphics coprocessor.
16. The system of claim 13 comprising:
a register set associated with each TPC of the plurality.
17. The system of claim 15 further comprising:
an accelerated graphics port coupling the graphics coprocessor to the memory.
18. A computer readable storage media containing executable computer program instructions which when executed cause a digital processing system to perform a method comprising:
fetching coordinate data for a pixel to be rendered;
fetching texel values corresponding to the pixel;
filtering the texel values through a programmable filter; and
outputting a filtered texture value for the pixel.
19. The computer readable storage media of claim 18 which when executed cause a digital processing system to perform a method further comprising:
reading a control register; and
using at least one location specified in the control register as a source location.
20. The computer readable storage media of claim 18 which when executed cause a digital processing system to perform a method further comprising:
retrieving X, Y, Z coordinate data from a vertex pipeline.
21. The computer readable storage media of claim 18 which when executed cause a digital processing system to perform a method further comprising:
writing coordinate fraction data to a plurality of registers.
22. The computer readable storage media of claim 18 which when executed cause a digital processing system to perform a method further comprising:
writing the filtered texture value to a register; and
signaling a processor that the filtered texture value is available.
US10747966 2003-12-29 2003-12-29 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems Abandoned US20050140688A1 (en)

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US10747966 US20050140688A1 (en) 2003-12-29 2003-12-29 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
US10872049 US7133047B2 (en) 2003-12-29 2004-06-18 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
KR20067013145A KR100823373B1 (en) 2003-12-29 2004-12-23 Method and mechanism for programmable filtering of texture map data in 3d graphics subsystems
JP2006547482A JP4430678B2 (en) 2003-12-29 2004-12-23 Program of the texture map data in three-dimensional graphics subsystem available filtering method and apparatus
PCT/US2004/043670 WO2005066895A3 (en) 2003-12-29 2004-12-23 Method and mechanism for programmable filtering of texture map data in 3d graphics subsystems
EP20040815685 EP1700272A2 (en) 2003-12-29 2004-12-23 Method and mechanism for programmable filtering of texture map data in 3d graphics subsystems
CN 200480039384 CN1910621B (en) 2003-12-29 2004-12-23 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
TW93140925A TWI280513B (en) 2003-12-29 2004-12-28 Method, apparatus and system for providing flexible texture filtering, and computer readable storage media containing executable computer program instructions
US11515110 US7477261B2 (en) 2003-12-29 2006-08-31 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
US12260057 US7697010B2 (en) 2003-12-29 2008-10-28 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
US12688594 US20100118028A1 (en) 2003-12-29 2010-01-15 Method and Mechanism for Programmable Filtering of Texture Map Data in 3D Graphics Subsystems

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US12260057 Active US7697010B2 (en) 2003-12-29 2008-10-28 Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050283559A1 (en) * 2004-06-18 2005-12-22 Broadcom Corporation Motherboard with video data processing card capability
US20050289507A1 (en) * 2004-06-25 2005-12-29 Broadcom Corporation Video data processing circuits and systems comprising programmable blocks or components
US20050289523A1 (en) * 2004-06-24 2005-12-29 Broadcom Corporation Method and apparatus for transforming code of a non-proprietary program language into proprietary program language
US20060072831A1 (en) * 2004-09-27 2006-04-06 Kim Pallister Low-latency remote display rendering using tile-based rendering systems
US20060132491A1 (en) * 2004-12-20 2006-06-22 Nvidia Corporation Real-time display post-processing using programmable hardware
CN102678044A (en) * 2012-06-06 2012-09-19 浙江大学 Well drilling rod and pulse plasma drilling machine system
US20140146080A1 (en) * 2012-11-29 2014-05-29 Seiko Epson Corporation Method for Multiple Projector Display Using a GPU Frame Buffer
US9983763B2 (en) 2009-06-10 2018-05-29 Hexagon Technology Center Gmbh Geometrical and ontological filtering using spatial boundary of 3D objects
US10102015B1 (en) 2017-06-22 2018-10-16 Microsoft Technology Licensing, Llc Just in time GPU executed program cross compilation

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140688A1 (en) * 2003-12-29 2005-06-30 Kim Pallister Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
KR100823373B1 (en) * 2003-12-29 2008-04-17 인텔 코오퍼레이션 Method and mechanism for programmable filtering of texture map data in 3d graphics subsystems
US20080252652A1 (en) * 2007-04-13 2008-10-16 Guofang Jiao Programmable graphics processing element
KR100980449B1 (en) * 2007-12-17 2010-09-07 한국전자통신연구원 Method and system for rendering of parallel global illumination
CN101840565B (en) * 2010-04-19 2011-09-21 浙江大学 Octree parallel constructing method based on GPU
US9460546B1 (en) 2011-03-30 2016-10-04 Nvidia Corporation Hierarchical structure for accelerating ray tracing operations in scene rendering
US9142043B1 (en) 2011-06-24 2015-09-22 Nvidia Corporation System and method for improved sample test efficiency in image rendering
US9147270B1 (en) 2011-06-24 2015-09-29 Nvidia Corporation Bounding plane-based techniques for improved sample test efficiency in image rendering
US8970584B1 (en) 2011-06-24 2015-03-03 Nvidia Corporation Bounding box-based techniques for improved sample test efficiency in image rendering
WO2013019609A1 (en) 2011-07-29 2013-02-07 Hexagon Metrology, Inc. Coordinate measuring system data reduction
US9269183B1 (en) 2011-07-31 2016-02-23 Nvidia Corporation Combined clipless time and lens bounds for improved sample test efficiency in image rendering
CN102413375A (en) * 2011-11-29 2012-04-11 康佳集团股份有限公司 Method and system for utilizing GPU (Graphic Processing Unit) to realize video playing
US9305394B2 (en) 2012-01-27 2016-04-05 Nvidia Corporation System and process for improved sampling for parallel light transport simulation
US9171394B2 (en) 2012-07-19 2015-10-27 Nvidia Corporation Light transport consistent scene simplification within graphics display system
US9159158B2 (en) 2012-07-19 2015-10-13 Nvidia Corporation Surface classification for point-based rendering within graphics display system
US9123167B2 (en) 2012-09-29 2015-09-01 Intel Corporation Shader serialization and instance unrolling
US8982124B2 (en) 2012-09-29 2015-03-17 Intel Corporation Load balancing and merging of tessellation thread workloads
US9449363B2 (en) * 2014-06-27 2016-09-20 Intel Corporation Sampling, fault management, and/or context switching via a compute pipeline
CN106355632A (en) * 2016-08-30 2017-01-25 广联达科技股份有限公司 Rendering object filtering method and rendering object filtering device

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835172A (en) * 1985-12-19 1989-05-30 Societe D'etudes Scientifiques Et Industrielles De L'ile-De-France Novel benzamides, intermediates and process for the preparation and therapeutic use thereof
US4897806A (en) * 1985-06-19 1990-01-30 Pixar Pseudo-random point sampling techniques in computer graphics
US5025400A (en) * 1985-06-19 1991-06-18 Pixar Pseudo-random point sampling techniques in computer graphics
US5239624A (en) * 1985-06-19 1993-08-24 Pixar Pseudo-random point sampling techniques in computer graphics
US6333743B1 (en) * 1997-10-23 2001-12-25 Silicon Graphics, Inc. Method and apparatus for providing image and graphics processing using a graphics rendering engine
US6366290B1 (en) * 1997-03-31 2002-04-02 Cirrus Logic, Inc. Dynamically selectable texture filter for a software graphics engine
US6452603B1 (en) * 1998-12-23 2002-09-17 Nvidia Us Investment Company Circuit and method for trilinear filtering using texels from only one level of detail
US20030234791A1 (en) * 2002-06-20 2003-12-25 Boyd Charles N. Systems and methods for providing controllable texture sampling
US6731296B2 (en) * 1999-05-07 2004-05-04 Broadcom Corporation Method and system for providing programmable texture processing
US20040227765A1 (en) * 2003-05-16 2004-11-18 Emberling Brian D. Method for improving texture cache access by removing redundant requests
US6867778B2 (en) * 2002-02-28 2005-03-15 Sun Microsystems, Inc. End point value correction when traversing an edge using a quantized slope value

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835712A (en) * 1986-04-14 1989-05-30 Pixar Methods and apparatus for imaging volume data with shading
JP2673101B2 (en) 1994-08-29 1997-11-05 インターナショナル・ビジネス・マシーンズ・コーポレイション Computer graphics equipment
EP0747859B1 (en) 1995-06-06 2005-08-17 Hewlett-Packard Company, A Delaware Corporation Interrupt scheme for updating a local memory
JPH09212658A (en) 1996-02-02 1997-08-15 Toshiba Corp Information processor
WO2002103633A1 (en) 2001-06-19 2002-12-27 Nvidia Corporation System, method and computer program product for a programmable pixel processing model with instruction set
US6999100B1 (en) * 2000-08-23 2006-02-14 Nintendo Co., Ltd. Method and apparatus for anti-aliasing in a graphics system
KR100823373B1 (en) * 2003-12-29 2008-04-17 인텔 코오퍼레이션 Method and mechanism for programmable filtering of texture map data in 3d graphics subsystems
US20050140688A1 (en) * 2003-12-29 2005-06-30 Kim Pallister Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897806A (en) * 1985-06-19 1990-01-30 Pixar Pseudo-random point sampling techniques in computer graphics
US5025400A (en) * 1985-06-19 1991-06-18 Pixar Pseudo-random point sampling techniques in computer graphics
US5239624A (en) * 1985-06-19 1993-08-24 Pixar Pseudo-random point sampling techniques in computer graphics
US4835172A (en) * 1985-12-19 1989-05-30 Societe D'etudes Scientifiques Et Industrielles De L'ile-De-France Novel benzamides, intermediates and process for the preparation and therapeutic use thereof
US6366290B1 (en) * 1997-03-31 2002-04-02 Cirrus Logic, Inc. Dynamically selectable texture filter for a software graphics engine
US6333743B1 (en) * 1997-10-23 2001-12-25 Silicon Graphics, Inc. Method and apparatus for providing image and graphics processing using a graphics rendering engine
US6452603B1 (en) * 1998-12-23 2002-09-17 Nvidia Us Investment Company Circuit and method for trilinear filtering using texels from only one level of detail
US6731296B2 (en) * 1999-05-07 2004-05-04 Broadcom Corporation Method and system for providing programmable texture processing
US6867778B2 (en) * 2002-02-28 2005-03-15 Sun Microsystems, Inc. End point value correction when traversing an edge using a quantized slope value
US20030234791A1 (en) * 2002-06-20 2003-12-25 Boyd Charles N. Systems and methods for providing controllable texture sampling
US20040227765A1 (en) * 2003-05-16 2004-11-18 Emberling Brian D. Method for improving texture cache access by removing redundant requests

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100005210A1 (en) * 2004-06-18 2010-01-07 Broadcom Corporation Motherboard With Video Data Processing Card Capability
US8074008B2 (en) 2004-06-18 2011-12-06 Broadcom Corporation Motherboard with video data processing card capability
US20050283559A1 (en) * 2004-06-18 2005-12-22 Broadcom Corporation Motherboard with video data processing card capability
US7603506B2 (en) 2004-06-18 2009-10-13 Broadcom Corporation Motherboard with video data processing card capability
US20050289523A1 (en) * 2004-06-24 2005-12-29 Broadcom Corporation Method and apparatus for transforming code of a non-proprietary program language into proprietary program language
US7961193B2 (en) 2004-06-25 2011-06-14 Broadcom Corporation Video data processing circuits and systems comprising programmable blocks or components
US20100007794A1 (en) * 2004-06-25 2010-01-14 Broadcom Corporation Video Data Processing Circuits And Systems Comprising Programmable Blocks Or Components
US20050289507A1 (en) * 2004-06-25 2005-12-29 Broadcom Corporation Video data processing circuits and systems comprising programmable blocks or components
US7612779B2 (en) * 2004-06-25 2009-11-03 Broadcom Corporation Video data processing circuits and systems comprising programmable blocks or components
US8472732B2 (en) 2004-09-27 2013-06-25 Intel Corporation Low-latency remote display rendering using tile-based rendering systems
US7813562B2 (en) 2004-09-27 2010-10-12 Intel Corporation Low-latency remote display rendering using tile-based rendering systems
US8768076B2 (en) 2004-09-27 2014-07-01 Intel Corporation Low-latency remote display rendering using tile-based rendering systems
US20060072831A1 (en) * 2004-09-27 2006-04-06 Kim Pallister Low-latency remote display rendering using tile-based rendering systems
US8208741B2 (en) 2004-09-27 2012-06-26 Intel Corporation Low-latency remote display rendering using tile-based rendering systems
US20110001755A1 (en) * 2004-09-27 2011-01-06 Kim Pallister Low-latency remote display rendering using tile-based rendering systems
US7586492B2 (en) * 2004-12-20 2009-09-08 Nvidia Corporation Real-time display post-processing using programmable hardware
US20060132491A1 (en) * 2004-12-20 2006-06-22 Nvidia Corporation Real-time display post-processing using programmable hardware
US10031640B2 (en) 2009-06-10 2018-07-24 Hexagon Technology Center Gmbh Hierarchical filtering using spatial boundary of 3D objects
US9983763B2 (en) 2009-06-10 2018-05-29 Hexagon Technology Center Gmbh Geometrical and ontological filtering using spatial boundary of 3D objects
CN102678044A (en) * 2012-06-06 2012-09-19 浙江大学 Well drilling rod and pulse plasma drilling machine system
US20140146080A1 (en) * 2012-11-29 2014-05-29 Seiko Epson Corporation Method for Multiple Projector Display Using a GPU Frame Buffer
US9035969B2 (en) * 2012-11-29 2015-05-19 Seiko Epson Corporation Method for multiple projector display using a GPU frame buffer
US10102015B1 (en) 2017-06-22 2018-10-16 Microsoft Technology Licensing, Llc Just in time GPU executed program cross compilation

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