Connect public, paid and private patent data with Google Patents Public Datasets

Transistor of semiconductor device, and method for manufacturing the same

Download PDF

Info

Publication number
US20050104055A1
US20050104055A1 US11018350 US1835004A US2005104055A1 US 20050104055 A1 US20050104055 A1 US 20050104055A1 US 11018350 US11018350 US 11018350 US 1835004 A US1835004 A US 1835004A US 2005104055 A1 US2005104055 A1 US 2005104055A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
film
layer
epitaxial
gate
process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11018350
Inventor
Byung Kwak
Kyung Ahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66651Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an epitaxial source/drain junction layer having an insulating film thereunder. The method comprises the step of forming a under-cut under an epitaxial source/drain junction layer so that an insulating film filling the under-cut can be formed.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to transistor of semiconductor device and method for manufacturing the same, and more particularly to improved transistor of memory device and method for manufacturing the same which provides a high speed and high integrated device by preventing deterioration of the characteristics of the device resulting from increase of impurity concentration as the integration of the device is increased.
  • [0003]
    2. Description of the Background Art
  • [0004]
    As the integration of a semiconductor device has been increased, integration of a DRAM has increased. However, the refresh time of the DRAM is almost double in each generation because of a high speed and low power requirements.
  • [0005]
    As the density of a memory device continuously increases, the concentration of impurities implanted into a substrate must be increased to minimize short channel effects, threshold voltages and leakage currents. However, the increase of the concentration of impurities results in increase of junction electric intensity, which generates short channel effects and leakage currents.
  • [0006]
    Moreover, the increase of concentration increases junction capacitance, thereby reducing the operation speed of the device.
  • [0007]
    As described above, in the conventional transistor of the semiconductor device and a method for manufacturing the same, the characteristics of the device is degradeddue to the increased concentration of impurities implanted into the substrate, thereby making the achievement of the high operation speed and high integration of the semiconductor device more difficult.
  • SUMMARY OF THE INVENTION
  • [0008]
    Accordingly, it is an object of the present invention to provide a transistor of a semiconductor device and a method for forming the same wherein capacitance generated by junction leakage current and junction depletion in a source/drain junction layer is remove to achieve a high speed and high integration of the device.
  • [0009]
    According to one aspect of the present invention, a transistor of a semiconductor device, comprising: an epitaxial channel region disposed on an active region of a semiconductor substrate; a stacked structure of an insulating film and an epitaxial source/drain junction layer disposed at both sides of the channel region; and a stacked structure of a gate insulating film and a gate electrode disposed on the epitaxial channel region, wherein at least a portion of the gate insulating film overlap with the source/drain junction layer is provided.
  • [0010]
    According to another aspect of the invention, a method for forming a transistor of a semiconductor device., comprising the steps of: forming a stacked structure of a first epitaxial layer and a second epitaxial layer on a semiconductor substrate; forming a device isolation film of trench type defining an active region, wherein a thickness of the device isolation film is substantially the same as that of the stacked structure; implanting an impurity into the second epitaxial layer using the device isolation film as a mask; sequentially forming a thermal oxide film and a sacrificial film on the entire surface of the resulting structure; etching the sacrificial film, the thermal oxide film, and the second and first epitaxial layers using a gate electrode mask to form an opening exposing the semiconductor substrate; removing the first epitaxial layer to form an under-cut under the second epitaxial layer; forming an insulating film filling the under-cut; growing a third epitaxial layer on the semiconductor substrate exposed by the opening; removing the sacrificial film and the thermal oxide film; implanting an impurity into the third epitaxial layer to form a channel region; and forming a gate electrode on the channel region is provided.
  • [0011]
    According to yet another aspect of the invention, a method for forming a transistor of a semiconductor device, comprising the steps of: forming a stacked structure of a first epitaxial layer and a second epitaxial layer on a semiconductor substrate; forming a device isolation film of trench type defining an active region; forming a dummy gate electrode on the second epitaxial layer; implanting an impurity into the second epitaxial layer using the dummy gate electrode as a mask; forming an insulating film spacer at a sidewall of the dummy gate; forming a thermal oxide film on the entire surface of the resulting structure; forming a planarized interlayer insulating film exposing the top surface of the dummy gate; etching the dummy gate and the second and first epitaxial layers therebelow to form an opening exposing the semiconductor substrate; removing the first epitaxial layer to form an under-cut under the second epitaxial layer; forming an insulating film filling the under-cut; growing a third epitaxial layer having an impurity implanted therein on the semiconductor substrate exposed by the opening; and forming a stacked structure of a gate oxide film and a gate electrode on the third epitaxial layer is provided.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:
  • [0013]
    FIG. 1 is a layout diagram illustrating an active region and a gate region formed in one field;
  • [0014]
    FIGS. 2 a to 2 f are cross-sectional diagrams illustrating sequential steps of a method for forming a transistor of a semiconductor device in accordance with a first embodiment of the present invention; and
  • [0015]
    FIGS. 3 a to 3 i are cross-sectional diagrams illustrating sequential steps of a method for forming a transistor of a semiconductor device in accordance with a second embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0016]
    A transistor of a semiconductor device and a method for forming the same in accordance with preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
  • [0017]
    FIG. 1 is a layout diagram illustrating an active region and a gate electrode region 22 formed on a semiconductor substrate 11, and FIGS. 2 a to 2 f are cross-sectional diagrams illustrating sequential steps of a method for forming a transistor of a semiconductor device in accordance with a first embodiment of the present invention, taken along lines I-I of FIG. 1.
  • [0018]
    Referring to FIG. 2 a, an first epitaxial layer 13 and a conductive second epitaxial layer 15 are sequentially formed on the semiconductor substrate 11 consisting of silicon.
  • [0019]
    Preferably, the first epitaxial layer 13 is an epitaxial SiGe layer formed under an atmosphere of a mixture gas of a gas from the group consisting of GeH4, SiH4, SiH2Cl2 and combinations thereof, HCl and H2, and has a thickness ranging from 50 to 1000 Å, and the second epitaxial layer 15 is an epitaxial Si layer formed under an atmosphere of a gas from the group consisting of SiH4, SiH2Cl2 and combinations thereof, HCl and H2, and has a thickness ranging from 50 to 1000 Å.
  • [0020]
    A pad oxide film (not shown) and a nitride film (not shown) are sequentially formed on the entire surface of the resulting structure.
  • [0021]
    Thereafter, the nitride film, the oxide film, the second epitaxial layer 15, the first epitaxial layer 13 and a predetermined depth of semiconductor substrate 11 are etched via a photoetching process using a device isolation mask (not shown) to form a trench. A device isolation film 17 is formed by filling the trench to define an active region.
  • [0022]
    Next, the second epitaxial layer 15 is subjected to an implant process using the device isolation film 17 as a mask. The implant process is preferably performed using As having a concentration ranging from 1.0 E12 to 5.0 E13 atoms/cm2 with an energy ranging from 10 to 100 KeV. Other conventional impurities may be used.
  • [0023]
    A thermal oxide film 19 is formed on the entire surface of the resulting structure. The thermal oxide film preferably has a thickness ranging from 10 to 200 Å. A sacrificial film 21 is then formed on the thermal oxide film 19. Preferably, the sacrificial film 21 may be an oxide film, nitride film or polysilicon film having a thickness ranging from 500 to 3000 Å and used as a mask.
  • [0024]
    Referring to FIG. 2 b, a gate electrode region 22 exposing the semiconductor substrate 11 is formed by sequentially etching the sacrificial film 21, the thermal oxide film 19, the second epitaxial layer 15 and the first epitaxial layer 13 via a photoetching process using a mask exposing an region corresponding to the gate electrode region 22 of FIG. 1.
  • [0025]
    Referring to FIG. 2 c, the first epitaxial layer 13 exposed by a lower sidewall of the gate electrode region 22 is removed to form an under-cut 23 under the second epitaxial layer 15. Preferably, the process for removing the exposed portion of the first epitaxial layer 13 is a wet etching process or an isotropic dry etching process utilizing etching selectivity differences among adjacent layers and the first epitaxial layer 13.
  • [0026]
    Specifically, the wet etching process is preferably performed using a solution containing H2O, H2O2 and NH4OH having a ratio of 5:1:1 at a temperature ranging from 70 to 80° C. (ref. F. S. Johnson et al. journal of electronic materials, vol 21, p. 805-810, 1992). The isotropic dry etching process is preferably a plasma etching process using HBr, O2 and Cl2, and more preferably performed using microwaves to improve isotropic etching properties. In addition, the plasma etching process may be performed using SF6.
  • [0027]
    Now referring to FIG. 2 d, an insulating film 25 for filling the under-cut 23 is formed on the entire surface of the resulting structure. Preferably, the insulating film 25 is an oxide film or nitride film.
  • [0028]
    The insulating film 25 is preferably formed via thermal oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • [0029]
    Preferably, the CVD process is performed using SiH4 and N2O under a pressure of 50 Torr and at a temperature ranging from 50 to 800° C. The thermal oxidation process is a dry or wet process performed at a temperature of 700 to 1100° C.
  • [0030]
    Referring to FIG. 2 e, a wet etching process is performed so that only the portion of the insulating film 25 in the under-cut 23 remains. The wet etching process is preferably performed using a HF group etching solution.
  • [0031]
    As shown in FIG. 2 f, a third epitaxial layer 27 is grown on the semiconductor substrate 11 exposed by the gate electrode region 22.
  • [0032]
    Preferably, the third epitaxial layer 27 is an epitaxial Si layer having a thickness ranging from 100 to 2000 Å formed under an atmosphere of a mixture gas of a gas from the group consisting of SiH4, SiH2Cl2 and combinations thereof, HCl and H2.
  • [0033]
    The sacrificial oxide film 21 and the thermal oxide film 19 are removed via a wet etching process. Preferably, the wet etching process is performed by utilizing the etching selectivity difference among adjacent other layers and the sacrificial oxide film 21.
  • [0034]
    A channel region is formed on the third epitaxial layer 27 by performing a channel implant process and a punch stop implant process.
  • [0035]
    A gate electrode having a stacked structure of a gate oxide film 29, a conductive layer for gate electrode 31 and a hard mask layer 33 is formed via a photoetching process using a gate electrode mask. Conventional conductive materials may be used as the conductive layer for gate electrode 31. The hard mask layer 33 is preferably a nitride film or an oxide film.
  • [0036]
    The formation of the channel region and removal of the sacrificial oxide film 21 and the thermal oxide film 19 may be performed prior to the formation of the gate electrode.
  • [0037]
    In the transistor of the semiconductor device formed according to the method of FIGS. 2 a to 2 f, the conductive third epitaxial layer 27 formed in the active region of the semiconductor substrate 11 corresponds to the channel region of the transistor. The stacked structure of the insulating film 25 and the conductive second epitaxial layer 15 is formed at both sides of the third epitaxial layer 27, and the gate insulating film 29 and the gate electrode 31 are formed on the third epitaxial layer 27. The second epitaxial layer 15 corresponds to a source/drain junction layer, and at least a portion of the gate insulating film 29 overlap with the second epitaxial layer 15.
  • [0038]
    FIGS. 3 a to 3 i are cross-sectional diagrams illustrating sequential steps of a method for forming a transistor of a semiconductor device in accordance with a second embodiment of the present invention, taken along lines I-I of FIG. 1.
  • [0039]
    Referring to FIG. 3 a, an first epitaxial layer 43 and a conductive second epitaxial layer 45 are sequentially formed on the semiconductor substrate 41 comprised of silicon. Preferably, the first epitaxial layer 43 is an epitaxial SiGe layer having a thickness ranging from 50 to 1000 Å formed under an atmosphere of a mixture gas of a gas from the group consisting of GeH4, SiH4, SiH2Cl2 and combinations thereof, HCl and H2, and the second epitaxial layer. 45 is an epitaxial Si layer having a thickness ranging from 50 to 1000 Å formed under an atmosphere of a mixture gas of a gas from the group consisting of SiH4, SiH2Cl2 and combinations thereof, HCl and H2.
  • [0040]
    A pad oxide film (not shown) and a nitride film (not shown) are sequentially formed on the entire surface of the resulting structure.
  • [0041]
    Thereafter, the nitride film, the oxide film, the second epitaxial layer 45, the first epitaxial layer 43 and a predetermined depth of semiconductor substrate 41 are etched via a photoetching process using a device isolation mask (not shown) to form a trench. A device isolation film 47 is formed by filling the trench to define an active region.
  • [0042]
    Referring to FIG. 3 b, a polysilicon layer (not shown) is formed on the entire surface of the resulting structure., and then etched via a photoetching process using a gate electrode mask to form a dummy gate electrode 49 in a predetermined region where a gate electrode region is to be formed. The thickness of the polysilicon layer is substantially the same as that of the gate electrode formed in a subsequent process, for example, 500 to 3000 Å in thickness. An oxide film or nitride film may be used other than the polysilicon layer.
  • [0043]
    Thereafter, the second epitaxial layer 45 is subjected to an implant process using the dummy gate electrode 49 as a mask. The implant process is preferably performed using As having a concentration ranging from 1.0 E12 to 5.0 E13 atoms/cm2 with an energy ranging from 10 to 100 KeV. Other conventional impurities may be used.
  • [0044]
    The implant process may also be performed prior to the formation of the polysilicon layer using the device isolation film 47 as a mask.
  • [0045]
    Referring to FIG. 3 c, an insulating film spacer 51, preferably a nitride film or an oxide film is formed at sidewalls of the dummy gate electrode 49. A thermal oxide film 53 is then formed on the entire surface of the resulting structure.
  • [0046]
    Now referring to FIG. 3 d, an interlayer insulating film 55 is formed on the entire surface of the resulting structure, and then planarized to expose the top surface of the dummy gate electrode 49. Preferably, the planarization process is a CMP process.
  • [0047]
    Referring to FIG. 3 e, the exposed dummy gate electrode 49 is first removed, and the second epitaxial layer 45 and the first epitaxial layer 43 are etched using the interlayer insulating film 55 and the insulating film spacer 51 as a mask to form a gate electrode region 57 exposing the semiconductor substrate 41.
  • [0048]
    Referring to FIG. 3 f, the first epitaxial layer 43 exposed by a lower sidewall of the gate electrode region 57 is removed to form an under-cut 59 under the second epitaxial layer 45. Preferably, the process for removing the exposed portion of the first epitaxial layer 43 is a wet etching process or an isotropic dry etching process utilizing etching selectivity differences among adjacent and the first signal-crystalline layer 43.
  • [0049]
    Specifically, the wet etching process is preferably performed using a solution containing H2O, H2O2, NH4OH having a ratio of 5:1:1 at a temperature ranging from 70 to 80° C. (ref. F. S. Johnson et al. journal of electronic materials, vol 21, p. 805-810, 1992). The isotropic dry etching process is preferably a plasma etching process using HBr, O2 and Cl2, and more preferably performed using microwaves to improve isotropic etching properties. In addition, the plasma etching process may be performed using SF6.
  • [0050]
    Referring to FIG. 3 g, an insulating film 61 for filling the under-cut 59 is formed on the entire surface of the resulting structure. Preferably, the insulating film 61 is an oxide film or a nitride film.
  • [0051]
    The insulating film 61 is preferably formed via thermal oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • [0052]
    Preferably, the CVD process is performed using SiH4 and N2O under a pressure of 50 Torr and at a temperature ranging from 50 to 800° C. The thermal oxidation process is a dry or wet process performed at a temperature ranging from 700 to 1100° C.
  • [0053]
    Referring to FIG. 3 h, a wet etching process is performed so that only the portion of the insulating film 61 in the under-cut 59 remains. The wet etching process is preferably performed using a HF group etching solution.
  • [0054]
    Referring to FIG. 3 i, a third epitaxial layer 63, which is preferably an epitaxial Si layer having a thickness ranging from 100 to 2000 Å, is grown on the semiconductor substrate 41 exposed by the gate electrode region 57.
  • [0055]
    A channel region is formed on the third epitaxial layer 63 by performing a channel implant process and a punch stop implant process.
  • [0056]
    A gate oxide film 65 is grown on the third epitaxial layer 63, and a conductive layer for gate electrode 67 is formed on the gate oxide film 65, and then planarized using the interlayer insulating film 55 as an etch barrier to form a gate electrode.
  • [0057]
    The gate electrode may include a stacked structure of a conductive layer and a hard mask layer.
  • [0058]
    As discussed earlier, in accordance with the present invention, the transistor of the semiconductor device and the method for forming the same have the following advantages:
  • [0059]
    1. Generation of junction leakage current is prevented.
  • [0060]
    2. Removal of capacitance generated by junction depletion provides improved operation speed of the device.
  • [0061]
    3. Improved short channel effects/drain induced barrier lowering characteristics due to the decrease in junction depth provide decrease of a critical dimension of the gate electrode and less threshold voltage reduction.
  • [0062]
    4. The epitaxial Si layer consisting the source/drain junction region represses depletion in a bulk-wise direction to improve punch-through characteristics and allows a reduction of the dose of punch stop implant to improve refresh characteristics of the DRAM.
  • [0063]
    5. The improved punch-through characteristics allow reduction of channel threshold voltage control implant dose, thereby improving swing phenomenon and leakage current characteristics in an off state.
  • [0064]
    6. An increase in junction breakdown voltage allows a high-speed operation of the device which uses a high driving voltage.
  • [0065]
    7. A remarkable decrease in leakage current between the devices allows reduction of the depth and width of the device isolation film and achievement of high integration.
  • [0066]
    8. The epitaxial channel region and the source/drain junction region provide an improved interface characteristics of the semiconductor substrate.
  • [0067]
    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.

Claims (7)

1. A transistor of a semiconductor device, comprising:
an epitaxial channel region disposed on an active region of a semiconductor substrate;
a stacked structure of an insulating film and an epitaxial source/drain junction layer disposed at both sides of the channel region; and
a stacked structure of a gate insulating film and a gate electrode disposed on the epitaxial channel region, wherein at least a portion of the gate insulating film overlap with the source/drain junction layer.
2. The transistor of claim 1, wherein the insulating film is an oxide film or a nitride film.
3. The transistor of claim 1, wherein the insulating film and the source/drain junction layer have a thickness ranging from 50 to 1000 Å, respectively.
4. The transistor of claim 1, further comprising a device isolation film defining the active region, the thickness of the device isolation film being substantially the same as that of the stacked structure of the insulating film and the source/drain junction layer.
5. The transistor of claim 1, wherein the source/drain junction layer and the channel region consist of epitaxial Si layers.
6. The transistor of claim 1, wherein the thickness of the epitaxial channel region is substantially the same as that of the stacked structure of the insulating film and the source/drain junction layer.
7-26. (canceled).
US11018350 2002-12-06 2004-12-22 Transistor of semiconductor device, and method for manufacturing the same Abandoned US20050104055A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR20020077492A KR100487922B1 (en) 2002-12-06 2002-12-06 A transistor of a semiconductor device and a method for forming the same
KR2002-77492 2002-12-06
US10608194 US6852559B2 (en) 2002-12-06 2003-06-30 Transistor of semiconductor device, and method for manufacturing the same
US11018350 US20050104055A1 (en) 2002-12-06 2004-12-22 Transistor of semiconductor device, and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11018350 US20050104055A1 (en) 2002-12-06 2004-12-22 Transistor of semiconductor device, and method for manufacturing the same

Publications (1)

Publication Number Publication Date
US20050104055A1 true true US20050104055A1 (en) 2005-05-19

Family

ID=32464547

Family Applications (2)

Application Number Title Priority Date Filing Date
US10608194 Expired - Fee Related US6852559B2 (en) 2002-12-06 2003-06-30 Transistor of semiconductor device, and method for manufacturing the same
US11018350 Abandoned US20050104055A1 (en) 2002-12-06 2004-12-22 Transistor of semiconductor device, and method for manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10608194 Expired - Fee Related US6852559B2 (en) 2002-12-06 2003-06-30 Transistor of semiconductor device, and method for manufacturing the same

Country Status (2)

Country Link
US (2) US6852559B2 (en)
KR (1) KR100487922B1 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050266692A1 (en) * 2004-06-01 2005-12-01 Brask Justin K Method of patterning a film
US20060068591A1 (en) * 2004-09-29 2006-03-30 Marko Radosavljevic Fabrication of channel wraparound gate structure for field-effect transistor
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060128131A1 (en) * 2004-09-29 2006-06-15 Chang Peter L Independently accessed double-gate and tri-gate transistors in same process flow
US20060223302A1 (en) * 2005-03-31 2006-10-05 Chang Peter L Self-aligned contacts for transistors
US20060261411A1 (en) * 2003-06-27 2006-11-23 Hareland Scott A Nonplanar device with stress incorporation layer and method of fabrication
US20060286755A1 (en) * 2005-06-15 2006-12-21 Brask Justin K Method for fabricating transistor with thinned channel
US20070069293A1 (en) * 2005-09-28 2007-03-29 Kavalieros Jack T Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20080090397A1 (en) * 2004-09-30 2008-04-17 Brask Justin K Nonplanar transistors with metal gate electrodes
US20090142897A1 (en) * 2005-02-23 2009-06-04 Chau Robert S Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20090149531A1 (en) * 2007-12-11 2009-06-11 Apoteknos Para La Piel, S.L. Chemical composition derived from p-hydroxyphenyl propionic acid for the treatment of psoriasis
US7736956B2 (en) 2005-08-17 2010-06-15 Intel Corporation Lateral undercut of metal gate in SOI device
US7781771B2 (en) 2004-03-31 2010-08-24 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7820513B2 (en) 2003-06-27 2010-10-26 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7879675B2 (en) 2005-03-14 2011-02-01 Intel Corporation Field effect transistor with metal source/drain regions
US7898041B2 (en) 2005-06-30 2011-03-01 Intel Corporation Block contact architectures for nanoscale channel transistors
US7902014B2 (en) 2005-09-28 2011-03-08 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US7960794B2 (en) 2004-08-10 2011-06-14 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7989280B2 (en) 2005-11-30 2011-08-02 Intel Corporation Dielectric interface for group III-V semiconductor device
US8071983B2 (en) 2005-06-21 2011-12-06 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US8084818B2 (en) 2004-06-30 2011-12-27 Intel Corporation High mobility tri-gate devices and methods of fabrication
CN102347234A (en) * 2010-07-29 2012-02-08 中国科学院微电子研究所 Structure of semiconductor device and manufacturing method thereof
WO2012022109A1 (en) * 2010-08-19 2012-02-23 中国科学院微电子研究所 Semiconductor device structure and manufacturing method thereof
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20130109144A1 (en) * 2011-10-26 2013-05-02 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US8617945B2 (en) 2006-08-02 2013-12-31 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100641494B1 (en) * 2002-12-30 2006-10-31 동부일렉트로닉스 주식회사 Method for manufacturing semiconductor device
US6936516B1 (en) * 2004-01-12 2005-08-30 Advanced Micro Devices, Inc. Replacement gate strained silicon finFET process
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
KR100549579B1 (en) * 2004-06-14 2006-02-08 주식회사 하이닉스반도체 Method for manufacturing cell transistor
KR100604870B1 (en) 2004-06-16 2006-07-31 삼성전자주식회사 Field effect transistor improvable junction abruptness and method for manufacturing the same
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US7808081B2 (en) 2004-08-31 2010-10-05 International Business Machines Corporation Strained-silicon CMOS device and method
KR100956575B1 (en) * 2004-06-24 2010-05-07 인터내셔널 비지네스 머신즈 코포레이션 Improved strained-silicon cmos device and method
US7704833B2 (en) * 2004-08-25 2010-04-27 Intel Corporation Method of forming abrupt source drain metal gate transistors
KR100669556B1 (en) 2004-12-08 2007-01-15 주식회사 하이닉스반도체 Semiconductor device and method for forming the same
KR100671562B1 (en) * 2004-12-23 2007-01-19 동부일렉트로닉스 주식회사 A method for forming source/drain of semiconductor device using the epitaxial process
KR100663363B1 (en) * 2005-06-10 2007-01-02 삼성전자주식회사 Recessed transistors removing fence of semiconductor substrate on sidewall of device isolation layer and methods of forming the same
KR100630760B1 (en) * 2005-08-17 2006-09-26 삼성전자주식회사 Multi-level transistor and method of manufacturing the same
US7256464B2 (en) * 2005-08-29 2007-08-14 United Microelectronics Corp. Metal oxide semiconductor transistor and fabrication method thereof
US7531404B2 (en) * 2005-08-30 2009-05-12 Intel Corporation Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
US20080121932A1 (en) 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
KR100855977B1 (en) 2007-02-12 2008-09-02 삼성전자주식회사 Semiconductor device and methods for manufacturing the same
KR20090004147A (en) * 2007-07-06 2009-01-12 삼성전자주식회사 Semiconductor device and method of forming the same
DE102007041206B4 (en) * 2007-08-31 2015-12-17 Advanced Micro Devices, Inc. Semiconductor device and method of self-aligned removal of a high-k gate dielectric over a STI region
CN101431099B (en) 2007-11-06 2011-07-27 联华电子股份有限公司 Semiconductor element
KR100967478B1 (en) 2007-12-24 2010-07-07 주식회사 동부하이텍 Method of fabricating semiconductor device
US7994010B2 (en) 2007-12-27 2011-08-09 Chartered Semiconductor Manufacturing Ltd. Process for fabricating a semiconductor device having embedded epitaxial regions
KR100929638B1 (en) * 2008-01-02 2009-12-03 주식회사 하이닉스반도체 MOSFET devices and a method of producing
US7964487B2 (en) * 2008-06-04 2011-06-21 International Business Machines Corporation Carrier mobility enhanced channel devices and method of manufacture
CN102237277B (en) * 2010-04-27 2014-03-19 中国科学院微电子研究所 Semiconductor device and method for forming same
CN102376715B (en) * 2010-08-11 2014-03-12 中国科学院微电子研究所 Capacitance-free dynamic random access memory structure and preparation method thereof
CN102468303B (en) * 2010-11-10 2015-05-13 中国科学院微电子研究所 Semiconductor memory cell, device and preparation method thereof
FR2970812B1 (en) * 2011-01-24 2013-11-15 Commissariat Energie Atomique Device field effect with low junction capacitance
US8921188B2 (en) * 2013-02-07 2014-12-30 Globalfoundries Inc. Methods of forming a transistor device on a bulk substrate and the resulting device
US9368626B2 (en) * 2013-12-04 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with strained layer
US20170077297A1 (en) * 2015-09-14 2017-03-16 Globalfoundries Inc. Semiconductor device with gate inside u-shaped channel and methods of making such a device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614739A (en) * 1995-06-02 1997-03-25 Motorola HIGFET and method
US20020001926A1 (en) * 2000-06-20 2002-01-03 Taiji Noda Semiconductor device and method for fabricating the same
US20020142557A1 (en) * 2001-03-28 2002-10-03 Takashi Hashimoto Semiconductor device and a method of manufacturing the same
US20020190344A1 (en) * 2001-06-15 2002-12-19 Michejda John A. Semiconductor device having a ghost source/drain region and a method of manufacture therefor
US20030008452A1 (en) * 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and its fabrication method
US20030071306A1 (en) * 1995-06-07 2003-04-17 Kuei-Wu Huang Method of forming planarized structures in an integrated circuit
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
US20030107052A1 (en) * 2001-12-10 2003-06-12 Kwang-Yang Chan Structure and method for fabricating a semiconductor device
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US6753555B2 (en) * 1999-11-15 2004-06-22 Matsushita Electric Industrial Co., Ltd. DTMOS device having low threshold voltage

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614739A (en) * 1995-06-02 1997-03-25 Motorola HIGFET and method
US20030071306A1 (en) * 1995-06-07 2003-04-17 Kuei-Wu Huang Method of forming planarized structures in an integrated circuit
US6753555B2 (en) * 1999-11-15 2004-06-22 Matsushita Electric Industrial Co., Ltd. DTMOS device having low threshold voltage
US20020001926A1 (en) * 2000-06-20 2002-01-03 Taiji Noda Semiconductor device and method for fabricating the same
US6720632B2 (en) * 2000-06-20 2004-04-13 Matsushita Electric Industrial Co., Ltd. Semiconductor device having diffusion layer formed using dopant of large mass number
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
US20020142557A1 (en) * 2001-03-28 2002-10-03 Takashi Hashimoto Semiconductor device and a method of manufacturing the same
US20020190344A1 (en) * 2001-06-15 2002-12-19 Michejda John A. Semiconductor device having a ghost source/drain region and a method of manufacture therefor
US20030008452A1 (en) * 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and its fabrication method
US20030107052A1 (en) * 2001-12-10 2003-06-12 Kwang-Yang Chan Structure and method for fabricating a semiconductor device
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060261411A1 (en) * 2003-06-27 2006-11-23 Hareland Scott A Nonplanar device with stress incorporation layer and method of fabrication
US7714397B2 (en) 2003-06-27 2010-05-11 Intel Corporation Tri-gate transistor device with stress incorporation layer and method of fabrication
US8405164B2 (en) 2003-06-27 2013-03-26 Intel Corporation Tri-gate transistor device with stress incorporation layer and method of fabrication
US7820513B2 (en) 2003-06-27 2010-10-26 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8273626B2 (en) 2003-06-27 2012-09-25 Intel Corporationn Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7781771B2 (en) 2004-03-31 2010-08-24 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050266692A1 (en) * 2004-06-01 2005-12-01 Brask Justin K Method of patterning a film
US8084818B2 (en) 2004-06-30 2011-12-27 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7960794B2 (en) 2004-08-10 2011-06-14 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US8268709B2 (en) 2004-09-29 2012-09-18 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060128131A1 (en) * 2004-09-29 2006-06-15 Chang Peter L Independently accessed double-gate and tri-gate transistors in same process flow
US8399922B2 (en) 2004-09-29 2013-03-19 Intel Corporation Independently accessed double-gate and tri-gate transistors
US7915167B2 (en) 2004-09-29 2011-03-29 Intel Corporation Fabrication of channel wraparound gate structure for field-effect transistor
US20060068591A1 (en) * 2004-09-29 2006-03-30 Marko Radosavljevic Fabrication of channel wraparound gate structure for field-effect transistor
US7859053B2 (en) 2004-09-29 2010-12-28 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20080090397A1 (en) * 2004-09-30 2008-04-17 Brask Justin K Nonplanar transistors with metal gate electrodes
US9741809B2 (en) 2004-10-25 2017-08-22 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8502351B2 (en) 2004-10-25 2013-08-06 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US9190518B2 (en) 2004-10-25 2015-11-17 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8067818B2 (en) 2004-10-25 2011-11-29 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8749026B2 (en) 2004-10-25 2014-06-10 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8183646B2 (en) 2005-02-23 2012-05-22 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20100295129A1 (en) * 2005-02-23 2010-11-25 Chau Robert S Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US8816394B2 (en) 2005-02-23 2014-08-26 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US9614083B2 (en) 2005-02-23 2017-04-04 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20110121393A1 (en) * 2005-02-23 2011-05-26 Chau Robert S Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US9748391B2 (en) 2005-02-23 2017-08-29 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7893506B2 (en) 2005-02-23 2011-02-22 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US8368135B2 (en) 2005-02-23 2013-02-05 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US9048314B2 (en) 2005-02-23 2015-06-02 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20090142897A1 (en) * 2005-02-23 2009-06-04 Chau Robert S Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US9368583B2 (en) 2005-02-23 2016-06-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7825481B2 (en) 2005-02-23 2010-11-02 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US8664694B2 (en) 2005-02-23 2014-03-04 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7879675B2 (en) 2005-03-14 2011-02-01 Intel Corporation Field effect transistor with metal source/drain regions
US7563701B2 (en) 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US20060223302A1 (en) * 2005-03-31 2006-10-05 Chang Peter L Self-aligned contacts for transistors
US9337307B2 (en) * 2005-06-15 2016-05-10 Intel Corporation Method for fabricating transistor with thinned channel
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US9806195B2 (en) 2005-06-15 2017-10-31 Intel Corporation Method for fabricating transistor with thinned channel
US20060286755A1 (en) * 2005-06-15 2006-12-21 Brask Justin K Method for fabricating transistor with thinned channel
US20110062520A1 (en) * 2005-06-15 2011-03-17 Brask Justin K Method for fabricating transistor with thinned channel
US8933458B2 (en) 2005-06-21 2015-01-13 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US8071983B2 (en) 2005-06-21 2011-12-06 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US9761724B2 (en) 2005-06-21 2017-09-12 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US8581258B2 (en) 2005-06-21 2013-11-12 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US9385180B2 (en) 2005-06-21 2016-07-05 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US7898041B2 (en) 2005-06-30 2011-03-01 Intel Corporation Block contact architectures for nanoscale channel transistors
US7736956B2 (en) 2005-08-17 2010-06-15 Intel Corporation Lateral undercut of metal gate in SOI device
US20070069293A1 (en) * 2005-09-28 2007-03-29 Kavalieros Jack T Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7902014B2 (en) 2005-09-28 2011-03-08 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US8193567B2 (en) 2005-09-28 2012-06-05 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US8294180B2 (en) 2005-09-28 2012-10-23 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US7989280B2 (en) 2005-11-30 2011-08-02 Intel Corporation Dielectric interface for group III-V semiconductor device
US8617945B2 (en) 2006-08-02 2013-12-31 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20090149531A1 (en) * 2007-12-11 2009-06-11 Apoteknos Para La Piel, S.L. Chemical composition derived from p-hydroxyphenyl propionic acid for the treatment of psoriasis
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US9450092B2 (en) 2008-06-23 2016-09-20 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US9224754B2 (en) 2008-06-23 2015-12-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US9806193B2 (en) 2008-06-23 2017-10-31 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8741733B2 (en) 2008-06-23 2014-06-03 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8759923B2 (en) * 2010-07-29 2014-06-24 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device structure and method for manufacturing the same
CN102347234A (en) * 2010-07-29 2012-02-08 中国科学院微电子研究所 Structure of semiconductor device and manufacturing method thereof
WO2012022109A1 (en) * 2010-08-19 2012-02-23 中国科学院微电子研究所 Semiconductor device structure and manufacturing method thereof
US9653358B2 (en) 2010-08-19 2017-05-16 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device structure and method for manufacturing the same
GB2488401B (en) * 2010-08-19 2015-02-18 Inst Of Microelectronics Cas Method of manufacturing semiconductor device structure
GB2488401A (en) * 2010-08-19 2012-08-29 Inst Of Microelectronics Cas Semiconductor device structure and manufacturing method thereof
US8921192B2 (en) * 2011-10-26 2014-12-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US20130109144A1 (en) * 2011-10-26 2013-05-02 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9178060B2 (en) 2011-10-26 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

Also Published As

Publication number Publication date Type
KR20040049658A (en) 2004-06-12 application
KR100487922B1 (en) 2005-05-06 grant
US6852559B2 (en) 2005-02-08 grant
US20040108558A1 (en) 2004-06-10 application

Similar Documents

Publication Publication Date Title
US6617226B1 (en) Semiconductor device and method for manufacturing the same
US7345341B2 (en) High voltage semiconductor devices and methods for fabricating the same
US7459752B2 (en) Ultra thin body fully-depleted SOI MOSFETs
US6432754B1 (en) Double SOI device with recess etch and epitaxy
US6566734B2 (en) Semiconductor device
US5436190A (en) Method for fabricating semiconductor device isolation using double oxide spacers
US6483158B1 (en) Semiconductor memory device and fabrication method therefor
US6455362B1 (en) Double LDD devices for improved dram refresh
US6787423B1 (en) Strained-silicon semiconductor device
US6333234B1 (en) Method for making a HVMOS transistor
US7101763B1 (en) Low capacitance junction-isolation for bulk FinFET technology
EP1091413A2 (en) Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US7326634B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US6509613B1 (en) Self-aligned floating body control for SOI device through leakage enhanced buried oxide
US4373965A (en) Suppression of parasitic sidewall transistors in locos structures
US6495898B1 (en) Semiconductor device and method of manufacturing the same
US6501135B1 (en) Germanium-on-insulator (GOI) device
US20110042729A1 (en) Method for improving selectivity of epi process
US5969393A (en) Semiconductor device and method of manufacture of the same
US20020076879A1 (en) Integrated circuit devices having trench isolation structures and methods of fabricating the same
US20050098094A1 (en) Semiconductor device having partially insulated field effect transistor (PiFET) and method of fabricating the same
US20060131648A1 (en) Ultra thin film SOI MOSFET having recessed source/drain structure and method of fabricating the same
US6541343B1 (en) Methods of making field effect transistor structure with partially isolated source/drain junctions
US7071515B2 (en) Narrow width effect improvement with photoresist plug process and STI corner ion implantation
US20070134859A1 (en) Strained silicon MOS device with box layer between the source and drain regions