US20050074943A1 - [method of fabricating deep trench capacitor] - Google Patents
[method of fabricating deep trench capacitor] Download PDFInfo
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- US20050074943A1 US20050074943A1 US10/707,357 US70735703A US2005074943A1 US 20050074943 A1 US20050074943 A1 US 20050074943A1 US 70735703 A US70735703 A US 70735703A US 2005074943 A1 US2005074943 A1 US 2005074943A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
Definitions
- the present invention relates to a method of fabricating a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method of fabricating a deep trench capacitor.
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- device miniaturization means the area for accommodating each DRAM capacitor is reduced.
- an increase in the processing power of computer software demands more memory capacity to run each software program.
- the demand for more memory storage capacity from a smaller chip necessarily requires a modification of the method of fabricating the DRAM capacitor.
- DRAM can be divided into a stack capacitor DRAM and a deep trench capacitor DRAM.
- Stack capacitor is currently the most conventional semiconductor capacitor.
- means of increasing the surface area of a stack capacitor includes performing a hemi-spherical grain (HSG) process or modifying the shape of the capacitor such as forming a crown, a fin, a cylinder or a spread-out structure.
- HSG hemi-spherical grain
- FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a conventional deep trench capacitor.
- a substrate 100 having a patterned liner layer 102 and a patterned mask layer 104 thereon is provided. Thereafter, using the liner layer 102 and the mask layer 104 as an etching mask, a deep trench 106 is formed in the substrate 100 .
- a bottom electrode 108 is formed at a bottom of the deep trench 106 in the substrate 100 and then a capacitor dielectric layer 110 and a polysilicon layer 112 are sequentially formed at the bottom of the deep trench 106 .
- a collar oxide layer 114 is formed over the mask layer 104 and the surface of the deep trench 106 .
- an anisotropic etching process is carried out to remove the collar oxide layer 114 on the surface of the mask layer 104 and the polysilicon layer 112 to retain a collar oxide layer 114 a on the sidewall of the deep trench 106 .
- polysilicon material is deposited into the deep trench 106 to form a polysilicon layer 118 . Due to the high level of integration, width of each deep trench 106 is increasingly narrow and hence the aspect ratio of each deep trench 106 is increasingly high. With a large aspect ratio, polysilicon material deposited into the deep trench 106 through a chemical vapor deposition process can hardly fill the entire space and a large seam 120 is thereby formed within the polysilicon layer 118 .
- the polysilicon layer 118 outside the deep trench 106 and a portion of the polysilicon layer 118 inside the deep trench 106 is removed to form a polysilicon layer 118 a.
- the mask layer 104 is also abraded to produce some defects 116 .
- the collar oxide layer 114 a not covered by the polysilicon layer 118 a is removed. Thereafter, a polysilicon layer 122 is formed inside the deep trench 106 .
- the polysilicon layers ( 112 , 118 a and 122 ) are electrically connected to form an upper electrode of the capacitor.
- the seam 120 inside the polysilicon layer 118 a can be reduced by recessing, the presence of the seam 120 a often leads to electrical connectivity problems in the polysilicon layers ( 122 and 118 a ). With poor connectivity in the device, the capacitor may malfunction and lead to a breakdown of the memory cell.
- the mask layer 104 contains defects 116 after the recessing process, planarity and uniformity of a subsequently polished surface using the mask layer 104 as a polishing stop layer is likely to be affected. Furthermore, the defects 116 may affect the recessing of the polysilicon layer and subsequent depth measurement leading to a drop in the yield of the device.
- one objective of the present invention is to provide a method of fabricating a deep trench capacitor capable of reducing (or entirely eliminating) overall size of the seam in the conductive layer (the upper electrode) of a conventional deep trench capacitor.
- Another objective of this invention is to provide a method of fabricating a deep trench capacitor capable of minimizing the effects caused by the planarization of the conductive material layer using a polishing stop layer with a defective profile in a conventional deep trench fabrication process.
- the process of recessing the polysilicon layer and subsequent depth measurement are negligibly affected.
- the invention provides a method of fabricating a deep trench capacitor.
- a substrate with a patterned liner layer and a patterned mask layer thereon, and a deep trench therein is provided.
- a bottom electrode has already been formed at a bottom of the deep trench in the substrate and a capacitor dielectric layer has already been formed on the surface of the deep trench.
- a first conductive layer is formed at the bottom of the deep trench.
- a protective layer is formed on the mask layer and the surface of the deep trench. The protective layer is formed in a plasma-enhanced chemical vapor deposition process.
- the depositing rate on a horizontal surface is higher than on a vertical surface so that the vertical surface of the deep trench is coated with a thin protective layer.
- a collar oxide layer is formed on the surface of the protective layer.
- the protective layer and the collar oxide layer on the surface of the first conductive layer are removed.
- Material is deposited into the deep trench to form a material layer.
- a portion of the material layer inside the deep trench is removed to form a first opening such that the upper surface of the material layer is at a level higher than the liner layer. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed.
- a portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening having a width greater than the first opening.
- the material layer is next removed.
- Conductive material is deposited into the deep trench to form a second conductive layer.
- a portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench.
- the collar oxide layer and the protective layer on the sidewall of the deep trench not covered by the second conductive layer are removed.
- conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- a protective layer with an removal rate smaller than the collar oxide layer is formed over the mask layer.
- the protective layer can serve as an etching stop layer.
- the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is always maintained.
- the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- an additional process for removing a portion of the material from the sidewall of the first opening and enlarging the first opening is provided. This process reduces the aspect ratio of the deep trench and prevents the formation of a large seam in the conductive material filling the deep trench.
- This invention also provides an alternative method of fabricating a deep trench capacitor.
- a substrate with a patterned liner layer and a patterned mask layer thereon and a deep trench therein is provided. Furthermore, a bottom electrode has already been formed at a bottom of the deep trench in the substrate and a capacitor dielectric layer has already been formed on the surface of the deep trench.
- a first conductive layer is formed at the bottom of the deep trench.
- a collar oxide layer is formed on the mask layer and the surface of the deep trench. The collar oxide layer on the surface of the first conductive layer is removed. Material is deposited into the deep trench to form a material layer.
- a portion of the material layer inside the deep trench is removed to form a first opening such that the upper surface of the material layer is at a level higher than the liner layer. Thereafter, the collar oxide layer not covered by the material layer is removed. A portion of the mask layer on the sidewall of the first opening is removed to form a second opening having a width greater than the first opening. The material layer is next removed. Conductive material is deposited into the deep trench to form a second conductive layer. A portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench. The collar oxide layer on the sidewall of the deep trench not covered by the second conductive layer is removed. Finally, conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- an additional process for removing a portion of the material from the sidewall of the first opening and enlarging the first opening is provided. This process reduces the aspect ratio of the deep trench and prevents the formation of a large seam in the conductive material filling the deep trench.
- This invention also provides yet another method of fabricating a deep trench capacitor.
- a substrate with a patterned mask layer thereon and a deep trench therein is provided. Furthermore, a bottom electrode has already been formed at a bottom of the deep trench and a capacitor dielectric layer has already been formed on the surface of the deep trench.
- a first conductive layer is formed at the bottom of the deep trench.
- a protective layer is formed on the mask layer and the surface of the deep trench.
- the protective layer is formed in a plasma-enhanced chemical vapor deposition process. In the plasma-enhanced chemical vapor deposition process, the depositing rate on a horizontal surface is higher than on a vertical surface so that the vertical surface of the deep trench is coated with a thin protective layer.
- a collar oxide layer is formed on the surface of the protective layer.
- the protective layer and the collar oxide layer on the surface of the first conductive layer are removed.
- Conductive material is deposited into the deep trench to form a second conductive layer.
- a portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench.
- the collar oxide layer and the protective layer on the sidewall of the deep trench not covered by the second conductive layer are removed.
- conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- a protective layer with an removal rate smaller than the collar oxide layer is formed over the mask layer.
- the protective layer can serve as an etching stop layer.
- the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is always maintained.
- the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- FIGS. 1A through 1D are schematic cross-sectional views showing the steps of fabricating a conventional deep trench capacitor.
- FIGS. 2A through 2H are schematic cross-sectional views showing the progression of steps of fabricating a deep trench capacitor according to one preferred embodiment of this invention.
- FIGS. 2A through 2H are schematic cross-sectional views showing the progression of steps of fabricating a deep trench capacitor according to one preferred embodiment of this invention.
- a substrate 200 having a patterned liner layer 202 and a patterned mask layer 204 thereon is provided.
- the liner layer 202 is a silicon oxide layer and the mask layer 204 is a silicon nitride layer, for example.
- the patterned liner layer 202 and the mask layer 204 are formed, for example, by performing a thermal oxidation to form a liner layer 202 over the entire substrate 200 , performing a chemical vapor deposition process to form a mask layer 204 over the liner layer 202 and finally carrying out a photolithographic and etching process on the mask layer 204 and the liner layer 202 . Thereafter, using the mask layer 204 and the liner layer 202 as an etching mask, an etching process such as a dry etching process is carried out to form a deep trench in the substrate 200 . A doped insulating layer 208 is formed on the sidewall of the deep trench 206 .
- the doped insulation layer 208 is an arsenic doped silicon oxide layer formed, for example, by performing a chemical vapor deposition process with in-situ doping.
- a photoresist layer 210 is formed at a bottom of the deep trench 206 .
- the photoresist layer 210 partially fills the deep trench 206 so that the upper surface of the photoresist layer 210 is at a level well below an upper surface 200 a of the substrate 200 .
- a portion of the doped insulating layer 208 not covered by the photoresist layer 210 is removed in a wet etching process using buffered hydrofluoric acid (BHF) or diluted hydrofluoric acid (diluted HF) as the etching agent. Thereafter, the photoresist layer 210 is removed and a conformal insulating layer 212 is formed over the substrate 200 to cover the mask layer 204 and the surface of the deep trench 206 .
- the insulating layer 212 is a silicon oxide layer formed, for example, by carrying out a chemical vapor deposition process using tetraethyl-ortho-silicate (TEOS)/ozone (O 3 ) as the reactive gases.
- TEOS tetraethyl-ortho-silicate
- O 3 ozone
- a thermal processing of the substrate 200 is carried out so that dopants within the doped insulating layer 208 a diffuse into the substrate 200 at the bottom of the deep trench 206 in the substrate 200 to form a doped region 214 .
- the doped region 214 serves as a bottom electrode in the final deep trench capacitor. Since the insulating layer 212 over the surface of the deep trench 206 is effective in stopping the outward diffusion of the dopants from the doped insulating layer 208 a, the diffusion of dopants is constrained within the bottom of the deep trench 206 . Thereafter, the doped insulating layer 208 a and the insulating layer 212 at the bottom of the deep trench 206 is removed.
- the insulating layers 208 a and 212 are removed, for example, by performing a wet etching process using buffered hydrofluoric acid (BHF) or diluted hydrofluoric acid (diluted HF) as the etchant.
- BHF buffered hydrofluoric acid
- a conformal capacitor dielectric layer 216 is formed over the surface of the deep trench 206 to cover the bottom electrode 214 .
- the capacitor dielectric layer 216 is an oxide/nitride composite layer formed by performing a thermal oxidation process or a chemical vapor deposition process, for example.
- a conductive material layer 218 is formed partially filling the deep trench 206 .
- the conductive material layer 218 is a doped polysilicon layer formed by performing a chemical vapor deposition process with in-situ doping and then removing the doped polysilicon layer outside the deep trench 206 and a portion of the doped polysilicon layer at a top of the deep trench 206 .
- the doped polysilicon layer is removed, for example, by performing a dry etching process or a wet etching process.
- the capacitor dielectric layer 216 not covered by the conductive layer 218 is removed to form a capacitor dielectric layer 216 a.
- the capacitor dielectric material is removed, for example, by performing a dry etching process or a wet etching process.
- a protective layer 220 is formed over the mask layer 204 and the surface of the deep trench 206 .
- the protective layer 220 can be fabricated using a material including silicon oxide or silicon oxynitride, for example.
- a plasma-enhanced chemical vapor deposition process is performed using tetra-ethyl-ortho-silicate (TEOS)/ozone (O 3 ) as the reactive gases.
- TEOS tetra-ethyl-ortho-silicate
- O 3 ozone
- a thin protective layer 220 ( 220 b ) is formed on the vertical surface of the deep trench 206 .
- three protective layers 220 a, 220 b and 220 c can be distinguished.
- the protective layer 220 a is positioned over the mask layer 204
- the protective layer 220 b is positioned on the sidewall of the deep trench 206
- the protective layer 220 c is positioned over the conductive layer 218 .
- the protective layer 200 a has a thickness greater than the protective layer 200 c and the protective layer 200 c has a thickness greater than the protective layer 200 b.
- a conformal collar oxide layer 222 is formed over the protective layer 220 ( 220 a, 220 b and 220 c ).
- the collar oxide layer 222 is formed, for example, by performing a chemical vapor deposition process using ozone (O 3 )/tetra-ethyl-ortho-silicate (TEOS) as the reactive gases.
- the protective layer 220 c and the collar oxide layer 222 on the surface of the conductive layer 218 is removed to form a collar oxide layer 222 a.
- material is deposited into the deep trench 206 to form a material layer 224 with an upper surface at a level higher than the linear layer 202 .
- the material layer 224 is a photoresist layer or a anti-reflection coating formed, for example, by filling the deep trench 206 with the material and then recessing the material so that an opening 226 is also formed.
- the collar oxide layer 222 a and the thin protective layer 220 b on the sidewall of the deep trench 206 not covered by the material layer 224 is removed.
- the protective layer 220 a Since the protective layer 220 a has a thickness greater than the protective layer 220 b, the protective layer 220 a is retained after removing the protective layer 220 b.
- the collar oxide layer 222 a and the thin protective layer 220 b are removed by performing a wet etching process, for example.
- the removal rate for the protective layers 220 a and 220 b is between 20 to 35 ⁇ /min and the removal rate for the collar oxide layer 222 a is between about 40 to 65 ⁇ /min. It is to be noted that the removal rate of the protective layer 220 a is considerably smaller than the collar oxide layer 222 a.
- the protective layer 220 a may serve as an etching stop layer in the removal of the collar oxide layer 222 a.
- the protective layer 220 a has such as a low removal rate and capacity to withstand corrosion, it protects the underlying mask layer 204 against any change in profile.
- the protective layer 220 a and the mask layer 204 may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- a portion of the mask layer 204 and the protective layer 220 a on the sidewall of the opening 226 is removed to form a mask layer 204 a, a protective layer 220 d and a wider opening 228 .
- the opening 228 is wider than the opening 226 by about 5 to 20 nm.
- the mask layer 204 and the protective layer 220 a are removed by performing a wet etching process using hydrofluoric acid/ethylene glycol (HF/EG) or phosphoric acid (H 3 PO 4 ) as the etchant, for example. Thereafter, the material layer 224 is removed by performing a wet etching process, for example.
- Conductive material is deposited into the deep trench 206 to form a conductive layer 230 .
- the conductive layer 230 is a doped polysilicon layer or a polysilicon layer formed in the same way as the conductive layer 218 . Furthermore, the conductive layer 218 and the conductive layer 230 are electrically connected together. Because the opening 226 has been enlarged to decrease the aspect ratio of the deep trench 206 , the seam after performing a conventional conductive material deposition process is reduced (or completely eliminated) when the conductive layer 230 is formed.
- a recessing process is carried out to remove the conductive layer 230 outside the deep trench 206 and a portion of the conductive layer 230 at a top of the deep trench 206 to form a conductive layer 230 a.
- the conductive layer 230 a has an upper surface below the surface 200 a of the substrate 200 .
- the collar oxide layer 222 a and the protective layer 220 b on the sidewall of the deep trench 206 not covered by the conductive layer 230 a is removed to form a collar oxide layer 222 b.
- Another conductive layer 232 is formed inside the deep trench 206 .
- the conductive layer 232 is a doped polysilicon layer or a polysilicon layer formed in the same way as the conductive layers ( 230 a or 218 ), for example. Furthermore, all the conductive layers ( 218 , 230 a and 232 ) are electrically connected together to serve as a top electrode of the capacitor.
- a protective layer with a removal rate smaller than the collar oxide layer is formed over the mask layer.
- the protective layer can serve as an etching stop layer.
- the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is maintained.
- the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- This invention also provides an additional step for removing a portion of the sidewall material to enlarge the first opening. This reduces the aspect ratio of the deep trench so that the large seam normally present after performing a conventional conductive material deposition process is reduced.
Abstract
Description
- This application claims the priority benefit of Taiwan application serial no. 92127382, filed on Oct. 3, 2003.
- 1. Field of the Invention
- The present invention relates to a method of fabricating a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method of fabricating a deep trench capacitor.
- 2. Description of the Related Art
- In the deep sub-micron regime of semiconductor production, size of each device is greatly reduced. For dynamic random access memory (DRAM), device miniaturization means the area for accommodating each DRAM capacitor is reduced. On the other hand, an increase in the processing power of computer software demands more memory capacity to run each software program. The demand for more memory storage capacity from a smaller chip necessarily requires a modification of the method of fabricating the DRAM capacitor.
- According to the structure of the capacitor, DRAM can be divided into a stack capacitor DRAM and a deep trench capacitor DRAM. With the miniaturization of semiconductor device, both the stack capacitor and the deep trench capacitor DRAM encounters increasingly difficult processing problems. Stack capacitor is currently the most conventional semiconductor capacitor. At present, means of increasing the surface area of a stack capacitor includes performing a hemi-spherical grain (HSG) process or modifying the shape of the capacitor such as forming a crown, a fin, a cylinder or a spread-out structure.
- Although stack capacitor is popular, planarization is a big issue that needs to be solved before the memory device can be further miniaturized. Because deep trench capacitors are formed in a substrate, the fabrication of miniaturized memory device is easier. Nevertheless, as semiconductor devices continue to shrink, width of the trenches must be reduced accordingly. As a result, there is a corresponding increase in the aspect ratio of the trenches. With an increase in the aspect ratio, forming deep trenches with the desired profile through photolithographic and etching process and the subsequent filling of the trenches with a conductive material is increasingly difficult.
-
FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a conventional deep trench capacitor. As shown inFIG. 1A , asubstrate 100 having a patternedliner layer 102 and a patternedmask layer 104 thereon is provided. Thereafter, using theliner layer 102 and themask layer 104 as an etching mask, adeep trench 106 is formed in thesubstrate 100. Abottom electrode 108 is formed at a bottom of thedeep trench 106 in thesubstrate 100 and then a capacitordielectric layer 110 and apolysilicon layer 112 are sequentially formed at the bottom of thedeep trench 106. Acollar oxide layer 114 is formed over themask layer 104 and the surface of thedeep trench 106. - As shown in
FIG. 1B , an anisotropic etching process is carried out to remove thecollar oxide layer 114 on the surface of themask layer 104 and thepolysilicon layer 112 to retain acollar oxide layer 114 a on the sidewall of thedeep trench 106. Thereafter, polysilicon material is deposited into thedeep trench 106 to form apolysilicon layer 118. Due to the high level of integration, width of eachdeep trench 106 is increasingly narrow and hence the aspect ratio of eachdeep trench 106 is increasingly high. With a large aspect ratio, polysilicon material deposited into thedeep trench 106 through a chemical vapor deposition process can hardly fill the entire space and alarge seam 120 is thereby formed within thepolysilicon layer 118. - As shown in
FIG. 1C , thepolysilicon layer 118 outside thedeep trench 106 and a portion of thepolysilicon layer 118 inside thedeep trench 106 is removed to form apolysilicon layer 118 a. In the process of recessing thepolysilicon layer 118, themask layer 104 is also abraded to produce somedefects 116. - As shown in
FIG. 1D , thecollar oxide layer 114 a not covered by thepolysilicon layer 118 a is removed. Thereafter, apolysilicon layer 122 is formed inside thedeep trench 106. The polysilicon layers (112, 118 a and 122) are electrically connected to form an upper electrode of the capacitor. - In the aforementioned process, although the
seam 120 inside thepolysilicon layer 118 a can be reduced by recessing, the presence of theseam 120 a often leads to electrical connectivity problems in the polysilicon layers (122 and 118 a). With poor connectivity in the device, the capacitor may malfunction and lead to a breakdown of the memory cell. - Because the
mask layer 104 containsdefects 116 after the recessing process, planarity and uniformity of a subsequently polished surface using themask layer 104 as a polishing stop layer is likely to be affected. Furthermore, thedefects 116 may affect the recessing of the polysilicon layer and subsequent depth measurement leading to a drop in the yield of the device. - Accordingly, one objective of the present invention is to provide a method of fabricating a deep trench capacitor capable of reducing (or entirely eliminating) overall size of the seam in the conductive layer (the upper electrode) of a conventional deep trench capacitor.
- Another objective of this invention is to provide a method of fabricating a deep trench capacitor capable of minimizing the effects caused by the planarization of the conductive material layer using a polishing stop layer with a defective profile in a conventional deep trench fabrication process. Thus, the process of recessing the polysilicon layer and subsequent depth measurement are negligibly affected.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a deep trench capacitor. First, a substrate with a patterned liner layer and a patterned mask layer thereon, and a deep trench therein is provided. Furthermore, a bottom electrode has already been formed at a bottom of the deep trench in the substrate and a capacitor dielectric layer has already been formed on the surface of the deep trench. Thereafter, a first conductive layer is formed at the bottom of the deep trench. A protective layer is formed on the mask layer and the surface of the deep trench. The protective layer is formed in a plasma-enhanced chemical vapor deposition process. In the plasma-enhanced chemical vapor deposition process, the depositing rate on a horizontal surface is higher than on a vertical surface so that the vertical surface of the deep trench is coated with a thin protective layer. A collar oxide layer is formed on the surface of the protective layer. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed. Material is deposited into the deep trench to form a material layer. A portion of the material layer inside the deep trench is removed to form a first opening such that the upper surface of the material layer is at a level higher than the liner layer. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed. A portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening having a width greater than the first opening. The material layer is next removed. Conductive material is deposited into the deep trench to form a second conductive layer. A portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench. The collar oxide layer and the protective layer on the sidewall of the deep trench not covered by the second conductive layer are removed. Finally, conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- In the aforementioned method of fabricating the deep trench capacitor, a protective layer with an removal rate smaller than the collar oxide layer is formed over the mask layer. When the collar oxide layer is removed, the protective layer can serve as an etching stop layer. Furthermore, because the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is always maintained. In a subsequent polishing process, the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- In this invention, an additional process for removing a portion of the material from the sidewall of the first opening and enlarging the first opening is provided. This process reduces the aspect ratio of the deep trench and prevents the formation of a large seam in the conductive material filling the deep trench.
- This invention also provides an alternative method of fabricating a deep trench capacitor. First, a substrate with a patterned liner layer and a patterned mask layer thereon and a deep trench therein is provided. Furthermore, a bottom electrode has already been formed at a bottom of the deep trench in the substrate and a capacitor dielectric layer has already been formed on the surface of the deep trench. Thereafter, a first conductive layer is formed at the bottom of the deep trench. A collar oxide layer is formed on the mask layer and the surface of the deep trench. The collar oxide layer on the surface of the first conductive layer is removed. Material is deposited into the deep trench to form a material layer. A portion of the material layer inside the deep trench is removed to form a first opening such that the upper surface of the material layer is at a level higher than the liner layer. Thereafter, the collar oxide layer not covered by the material layer is removed. A portion of the mask layer on the sidewall of the first opening is removed to form a second opening having a width greater than the first opening. The material layer is next removed. Conductive material is deposited into the deep trench to form a second conductive layer. A portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench. The collar oxide layer on the sidewall of the deep trench not covered by the second conductive layer is removed. Finally, conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- In this invention, an additional process for removing a portion of the material from the sidewall of the first opening and enlarging the first opening is provided. This process reduces the aspect ratio of the deep trench and prevents the formation of a large seam in the conductive material filling the deep trench.
- This invention also provides yet another method of fabricating a deep trench capacitor. First, a substrate with a patterned mask layer thereon and a deep trench therein is provided. Furthermore, a bottom electrode has already been formed at a bottom of the deep trench and a capacitor dielectric layer has already been formed on the surface of the deep trench. Thereafter, a first conductive layer is formed at the bottom of the deep trench. A protective layer is formed on the mask layer and the surface of the deep trench. The protective layer is formed in a plasma-enhanced chemical vapor deposition process. In the plasma-enhanced chemical vapor deposition process, the depositing rate on a horizontal surface is higher than on a vertical surface so that the vertical surface of the deep trench is coated with a thin protective layer. A collar oxide layer is formed on the surface of the protective layer. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed. Conductive material is deposited into the deep trench to form a second conductive layer. A portion of the second conductive layer at the top of the deep trench is removed so that the second conductive layer only partially fills the deep trench. The collar oxide layer and the protective layer on the sidewall of the deep trench not covered by the second conductive layer are removed. Finally, conductive material is deposited into the deep trench to form a third conductive layer that completely fills the trench.
- In the aforementioned method of fabricating the deep trench capacitor, a protective layer with an removal rate smaller than the collar oxide layer is formed over the mask layer. Hence, in the process of removing the collar oxide layer, the protective layer can serve as an etching stop layer. Furthermore, because the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is always maintained. In a subsequent polishing process, the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIGS. 1A through 1D are schematic cross-sectional views showing the steps of fabricating a conventional deep trench capacitor. -
FIGS. 2A through 2H are schematic cross-sectional views showing the progression of steps of fabricating a deep trench capacitor according to one preferred embodiment of this invention. - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIGS. 2A through 2H are schematic cross-sectional views showing the progression of steps of fabricating a deep trench capacitor according to one preferred embodiment of this invention. First, as shown inFIG. 2A , asubstrate 200 having a patternedliner layer 202 and apatterned mask layer 204 thereon is provided. Theliner layer 202 is a silicon oxide layer and themask layer 204 is a silicon nitride layer, for example. The patternedliner layer 202 and themask layer 204 are formed, for example, by performing a thermal oxidation to form aliner layer 202 over theentire substrate 200, performing a chemical vapor deposition process to form amask layer 204 over theliner layer 202 and finally carrying out a photolithographic and etching process on themask layer 204 and theliner layer 202. Thereafter, using themask layer 204 and theliner layer 202 as an etching mask, an etching process such as a dry etching process is carried out to form a deep trench in thesubstrate 200. A doped insulatinglayer 208 is formed on the sidewall of thedeep trench 206. The dopedinsulation layer 208 is an arsenic doped silicon oxide layer formed, for example, by performing a chemical vapor deposition process with in-situ doping. Aphotoresist layer 210 is formed at a bottom of thedeep trench 206. Thephotoresist layer 210 partially fills thedeep trench 206 so that the upper surface of thephotoresist layer 210 is at a level well below anupper surface 200 a of thesubstrate 200. - As shown in
FIG. 2B , a portion of the doped insulatinglayer 208 not covered by thephotoresist layer 210 is removed in a wet etching process using buffered hydrofluoric acid (BHF) or diluted hydrofluoric acid (diluted HF) as the etching agent. Thereafter, thephotoresist layer 210 is removed and a conformal insulatinglayer 212 is formed over thesubstrate 200 to cover themask layer 204 and the surface of thedeep trench 206. The insulatinglayer 212 is a silicon oxide layer formed, for example, by carrying out a chemical vapor deposition process using tetraethyl-ortho-silicate (TEOS)/ozone (O3) as the reactive gases. - As shown in
FIG. 2C , a thermal processing of thesubstrate 200 is carried out so that dopants within the doped insulatinglayer 208 a diffuse into thesubstrate 200 at the bottom of thedeep trench 206 in thesubstrate 200 to form a dopedregion 214. The dopedregion 214 serves as a bottom electrode in the final deep trench capacitor. Since the insulatinglayer 212 over the surface of thedeep trench 206 is effective in stopping the outward diffusion of the dopants from the doped insulatinglayer 208 a, the diffusion of dopants is constrained within the bottom of thedeep trench 206. Thereafter, the doped insulatinglayer 208 a and the insulatinglayer 212 at the bottom of thedeep trench 206 is removed. The insulatinglayers - As shown in
FIG. 2D , a conformalcapacitor dielectric layer 216 is formed over the surface of thedeep trench 206 to cover thebottom electrode 214. Thecapacitor dielectric layer 216 is an oxide/nitride composite layer formed by performing a thermal oxidation process or a chemical vapor deposition process, for example. Thereafter, aconductive material layer 218 is formed partially filling thedeep trench 206. Theconductive material layer 218 is a doped polysilicon layer formed by performing a chemical vapor deposition process with in-situ doping and then removing the doped polysilicon layer outside thedeep trench 206 and a portion of the doped polysilicon layer at a top of thedeep trench 206. The doped polysilicon layer is removed, for example, by performing a dry etching process or a wet etching process. - As shown in
FIG. 2E , thecapacitor dielectric layer 216 not covered by theconductive layer 218 is removed to form acapacitor dielectric layer 216 a. The capacitor dielectric material is removed, for example, by performing a dry etching process or a wet etching process. Thereafter, aprotective layer 220 is formed over themask layer 204 and the surface of thedeep trench 206. Theprotective layer 220 can be fabricated using a material including silicon oxide or silicon oxynitride, for example. To form a silicon oxideprotective layer 220, a plasma-enhanced chemical vapor deposition process is performed using tetra-ethyl-ortho-silicate (TEOS)/ozone (O3) as the reactive gases. Because the depositing rate of theprotective layer 220 on a horizontal surface is much greater than the depositing rate on a vertical surface, a thin protective layer 220 (220 b) is formed on the vertical surface of thedeep trench 206. Thus, according to the thickness of theprotective layer 220, threeprotective layers protective layer 220 a is positioned over themask layer 204, theprotective layer 220 b is positioned on the sidewall of thedeep trench 206 and theprotective layer 220 c is positioned over theconductive layer 218. Furthermore, theprotective layer 200 a has a thickness greater than the protective layer 200 c and the protective layer 200 c has a thickness greater than the protective layer 200 b. Thereafter, a conformalcollar oxide layer 222 is formed over the protective layer 220 (220 a, 220 b and 220 c). Thecollar oxide layer 222 is formed, for example, by performing a chemical vapor deposition process using ozone (O3)/tetra-ethyl-ortho-silicate (TEOS) as the reactive gases. - As shown in
FIG. 2F , theprotective layer 220 c and thecollar oxide layer 222 on the surface of theconductive layer 218 is removed to form acollar oxide layer 222 a. Thereafter, material is deposited into thedeep trench 206 to form amaterial layer 224 with an upper surface at a level higher than thelinear layer 202. Thematerial layer 224 is a photoresist layer or a anti-reflection coating formed, for example, by filling thedeep trench 206 with the material and then recessing the material so that anopening 226 is also formed. Thecollar oxide layer 222 a and the thinprotective layer 220 b on the sidewall of thedeep trench 206 not covered by thematerial layer 224 is removed. Since theprotective layer 220 a has a thickness greater than theprotective layer 220 b, theprotective layer 220 a is retained after removing theprotective layer 220 b. Thecollar oxide layer 222 a and the thinprotective layer 220 b are removed by performing a wet etching process, for example. The removal rate for theprotective layers collar oxide layer 222 a is between about 40 to 65 Å/min. It is to be noted that the removal rate of theprotective layer 220 a is considerably smaller than thecollar oxide layer 222 a. Hence, theprotective layer 220 a may serve as an etching stop layer in the removal of thecollar oxide layer 222 a. Because theprotective layer 220 a has such as a low removal rate and capacity to withstand corrosion, it protects theunderlying mask layer 204 against any change in profile. In a subsequent polishing process, theprotective layer 220 a and themask layer 204 may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement. - As shown in
FIG. 2G , a portion of themask layer 204 and theprotective layer 220 a on the sidewall of theopening 226 is removed to form amask layer 204 a, aprotective layer 220 d and awider opening 228. Theopening 228 is wider than theopening 226 by about 5 to 20 nm. Themask layer 204 and theprotective layer 220 a are removed by performing a wet etching process using hydrofluoric acid/ethylene glycol (HF/EG) or phosphoric acid (H3PO4) as the etchant, for example. Thereafter, thematerial layer 224 is removed by performing a wet etching process, for example. Conductive material is deposited into thedeep trench 206 to form aconductive layer 230. Theconductive layer 230 is a doped polysilicon layer or a polysilicon layer formed in the same way as theconductive layer 218. Furthermore, theconductive layer 218 and theconductive layer 230 are electrically connected together. Because theopening 226 has been enlarged to decrease the aspect ratio of thedeep trench 206, the seam after performing a conventional conductive material deposition process is reduced (or completely eliminated) when theconductive layer 230 is formed. - As shown in
FIG. 2H , a recessing process is carried out to remove theconductive layer 230 outside thedeep trench 206 and a portion of theconductive layer 230 at a top of thedeep trench 206 to form aconductive layer 230 a. Hence, theconductive layer 230 a has an upper surface below thesurface 200 a of thesubstrate 200. Thereafter, thecollar oxide layer 222 a and theprotective layer 220 b on the sidewall of thedeep trench 206 not covered by theconductive layer 230 a is removed to form acollar oxide layer 222 b. Anotherconductive layer 232 is formed inside thedeep trench 206. Theconductive layer 232 is a doped polysilicon layer or a polysilicon layer formed in the same way as the conductive layers (230 a or 218), for example. Furthermore, all the conductive layers (218, 230 a and 232) are electrically connected together to serve as a top electrode of the capacitor. - In fabricating the deep trench capacitor according to this invention, a protective layer with a removal rate smaller than the collar oxide layer is formed over the mask layer. Hence, in the process of removing the collar oxide layer, the protective layer can serve as an etching stop layer. Furthermore, because the protective layer has a small removal rate, damages to the protective layer are minimal after the etching process. Therefore, the protective layer is able to protect the underlying mask layer so that a constant profile is maintained. In a subsequent polishing process, the protective layer or the mask layer may serve as a polishing stop layer for providing a high degree of polishing planarity and uniformity and minimizing the effects of recessing process of polysilicon and depth measurement.
- This invention also provides an additional step for removing a portion of the sidewall material to enlarge the first opening. This reduces the aspect ratio of the deep trench so that the large seam normally present after performing a conventional conductive material deposition process is reduced.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (25)
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TW092127382A TWI229414B (en) | 2003-10-03 | 2003-10-03 | Method of fabricating deep trench capacitor |
TW92127382 | 2003-10-03 |
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US20050074943A1 true US20050074943A1 (en) | 2005-04-07 |
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US20080277760A1 (en) * | 2007-05-07 | 2008-11-13 | Qimonda Ag | Integrated circuit device having openings in a layered structure |
WO2013048872A1 (en) * | 2011-09-26 | 2013-04-04 | Applied Materials, Inc. | Pretreatment and improved dielectric coverage |
US20170323962A1 (en) * | 2014-12-17 | 2017-11-09 | Intel Corporation | Carrier confinement for high mobility channel devices |
CN113130746A (en) * | 2019-12-30 | 2021-07-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
US11088239B2 (en) | 2018-11-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cap structure for trench capacitors |
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KR100591016B1 (en) * | 2003-12-30 | 2006-06-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method |
US7344954B2 (en) * | 2006-01-03 | 2008-03-18 | United Microelectonics Corp. | Method of manufacturing a capacitor deep trench and of etching a deep trench opening |
US7888723B2 (en) * | 2008-01-18 | 2011-02-15 | International Business Machines Corporation | Deep trench capacitor in a SOI substrate having a laterally protruding buried strap |
US9443857B2 (en) | 2014-12-05 | 2016-09-13 | Globalfoundries Inc. | Vertical fin eDRAM |
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Also Published As
Publication number | Publication date |
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US6881620B1 (en) | 2005-04-19 |
TWI229414B (en) | 2005-03-11 |
TW200514205A (en) | 2005-04-16 |
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