US20050007825A1

US20050007825A1 - Memory cell strings in a resistive cross point memory cell array

Info

Publication number: US20050007825A1
Application number: US10/614,505
Authority: US
Inventors: Richard Hilton; Corbin Champion; Kenneth Smith; Frederick Perner
Original assignee: Hewlett Packard Development Co LP
Current assignee: Samsung Electronics Co Ltd
Priority date: 2003-07-07
Filing date: 2003-07-07
Publication date: 2005-01-13
Also published as: DE102004011419A1; JP2005032416A; JP2008091015A; US6842364B1

Abstract

A method for performing a read operation from a memory cell in a memory cell string is provided. The method includes applying a constant current across the memory cell string, measuring a first voltage across the memory cell string, writing the memory cell to a first state, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.

Description

BACKGROUND OF THE INVENTION

Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that may be suitable for long term data storage. MRAM devices may perform read and write operations faster than conventional long term storage devices such as hard drives. In addition, MRAM devices may be more compact and may consume less power than conventional storage devices.
A typical MRAM device may include an array of memory cells where word lines extend along rows of the memory cells and bit lines extend along columns of the memory cells. Each memory cell may be located at a cross point of a word line and a bit line.
A memory cell in an MRAM device stores a bit of information according to an orientation of a magnetization. The magnetization of a memory cell assumes one of two stable orientations at a given time. These two orientations are known as parallel and anti-parallel and represent logic level values of ‘0’ and ‘1’, respectively.
The magnetization orientation affects the resistance of a memory cell such as a spin dependent tunneling junction device. For instance, the resistance of a memory cell is a first value R if the magnetization orientation is parallel, the resistance of the memory cell is increased to a second value (R+ΔR) if the magnetization orientation changed from parallel to anti-parallel. The magnetization orientation of a selected memory cell, and therefore the logic state of the memory cell, may be read by determining the resistance state of the selected memory cell.
One of the challenges with MRAM devices involves electrically isolating the circuits that comprise the memory cells while maintaining a sufficient level of packing density. Although additional components such as transistors may be used to increase the isolation of memory cells, an increase in the number of components typically results in a decrease in the packing density of the memory cells, i.e., the number of memory cells per a given area, and a decrease in the packing density generally results in increased costs. It would be desirable to be able to increase packing densities while increasing the electrical isolation of memory cells.

SUMMARY OF THE INVENTION

In one exemplary embodiment, the present disclosure provides a method of performing a read operation from a memory cell in a memory cell string. The method includes applying a constant current across the memory cell string, measuring a first voltage across the memory cell string, writing the memory cell to a first state, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 is a diagram illustrating an embodiment of a data storage device that includes memory cell strings.
FIG. 2 a is a diagram illustrating an embodiment of a parallel magnetization orientation of an MRAM memory cell.
FIG. 2 b is a diagram illustrating an embodiment of an anti-parallel magnetization orientation of an MRAM memory cell.
FIG. 3 is a diagram illustrating an embodiment of a first memory cell string.
FIG. 4 is a flow chart illustrating an embodiment of a first method for reading a memory cell in memory cell string.
FIG. 5 is a diagram illustrating an embodiment of a second memory cell string.
FIG. 6 is a flow chart illustrating an embodiment of a second method for reading a memory cell in memory cell string.
FIG. 7 is a diagram illustrating an embodiment of an MRAM device that includes multiple levels.
FIG. 8 is a diagram illustrating an embodiment of a system that includes one or more MRAM devices.

DETAILED DESCRIPTION

As shown in the drawings for purposes of illustration, the present invention is embodied in an MRAM device. The MRAM device includes an array of memory cells and circuitry for reliably sensing resistance states of the memory cells. The array of memory cells is divided into memory cell strings as described herein. To read a memory cell in a memory cell string, the total resistance of the string is determined before and after the memory cell is written to a first state using either a voltage or a current measurement. If the total resistance does not change after being written to the first state, then the memory cell was in the first state prior to being written to the first state. If the total resistance changes after being written to the first state, then the memory cell was in a second state prior to being written to the first state. In this case, the memory cell is written back to the second state.
Reference is now made to FIG. 1, which illustrates an embodiment of an MRAM device 8 including an array 10 of memory cell strings 12. Each memory cell string includes a plurality of memory cells as shown in the embodiments of FIGS. 3 and 5. The memory cell strings 12 are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Only a relatively small number of memory cell strings 12 are shown to simplify the description of the invention. In practice, arrays of any size may be used with any number of memory cell strings. The memory cell strings may each include any number of memory cells greater than or equal to two.
Traces functioning as word lines 14 extend along the x-direction in a plane on one side of the memory cell array 10. The word lines 14 shown in FIG. 1 represent one word line for each memory cell in memory cell strings 12. Traces functioning as bit lines 16 extend along the y-direction in a plane on an opposite side of the memory cell array 10. Each memory cell in memory cell strings 12 is located at a cross point of a corresponding word line 14 and bit line 16.
The memory cells are not limited to any particular type of device. For example the memory cells may be spin dependent tunneling (“SDT”) junction devices.
Referring now to FIGS. 2 a and 2 b, a typical SDT junction device includes a pinned layer 52. The free and pinned layers 50 and 52 are separated by an insulating tunnel barrier 51. The insulating tunnel barrier 51 allows quantum mechanical tunneling to occur between the free and pinned layers 50 and 52. This tunneling phenomenon is electron spin dependent, making the resistance of the SDT junction device 12 a function of the relative orientations of the magnetization of the free and pinned layers 50 and 52. For instance, resistance of the SDT junction device is a first value R if the orientation of magnetization of the free and pinned layers 50 and 52 is parallel and a second value (R+ΔR) if the magnetization of orientation is anti-parallel.
Returning to FIG. 1, the MRAM device 8 also includes a row decode circuit 18. During write operations, the row decode circuit 18 applies a write current to a selected word line 14 to cause a memory cell to be written to a desired state. During read operations, the row decode circuit 18 applies a write current to a selected word line 14 to cause a memory cell to be written to a known state and may apply a write current to the selected word line 14 to cause the memory cell to be written to a previous state.
The MRAM device 8 further includes a column decode circuit 20. During write operations, the column decode circuit 20 applies a write current to selected bit lines 16. During read operations, column decode circuit 20 selects a memory cell string 12 and connects the memory cell string 12 to detection circuit 26 using steering circuit 24.
The MRAM device 8 further includes a read circuit 22 for sensing the resistance of selected memory cells during read operations and a write circuit (not shown) for orienting the magnetization of selected memory cells during write operations.
The read circuit 22 includes a plurality of steering circuits 24 and detection circuits 26. Multiple bit lines 16 are connected to each steering circuit 24. Each steering circuit 24 includes a set of switches that connect a write current supply to a selected bit line 16 and connects a selected memory cell string 12 to a detection circuit 26. An output of the detection circuit 26 is supplied to a data register 30, which, in turn, is coupled to an I/O pad 32 of the MRAM device 8. If the MRAM device 8 has multiple levels of memory cell arrays (see, for example, FIG. 7), bit lines 16 and memory cell strings 12 from the additional levels may be multiplexed into the detection circuits 26.
Control circuit 34 provides control signals such as timing signals to row decode circuit 18, column decode circuit 20, and read circuit 22.
FIG. 3 illustrates an embodiment of memory cell string 12. Memory cell string 12 includes memory cells 70 a, 70 b, 70 c, and 70 d, as represented by resistors, coupled in series. Word lines 14 a, 14 b, 14 c, and 14 d are used to write memory cells 70 a, 70 b, 70 c, and 70 d, respectively, in conjunction with bit line 16.
A current source 72 is coupled to one end of memory cell string 12 and the other end of memory cell string 12 is coupled to a ground source. Current source 72 is configured to provide a constant current to memory cell string 12. Current source 72 provides the constant current to memory cell string 12 in response to control signals received from row decode circuit 18, column decode circuit 20, and/or control circuit 34. In particular, current source 72 provides current to the memory cell string 12 in response to a read operation to allow one or more of memory cells 70 a, 70 b, 70 c, and/or 70 d to be read.
A voltage detection circuit 74 is coupled to memory cell string 12 between current source 72 and memory cell 70 a. The voltage detection circuit 74 is configured to measure the voltage across memory cell string 12 in response to the current provided by current source 72. Voltage detection circuit 74 may be included as part of detection circuit 26.
FIG. 4 is a flow chart illustrating an embodiment of a method for reading a memory cell in the embodiment of memory cell string 12 shown in FIG. 3. In FIG. 4, a constant current is applied to memory cell string 12 by current source 72 as indicated in a block 402. A first voltage is measured across memory cell string 12 by voltage detection circuit 74 as indicated in a block 404.
A selected memory cell in memory cell string 12, e.g., memory cell 70 b, is written to a first state as indicated in a block 406. In one embodiment, the first state may be anti-parallel to represent a logic level of ‘1’. In other embodiments, the first state may be parallel to represent a logic level of ‘0’.
A second voltage is measured across memory cell string 12 by voltage detection circuit 74 as indicated in a block 408. The second voltage is measured subsequent to the selected memory cell, e.g., memory cell 70 b, being written to the first state.
A determination is made by detection circuit 26 as to whether the first voltage differs from the second voltage as indicated in a block 410. If the first voltage does not differ from the second voltage, then a first logic level associated with the first state is read out from the selected memory cell, e.g., memory cell 70 b, as indicated in a block 412. If the first voltage differs from the second voltage, then a second logic level associated with a second state is read out from the selected memory cell, e.g., memory cell 70 b, as indicated in a block 414. In addition, the selected memory cell, e.g., memory cell 70 b, is written to the second state as indicated in a block 416.
Detection circuit 26 causes the first or second state to be read out from the selected memory cell by causing a ‘1’ or a ‘0’ to be stored in register 30 and to be provided to I/O pad 32.
As noted above, the parallel state and the anti-parallel state cause different resistances to be measured across a memory cell. Because memory cell string 12 is supplied with a constant current source, the total resistance across memory cell string 12, i.e., the sum of the resistances of the memory cells 70 a, 70 b, 70 c, and 70 d, can be deduced by measuring the voltage across the string. After measuring a first voltage in block 404, the state of a selected memory cell is determined by writing the memory cell to a known state, e.g., anti-parallel, and determining whether the voltage across memory cell string 12 changed. If the voltage has changed when the second voltage measurement is taken in block 408, then the selected memory cell was in a state that was different than the known state, e.g., parallel, prior to being written to the known state. If the voltage has not changed when the second voltage measurement is taken in block 408, then the selected memory cell was in the known state, e.g., anti-parallel, prior to being written to the known state in block 406. In other words, if the voltage did not change in response to the write, then the state of the selected memory cell did not change either.
If the write in block 406 caused the state of the selected memory cell to change, then the memory cell is re-written to its original state as illustrated by block 416. If the write in block 406 did not cause the state of the selected memory cell to change, then the memory cell remains in its original state and may not need to be re-written.
Voltage detection circuit 74 may detect a change in the voltage across memory cell string 12 in various ways. For example, voltage detection circuit 74 may measure and store the first voltage, measure the second voltage, and compare the second voltage to the stored first voltage. Alternatively, voltage detection circuit 74 may continuously monitor the voltage across the memory cell string 12 and detect whether a change occurs in the voltage in response to the selected memory cell being written to the known state.
Control circuit 34 provides appropriate timing signals to row decode circuit 18, write decode circuit 20, read circuit 22, detection circuit 26, and voltage detection circuit 74 to allow the functions of the method shown in FIG. 4 to be performed.
Any one of the memory cells 70 a, 70 b, 70 c, and 70 d may be read using the method just described. Although four memory cells are shown in the memory cell string illustrated in FIG. 3, other memory cell strings may include other numbers of memory cells coupled in series.
FIG. 5 illustrates another embodiment of memory cell string 12. Memory cell string 12 includes memory cells 70 a, 70 b, 70 c, and 70 d, as represented by resistors, coupled in parallel. Word lines 14 a, 14 b, 14 c, and 14 d are used to write memory cells 70 a, 70 b, 70 c, and 70 d, respectively, in conjunction with bit line 16.
A voltage source 92 is coupled to one end of each memory cell 70 a, 70 b, 70 c, and 70 d, and the other end of each memory cell 70 a, 70 b, 70 c, and 70 d is coupled to a ground source. Voltage source 92 is configured to provide a constant voltage to memory cell string 12. Voltage source 92 provides the constant voltage to memory cell string 12 in response to control signals received from row decode circuit 18, column decode circuit 20, and/or control circuit 34. In particular, voltage source 72 provides voltage to the memory cell string 12 in response to a read operation to allow one or more of memory cells 70 a, 70 b, 70 c, and/or 70 d to be read.
A current detection circuit 94 is coupled to memory cell string 12 between the ends of memory cells 70 a, 70 b, 70 c, and 70 d and the ground source. The current detection circuit 94 is configured to measure the current across memory cell string 12 in response to the voltage provided by voltage source 92. Current detection circuit 94 may be included as part of detection circuit 26.
FIG. 6 is a flow chart illustrating an embodiment of a method for reading a memory cell in the embodiment of memory cell string 12 shown in FIG. 5. In FIG. 6, a constant voltage is applied to memory cell string 12 by voltage source 92 as indicated in a block 602. A first current is measured across memory cell string 12 by current detection circuit 94 as indicated in a block 604.
A selected memory cell in memory cell string 12, e.g., memory cell 70 c, is written to a first state as indicated in a block 606. As with the method described above in FIG. 4, the first state may be anti-parallel to represent a logic level of ‘1’ in one embodiment and may be parallel to represent a logic level of ‘0’ in other embodiments.
A second current is measured across memory cell string 12 by current detection circuit 94 as indicated in a block 608. The second current is measured subsequent to the selected memory cell, e.g., memory cell 70 c, being written to the first state.
A determination is made by detection circuit 26 as to whether the first current differs from the second current as indicated in a block 610. If the first current does not differ from the second current, then a first logic level associated with the first state is read out from the selected memory cell, e.g., memory cell 70 c, as indicated in a block 612. If the first current differs from the current voltage, then a second logic level associated with a second state is read out from the selected memory cell, e.g., memory cell 70 c, as indicated in a block 614. In addition, the selected memory cell, e.g., memory cell 70 c, is written to the second state as indicated in a block 616.
Detection circuit 26 causes the first or second state to be read out from the selected memory cell by causing a ‘1’ or a ‘0’ to be stored in register 30 and to be provided to I/O pad 32.
Because memory cell string 12 is supplied with a constant voltage source in the embodiment of FIG. 5, the total resistance across memory cell string 12 can be deduced by measuring the current across memory cell string 12. After measuring a first current in block 604, the state of a selected memory cell is determined by writing the memory cell to a known state, e.g., anti-parallel, and detecting whether the current across memory cell string 12 changed. If the current has changed when the second current measurement is taken in block 408, then the selected memory cell was in a state that was different than the known state, e.g., parallel, prior to being written to the known state. If the current has not changed when the second current measurement is taken in block 608, then the selected memory cell was in the known state, e.g., anti-parallel, prior to being written to the known state in block 606. In other words, if the current did not change in response to the write, then the state of the selected memory cell did not change either.
If the write in block 606 caused the state of the selected memory cell to change, then the memory cell is re-written to its original state as illustrated by block 616. If the write in block 606 did not cause the state of the selected memory cell to change, then the memory cell remains in its original state and may not need to be re-written.
Current detection circuit 94 may detect a change in the current across memory cell string 12 in various ways. For example, current detection circuit 94 may measure and store the first current, measure the second current, and compare the second current to the stored first current. Alternatively, current detection circuit 94 may continuously monitor the current across the memory cell string 12 and detect whether a change occurs in the current in response to the selected memory cell being written to the known state.
Control circuit 34 provides appropriate timing signals to row decode circuit 18, write decode circuit 20, read circuit 22, detection circuit 26, and current detection circuit 94 to allow the functions of the method shown in FIG. 6 to be performed.
Any one of the memory cells 70 a, 70 b, 70 c, and 70 d may be read using the method described with reference to FIG. 6. Although four memory cells are shown in the memory cell string illustrated in FIG. 5, other memory cell strings may include other numbers of memory cells coupled in parallel.
Reference is now made to FIG. 7 which illustrates an embodiment of a multi-level MRAM chip 700. MRAM chip 700 includes a number Z of memory cell levels or planes 702 that are stacked in a z-direction on a substrate 704. The number Z is a positive integer where Z>1. Memory cell levels 702 may be separated by insulating material (not shown) such as silicon dioxide. Read and write circuits may be fabricated on substrate 704. The read and write circuits may include additional multiplexers for selecting the levels that are read from and written to.
Thus, disclosed is an MRAM device in which resistance states of memory cells can be sensed during read operations. The MRAM device described herein may be used in a variety of applications. FIG. 8 shows an exemplary general application for one or more MRAM chips 700. The general application is embodied by a device 850 including a MRAM storage module 852, an interface module 854 and a processor 856. MRAM storage module 852 includes one or more MRAM chips 700 for non-volatile storage. Interface module 854 provides an interface between processor 856 and MRAM storage module 852. Device 850 could also include other types and/or levels of memory.
For a device 850 such as a notebook computer or personal computer, MRAM storage module 852 might include a number of MRAM chips 700 and interface module 854 might include an IDE or SCSI interface. For a device 850 such as a server, MRAM storage module 852 might include a greater number of MRAM chips 700, and interface module 854 might include a fiber channel or SCSI interface. Such MRAM storage modules 852 could replace or supplement conventional non-volatile storage devices such as hard drives.
For a device 850 such as a digital camera, MRAM storage module 852 might include a smaller number of MRAM chips 700 and interface module 854 might include a camera interface. Such a MRAM storage module 852 would allow non-volatile storage of digital images on-board the digital camera.
The above embodiments of the MRAM device may offer advantages over other MRAM devices. For example, the a higher level of memory cell densities may be achieved compared to other MRAM devices that include additional elements. Increased densities may result in decreased costs for a given amount of storage capacity. In addition, the memory cell strings described herein may provide better electrical circuit isolation compared to previous MRAM devices. The improved isolation may allow for more reliable detection of the state of memory cells in a memory cell string.
The memory device is not limited to the specific embodiments described and illustrated above. For instance, an MRAM device is not limited to the use of spin dependent tunneling devices. Other types of devices that could be used include, but are not limited to, giant magnetoresistance (“GMR”) devices.
The MRAM device has been described in connection with the rows being oriented along the x-axis and columns being oriented along the y-axis. However, the rows and columns could be transposed.
The memory device is not limited to MRAM cells. The memory device may include any type of memory cell in a resistive cross point array.

Claims

1. A method of performing a read operation from a memory cell in a memory cell string comprising:

applying a constant current across the memory cell string;

measuring a first voltage across the memory cell string;

writing the memory cell to a first state;

measuring a second voltage across the memory cell string; and

determining whether the first voltage differs from the second voltage.

2. The method of claim 1 further comprising:

determining that the memory cell was in a second state prior to being written to the first state in response to the first voltage differing from the second voltage.

3. The method of claim 2 further comprising:

reading out a logic level associated with the second state in response to the first voltage differing from the second voltage.

4. The method of claim 2 further comprising:

writing the memory cell to the second state in response to the first voltage differing from the second voltage.

5. The method of claim 1 further comprising:

determining that the memory cell was in the first state prior to being written to the first state in response to the first voltage not differing from the second voltage.

6. The method of claim 5 further comprising:

reading out a logic level associated with the first state in response to the first voltage not differing from the second voltage.

7. A data storage device comprising:

a memory cell string that includes a first memory cell and a second memory cell coupled in series;

a current source configured to apply a constant current across the string; and

a circuit coupled to the memory cell string, the circuit configured to detect a change in a voltage across the memory cell string in response to the current source applying the constant current across the memory cell string and the first memory cell being written to a first state.

8. The data storage device of claim 7 wherein the memory cell string has a first end and a second end, and wherein the current source is coupled to the first end.

9. The data storage device of claim 8 further comprising:

a ground source coupled to the second end of the memory cell string.

10. The data storage device of claim 7 wherein the circuit is configured to detect that the first memory cell was in a second state prior to being written to the first state in response to detecting a change in the voltage across the memory cell string.

11. The data storage device of claim 7 wherein the circuit is configured to detect that the first memory cell was in the first state prior to being written to the first state in response to not detecting a change in the voltage across the memory cell string.

12. A method of performing a read operation from a memory cell in a memory cell string comprising:

applying a constant voltage across the memory cell string;

measuring a first current across the memory cell string;

writing the memory cell to a first state;

measuring a second current across the memory cell string; and

determining whether the first current differs from the second current.

13. The method of claim 12 further comprising:

determining that the memory cell was in the first state prior to being written to the first state in response to the first current not differing from the second current.

14. The method of claim 13 further comprising:

reading out a logic level associated with the first state in response to the first current not differing from the second current.

15. The method of claim 12 further comprising:

determining that the memory cell was in a second state prior to being written to the first state in response to the first current differing from the second current.

16. The method of claim 15 further comprising:

reading out a logic level associated with the second state in response to the first current differing from the second current.

17. The method of claim 15 further comprising:

writing the memory cell to the second state in response to the first current differing from the second current.

18. A data storage device comprising:

a memory cell string that includes a first memory cell and a second memory cell coupled in parallel;

a voltage source configured to apply a constant voltage across the string; and

a means for detecting a change in a current across the memory cell string in response to the voltage source applying the constant voltage across the memory cell string and the first memory cell being written to a first state.

19. The data storage device of claim 18 wherein the first and second memory cells each have a first end and a second end, and wherein the voltage source is coupled to the first end of each of the first and second memory cells.

20. The data storage device of claim 19 further comprising:

a ground source coupled to the second end of each of the first and second memory cells.

21. The data storage device of claim 18 wherein the means is for detecting that the first memory cell was in a second state prior to being written to the first state in response to detecting a change in the current across the memory cell string.

22. The data storage device of claim 18 wherein the means is for detecting that the first memory cell was in the first state prior to being written to the first state in response to not detecting a change in the current across the memory cell string.