US20040238915A1 - Semiconductor device isolation structure and method of forming - Google Patents

Semiconductor device isolation structure and method of forming Download PDF

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Publication number
US20040238915A1
US20040238915A1 US10818631 US81863104A US2004238915A1 US 20040238915 A1 US20040238915 A1 US 20040238915A1 US 10818631 US10818631 US 10818631 US 81863104 A US81863104 A US 81863104A US 2004238915 A1 US2004238915 A1 US 2004238915A1
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trench isolation
isolation region
approximately
oxide layer
region
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US10818631
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Zhihao Chen
Douglas Grider
Freidoon Mehrad
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Zhihao Chen
Grider Douglas T.
Freidoon Mehrad
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention relates generally to the field of semiconductor devices and, more particularly, to a semiconductor device isolation structure and method of forming. [0001]
  • BACKGROUND OF THE INVENTION
  • Semiconductor devices are used in many electronic applications. One type of semiconductor device is a transistor. Manufacturers of transistors are continually reducing the size of transistors to increase their performance and to manufacture electronic devices in smaller sizes. [0002]
  • When many transistors are manufactured on a single integrated circuit die, oftentimes leakage current increases and breakdown voltage decreases, which severely degrades transistor performance. Manufacturers of transistors use isolation methods between transistors and other semiconductor devices to address these problems and others. [0003]
  • Shallow Trench Isolation (“STI”) is one method used for isolating transistors and other semiconductor devices. However, as transistor geometry shrinks, STI falls short of providing adequate isolation. [0004]
  • SUMMARY OF THE INVENTION
  • According to one embodiment of the invention, a method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region. [0005]
  • Embodiments of the invention provide a number of technical advantages. Embodiments of the invention may include all, some, or none of these advantages. According to one embodiment, semiconductor device isolation is improved while eliminating a channel stop implant. This elimination reduces junction capacitance, resulting in faster devices. In that embodiment, such advantages are achieved without stringent lithographic alignment requirements. [0006]
  • Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims. [0007]
  • DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE INVENTION
  • Example embodiments of the present invention and their advantages are best understood by referring now to FIGS. 1 through 2F of the drawings, in which like numerals refer to like parts. [0008]
  • FIG. 1 is a cross-sectional view of a partially completed semiconductor chip [0009] 100 showing a pair of trench isolation regions 102 isolating a semiconductor device 104 from other semiconductor devices 104 (not explicitly shown). Semiconductor device 104 is any suitable semiconductor device, such as a bipolar junction transistor, an NMOS transistor, a PMOS transistor, a diode, a resistor, or a capacitor.
  • Semiconductor devices, especially transistors, are continually being reduced in size to increase their performance. Some problems arise when reducing the size of transistors and other semiconductor devices. For example, an increase in leakage current and a decrease in breakdown voltage may occur when many transistors are manufactured on a single integrated circuit die, which may severely degrade performance of integrated circuits. The present invention addresses these problems, and others, by providing a method for isolating semiconductor devices. One embodiment of such a method is illustrated in FIGS. 2A-2F. [0010]
  • FIGS. 2A-2F are a series of cross-sectional views illustrating various manufacturing stages of trench isolation region [0011] 102 in accordance with the teachings of the present invention.
  • FIG. 2A shows a substrate [0012] 200 having a first oxide layer 202 formed outwardly therefrom and a first nitride layer 204 formed outwardly from first oxide layer 202. Substrate 200 may be formed from any suitable material used in semiconductor chip fabrication, such as silicon or germanium. First oxide layer 202 comprises any suitable type of oxide and is formed using any suitable growth and/or deposition technique used in semiconductor processing. In one embodiment, first oxide layer 202 is referred to as a “pad ox” and is approximately 100 angstroms thick; however, other suitable thicknesses may be used. In one embodiment, first nitride layer 204 is formed from any suitable type of nitride using any suitable growth and/or deposition technique used in semiconductor processing; however, first nitride layer 204 may be formed from other suitable materials that act as a dielectric. In one embodiment, first nitride layer 204 is approximately 2000 angstroms thick; however, other suitable thicknesses may be used.
  • Although FIG. 2A describes first oxide layer [0013] 202 and first nitride layer 204 as being separate dielectric layers, in other embodiments, only one dielectric layer is grown and/or deposited on substrate 200. For example, a layer of oxide only or another suitable dielectric layer only may be grown and/or deposited on substrate 200.
  • FIG. 2B shows a trench isolation region [0014] 206 and a second oxide layer 208 formed in trench isolation region 206. In one embodiment, trench isolation region 206 is formed as follows: A photoresist layer (not explicitly shown) is applied to the outer surface of first nitride layer 204. The photoresist layer is then masked and selectively stripped using suitable photolithographic techniques to expose a portion of first nitride layer 204. The exposed portion is then etched using any suitable etching technique to remove the exposed portion of first nitride layer 204 and a portion of first oxide layer 202. The photoresist layer is then stripped and removed. After stripping and removing the photoresist layer, an anisotropic dry etch is performed on the exposed portion of substrate 200 to etch substrate 200 down to a predetermined depth 209. In this anisotropic dry etch process first nitride layer 204 is used as a hard masking layer. Any suitable anisotropic dry etch process, such as a plasma etch, may be used to define trench isolation region 206. In one embodiment, trench isolation region 206 has depth 209 between approximately 0.7 microns and 1.3 microns and a width 207 between approximately 0.1 microns and 0.13 microns. In a more particular embodiment, depth 209 is approximately 1 micron and width 207 is approximately 0.12 microns.
  • After defining trench isolation region [0015] 206, second oxide layer 208 is formed in trench isolation region 206. Second oxide layer 206 comprises any suitable type of oxide and is formed using any suitable growth and/or deposition technique used in semiconductor processing. In one embodiment, second oxide layer 208 is approximately 150 angstroms thick; however, other suitable thicknesses may be used.
  • According to the teachings of the present invention, a spin-on-glass (“SOG”) region [0016] 211 is formed in trench isolation region 206 for isolating semiconductor devices 104. One method of forming SOG region 211 in trench isolation region 206 is outlined below in conjunction with FIGS. 2C and 2D.
  • FIG. 2C shows an SOG layer [0017] 210 formed in trench isolation region 206 and outwardly from first nitride layer 204. SOG is well known in the art of semiconductor fabrication. The “glass” used in SOG is typically silicon dioxide; however, other suitable silicates may be used. In one embodiment, the application of SOG layer 210 involves applying a liquid mixture of silicon dioxide, or other suitable silicate, in a solvent while the associated wafer containing semiconductor chip 100 is spun. Because of the relatively small width 207 of trench isolation region 206, dielectric materials other than those applied as SOG will experience difficulties when trying to fill trench isolation region 206. Polysilicon could be used to fill trench isolation region 206; however, polysilicon has a low dielectric strength and is inadequate for isolating semiconductor devices 104 manufactured close to one another. One technical advantage of the present invention is that SOG layer 210, which has adequate dielectric properties, is able to fill trench isolation region 206 even though a small width 207 is utilized.
  • After filling trench isolation region [0018] 206 with SOG layer 210, SOG layer 210 is annealed to evaporate the solvent in the SOG material so that SOG layer 210 may be cured. In one embodiment, annealing SOG layer 210 includes placing semiconductor chip 100 into an oven that is heated to a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then subsequently raising the temperature to between 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes. In a particular embodiment, the oven is heated to a temperature of approximately 400° C. for a time period of approximately 30 minutes, followed by raising the temperature to approximately 1000° C. for a time period between approximately 5 and 10 minutes.
  • FIG. 2D shows a portion of SOG layer [0019] 210 removed to define SOG region 211 and to expose a shallow trench isolation (“STI”) region 212. In one embodiment, STI region 212 is formed by using a plasma dry etch process that etches SOG layer 210 down to a desired depth 213. This plasma dry etch process is highly selective, which reduces the thickness of SOG layer 210 with only a negligible reduction in thickness of first nitride layer 204. Other suitable etching processes may be used to reduce the thickness of SOG layer 210 to depth 213. In one embodiment, depth 213 is between approximately 2000 angstroms and 2700 angstroms. In a particular embodiment, depth 213 is approximately 2000 angstroms.
  • FIG. 2E shows a third oxide layer [0020] 214 formed in STI region 212. Third oxide layer 214 comprises any suitable type of oxide and is formed using any suitable growth and/or deposition technique used in semiconductor processing. For example, an atmospheric pressure chemical vapor deposition (“APCVD”) process may be used to form third oxide layer 214.
  • FIG. 2F shows trench isolation region [0021] 102 after third oxide layer 214 is reduced in thickness by any suitable process, such as a chemical mechanical polish (“CMP”) process. First nitride layer 204 is used as a stopping layer for the CMP process, which may result in a reduction in thickness of first nitride layer 204. After reducing the thickness of third oxide layer 214, semiconductor devices 104 may then be fabricated on semiconductor chip 100 in any suitable manner. Because of the excellent isolation that trench isolation regions 102 provide, based in part on SOG regions 211, semiconductor devices 104 may be fabricated closer to one another, thereby improving speed and performance of semiconductor devices 104 while ensuring that problems, such as an increase in current leakage or a decrease in breakdown voltage, are substantially reduced or eliminated.
  • Although embodiments of the invention and their advantages are described in detail, a person skilled in the art could make various alterations, additions, and omissions without departing from the spirit and scope of the present invention as defined by the appended claims. [0022]

Claims (9)

  1. 1-8. (cancelled)
  2. 9. A semiconductor device isolation structure, comprising:
    a first oxide layer disposed outwardly from a semiconductor substrate;
    a first nitride layer disposed outwardly from the first oxide layer;
    a trench isolation region formed by removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate;
    a second oxide layer lining the trench isolation region;
    a spin-on-glass region disposed in the isolation region; and
    a third oxide layer disposed outwardly from the spin-on-glass region.
  3. 10. (cancelled)
  4. 11. (cancelled)
  5. 12. The structure of claim 9, wherein the spin-on-glass region is annealed at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and afterward annealed at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes.
  6. 13. The structure of claim 9, wherein the spin-on-glass region is annealed at a temperature of approximately 400° C. for a time period of approximately 30 minutes, and afterward annealed at a temperature of approximately 1000° C. for a time period between approximately 5 and 10 minutes.
  7. 14. The structure of claim 9, further comprising a shallow trench isolation region formed by removing a portion of the trench isolation region, the shallow trench isolation region having a depth between approximately 2000 Å and 2700 Å.
  8. 15. The structure of claim 9, further comprising a shallow trench isolation region formed by removing a portion of the trench isolation region, the shallow trench isolation region having a depth of approximately 2000 Å.
  9. 16. The structure of claim 9, wherein the second oxide layer has a thickness of approximately 150 Å.
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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090181516A1 (en) * 2008-01-10 2009-07-16 Min Sik Jang Method of Forming Isolation Layer of Semiconductor Device
US7736956B2 (en) 2005-08-17 2010-06-15 Intel Corporation Lateral undercut of metal gate in SOI device
US7781771B2 (en) 2004-03-31 2010-08-24 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7820513B2 (en) 2003-06-27 2010-10-26 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7859053B2 (en) * 2004-09-29 2010-12-28 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7879675B2 (en) 2005-03-14 2011-02-01 Intel Corporation Field effect transistor with metal source/drain regions
US7898041B2 (en) 2005-06-30 2011-03-01 Intel Corporation Block contact architectures for nanoscale channel transistors
US7902014B2 (en) 2005-09-28 2011-03-08 Intel Corporation CMOS devices with a single work function gate electrode and method of fabrication
US7960794B2 (en) 2004-08-10 2011-06-14 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7989280B2 (en) 2005-11-30 2011-08-02 Intel Corporation Dielectric interface for group III-V semiconductor device
US8067818B2 (en) 2004-10-25 2011-11-29 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8071983B2 (en) 2005-06-21 2011-12-06 Intel Corporation Semiconductor device structures and methods of forming semiconductor structures
US8084818B2 (en) 2004-06-30 2011-12-27 Intel Corporation High mobility tri-gate devices and methods of fabrication
US8183646B2 (en) 2005-02-23 2012-05-22 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US8193567B2 (en) 2005-09-28 2012-06-05 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8405164B2 (en) 2003-06-27 2013-03-26 Intel Corporation Tri-gate transistor device with stress incorporation layer and method of fabrication
US8617945B2 (en) 2006-08-02 2013-12-31 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
CN104347470A (en) * 2013-07-29 2015-02-11 中芯国际集成电路制造(上海)有限公司 Preparation method of the semiconductor device
US9337307B2 (en) 2005-06-15 2016-05-10 Intel Corporation Method for fabricating transistor with thinned channel

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869860B2 (en) * 2003-06-03 2005-03-22 International Business Machines Corporation Filling high aspect ratio isolation structures with polysilazane based material
GB0312796D0 (en) * 2003-06-04 2003-07-09 Trikon Technologies Ltd Trench filling methods
US7129559B2 (en) * 2004-04-09 2006-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage semiconductor device utilizing a deep trench structure
US7098105B2 (en) * 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7332409B2 (en) * 2004-06-11 2008-02-19 Samsung Electronics Co., Ltd. Methods of forming trench isolation layers using high density plasma chemical vapor deposition
US7332408B2 (en) * 2004-06-28 2008-02-19 Micron Technology, Inc. Isolation trenches for memory devices
KR100673896B1 (en) * 2004-07-30 2007-01-26 주식회사 하이닉스반도체 Semiconductor device with trench type isolation and method for fabricating the same
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
KR100835478B1 (en) * 2007-06-29 2008-06-04 주식회사 하이닉스반도체 Method for forming the isolation of semiconductor device
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8367515B2 (en) * 2008-10-06 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid shallow trench isolation for high-k metal gate device improvement
KR20100090397A (en) * 2009-02-06 2010-08-16 삼성전자주식회사 Method of forming semiconductor device
US8349985B2 (en) * 2009-07-28 2013-01-08 Cheil Industries, Inc. Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801082A (en) * 1997-08-18 1998-09-01 Vanguard International Semiconductor Corporation Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion
US6214735B1 (en) * 1997-05-17 2001-04-10 Samsung Electronics Co., Ltd. Method for planarizing a semiconductor substrate
US6401082B1 (en) * 1999-11-08 2002-06-04 The United States Of America As Represented By The Secretary Of The Air Force Autoassociative-heteroassociative neural network
US6417073B2 (en) * 2000-03-21 2002-07-09 Nec Corporation Method for forming element isolating region
US6479369B1 (en) * 1999-11-08 2002-11-12 Nec Corporation Shallow trench isolation (STI) and method of forming the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789562B2 (en) * 1985-11-01 1995-09-27 富士通株式会社 Isolation method for an integrated circuit
JPH03234041A (en) * 1990-02-09 1991-10-18 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214735B1 (en) * 1997-05-17 2001-04-10 Samsung Electronics Co., Ltd. Method for planarizing a semiconductor substrate
US5801082A (en) * 1997-08-18 1998-09-01 Vanguard International Semiconductor Corporation Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits
US6020230A (en) * 1998-04-22 2000-02-01 Texas Instruments-Acer Incorporated Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion
US6401082B1 (en) * 1999-11-08 2002-06-04 The United States Of America As Represented By The Secretary Of The Air Force Autoassociative-heteroassociative neural network
US6479369B1 (en) * 1999-11-08 2002-11-12 Nec Corporation Shallow trench isolation (STI) and method of forming the same
US6417073B2 (en) * 2000-03-21 2002-07-09 Nec Corporation Method for forming element isolating region

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US7820513B2 (en) 2003-06-27 2010-10-26 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8273626B2 (en) 2003-06-27 2012-09-25 Intel Corporationn Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8405164B2 (en) 2003-06-27 2013-03-26 Intel Corporation Tri-gate transistor device with stress incorporation layer and method of fabrication
US7781771B2 (en) 2004-03-31 2010-08-24 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US8084818B2 (en) 2004-06-30 2011-12-27 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7960794B2 (en) 2004-08-10 2011-06-14 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US8268709B2 (en) 2004-09-29 2012-09-18 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7859053B2 (en) * 2004-09-29 2010-12-28 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US8399922B2 (en) 2004-09-29 2013-03-19 Intel Corporation Independently accessed double-gate and tri-gate transistors
US8502351B2 (en) 2004-10-25 2013-08-06 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
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US8749026B2 (en) 2004-10-25 2014-06-10 Intel Corporation Nonplanar device with thinned lower body portion and method of fabrication
US8816394B2 (en) 2005-02-23 2014-08-26 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
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