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US20040232407A1 - Power MOS device with improved gate charge performance - Google Patents

Power MOS device with improved gate charge performance Download PDF

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US20040232407A1
US20040232407A1 US10391126 US39112603A US2004232407A1 US 20040232407 A1 US20040232407 A1 US 20040232407A1 US 10391126 US10391126 US 10391126 US 39112603 A US39112603 A US 39112603A US 2004232407 A1 US2004232407 A1 US 2004232407A1
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gate
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conductivity
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Daniel Calafut
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Fairchild Semiconductor Corp
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
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    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Abstract

A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    The present invention relates to field-effect transistors, in particular double-diffused metal-oxide-semiconductor (“DMOS”) transistors, and their method of manufacture.
  • [0002]
    A DMOS transistor is a type of field-effect transistor (“FET”) that can be used as a power transistor, that is, a transistor that is used to switch or control relatively large amounts of electrical power compared to a transistor that might be used in a logic circuit application. Power transistors might operate between 1-1000 volts, or higher, and might carry from several tenths of an amp to several amps of current, or higher. Power MOSFETs are designed to operate under conditions that would destroy conventional MOSFETs, or accelerate their failure.
  • [0003]
    Design of DMOS transistors presents challenges over other conventional MOS transistor devices, in particular relating to the structure of the channel and drain regions. FIGS. 1 and 2 illustrate a conventional trench DMOS transistor 100 and planar DMOS transistor 200, respectively. FIG. 1 shows a semiconductor substrate 102 with a trench 110 formed to a predetermined depth into the substrate. At the bottom of the substrate is an n+ drain region 120. Above the drain is an epitaxial layer 125 doped to a lighter degree of the same conductivity as the drain region. Overlying the epitaxial region is a channel region 105 implanted with a dopant having a polarity that is opposite the substrate and epitaxial regions. As illustrated in FIG. 1, the dopant profile ranges from a lesser degree to a greater degree away from the trench, to where a concentration of dopant forms a body region.
  • [0004]
    Formed near the surface of the substrate on either side of the trench are source regions 130, implanted with a dopant of the same conductivity type as the drain. Source and drain regions of the transistor shown in FIG. 1 are illustrated as n+, the channel region as p−, and a body region as p+. It should be readily apparent to a person skilled in the art that the polarity of the conductivity type for the transistor structure could be reversed. A dielectric layer 112 lines the trench. Filling the trench over the dielectric layer is a gate 114, which is typically made of polysilicon material doped to a similar conductivity type as the source and drain regions.
  • [0005]
    In operation, a charge applied to the gate creates a channel for electron migration across a channel 132 alongside the trench between the sources 130 and the epitaxial region 125, and flowing to the drain 120. The charge applied to the gate also forms an accumulation area 134 in the epitaxial layer under the trench, where electrons accumulate.
  • [0006]
    [0006]FIG. 2 illustrates a conventional planar DMOS transistor 200 fabricated on a semiconductor substrate 202. An n+ drain region lies at the bottom of the substrate. Overlying the drain is an n− epitaxial layer 225. Source regions 230 are formed of an implant of n+ dopants into an area just below the top surface of the substrate. Surrounding each source region underneath are P-type channel regions 205, which form a channel 232 between the source and the epitaxial layer. At least partially overlying each source region is a dielectric layer 212. Coextensively overlying the dielectric layer is a polysilicon gate 214 implanted with dopants of the same conductivity type as the source regions.
  • [0007]
    A charge applied to the gate causes electrons to flow from the sources, across the channels to the epitaxial region, and then down to the drain. Because of the uniform charge on the gate, an accumulation of electrons forms at the surface in the epitaxial layer just below the gate, between the channel regions, in an accumulation area 234.
  • [0008]
    An important design issue for both trench and planar DMOS transistors is the gate charge required to drive the gate of the MOSFET to a specific voltage. FIG. 3 illustrates an ideal gate charge curve for a conventional DMOS transistor. In a particular range, denoted as the Miller Q range, additional charge on the gate is insufficient to overcome certain parasitic capacitance that arise during operation. Several important ones of the parasitic capacitance are labeled in FIGS. 1 and 2. A capacitance between the gate and the source, Cgs, forms in the area where the gate overlaps the source. A gate-to-drain capacitance, Cgd, forms between the gate and the accumulation region, where electrons accumulate as a current path is formed from the channel region to the drain.
  • [0009]
    The capacitance Cgd is also known as the “Miller capacitance.” The Miller capacitance is an effective build-up of capacitative charge which must be overcome in order to bias the transistor to a particular voltage, as shown in FIG. 3. Increasing the gate charge has adverse effects. Transistor switching speed is significantly reduced where a larger gate charge is required. Further, the failure rate of transistors subject to higher gate charge is increased. Thus, it is desired to minimize the Miller capacitance over a range of charge, so as to reduce the gate charge and enhance transistor switching speed, efficiency, and improve failure rates.
  • [0010]
    One method of reducing the Miller capacitance is shown in U.S. Pat. No. 5,879,994, which describes a process and structure to apply a non-uniform gate dielectric layer, where a thicker oxide is applied over the accumulation area, and a thinner oxide is formed over the inversion channel area. The extra-thick oxide, or “terrace oxide” over the region where the Miller capacitance occurs, has some limitations. First, for planar DMOS transistors, alignment of the terrace oxide is difficult to achieve, and adds significantly to the costs of manufacturing the devices. Being easily misaligned, transistors formed with a terrace oxide have substantially lower yields. The difficulty with which to build a nonuniform dielectric layer exists in trench DMOS structures as well.
  • [0011]
    An alternative approach for reducing the Miller capacitance begins by considering voltage-dependent capacitance characteristics of MOS devices under various gate bias conditions. FIG. 4 shows a well-known CV curve for a conventional MOS device. At the extremes of the applied gate voltage |Vg|, the capacitance value maintains a constant value that depends only on the thickness of the dielectric (assumed to be SiO2, although not limited herein as such). This is due to a layer of mobile charge, at the extreme points on the curve, which causes the interface between the dielectric and the silicon substrate to effectively become a second plate of a capacitor.
  • [0012]
    As the gate voltage approaches a value known as the “flat band” voltage, as viewed from the accumulation side, the capacitance begins to decrease until a point called the “threshold” voltage is reached. This point is reached when the mobile charge distribution near the SiO2—Si interface transitions from accumulation to inversion. Beyond the threshold voltage Vt, the area immediately around the SiO2—Si interface is said to be inverted and there is again a layer of mobile charge, albeit of opposite polarity. In this range the MOS capacitance is limited by the gate oxide thickness.
  • [0013]
    Close to the threshold Vt, there is a point Cmin that represents the lowest value of capacitance for a given gate bias voltage in conventional MOS devices. However, a novel DMOS structure could be made so as to shift Cmin to as near the Vgs value range for the Miller region shown in FIG. 3. This would lower the capacitance within the Miller range, and effectively decrease the range of charge needed to overcome the Miller capacitance.
  • SUMMARY OF THE INVENTION
  • [0014]
    The present invention provides a method of fabricating a gate structure of a DMOS device. The fabrication method includes the steps of forming a polysilicon gate on a portion of a semiconductor substrate, implanting a dopant of a first conductivity type into the polysilicon gate, masking the polysilicon gate to define an alternation region within the gate, and implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.
  • [0015]
    In another embodiment, the present invention provides a gate of a semiconductor device that includes a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region. The polysilicon gate structure has a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region. The second conductivity type has a polarity that is opposite a polarity of the first conductivity type.
  • [0016]
    In yet another embodiment, the present invention provides a method of fabricating a gate structure of a trench-type DMOS device. The method includes the steps of forming a trench in a semiconductor substrate, lining the trench with a dielectric layer, and forming a first polysilicon gate portion to an intermediate depth of the trench. The method further includes the steps of implanting a dopant of a first conductivity type into the first gate portion, forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate, and implanting a dopant of a second conductivity type into the second gate portion.
  • [0017]
    In still yet another embodiment, the present invention provides a composite gate structure in a trench transistor. The composite gate structure includes a trench extending a selected depth from a top surface of a semiconductor substrate, a conformal dielectric layer lining the trench, a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type, and a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.
  • [0018]
    In still yet another embodiment, the present invention provides a semiconductor device having a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type, a gate dielectric disposed on the substrate, and an implant region of a second conductivity type formed by diffusing a dopant of the second conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0019]
    [0019]FIG. 1 is a simplified cross section of a conventional trench DMOS transistor;
  • [0020]
    [0020]FIG. 2 is a simplified cross section of a conventional planar DMOS transistor;
  • [0021]
    [0021]FIG. 3 shows a gate charge-gate voltage (QV) curve for conventional MOS devices;
  • [0022]
    [0022]FIG. 4 is a capacitance-voltage curve (CV) for conventional MOS devices;
  • [0023]
    [0023]FIG. 5 is a simplified cross section of a trench DMOS transistor according to the present invention;
  • [0024]
    [0024]FIG. 6 is a simplified cross section of a planar DMOS transistor according to the present invention;
  • [0025]
    [0025]FIG. 7 is a simplified cross section of a trench DMOS transistor according to an alternative embodiment of the invention; and
  • [0026]
    [0026]FIG. 8 is a simplified cross section of a planar DMOS transistor according to an alternative embodiment of the invention.
  • DESCRIPTION OF THE SPECIFIC EMBODIMENTS
  • [0027]
    The present invention provides a composite gate structure and methods of manufacture. The composite gate structure lowers gate to drain overlap capacitance and enhances switching speed and efficiency.
  • [0028]
    [0028]FIG. 5 is a simplified cross section of a trench DMOS transistor 300 according to an embodiment of the present invention. This example illustrates a n− channel device, however, it is understood that the invention could be applied to an p− channel device. The DMOS transistor is fabricated on an n+ silicon substrate 320 that serves as the drain of the DMOS transistor. An n− epitaxial layer 325 is grown on the substrate. A p− channel region 332 and a p+ body region 305 is formed over the n− epitaxial layer, which is considered part of the “substrate” for purposes of this description. The p− channel region and p+ body region are formed by implanting and diffusing dopants of a p-type conductivity.
  • [0029]
    A trench 310 is formed into the substrate to a predetermined depth, extending into the n− epitaxial layer. N+ source regions are implanted and diffused into both the p+ body region and the p− channel region, as well as adjacent to opposing sides of the trench at the top surface of the substrate. A gate oxide 312 is deposited over the walls of the trench, and a composite gate structure 311 fills the trench over the gate oxide.
  • [0030]
    According to the present invention, the gate structure is initially formed of a first portion 340, deposited into the trench, preferably from the bottom of the trench to a depth substantially corresponding to a depth of the n− epitaxial layer. According to one embodiment of the invention, the first portion is a polysilicon grown in the trench, and a p-type dopant is implanted directly into the trench into the polysilicon. The first portion is doped with a sufficient amount of implant to minimize the capacitance in the accumulation area for a certain predetermined voltage, such as 1 volt.
  • [0031]
    A second portion 350 of the gate structure is grown on top of the first portion. As illustrated in FIG. 5, the second portion is preferably etched in the middle down to the first portion. A conformal polycide layer 345 is then deposited over sides of the second portions and the top of the first portion. The polycide layer acts to short out the second portion, which would otherwise be floating, or basically cuts the portion in half to divide it into two isolated cells. An insulator 355 is then formed over the polycide layer in the trench, as well as over the top of the trench and at least partially extending over the source regions on the surface of the substrate. In a preferred embodiment, the insulator is boro-phospho silicon glass (BPSG), but also may be any material exhibiting generally nonconductive properties, such as silicon dioxide (SiO2). A metal layer 360 is formed on the top of the substrate and over the insulator, to provide electrical contact to the source regions.
  • [0032]
    [0032]FIG. 6 is a simplified cross section of a planar DMOS transistor 400 according to an embodiment of the present invention. The DMOS transistor is illustrated in FIG. 6 to show the composite gate structure in an n-channel transistor, but it is understood the invention could equally be applied to a p-channel transistor by reversing most of the polarities of the portions of the transistor.
  • [0033]
    An n+ region 420 serves as the drain of the planar DMOS transistor, just as in the trench case. An n− epitaxial layer 425 is grown on the n+ region. A p− channel region 405 and a p+ body region 407 are formed in the substrate in the epitaxial layer, and defining an accumulation area in the epitaxial layer therebetween. The channel and body regions are doped according to a predetermined doping profile that need not be further explained here. N+ source regions 430 are implanted and diffused into each of both the channel region and body region, as well as laterally under a gate structure 414. A gate oxide 412 is grown over the p-channel regions and the accumulation area.
  • [0034]
    The gate structure is formed over the gate oxide, preferably of a deposited and etched polysilicon layer. In a preferred embodiment, the polysilicon gate structure is implanted with a dopant of a first conductivity type to yield a polarity of n+. The gate structure is then masked, and a dopant of a second coductivity type, having a polarity that is opposite to the polarity of the first conductivity type, such as p+, for example, is implanted into the masked area. The p+ implanted material is then driven by diffusion to extend over an area with edges that substantially correspond to the extent of the accumulation area in the substrate.
  • [0035]
    The gate structure is then overlaid with an insulator 455, as discussed above. A metal layer 460 is then formed over the insulator and extended to the source regions 430, to provide electrical contact to the source regions. In operation, a charge applied to the gate will cause the greatest current flow between the sources through the channels, while charge in the accumulation area is repelled by the opposing polarity of the second conductivity type formed above it. In this way, the capacitative charge built up in the accumulation area is minimized within a given range of current.
  • [0036]
    In exemplary preferred embodiments of either the trench or planar DMOS structures, the n-type portion of the gate structure is formed by implanting ions of either arsenic or phosphorous into the polysilicon. The p-type portion of the gate structure is preferably formed by implanting ions of boron into the polysilicon. It should be understood, however, that other dopants may be implanted into the gate structure of the present invention to produce the desired conductivity profile, as described above with reference to FIGS. 5 and 6.
  • [0037]
    The present invention mitigates a build up of charge in the accumulation area proximate the gate structure of a DMOS transistor cell. In an alternative embodiment, as illustrated in FIGS. 7 and 8, the present invention provides an implant region into the epitaxial layer just underneath the gate between channel regions of two transistor cells. The alternative embodiment of the invention is adaptable to both the trench and planar configurations.
  • [0038]
    With reference to FIG. 7, there is illustrated a simplified cross section of a trench DMOS transistor 500, showing only the improved structure of the present invention. The DMOS transistor includes a trench 510 formed into a semiconductor substrate as described above in detail. At the bottom of the trench, in the area of the epitaxial layer where the accumulation area is formed, as shown in FIG. 1, an implant area 520 is formed as a lightly doped region. The implant area has a cross-sectional profile that surrounds the bottom of the trench at least within the n− epitaxial layer.
  • [0039]
    The implant area may be formed in one of several ways. Once the trench is formed, n-type ions may be implanted directly into the bottom of the trench, in a zero-angle ion implant step. Once implanted, the device is subjected to a drive step to diffuse the n-type ions out from the trench into the epitaxial layer. The drive step is preferably accomplished by annealing the transistor, then driving it at approximately 900-1500 degrees F, to diffuse the ion atoms. The resultant implant area preferably exhibits a Gaussian profile concentration, with the heaviest concentration of n-type ion. Or, the drive step can include multiple implant steps, until a desired implant profile is achieved.
  • [0040]
    [0040]FIG. 8 illustrates an implant area 620 in a planar DMOS transistor 600, to counteract the adverse effects of the Miller capacitance near a gate structure 614 of the transistor. The implant area is formed by an ion implant of n-type atoms into the accumulation area, between channel regions 632 underlying the n+ source regions. The implant area is preferably formed by masking an area of the semiconductor substrate surface, after p-type implant to form the channels. Then, the n-type material is implanted into the masked area. Next, the implant is driven to a desired profile, preferably extending to each channel region. The n-type material should have a higher density at the surface of the substrate. After the implant area is formed, the gate structure may be formed by employing conventional fabrication techniques.
  • [0041]
    While the above is a complete description of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. For example, although a silicon is given as an example of a substrate material, other materials may be used. The invention is illustrated for a two-transistor cell DMOS FET, but it could be applied to other DMOS structures, such as a multi-cell array of DMOS transistors on a single substrate. Similarly, implantation is given as an example of providing dopants to the substrate, but other doping methods, such as a gas or topical dopant source may be used to provide dopants for diffusion, depending on the appropriate mask being used. These and other alternatives may appear to those skilled in the art; hence, the scope of this invention should not be limited to the embodiments described, but are instead defined by the following claims.

Claims (24)

    What is claimed is:
  1. 1. A method of fabricating a gate structure of a DMOS device, comprising the steps of:
    forming a polysilicon gate on a portion of a semiconductor substrate;
    implanting a dopant of a first conductivity type into the polysilicon gate;
    masking the polysilicon gate to define an alternation region within the gate; and
    implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.
  2. 2. The method of claim 1, wherein the step of forming a polysilicon gate further comprises the steps of:
    growing a dielectric layer on the semiconductor substrate;
    depositing a polysilicon layer on the dielectric layer; and
    masking the polysilicon layer to define a polysilicon gate.
  3. 3. The method of claim 1, wherein the step of implanting a dopant of a second conductivity type further comprises diffusing the dopant of the second conductivity type to drive the dopant to an outer boundary of the alternation region.
  4. 4. The method of claim 1, wherein the polarity of the first conductivity type is n-type and the polarity of the second conductivity type is p-type.
  5. 5. The method of claim 1, wherein the polysilicon gate overlies a channel region in the semiconductor substrate and extends at least partially over a source formed in the substrate, and wherein an extent of the alternation region corresponds to a boundary between the channel region and an accumulation area.
  6. 6. A gate of a semiconductor device, comprising:
    a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region, the polysilicon gate structure having a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region.
  7. 7. The device as in claim 6, wherein an extent of the alternation region substantially corresponds to a boundary between the channel region and an accumulation area in the semiconductor substrate.
  8. 8. The device as in claim 6, wherein an electrical polarity of the first conductivity type is opposite an electrical polarity of the second conductivity type.
  9. 9. The device as in claim 8, wherein the first portion of the polysilicon gate is doped with n-type impurities.
  10. 10. The device as in claim 9, wherein the second portion of the polysilicon gate is doped with p-type impurities.
  11. 11. The device as in claim 10, wherein the p-type impurities are boron ions, and wherein the n-type impurities are ions selected from the group comprised of arsenic and phosphorous.
  12. 12. The device as in claim 6, further comprising a polycide layer disposed over the polysilicon gate structure.
  13. 13. A method of fabricating a gate structure of a DMOS device, comprising the steps of:
    forming a trench in a semiconductor substrate;
    lining the trench with a dielectric layer;
    forming a first polysilicon gate portion to an intermediate depth of the trench;
    implanting a dopant of a first conductivity type into the first gate portion;
    forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate; and
    implanting a dopant of a second conductivity type into the second gate portion.
  14. 14. The method of claim 13, further comprising the steps of:
    etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and
    forming a polycide strap layer over the first polysilicon gate layer in the intermediate portion and on opposite side walls of the second polysilicon gate portion.
  15. 15. The method of claim 14, further comprising the step of depositing a conductive material in the intermediate portion to the level substantially equal to the top surface of the silicon substrate.
  16. 16. A composite gate structure in a trench transistor, comprising:
    a trench extending a selected depth from a top surface of a semiconductor substrate;
    a conformal dielectric layer lining the trench;
    a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type; and
    a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.
  17. 17. The gate structure of claim 16, further comprising a polycide layer disposed on two side portions of the second gate portion, and over a mid-portion of the first gate portion.
  18. 18. The gate structure of claim 16, wherein the first conductivity type is p-type and the second conductivity type is n-type.
  19. 19. The gate structure of claim 16, wherein the first gate portion is formed by implanting a dopant of the first conductivity type into polysilicon comprising the first gate portion.
  20. 20. The gate structure of claim 16, wherein the second gate portion is formed by implanting a dopant of the second conductivity type into polysilicon comprising the second gate portion.
  21. 21. The gate structure of claim 17, wherein the two side portions of the second gate portion are formed by etching away a mid-portion of the second gate portion.
  22. 22. The gate structure of claim 16, wherein the intermediate depth substantially corresponds to a boundary between a source region and an epitaxial layer in the substrate.
  23. 23. A semiconductor device, comprising:
    a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type;
    a gate dielectric disposed on the substrate; and
    an implant region of a second conductivity type formed by diffusing a dopant of the first conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.
  24. 24. The semiconductor device of claim 23, wherein the gate dielectric conforms to a trench in the substrate.
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US20090057754A1 (en) * 2006-06-19 2009-03-05 Nathan Kraft Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region
US9224853B2 (en) 2007-12-26 2015-12-29 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
CN104934471A (en) * 2014-03-20 2015-09-23 帅群微电子股份有限公司 Trench type power metal-oxide-semiconductor field effect transistor and manufacturing method thereof
CN104779294A (en) * 2015-04-17 2015-07-15 上海华虹宏力半导体制造有限公司 Groove-type power MOS transistor and manufacturing method thereof as well as integrated circuit

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US20060024890A1 (en) 2006-02-02 application
US6534825B2 (en) 2003-03-18 grant
US7625793B2 (en) 2009-12-01 grant
US6461918B1 (en) 2002-10-08 grant
US20020190282A1 (en) 2002-12-19 application

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