US20040229400A1 - Multichip wafer level system packages and methods of forming same - Google Patents

Multichip wafer level system packages and methods of forming same Download PDF

Info

Publication number
US20040229400A1
US20040229400A1 US10873691 US87369104A US2004229400A1 US 20040229400 A1 US20040229400 A1 US 20040229400A1 US 10873691 US10873691 US 10873691 US 87369104 A US87369104 A US 87369104A US 2004229400 A1 US2004229400 A1 US 2004229400A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
semiconductor
substrate
layer
dice
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10873691
Inventor
Swee Chua
Siu Low
Yong Chia
Meow Eng
Yong Neo
Suan Boon
Shuangwu Huang
Wei Zhou
Original Assignee
Chua Swee Kwang
Low Siu Waf
Chia Yong Poo
Eng Meow Koon
Neo Yong Loo
Boon Suan Jeung
Shuangwu Huang
Wei Zhou
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Abstract

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application is a divisional of application Ser. No. 10/229/914, filed Aug. 27, 2002, pending.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates generally to semiconductor packaging. More particularly, the present invention relates to wafer level multichip packaging such as, for example, a system in a package solution.
  • [0004]
    2. State of the Art
  • [0005]
    Semiconductor chips (also referred to as die/dice herein) are found in many electronic products today. As semiconductor dice get smaller and more complex, the problem of making electrical connections between semiconductor dice, connections to carrier substrates such as printed circuit boards, and connections to intermediate substrates such as multichip modules which are, in turn, connected to carrier substrates has been addressed with a variety of constantly evolving solutions.
  • [0006]
    One of the earlier solutions included wire bonding from signal connection devices, such as bond pads of a semiconductor die, to pins or leads of a lead frame contained in a ceramic or plastic package. Finished packages are mounted to a carrier substrate, such as a printed circuit board, where the pins or leads make electrical connection with contact pads on the carrier substrate.
  • [0007]
    The term “signal connection devices” as used herein regarding semiconductor devices includes not only contact pads of a substrate and bond pads of a semiconductor device but also I/O connections for a semiconductor device created by adding circuitry from bond pads located on the active surface of the semiconductor device to different locations on the active surface of the semiconductor device. Such additional circuitry is typically effected using a so-called “redistribution layer” extending over the active surface or a surface of a semiconductor die.
  • [0008]
    An evolution of electrical connection technology occurred when multiple semiconductor dice were mounted on an intermediate substrate. In this instance, the semiconductor dice are typically connected to a lead frame by way of bonding wires. Signals, or electrical connections, required for coupling with an external device, such as a circuit board, are brought out to contact pads, pins or leads of the multichip module package. Other signals or electrical interconnections may be established between multiple semiconductor dice by way of circuitry formed on the intermediate substrate.
  • [0009]
    In these solutions, using wires for connecting a semiconductor die to a substrate and wire bonding processes can create problems. Such problems may include, for example, size and pitch (spacing) requirements for the bond pads of the semiconductor die and contact pads of the substrate; inductance in the signals due to the long curved wires; wire bond breakage and wire sweep causing shorting between adjacent wires; and high signal frequency semiconductor dice making the wire bonding process difficult and expensive.
  • [0010]
    Flip-chip technologies using solder balls or bumps have helped to alleviate some of these problems. For example, instead of wire bonding, conductive bumps such as, for example, balls of solder may be formed at the locations of the bond pads of a semiconductor die. A specialized lead frame, a dielectric tape carrying circuit traces as used in tape automated bonding processes, or other carrier substrates such as a printed circuit board may have electrical connection locations such as terminals which correspond to the placement of the solder balls on the bond pads of the semiconductor die. The semiconductor die is “flipped” upside down so the solder balls are placed, for example, on the contact pads of a carrier substrate. A solder reflow. process heats the solder balls until the solder begins to flow and bond with a corresponding contact pad of a carrier substrate. Upon cooling, the solder forms both mechanical and electrical connections between the carrier substrate and the semiconductor die. This packaging solution may alleviate at least some of the inductance problems, allowing for higher frequency performance and better signal integrity of the semiconductor die. Also, to a certain extent, it allows the contact pads of a substrate where conductive bumps were formed to be larger, more widely pitched and placed anywhere on the semiconductor die active surface rather than just around the periphery or down the center thereof.
  • [0011]
    Chip scale packaging has evolved from various standard flip-chip processes to a configuration wherein the size of a package is reduced to only slightly larger than the size of the semiconductor die. Chip scale packages are typically created using an interposer substrate. The semiconductor die, with solder balls or bumps such as described above, is attached and electrically connected to the interposer substrate and an encapsulation material is applied over the chip for protection thereof from the elements. The interposer substrate can redistribute signal connections to new locations so they are physically positioned in a desired pattern or arrangement, or to just a different pitch more suitable for mounting to an interposer substrate. An additional set of conductive bumps may then be formed at other contact pad locations on the interposer substrate. The resulting package may then be attached to a carrier substrate such as a printed circuit board.
  • [0012]
    Chip scale packaging enables small packages using desired ball grid arrays or fine ball grid arrays. However, the interposer substrate is typically made of an organic material which is the same as, or similar to, that used for printed circuit boards. There is conventionally a significant mismatch in the coefficients of thermal expansion (CTE) of the interposer substrate and the semiconductor die, often resulting in substantial stress on the mechanical and electrical interconnections formed between the semiconductor die and interposer substrate (e.g., a reflowed solder connection) during the normal thermal cycling during normal operation of the semiconductor die. The use of a ceramic substrate may alleviate some of the CTE mismatch concerns but at a considerably higher cost relative to more conventional interposer substrates.
  • [0013]
    Another advance in the area of multichip modules includes wafer scale integration. Wafer scale integration generally comprises fabricating multiple types of functional semiconductor dice on a single wafer. For example, a four-chip system may be created by placing a microprocessor next to a memory controller and two memory-type semiconductor dice. This pattern may then be repeated across the entire wafer. After fabrication, the wafer is sawed into individual segments with each segment containing the four different functions. However, this approach has not been a very satisfactory solution due to yield problems created by the variations in processes for forming processors and various types of memory-type semiconductor dice. For example, if a defect causes any one of the four functions to be inoperable, the entire segment is defective and not usable.
  • [0014]
    In addition to that described above, there have been advances in bump technologies where the conductive bumps act as the signal connection device. Conventional solder bumps, in some cases, have been replaced by stud bumps. Stud bumps have conventionally been gold, but copper and plated-type stud bumps have also been used recently. The stud bumps may actually comprise short wires or wire stubs applied to a semiconductor die using a conventional wire bonding process. Stud bumping has the advantages of using a more cost effective wire bonding process for application of the bumps in comparison to the more complex, multistep solder bumping process. Further, conductive and conductor-filled adhesives have also been employed to attach the conductive bumps to a carrier substrate. The conductive or conductor-filled adhesive may provide an amount of flexibility to the mechanical and electrical connection, thereby compensating for some of the problems associated with the mismatch of CTE often associated with solder bump processes as discussed above.
  • [0015]
    However, in light of the advances made in fabricating semiconductor device packages, there is a continued need for a reliable, cost effective solution with a higher integration of various functional semiconductor dice in a single package to produce, for example, a system on a semiconductor die solution. There is also a need to create smaller packages with more consistent thermal expansion properties while enabling the redistribution of signal connection devices of the various semiconductor dice to a more convenient, possibly denser, and optionally standard configuration for attachment to a carrier substrate.
  • [0016]
    Finally, it would be advantageous to provide a system on a chip packaging solution using known good dice, such use thereby increasing the yield of usable packages and, thus, improving the efficiency and cost effectiveness associated with producing such packages.
  • BRIEF SUMMARY OF THE INVENTION
  • [0017]
    The present invention includes new packaging implementation methods to solve or at least reduce some of the problems encountered in the prior art. Generally, the present invention provides a multichip multilayer system on a chip-type solution. Greater integration is accomplished using a plurality and variety of known good dice contained within cavities formed in a separate silicon substrate. The term “variety” includes semiconductor dice of not only different types (microprocessor, logic, memory, etc.) but functionally similar semiconductor dice of different dimensions and I/O arrangements. he present invention also contemplates the use of so-called “known good die,” or KGD, as the semiconductor dice to be packaged.
  • [0018]
    The present invention enables the use of processes for making silicon-type semiconductor dice for creating additional redistribution and interconnect layers in the same plane or same planes vertically offset from the multichip arrangement. These additional layers may then be terminated with conductive bumps, optionally in a standard configuration, at the top layer for typical flip-chip application of the assembly to a carrier substrate such as printed circuit board or other multichip module substrate.
  • [0019]
    According to one embodiment of the present invention, a plurality of cavities is etched into the top of a substrate, such as a silicon wafer. The cavities are sized, configured and located to physically receive signal connection devices of a plurality and variety of types of semiconductor dice. The signal connection devices on the semiconductor die may be formed, for example, as gold stud bumps. A semiconductor die attach material adhesive with a high dielectric constant is applied to the top surface of the substrate and in the cavities. The substrate, a wafer, having the semiconductor dice thereon is flipped upside down and placed such that the signal connection devices are received by the cavities with the bond pads on the active surface of each semiconductor die making contact with the die attach material. A layer of molding compound is formed over the top of the substrate and over the backs of the various semiconductor dice. This molding compound creates the package structure, adds mechanical stability, and protects the semiconductor dice from the elements. A portion of the back surface of the substrate is removed, such as by back-grinding or another suitable process, until the signal connection devices are exposed through the back surface of the substrate. With the signal connection devices exposed, a dielectric layer is formed over the entire back surface of the wafer. The dielectric layer is then etched to expose the signal connection devices for use in connection to higher-level packaging.
  • [0020]
    According to another embodiment of the invention, a plurality of cavities is formed in the top surface of a substrate. The cavities are formed to receive the substantial entirety of each of the various semiconductor dice of a plurality to be packaged. Therefore, the cavities are individually sized and configured to correspond with the bond pads of each individual semiconductor die type that is used. It may be desirable to configure the cavities such that the active surface of a semiconductor die placed therein is approximately flush with the surface of the substrate. A die attach material is placed in the die cavities and the semiconductor dice are placed in the cavities with the active surface of each semiconductor die facing upwards and such that the back surfaces of the semiconductor dice contact the die attach material in the bottoms of the cavities. A dielectric layer is formed over the tops of the semiconductor dice, over the top of the substrate and into any gaps between the dice and the cavity sidewalls. Finally, vias are formed in the dielectric layer to expose signal connection devices on the various semiconductor dice.
  • [0021]
    The semiconductor device packages according to the present invention may further undergo a redistribution layer (RDL) process to form signal interconnections between semiconductor dice of the package or to redistribute signals from the signal connection device locations of the various types of semiconductor dice to more convenient and optionally standard locations for interconnection with an external device or component. In the redistribution layer process, a metal layer is deposited and patterned to create an interconnect layer from the exposed signal connection device (e.g., contact pad or conductive bump) locations to other locations.
  • [0022]
    Additional signal layers may be formed if so desired. This signal layering process includes three primary acts: first, a new dielectric layer is formed on the wafer; next, vias are formed in the dielectric layer so connections to an underlying metal layer may be formed; and finally, a new layer of metal is deposited and patterned to create an interconnect on this new layer as well as connections to the underlying layer through the vias.
  • [0023]
    Once the signal layering process is completed for the number of additional interconnect layers desired, a final interconnect layer is formed. At this juncture, a new dielectric layer is formed on the wafer. Next, openings are formed in the dielectric layer sufficient for the formation of new signal connection devices and for connections to the underlying metal layer. Finally the new signal connection devices, such as conductive bumps in the form of solder balls, are formed in the openings.
  • [0024]
    At this point, if desired, testing may be accomplished through the solder balls on each of the individual silicon wafer segments containing a complete system on a wafer segment including various types of semiconductor dice. Finally, the process is completed by sawing the wafer into multichip segments, creating a plurality of individual multichip multilayer systems on chip packages, each ready for test and assembly.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • [0025]
    In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:
  • [0026]
    [0026]FIGS. 1A through 1F show cross-sectional views of a system package at various stages of fabrication according to an embodiment of the present invention;
  • [0027]
    [0027]FIGS. 2A through 2D show cross-sectional views of a system package at various stages of fabrication according to another embodiment of the present invention;
  • [0028]
    [0028]FIGS. 3A through 3F show cross-sectional views of a system package including a redistribution layer according to another embodiment of the present invention;
  • [0029]
    [0029]FIG. 4 is a plan view showing a wafer including a plurality of sections, each containing a plurality of semiconductor dice, according to the present invention;
  • [0030]
    [0030]FIG. 5 is a plan view showing a plurality of multichip modules according to the present invention on a memory device; and
  • [0031]
    [0031]FIG. 6 is a block diagram showing a memory device including at least one of the multichip modules according to the present invention incorporated in a computing system.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0032]
    Referring to drawing FIGS. 1A through 1F, the process of manufacturing a packaged semiconductor device according to an embodiment of the present invention is shown. Illustrated in drawing FIG. 1A is a cross-sectional view of a bare substrate 102. The substrate 102 material may include a conventional silicon wafer or other bulk silicon substrate such as is well known in the art. However, it is understood that this substrate 102 may comprise other well-known substrates such as a ceramic or other suitable material. A plurality of cavities 105 is formed in the top surface 104 of the substrate 102, such as through a conventional anisotropic silicon etching process. The cavities 105 are each defined by a cavity base 108 and cavity walls 110. As indicated in drawing FIG. 1A, the cavity walls 110 may be formed to exhibit a generally rectangular geometry in cross section such that the cavities 105 are generally cubic in shape. However, the cavities 105 may exhibit other geometries such as, for example, cylindrical, conical, frustoconical, pyramidal, frustopyramidal or semispherical.
  • [0033]
    Referring next to drawing FIG. 1B, the top surface 104 of the substrate 102 is coated with a layer of die attach material 112 such as a die attach material which may be applied in a generally liquid form and then soft-baked or cured to a B-stage. The die attach material may include epoxy resins and polyimides, as well as organic and polymer-based resins. Exemplary die attach materials include resins derived from B-stage benzocyclobutene (BCB) and which are available from Dow Chemical Company of Midland, Michigan. The die attach material 112 may be applied to the substrate using a conventional spin or spray coating process wherein the top surface 104 of the substrate 102 is coated and the cavities 105 are filled with the die attach material 112 as will be appreciated by those of ordinary skill in the art. The die attach material 112 material may desirably exhibit, for example, a dielectric constant up to approximately three to ensure adequate electrically insulative properties. It is noted that the soft-bake or B-stage curing of the die attach material helps to prevent movement of the semiconductor dice 114 relative to the substrate 102 during subsequent baking or curing operations.
  • [0034]
    A plurality of discrete semiconductor dice 114is provided, each having a plurality of signal connection devices, shown as conductive bumps 116, attached to bond pads 115. The semiconductor dice 114 are placed upside down with the conductive bumps 116 positioned in the cavities 105 and with the active surface 118 of the semiconductor dice 114 in contact with the die attach material 112. It is noted that the size of the cavities 105 may be etched slightly larger in breadth and/or depth than the size of the conductive bumps 116 in order to ensure proper fit of the conductive bumps 116 within the cavities 105. The conductive bumps 116 may be formed, for example, as gold stud bumps applied with a conventional wire bond process. Other signal connection devices, such as copper stud bumps or plated-type stud bumps may also be used. Although drawing FIGS. 1C through 1F show the conductive bumps 116 as generally spherical balls, the conductive bumps 116 may actually be formed in other shapes, including pillars and columns.
  • [0035]
    In addition, for simplicity, drawing FIGS. 1A through 1F show a single row of conductive bumps 116 positioned extending down the longitudinal axis of each of the semiconductor dice 114, which longitudinal axis is oriented transverse to the plane of the page. However, other conductive bump arrangements such as, for example, an arrangement around the periphery of a semiconductor die 114 or an array of conductive bumps 116 across the active surface 118 of a semiconductor die 114 are also within the scope of the present invention. Furthermore, the semiconductor dice 114 may be of more than one functional variety appropriately arranged so as to create what is referred to as a system on a chip, as will be described in further detail below.
  • [0036]
    With the semiconductor dice 114 attached to the substrate 102, a molding or encapsulating layer 119 is formed over the top surface 104 of the substrate 102 and the back side 120 of the semiconductor dice 114 as shown in drawing FIG. 1D. The molding layer 119 may be any of a variety of compounds known in the art for the purpose of encapsulating the semiconductor dice 114 and substrate 102 to form a typical chip scale package. The molding layer 119 may include a filled polymer and may desirably comprise a material having properties sufficient to allow it to withstand temperatures of up to about 300° C. without substantial degradation thereof.
  • [0037]
    After the molding layer 119 is disposed on the top surface 104 of the substrate 102 and properly cured, a portion of the substrate 102 along its bottom surface 106 is removed as is shown in drawing FIG. 1E. It is noted that, for purposes of clarity, the assembly, as shown in drawing FIG. 1E (as well as in subsequent drawing FIG. 1F), is flipped upside down relative to that which is shown in drawing FIGS. 1A through 1D. The portion of material may be removed from the bottom surface 106 of the substrate 102 by techniques such as back-grinding, abrasive planarization techniques such as chemical-mechanical planarization (CMP), etching or an atmospheric downstream plasma (ADP) process offered by Tru-Si Technologies of Sunnyvale, Calif. which is known by those of ordinary skill in the art. Material is removed from the bottom surface 106 of the substrate 102 until the conductive bumps 116 are exposed, creating a new bottom surface 106′ of the substrate 102, as shown in FIG. 1E. With the conductive bumps 116 exposed, a system on a chip structure has been created with an array of exposed conductive bumps 116.
  • [0038]
    To prepare the wafer for a redistribution layer (RDL) process, a dielectric layer 122 is formed covering the new bottom surface 106′ of the wafer and the conductive bumps 116, as shown in drawing FIG. 1F. Finally, a plurality of vias or openings 124 is formed in the dielectric layer 122 over the conductive bumps 116, such as with a conventional etching process. The assembly may then be subjected to an RDL process to redistribute or relocate the signals to an arrangement of signal device or input/output connections.
  • [0039]
    Before describing the redistribution layer process, another embodiment of the present invention is described as shown in drawing FIGS. 2A through 2D. The process begins, as in the previously described embodiment, with a substrate 202 such as a silicon wafer as shown in drawing FIG. 2A. Again, cavities 205 are formed in the substrate 202, each cavity being defined by a cavity base 208 and cavity walls 210. However, in the presently described embodiment, the cavities 205 are of a size sufficient to receive substantially the entirety of each individual semiconductor die 214. Additionally, the cavities 205 are formed to a depth short of back side 206 sufficient to allow the active surface 220 of the semiconductor dice 214 to be substantially flush with the top surface 204 of the substrate 202. It is noted that, since different types of semiconductor dice 214 may be used, the cavities 205 may accordingly differ in size and shape from one cavity to another.
  • [0040]
    As shown in drawing FIG. 2B, a layer of die attach material 218 is applied in the cavities 205. Discrete semiconductor dice 214 are then placed in the cavities 205 with the active surface 220 of the semiconductor dice 214 facing upwards and the back surface 216 of the semiconductor dice 214 being attached to the base 208 of its respective cavity 205 via the die attach material 218. As shown in drawing FIG. 2C, a first dielectric layer 222 is applied over the top surface 204 of the substrate 202 and which may fill in any gaps 221 between the sides of the semiconductor dice 214 and the cavity walls 210. The first dielectric layer 222 may be applied in a conventional process such as spin coating or spray coating. Finally, as shown in drawing FIG. 2D, a plurality of vias or openings 224 is formed in the first dielectric layer 222, such as by an etching process, thereby exposing the plurality of underlying signal connection devices shown as bond pads 215.
  • [0041]
    The RDL process, which is applicable to both of the exemplary embodiments discussed above, is shown and described with respect to drawing FIGS. 3A through 3F. Illustrated in drawing FIG. 3A is a general substrate 302 with embedded semiconductor dice 304 and signal connection openings 306 representing any embodiment within the scope of the invention. The process begins, as shown in drawing FIG. 3B, by a metallization layer and patterning process to create a first circuit connection layer 308 of metal covering the plurality of signal connection openings 306. In the exemplary embodiments, the signal connection openings 306 expose either the conductive bumps 116 in the embodiment shown and described with respect to drawing FIGS. 1A through 1F or the bond pads 215 in the embodiment shown and described with respect to drawing FIGS. 2A through 2D. This results in an electrical connection to the underlying semiconductor dice 304 and creates first circuit connection layer 308, shown as circuit lines, to redistribute and possibly connect the signals to other metallization layers.
  • [0042]
    The RDL process may incorporate metallization layer deposition and etching processes well known in the art to form the pattern of openings and first circuit connection layers 308. Further, the metal layer may be formed of a material including, for example, aluminum, copper, or other alloys known and utilized in the art. It is also noted that signal connection devices (e.g., the conductive bumps 116 of drawing FIG. 1C or the bond pads 215 of drawing FIG. 2C) may be treated or have an under-bump metallization-type material placed thereon prior to connection with the first circuit connection layer 308 to enhance metallic adhesion therebetween.
  • [0043]
    A predetermined number of additional metal layers may be added in a basic three-step signal connection layering process as shown in drawing FIGS. 3C and 3D. For example, a new additional dielectric layer 310 is formed over the previous metal and dielectric layers, coating the entire wafer. Next, a plurality of vias or openings 312 is created in the dielectric layer 310, such as by etching, exposing the underlying first circuit connection layer 308 at a desired plurality of circuit connection areas. Finally, a new metallization and patterning process creates a new circuit connection layer 314, shown in drawing FIG. 3D, making desired electrical connections to the underlying first circuit connection layer 308 and redistributing signals to new locations, possibly for connection to higher metal layers. For simplicity, the drawing FIGS. 3A-3D show the formation of only one additional metal layer, However, this process may be repeated a predetermined number of times (for example, three times to create three intermediate signal routing layers), thereby forming a laminate-type structure. Multiple layers may be desired to create power planes, ground planes, and difficult signal interconnections not easily accomplished on two signal layers.
  • [0044]
    As shown in drawing FIGS. 3E and 3F, a final dielectric layer 316 is applied over the previous dielectric layer 310 and circuit connection layer 314. Again, a conventional etching process is used to create a plurality of vias or openings 318 in the final dielectric layer 316 exposing the underlying circuit connection layer 314. Finally, new signal device connections 320, such as solder balls or other conductive bumps, are formed in the plurality of openings 318 contacting the underlying circuit connection layer 314.
  • [0045]
    With the new signal device connections 320 formed, if desired, testing could be accomplished through connection with the new signal device connections of each of the individual multichip packages.
  • [0046]
    Referring now to drawing FIG. 4, an assembly 400 containing a plurality of semiconductor dice 404A-404D (collectively referred to as semiconductor dice 404) is shown according to an embodiment of the present invention. The substrate 402 is sawed into individual segments 406 along sawing lines 408 to form individual systems on chip modules with each segment 406 containing a plurality of semiconductor dice 404A-404D possibly of multiple functional varieties. For example, semiconductor die 404A might be a processor, semiconductor die 404B might be a memory controller and semiconductor dice 404C and 404D might be memory chips. Although FIG. 4 shows a segment 406 containing four semiconductor dice 404A-404D, it should be understood that the number of semiconductor dice within a segment 406 may be some other number depending on the design and intended use of the resulting semiconductor package.
  • [0047]
    Referring now to drawing FIG. 5, a memory device 500, also referred to as a memory module, is shown which incorporates at least one packaged multichip semiconductor device 510 according to the present invention. The memory device 500 includes a carrier substrate 520, such as a printed circuit board, to which one or more packaged multichip semiconductor devices 510 may be electrically and operably coupled therewith. A plurality of electrical connectors 530 is formed on the carrier substrate 520 to provide input and output connections with an external device, such as, for example, the motherboard of a computer, to the one or more packaged multichip semiconductor devices 510.
  • [0048]
    Referring now to drawing FIG. 6, a computing system 600 is shown which includes a carrier substrate 602 such as, for example, a motherboard. The carrier substrate 602 may be operably coupled to at least one processor 604, such as, for example, a central processing unit (CPU), and at least one memory device 606. The memory device 606 may include one or more packaged multichip semiconductor devices 608 such as described above. The carrier substrate 602 is operably coupled with at least one input device 610 such as, for example, a keyboard, a mouse, a sensor or another computing device. The carrier substrate 602 is also operably coupled with at least one output device 612 such as, for example, a printer, a monitor, an actuator or another computing device. Alternatively, the packaged multichip semiconductor device 608 may be coupled directly with the carrier substrate 602.
  • [0049]
    Specific embodiments have been shown by way of example in the drawings and have been described in detail herein; however, the invention may be susceptible to various modifications and alternative forms. It should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Claims (8)

    What is claimed is:
  1. 1. A method of manufacturing a multichip package comprising:
    providing a substrate having a top surface and a bottom surface;
    forming a plurality of cavities in the top surface of the substrate, each cavity being defined by a base and at least one cavity wall;
    providing a plurality of semiconductor dice, each semiconductor die having a back surface and a plurality of signal connection devices on an active surface thereof;
    applying a layer of die attach material to the base of each of the plurality of cavities;
    placing the plurality of semiconductor dice in the plurality of cavities with the back surfaces thereof facing the base of the plurality of cavities;
    forming a first dielectric layer upon the top surface of the substrate and the active surfaces of the semiconductor dice including the plurality of signal connection devices; and
    forming a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.
  2. 2. The method of claim 1, further comprising:
    forming a first circuit connection layer on the first dielectric layer; and
    electrically coupling the first circuit connection layer with the plurality of signal connection devices through the plurality of openings;
    forming at least one additional dielectric layer over the first dielectric layer and the first circuit connection layer;
    forming a plurality of openings in the at least one additional dielectric layer exposing a plurality of connection areas on the first circuit connection layer; and
    forming a plurality of conductive bumps in the plurality of openings of the at least one additional dielectric layer and electrically coupling the plurality of conductive bumps with the plurality of connection areas on the first circuit connection layer.
  3. 3. The method of claim 2, wherein providing a substrate includes providing a substrate comprising a silicon wafer.
  4. 4. The method of claim 3, further comprising forming the plurality of signal connection devices to include bond pads.
  5. 5. The method of claim 4, further comprising forming each of the plurality of cavities to exhibit a depth which is substantially equal to or greater than a height of each of the plurality of semiconductor dice.
  6. 6. The method of claim 5, wherein applying a layer of die attach material further includes applying a layer of epoxy material.
  7. 7. The method of claim 5, wherein applying a layer of die attach material further includes applying a layer of benzocyclobutene.
  8. 8. The method of claim 5, wherein applying a layer of die attach material further comprises applying a layer of material exhibiting a dielectric constant of up to about three.
US10873691 2002-08-27 2004-06-22 Multichip wafer level system packages and methods of forming same Abandoned US20040229400A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10229914 US6964881B2 (en) 2002-08-27 2002-08-27 Multi-chip wafer level system packages and methods of forming same
US10873691 US20040229400A1 (en) 2002-08-27 2004-06-22 Multichip wafer level system packages and methods of forming same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10873691 US20040229400A1 (en) 2002-08-27 2004-06-22 Multichip wafer level system packages and methods of forming same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10229914 Division US6964881B2 (en) 2002-08-27 2002-08-27 Multi-chip wafer level system packages and methods of forming same

Publications (1)

Publication Number Publication Date
US20040229400A1 true true US20040229400A1 (en) 2004-11-18

Family

ID=31976352

Family Applications (5)

Application Number Title Priority Date Filing Date
US10229914 Active US6964881B2 (en) 2002-08-27 2002-08-27 Multi-chip wafer level system packages and methods of forming same
US10656352 Active US6825553B2 (en) 2002-08-27 2003-09-05 Multichip wafer level packages and computing systems incorporating same
US10873691 Abandoned US20040229400A1 (en) 2002-08-27 2004-06-22 Multichip wafer level system packages and methods of forming same
US10999435 Active US7087992B2 (en) 2002-08-27 2004-11-30 Multichip wafer level packages and computing systems incorporating same
US11028374 Active 2023-09-10 US7485562B2 (en) 2002-08-27 2005-01-03 Method of making multichip wafer level packages and computing systems incorporating same

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10229914 Active US6964881B2 (en) 2002-08-27 2002-08-27 Multi-chip wafer level system packages and methods of forming same
US10656352 Active US6825553B2 (en) 2002-08-27 2003-09-05 Multichip wafer level packages and computing systems incorporating same

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10999435 Active US7087992B2 (en) 2002-08-27 2004-11-30 Multichip wafer level packages and computing systems incorporating same
US11028374 Active 2023-09-10 US7485562B2 (en) 2002-08-27 2005-01-03 Method of making multichip wafer level packages and computing systems incorporating same

Country Status (1)

Country Link
US (5) US6964881B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060151864A1 (en) * 2005-01-11 2006-07-13 Rosemount Inc. MEMS packaging with improved reaction to temperature changes
US20080295329A1 (en) * 2007-05-30 2008-12-04 Sriram Muthukumar Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US20080295325A1 (en) * 2007-05-30 2008-12-04 Sriram Muthukumar Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
WO2017040967A1 (en) * 2015-09-04 2017-03-09 Octavo Systems Llc Improved system using system in package components

Families Citing this family (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4403631B2 (en) * 2000-04-24 2010-01-27 ソニー株式会社 The method of manufacturing the chip-like electronic component, and manufacturing method of a pseudo wafer used in the manufacture
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
EP1398834A3 (en) * 2002-09-12 2006-03-22 Infineon Technologoes Ag Electronic device with voltage supply structure and method of producing it
US6998328B2 (en) * 2002-11-06 2006-02-14 Irvine Sensors Corp. Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method
US6969909B2 (en) * 2002-12-20 2005-11-29 Vlt, Inc. Flip chip FET device
KR20040066553A (en) * 2003-01-20 2004-07-27 삼성전자주식회사 Integrated monitoring burn in test method for Multi-chip Package
US7135780B2 (en) * 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
US7122404B2 (en) * 2003-03-11 2006-10-17 Micron Technology, Inc. Techniques for packaging a multiple device component
US6856009B2 (en) 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
JP3940694B2 (en) * 2003-04-18 2007-07-04 株式会社東芝 Semiconductor device and manufacturing method thereof
US7208758B2 (en) * 2003-09-16 2007-04-24 Micron Technology, Inc. Dynamic integrated circuit clusters, modules including same and methods of fabricating
DE10355925B4 (en) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg The power semiconductor module and method of manufacturing
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same
DE102004020877A1 (en) * 2004-04-28 2005-12-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Chip module and method of producing a chip module
US20060046433A1 (en) * 2004-08-25 2006-03-02 Sterrett Terry L Thinning semiconductor wafers
US7326629B2 (en) * 2004-09-10 2008-02-05 Agency For Science, Technology And Research Method of stacking thin substrates by transfer bonding
US7524351B2 (en) * 2004-09-30 2009-04-28 Intel Corporation Nano-sized metals and alloys, and methods of assembling packages containing same
US7049208B2 (en) * 2004-10-11 2006-05-23 Intel Corporation Method of manufacturing of thin based substrate
JP5592055B2 (en) 2004-11-03 2014-09-17 テッセラ,インコーポレイテッド Improvement of the laminated packaging
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
JP2006332094A (en) 2005-05-23 2006-12-07 Seiko Epson Corp Process for producing electronic substrate, process for manufacturing semiconductor device and process for manufacturing electronic apparatus
US20070001301A1 (en) * 2005-06-08 2007-01-04 Yongqian Wang Under bump metallization design to reduce dielectric layer delamination
US7300824B2 (en) * 2005-08-18 2007-11-27 James Sheats Method of packaging and interconnection of integrated circuits
US7439098B2 (en) * 2005-09-09 2008-10-21 Advanced Semiconductor Engineering, Inc. Semiconductor package for encapsulating multiple dies and method of manufacturing the same
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20070155049A1 (en) * 2005-12-30 2007-07-05 Advanced Semiconductor Engineering Inc. Method for Manufacturing Chip Package Structures
US8829661B2 (en) 2006-03-10 2014-09-09 Freescale Semiconductor, Inc. Warp compensated package and method
US20070212813A1 (en) * 2006-03-10 2007-09-13 Fay Owen R Perforated embedded plane package and method
US8030138B1 (en) * 2006-07-10 2011-10-04 National Semiconductor Corporation Methods and systems of packaging integrated circuits
US20080054429A1 (en) * 2006-08-25 2008-03-06 Bolken Todd O Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers
US7677701B2 (en) * 2006-09-28 2010-03-16 Lexmark International, Inc. Micro-fluid ejection head with embedded chip on non-conventional substrate
US8061811B2 (en) * 2006-09-28 2011-11-22 Lexmark International, Inc. Micro-fluid ejection heads with chips in pockets
US20080123318A1 (en) * 2006-11-08 2008-05-29 Atmel Corporation Multi-component electronic package with planarized embedded-components substrate
US7829987B2 (en) * 2006-12-20 2010-11-09 Unimicron Technology Corp. Carrier structure embedded with semiconductor chips and method for manufacturing the same
US20080160670A1 (en) * 2006-12-27 2008-07-03 Atmel Corporation Physical alignment features on integrated circuit devices for accurate die-in-substrate embedding
US20080186690A1 (en) * 2007-02-07 2008-08-07 Nokia Corporation Electronics Package And Manufacturing Method Thereof
DE102007012155B4 (en) 2007-03-12 2015-01-22 Intel Mobile Communications GmbH Moldings and benefits with semiconductor chips and processes for making the benefits
US7951697B1 (en) * 2007-06-20 2011-05-31 Amkor Technology, Inc. Embedded die metal etch stop fabrication method and structure
US7923645B1 (en) 2007-06-20 2011-04-12 Amkor Technology, Inc. Metal etch stop fabrication method and structure
US9093322B2 (en) * 2007-07-13 2015-07-28 Intel Mobile Communications GmbH Semiconductor device
US20090047754A1 (en) * 2007-08-17 2009-02-19 Chipmos Technologies (Bermuda) Ltd. Packaging method involving rearrangement of dice
DE102008046761A1 (en) * 2007-09-14 2009-04-09 Infineon Technologies Ag Semiconductor device with conductive connection assembly
US7986023B2 (en) * 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7958626B1 (en) 2007-10-25 2011-06-14 Amkor Technology, Inc. Embedded passive component network substrate fabrication method
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US7927922B2 (en) * 2007-12-20 2011-04-19 Chipmos Technologies Inc Dice rearrangement package structure using layout process to form a compliant configuration
US7662667B2 (en) * 2007-12-20 2010-02-16 Chipmos Technologies Inc Die rearrangement package structure using layout process to form a compliant configuration
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US20090206465A1 (en) * 2008-02-20 2009-08-20 Harvatek Corporation Semiconductor chip package structure for achieving electrical connection without using a wire-bonding process and method for making the same
US20090230554A1 (en) * 2008-03-13 2009-09-17 Broadcom Corporation Wafer-level redistribution packaging with die-containing openings
JP5280079B2 (en) * 2008-03-25 2013-09-04 新光電気工業株式会社 A method for manufacturing a wiring board
US8466550B2 (en) * 2008-05-28 2013-06-18 Agency For Science, Technology And Research Semiconductor structure and a method of manufacturing a semiconductor structure
US20090302465A1 (en) * 2008-06-05 2009-12-10 Cheng-Tang Huang Die rearrangement package structure and method thereof
US7888172B2 (en) * 2008-06-05 2011-02-15 Chipmos Technologies Inc Chip stacked structure and the forming method
US7884461B2 (en) * 2008-06-30 2011-02-08 Advanced Clip Engineering Technology Inc. System-in-package and manufacturing method of the same
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US8168470B2 (en) * 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US8531015B2 (en) 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
JP2010262992A (en) * 2009-04-30 2010-11-18 Sanyo Electric Co Ltd Semiconductor module and portable apparatus
JP5296636B2 (en) * 2009-08-21 2013-09-25 新光電気工業株式会社 A method of manufacturing a semiconductor package
EP2309535A1 (en) 2009-10-09 2011-04-13 Telefonaktiebolaget L M Ericsson (Publ) Chip package with a chip embedded in a wiring body
US8299632B2 (en) * 2009-10-23 2012-10-30 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US8227926B2 (en) * 2009-10-23 2012-07-24 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
DE102009058764A1 (en) 2009-12-15 2011-06-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A process for preparing an electronic assembly and electronic assembly
US8278214B2 (en) * 2009-12-23 2012-10-02 Intel Corporation Through mold via polymer block package
US8409926B2 (en) 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8623699B2 (en) * 2010-07-26 2014-01-07 General Electric Company Method of chip package build-up
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US20120129315A1 (en) * 2010-11-18 2012-05-24 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package
CN102479726B (en) * 2010-11-26 2014-01-22 矽品精密工业股份有限公司 Manufacturing method of semiconductor packaging component
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
KR101422437B1 (en) * 2011-05-13 2014-07-22 이비덴 가부시키가이샤 Circuit board and manufacturing method thereof
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
CN103219297B (en) * 2012-01-20 2016-08-10 矽品精密工业股份有限公司 Carrier plate, a semiconductor package and method
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
JP5728423B2 (en) * 2012-03-08 2015-06-03 株式会社東芝 Method of manufacturing a semiconductor device, a semiconductor integrated device and manufacturing method thereof
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9196537B2 (en) 2012-10-23 2015-11-24 Nxp B.V. Protection of a wafer-level chip scale package (WLCSP)
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9685350B2 (en) * 2013-03-08 2017-06-20 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
KR20160023874A (en) * 2013-06-24 2016-03-03 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 Printed three-dimensional (3d) functional part and method of making
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9496431B2 (en) * 2013-10-09 2016-11-15 Skorpios Technologies, Inc. Coplanar integration of a direct-bandgap chip into a silicon photonic device
DE102013222200A1 (en) * 2013-10-31 2015-08-27 Osram Opto Semiconductors Gmbh Electronic device and method for fabricating an electronic device
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
CN106463463A (en) * 2014-03-31 2017-02-22 穆尔泰拉生物公司 Low-cost packaging for fluidic and device co-integration
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9472518B2 (en) * 2014-04-04 2016-10-18 Micron Technology, Inc. Semiconductor structures including carrier wafers and methods of using such semiconductor structures
CN105097680A (en) 2014-05-16 2015-11-25 飞思卡尔半导体公司 Protective packaging for integrated circuit device
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
CN105321828A (en) * 2014-06-16 2016-02-10 恒劲科技股份有限公司 Package method
US9305809B1 (en) * 2014-06-26 2016-04-05 Stats Chippac Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
US9513913B2 (en) 2014-07-22 2016-12-06 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
CN105405812A (en) * 2014-09-15 2016-03-16 矽品精密工业股份有限公司 Semiconductor package, carrier structure and fabrication method thereof
US9467279B2 (en) 2014-09-26 2016-10-11 Intel Corporation Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
CN105870074A (en) * 2014-12-05 2016-08-17 矽品精密工业股份有限公司 Electronic package and manufacturing method thereof
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
KR20160094548A (en) 2015-01-30 2016-08-10 삼성전자주식회사 Semiconductor package and method of fabricating the same
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
CN105810593A (en) * 2016-05-09 2016-07-27 中芯长电半导体(江阴)有限公司 Fan-out type packaging structure and packaging method therefor
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding

Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181569B2 (en) *
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US4894115A (en) * 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
US4918811A (en) * 1986-09-26 1990-04-24 General Electric Company Multichip integrated circuit packaging method
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4937203A (en) * 1986-09-26 1990-06-26 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US5019946A (en) * 1988-09-27 1991-05-28 General Electric Company High density interconnect with high volumetric efficiency
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US5094709A (en) * 1986-09-26 1992-03-10 General Electric Company Apparatus for packaging integrated circuit chips employing a polymer film overlay layer
US5108825A (en) * 1989-12-21 1992-04-28 General Electric Company Epoxy/polyimide copolymer blend dielectric and layered circuits incorporating it
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5192716A (en) * 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
US5206712A (en) * 1990-04-05 1993-04-27 General Electric Company Building block approach to microwave modules
US5206091A (en) * 1988-06-28 1993-04-27 Amoco Corporation Low dielectric constant, low moisture uptake polyimides and copolyimides for interlevel dielectrics and substrate coatings
US5280192A (en) * 1990-04-30 1994-01-18 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5300812A (en) * 1992-12-09 1994-04-05 General Electric Company Plasticized polyetherimide adhesive composition and usage
US5302547A (en) * 1993-02-08 1994-04-12 General Electric Company Systems for patterning dielectrics by laser ablation
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US5401687A (en) * 1993-04-15 1995-03-28 Martin Marietta Corporation Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5736448A (en) * 1995-12-04 1998-04-07 General Electric Company Fabrication method for thin film capacitors
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5757072A (en) * 1994-12-19 1998-05-26 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US5861322A (en) * 1995-06-30 1999-01-19 Commissariat A L'energie Atomique Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US5872040A (en) * 1994-12-05 1999-02-16 General Electric Company Method for fabricating a thin film capacitor
US5874770A (en) * 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
US5888837A (en) * 1996-04-16 1999-03-30 General Electric Company Chip burn-in and test structure and method
US5897337A (en) * 1994-09-30 1999-04-27 Nec Corporation Process for adhesively bonding a semiconductor chip to a carrier film
US6025258A (en) * 1994-01-20 2000-02-15 Fujitsu Limited Method for fabricating solder bumps by forming solder balls with a solder ball forming member
US6040226A (en) * 1997-05-27 2000-03-21 General Electric Company Method for fabricating a thin film inductor
US6057593A (en) * 1996-10-10 2000-05-02 Samsung Electronics Co., Ltd. Hybrid high-power microwave-frequency integrated circuit
US6175161B1 (en) * 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6214642B1 (en) * 1997-11-21 2001-04-10 Institute Of Materials Research And Engineering Area array stud bump flip chip device and assembly process
US6229203B1 (en) * 1997-03-12 2001-05-08 General Electric Company Semiconductor interconnect structure for high temperature applications
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
US6236109B1 (en) * 1999-01-29 2001-05-22 United Microelectronics Corp. Multi-chip chip scale package
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6239367B1 (en) * 1999-01-29 2001-05-29 United Microelectronics Corp. Multi-chip chip scale package
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6365438B1 (en) * 1997-05-09 2002-04-02 Citizen Watch Co., Ltd. Process for manufacturing semiconductor package and circuit board assembly
US6368896B2 (en) * 1997-10-31 2002-04-09 Micron Technology, Inc. Method of wafer level chip scale packaging
US20020050585A1 (en) * 2000-08-31 2002-05-02 Tobita Masayuki Heat conductive adhesive film and manufacturing method thereof and electronic component
US6389689B2 (en) * 1997-02-26 2002-05-21 Amkor Technology, Inc. Method of fabricating semiconductor package
US6389691B1 (en) * 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US6396153B2 (en) * 1999-10-04 2002-05-28 General Electric Company Circuit chip package and fabrication method
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20020064935A1 (en) * 1999-11-16 2002-05-30 Hirokazu Honda Semiconductor device and manufacturing method the same
US6506664B1 (en) * 1999-04-02 2003-01-14 Imec Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device
US20030013232A1 (en) * 2001-07-11 2003-01-16 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US20030015342A1 (en) * 2000-02-25 2003-01-23 Hajime Sakamoto Multilayer printed wiring board and method for producing multilayer printed wiring board
US6515370B2 (en) * 1997-03-10 2003-02-04 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
US6518163B2 (en) * 1999-12-27 2003-02-11 Fujitsu Limited Method for forming bumps, semiconductor device, and solder paste
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US20030036257A1 (en) * 2001-08-10 2003-02-20 Mutsumi Masumoto Semiconductor device manufacturing method
US20030038378A1 (en) * 1998-05-06 2003-02-27 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein
US6531022B1 (en) * 1996-06-07 2003-03-11 Matsushita Electric Industrial Co., Ltd. Mounting method of semiconductor element
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6548329B1 (en) * 1997-07-28 2003-04-15 General Electric Company Amorphous hydrogenated carbon hermetic structure fabrication method
US6548189B1 (en) * 2001-10-26 2003-04-15 General Electric Company Epoxy adhesive
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US20030087475A1 (en) * 2001-11-08 2003-05-08 Terry Sterrett Method and apparatus for improving an integrated circuit device
US6671948B2 (en) * 2000-12-18 2004-01-06 General Electric Company Interconnection method using an etch stop
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US20040014317A1 (en) * 2000-09-25 2004-01-22 Hajime Sakamoto Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US20040038442A1 (en) * 2002-08-26 2004-02-26 Kinsman Larry D. Optically interactive device packages and methods of assembly
US20040043533A1 (en) * 2002-08-27 2004-03-04 Chua Swee Kwang Multi-chip wafer level system packages and methods of forming same
US6706624B1 (en) * 2001-10-31 2004-03-16 Lockheed Martin Corporation Method for making multichip module substrates by encapsulating electrical conductors
US6707124B2 (en) * 1992-10-26 2004-03-16 Texas Instruments Incorporated HID land grid array packaged device having electrical and optical interconnects
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6709897B2 (en) * 2002-01-15 2004-03-23 Unimicron Technology Corp. Method of forming IC package having upward-facing chip cavity
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6737297B2 (en) * 2000-09-26 2004-05-18 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US6845184B1 (en) * 1998-10-09 2005-01-18 Fujitsu Limited Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
US20050034888A1 (en) * 2001-12-28 2005-02-17 Christian Hoffmann Encapsulated component which is small in terms of height and method for producing the same
US20050048759A1 (en) * 2003-08-28 2005-03-03 Phoenix Precision Technology Corporation Method for fabricating thermally enhanced semiconductor device
US6867499B1 (en) * 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
US6876554B1 (en) * 1999-09-02 2005-04-05 Ibiden Co., Ltd. Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board
US6894395B2 (en) * 2002-02-13 2005-05-17 Sony Corporation System on a chip device including a re-wiring layer formed between groups of electronic devices
US6894384B1 (en) * 1999-11-11 2005-05-17 Oki Electric Industry, Co., Ltd. Semiconductor device and method of manufacturing the same
US6998533B2 (en) * 2002-04-11 2006-02-14 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
US6998644B1 (en) * 2001-08-17 2006-02-14 Alien Technology Corporation Display device with an array of display drivers recessed onto a substrate
US7019406B2 (en) * 2003-05-28 2006-03-28 Siliconware Precision Industries Co., Ltd. Thermally enhanced semiconductor package
US7040697B1 (en) * 2003-03-20 2006-05-09 Timely Innovations, Lp Headrest having an integrated video screen
US7161237B2 (en) * 2002-03-04 2007-01-09 Micron Technology, Inc. Flip chip packaging using recessed interposer terminals
US7189596B1 (en) * 2000-03-01 2007-03-13 Intel Corporation Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US573814A (en) * 1896-12-22 Insect-trap
US3679941A (en) * 1969-09-22 1972-07-25 Gen Electric Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator
JPS49131863U (en) * 1973-03-10 1974-11-13
US4613891A (en) * 1984-02-17 1986-09-23 At&T Bell Laboratories Packaging microminiature devices
US4866501A (en) * 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk A method of mounting an electronic module on a substrate and INTEGRATED CIRCUIT CARD
JPS6369258A (en) 1986-09-10 1988-03-29 Nec Corp Multilayer interconnection substrate
US4714516A (en) * 1986-09-26 1987-12-22 General Electric Company Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4884122A (en) * 1988-08-05 1989-11-28 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US5154793A (en) * 1988-09-27 1992-10-13 General Electric Company Method and apparatus for removing components bonded to a substrate
US4878991A (en) * 1988-12-12 1989-11-07 General Electric Company Simplified method for repair of high density interconnect circuits
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
US5225023A (en) * 1989-02-21 1993-07-06 General Electric Company High density interconnect thermoplastic die attach material and solvent die attach processing
US5258647A (en) * 1989-07-03 1993-11-02 General Electric Company Electronic systems disposed in a high force environment
JPH03211757A (en) * 1989-12-21 1991-09-17 General Electric Co <Ge> Hermetically sealed object
US5169678A (en) * 1989-12-26 1992-12-08 General Electric Company Laser ablatable polymer dielectrics and methods
JP3280394B2 (en) * 1990-04-05 2002-05-13 ロックヒード マーティン コーポレーション The electronic device
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
DE4115043A1 (en) * 1991-05-08 1997-07-17 Gen Electric High density interconnect structure for packaging microwave and other overlay sensitive chips
US5073814A (en) 1990-07-02 1991-12-17 General Electric Company Multi-sublayer dielectric layers
US5157589A (en) * 1990-07-02 1992-10-20 General Electric Company Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentially decreasing TG 's
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5161093A (en) * 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
US5144747A (en) * 1991-03-27 1992-09-08 Integrated System Assemblies Corporation Apparatus and method for positioning an integrated circuit chip within a multichip module
US5149662A (en) * 1991-03-27 1992-09-22 Integrated System Assemblies Corporation Methods for testing and burn-in of integrated circuit chips
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5257178A (en) * 1991-12-19 1993-10-26 General Electric Company Method of optimally operating a computer numerical control milling machine to mill optimal high density interconnect substrates
US5455459A (en) * 1992-03-27 1995-10-03 Martin Marietta Corporation Reconstructable interconnect structure for electronic circuits
US5255431A (en) * 1992-06-26 1993-10-26 General Electric Company Method of using frozen epoxy for placing pin-mounted components in a circuit module
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
US5366906A (en) * 1992-10-16 1994-11-22 Martin Marietta Corporation Wafer level integration and testing
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5796164A (en) * 1993-05-11 1998-08-18 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
US5432675A (en) * 1993-11-15 1995-07-11 Fujitsu Limited Multi-chip module having thermal contacts
CN1045865C (en) * 1994-03-18 1999-10-20 株式会社日立制作所 Fastening base board
US5434751A (en) * 1994-04-11 1995-07-18 Martin Marietta Corporation Reworkable high density interconnect structure incorporating a release layer
US5449427A (en) * 1994-05-23 1995-09-12 General Electric Company Processing low dielectric constant materials for high speed electronics
JPH0860103A (en) 1994-08-26 1996-03-05 Nitto Denko Corp Sheet type adhesive
US5546654A (en) * 1994-08-29 1996-08-20 General Electric Company Vacuum fixture and method for fabricating electronic assemblies
US5548099A (en) * 1994-09-13 1996-08-20 Martin Marietta Corporation Method for making an electronics module having air bridge protection without large area ablation
US5524339A (en) * 1994-09-19 1996-06-11 Martin Marietta Corporation Method for protecting gallium arsenide mmic air bridge structures
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
JP2792532B2 (en) * 1994-09-30 1998-09-03 日本電気株式会社 Manufacturing method and a semiconductor wafer of a semiconductor device
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
CA2135508C (en) * 1994-11-09 1998-11-03 Robert J. Lyn Method for forming solder balls on a semiconductor substrate
US5675310A (en) * 1994-12-05 1997-10-07 General Electric Company Thin film resistors on organic surfaces
US5559363A (en) * 1995-06-06 1996-09-24 Martin Marietta Corporation Off-chip impedance matching utilizing a dielectric element and high density interconnect technology
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6093971A (en) * 1996-10-14 2000-07-25 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Chip module with conductor paths on the chip bonding side of a chip carrier
US5691245A (en) * 1996-10-28 1997-11-25 He Holdings, Inc. Methods of forming two-sided HDMI interconnect structures
US5817541A (en) * 1997-03-20 1998-10-06 Raytheon Company Methods of fabricating an HDMI decal chip scale package
US5998291A (en) * 1997-04-07 1999-12-07 Raytheon Company Attachment method for assembly of high density multiple interconnect structures
US6426642B1 (en) * 1999-02-16 2002-07-30 Micron Technology, Inc. Insert for seating a microelectronic device having a protrusion and a plurality of raised-contacts
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6255137B1 (en) * 1999-07-01 2001-07-03 Lockheed Martin Corp. Method for making air pockets in an HDI context
US6774473B1 (en) * 1999-07-30 2004-08-10 Ming-Tung Shen Semiconductor chip module
US6284564B1 (en) * 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6475877B1 (en) * 1999-12-22 2002-11-05 General Electric Company Method for aligning die to interconnect metal on flex substrate
US6426545B1 (en) * 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6489185B1 (en) * 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US20020070443A1 (en) * 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US9030029B2 (en) * 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
KR100907232B1 (en) * 2002-05-31 2009-07-10 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Semiconductor device and manufacturing method thereof
US6756662B2 (en) * 2002-09-25 2004-06-29 International Business Machines Corporation Semiconductor chip module and method of manufacture of same

Patent Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181569B2 (en) *
US5094709A (en) * 1986-09-26 1992-03-10 General Electric Company Apparatus for packaging integrated circuit chips employing a polymer film overlay layer
US4918811A (en) * 1986-09-26 1990-04-24 General Electric Company Multichip integrated circuit packaging method
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4937203A (en) * 1986-09-26 1990-06-26 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5206091A (en) * 1988-06-28 1993-04-27 Amoco Corporation Low dielectric constant, low moisture uptake polyimides and copolyimides for interlevel dielectrics and substrate coatings
US5019946A (en) * 1988-09-27 1991-05-28 General Electric Company High density interconnect with high volumetric efficiency
US5192716A (en) * 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US4894115A (en) * 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
US5108825A (en) * 1989-12-21 1992-04-28 General Electric Company Epoxy/polyimide copolymer blend dielectric and layered circuits incorporating it
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
US5206712A (en) * 1990-04-05 1993-04-27 General Electric Company Building block approach to microwave modules
US5280192A (en) * 1990-04-30 1994-01-18 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US6707124B2 (en) * 1992-10-26 2004-03-16 Texas Instruments Incorporated HID land grid array packaged device having electrical and optical interconnects
US5300812A (en) * 1992-12-09 1994-04-05 General Electric Company Plasticized polyetherimide adhesive composition and usage
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US5302547A (en) * 1993-02-08 1994-04-12 General Electric Company Systems for patterning dielectrics by laser ablation
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5401687A (en) * 1993-04-15 1995-03-28 Martin Marietta Corporation Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US6025258A (en) * 1994-01-20 2000-02-15 Fujitsu Limited Method for fabricating solder bumps by forming solder balls with a solder ball forming member
US5897337A (en) * 1994-09-30 1999-04-27 Nec Corporation Process for adhesively bonding a semiconductor chip to a carrier film
US5872040A (en) * 1994-12-05 1999-02-16 General Electric Company Method for fabricating a thin film capacitor
US5757072A (en) * 1994-12-19 1998-05-26 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US6389691B1 (en) * 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US5861322A (en) * 1995-06-30 1999-01-19 Commissariat A L'energie Atomique Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US5736448A (en) * 1995-12-04 1998-04-07 General Electric Company Fabrication method for thin film capacitors
US5888837A (en) * 1996-04-16 1999-03-30 General Electric Company Chip burn-in and test structure and method
US6531022B1 (en) * 1996-06-07 2003-03-11 Matsushita Electric Industrial Co., Ltd. Mounting method of semiconductor element
US5874770A (en) * 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
US6057593A (en) * 1996-10-10 2000-05-02 Samsung Electronics Co., Ltd. Hybrid high-power microwave-frequency integrated circuit
US6389689B2 (en) * 1997-02-26 2002-05-21 Amkor Technology, Inc. Method of fabricating semiconductor package
US6515370B2 (en) * 1997-03-10 2003-02-04 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
US6229203B1 (en) * 1997-03-12 2001-05-08 General Electric Company Semiconductor interconnect structure for high temperature applications
US6365438B1 (en) * 1997-05-09 2002-04-02 Citizen Watch Co., Ltd. Process for manufacturing semiconductor package and circuit board assembly
US6040226A (en) * 1997-05-27 2000-03-21 General Electric Company Method for fabricating a thin film inductor
US6548329B1 (en) * 1997-07-28 2003-04-15 General Electric Company Amorphous hydrogenated carbon hermetic structure fabrication method
US6368896B2 (en) * 1997-10-31 2002-04-09 Micron Technology, Inc. Method of wafer level chip scale packaging
US6214642B1 (en) * 1997-11-21 2001-04-10 Institute Of Materials Research And Engineering Area array stud bump flip chip device and assembly process
US20030038378A1 (en) * 1998-05-06 2003-02-27 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein
US6175161B1 (en) * 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6845184B1 (en) * 1998-10-09 2005-01-18 Fujitsu Limited Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6236109B1 (en) * 1999-01-29 2001-05-22 United Microelectronics Corp. Multi-chip chip scale package
US6239367B1 (en) * 1999-01-29 2001-05-29 United Microelectronics Corp. Multi-chip chip scale package
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
US6506664B1 (en) * 1999-04-02 2003-01-14 Imec Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6350668B1 (en) * 1999-06-07 2002-02-26 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
US6876554B1 (en) * 1999-09-02 2005-04-05 Ibiden Co., Ltd. Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board
US6867499B1 (en) * 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
US6396153B2 (en) * 1999-10-04 2002-05-28 General Electric Company Circuit chip package and fabrication method
US6894384B1 (en) * 1999-11-11 2005-05-17 Oki Electric Industry, Co., Ltd. Semiconductor device and method of manufacturing the same
US20020064935A1 (en) * 1999-11-16 2002-05-30 Hirokazu Honda Semiconductor device and manufacturing method the same
US6518163B2 (en) * 1999-12-27 2003-02-11 Fujitsu Limited Method for forming bumps, semiconductor device, and solder paste
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US20030015342A1 (en) * 2000-02-25 2003-01-23 Hajime Sakamoto Multilayer printed wiring board and method for producing multilayer printed wiring board
US7189596B1 (en) * 2000-03-01 2007-03-13 Intel Corporation Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020050585A1 (en) * 2000-08-31 2002-05-02 Tobita Masayuki Heat conductive adhesive film and manufacturing method thereof and electronic component
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US20040014317A1 (en) * 2000-09-25 2004-01-22 Hajime Sakamoto Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US6737297B2 (en) * 2000-09-26 2004-05-18 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6671948B2 (en) * 2000-12-18 2004-01-06 General Electric Company Interconnection method using an etch stop
US20040099947A1 (en) * 2000-12-18 2004-05-27 Burdick William Edward Interconnection method and structure
US20030013232A1 (en) * 2001-07-11 2003-01-16 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US20030036257A1 (en) * 2001-08-10 2003-02-20 Mutsumi Masumoto Semiconductor device manufacturing method
US6998644B1 (en) * 2001-08-17 2006-02-14 Alien Technology Corporation Display device with an array of display drivers recessed onto a substrate
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6548189B1 (en) * 2001-10-26 2003-04-15 General Electric Company Epoxy adhesive
US6706624B1 (en) * 2001-10-31 2004-03-16 Lockheed Martin Corporation Method for making multichip module substrates by encapsulating electrical conductors
US20030087475A1 (en) * 2001-11-08 2003-05-08 Terry Sterrett Method and apparatus for improving an integrated circuit device
US6982380B2 (en) * 2001-12-28 2006-01-03 Epcos Ag Encapsulated component which is small in terms of height and method for producing the same
US20050034888A1 (en) * 2001-12-28 2005-02-17 Christian Hoffmann Encapsulated component which is small in terms of height and method for producing the same
US6709897B2 (en) * 2002-01-15 2004-03-23 Unimicron Technology Corp. Method of forming IC package having upward-facing chip cavity
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US6894395B2 (en) * 2002-02-13 2005-05-17 Sony Corporation System on a chip device including a re-wiring layer formed between groups of electronic devices
US7161237B2 (en) * 2002-03-04 2007-01-09 Micron Technology, Inc. Flip chip packaging using recessed interposer terminals
US6998533B2 (en) * 2002-04-11 2006-02-14 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
US20040038442A1 (en) * 2002-08-26 2004-02-26 Kinsman Larry D. Optically interactive device packages and methods of assembly
US20040043533A1 (en) * 2002-08-27 2004-03-04 Chua Swee Kwang Multi-chip wafer level system packages and methods of forming same
US7040697B1 (en) * 2003-03-20 2006-05-09 Timely Innovations, Lp Headrest having an integrated video screen
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US7019406B2 (en) * 2003-05-28 2006-03-28 Siliconware Precision Industries Co., Ltd. Thermally enhanced semiconductor package
US20050048759A1 (en) * 2003-08-28 2005-03-03 Phoenix Precision Technology Corporation Method for fabricating thermally enhanced semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060151864A1 (en) * 2005-01-11 2006-07-13 Rosemount Inc. MEMS packaging with improved reaction to temperature changes
US7642628B2 (en) * 2005-01-11 2010-01-05 Rosemount Inc. MEMS packaging with improved reaction to temperature changes
US20080295329A1 (en) * 2007-05-30 2008-12-04 Sriram Muthukumar Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US20080295325A1 (en) * 2007-05-30 2008-12-04 Sriram Muthukumar Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US7841080B2 (en) 2007-05-30 2010-11-30 Intel Corporation Multi-chip packaging using an interposer with through-vias
US7882628B2 (en) * 2007-05-30 2011-02-08 Intel Corporation Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US20110067236A1 (en) * 2007-05-30 2011-03-24 Sriram Muthukumar Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US8387240B2 (en) 2007-05-30 2013-03-05 Intel Corporation Methods for making multi-chip packaging using an interposer
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
WO2017040967A1 (en) * 2015-09-04 2017-03-09 Octavo Systems Llc Improved system using system in package components

Also Published As

Publication number Publication date Type
US6825553B2 (en) 2004-11-30 grant
US20050073029A1 (en) 2005-04-07 application
US7087992B2 (en) 2006-08-08 grant
US7485562B2 (en) 2009-02-03 grant
US6964881B2 (en) 2005-11-15 grant
US20040046250A1 (en) 2004-03-11 application
US20050116337A1 (en) 2005-06-02 application
US20040043533A1 (en) 2004-03-04 application

Similar Documents

Publication Publication Date Title
US7344917B2 (en) Method for packaging a semiconductor device
US6946325B2 (en) Methods for packaging microelectronic devices
US6472745B1 (en) Semiconductor device
US6852607B2 (en) Wafer level package having a side package
US6359790B1 (en) Multichip module having a silicon carrier substrate
US5637920A (en) High contact density ball grid array package for flip-chips
US6559528B2 (en) Semiconductor device and method for the fabrication thereof
US6784525B2 (en) Semiconductor component having multi layered leadframe
US6495912B1 (en) Structure of ceramic package with integrated passive devices
US6582992B2 (en) Stackable semiconductor package and wafer level fabrication method
US20080150155A1 (en) Stacked-die packages with silicon vias and surface activated bonding
US20030124767A1 (en) Integrated chip package structure using ceramic substrate and method of manufacturing the same
US20080048309A1 (en) Metal core foldover package structures, systems including same and methods of fabrication
US20020070443A1 (en) Microelectronic package having an integrated heat sink and build-up layers
US20080237828A1 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
US7345361B2 (en) Stackable integrated circuit packaging
US20090206461A1 (en) Integrated circuit and method
US20020030261A1 (en) Multi-flip-chip semiconductor assembly
US20080136004A1 (en) Multi-chip package structure and method of forming the same
US6271056B1 (en) Stacked semiconductor package and method of fabrication
US6627998B1 (en) Wafer scale thin film package
US6903458B1 (en) Embedded carrier for an integrated circuit chip
US20090321915A1 (en) System-in-package and manufacturing method of the same
US20080111233A1 (en) Semiconductor package with embedded die
US6965160B2 (en) Semiconductor dice packages employing at least one redistribution layer