Multisampling with reduced bit samples
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 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
 H04N5/00—Details of television systems
 H04N5/30—Transforming light or analogous information into electric information
 H04N5/335—Transforming light or analogous information into electric information using solidstate image sensors [SSIS]
 H04N5/357—Noise processing, e.g. detecting, correcting, reducing or removing noise

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
 H04N5/00—Details of television systems
 H04N5/30—Transforming light or analogous information into electric information
 H04N5/335—Transforming light or analogous information into electric information using solidstate image sensors [SSIS]
Abstract
A relatively noncomplex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample from a group of samples in a multiple sample to be transmitted to the signal processor at full resolution. The subsequent samples in that group can be transmitted using only a subset of least significant bits. The minimum number of required LSBs is based upon the level of noise in the system. In one embodiment, the number of LSBs transmitted is k+2 per sample, where k indicates the number bits corresponding to peak noise. In an alternative embodiment, each subsequent sample is transmitted using only k+1 bits.
Description
 [0001]The present invention relates generally to analogtodigital conversion of multiple digital signal samples, and more particularly to a method and apparatus for performing multiple digital sampling using a reduced number of bits.
 [0002]A digital imaging device may be arranged to produce digital image signals using multiple digital samples of pixel signals. FIG. 1 is a block diagram of an exemplary imaging sensor system 100. The system 100 includes an active pixel sensor array 101, which includes a plurality of pixels P arranged in an array. The array 101 is coupled via pairs of signal lines 111 to a plurality of sampleandhold circuits 102 a. The plurality of sampleandhold circuits 102 a are coupled to an analogtodigital converter 102 b via signal line 112 a. The analogtodigital converter 102 b is coupled to a buffer 103 via data path 112 b, and the buffer 103 is coupled to a signal processor 104 via a data path 113. The system 100 converts optical information focused upon the pixels P of the array 101 into a processed electronic signal S. The system 100 includes other well known components, such as a memory controller, a timing controller, a column decoder, and a row decoder, which are not illustrated in order to avoid cluttering the figure. The system 100 may also include additional components for further processing or using the signal S, such as mass storage devices, display drivers, etc.
 [0003]Each pixel P of array 101 produces two signals, namely a reset signal Vrst and a photo signal Vsig. The reset signals Vrst of each pixel P in a selected row are simultaneously output via a respective column line 111 to a corresponding sampleandhold circuit in the plurality of sampleandhold circuits 102 a. At a different time the photo signals Vsig of each pixel in the selected row are similarly output using respective lines 111. The sampleandhold circuit 102 a includes a differential amplifier output stage which subtract the reset and photo signals (VrstVsig) which represent the incident light on a pixel.
 [0004]The analogtodigital converter 102 b sequentially converts the electrical signal from each one of the sampleandhold circuits 102 a into digital form, and provides the digital data via data path 112 b to a buffer 103.
 [0005]The system 100 supports multiple sampling. Multiple sampling is a technique where multiple samples are taken of the same pixel and each sample is stored for further processing. When multiple sampling, the system repeatedly performs the above described processing so that each pixel has its photo and reset signal repeatedly read, converted to a single electric signal, and converted to digital form. The multiple digital values are stored in separate locations of the buffer 103 so that they can be separately accessed by the signal processor 104 over data path 113.
 [0006]One reason for performing multiple sampling is to reduce the effect of noise. Since noise is a random signal, the noise component across several samples should at least partially cancel out. Thus, if multiple samples were summed and then divided by the number of samples, the noise components should be diminished and the resulting average value over the multiple samples should be a more accurate reflection of the true signal value.
 [0007]The drawback to using multiple sampling is one of increased logic complexity. For example, the system 100 may utilize four times multisampling. That is, each pixel is sampled four times. In order to calculate an average value over four samples, the four samples must be summed, which requires the use of a wide adder. More specifically, for four times multiple sampling, the adder must be two bits wider than the full resolution of each sample. Another drawback of using multiple sampling is the increased communication bandwidth required to transmit the multiple samples from the buffer 103 to the signal processor 104. For example, four times multisampling requires four times the inputoutput bandwidth between the buffer 103 and the signal processor 104.
 [0008]The present invention provides a signal processor which supports multiple signal sampling. The signal processor does not require full resolution transmission of each one of the multiple samples, thereby decreasing the data throughput requirement between the signal processor and the buffer memory. Rather, the first one of a set of multiple samples is transmitted from the buffer memory to the signal processor at full resolution. A subset of least significant bits of each subsequent sample are then transmitted from the memory to the signal processor. The size of the required subset is dependent upon the level of noise within the system. The signal processor is able to produce a sum of the multiple pixel samples utilizing the transmitted full resolution sample and the subsets of subsequent samples. The multiple signal sampling employed in the invention may be applied to pixel signals of an active pixel sensor imaging system.
 [0009]The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings, in which:
 [0010][0010]FIG. 1 is a block diagram of a prior art active pixel sensor imaging system;
 [0011][0011]FIG. 2 is a block diagram of an active pixel sensor imaging system;
 [0012][0012]FIG. 3 is a block diagram of a signal processor;
 [0013][0013]FIG. 4 is flow chart illustrating the operation of the signal processor of FIG. 3; and
 [0014][0014]FIG. 5 is a block diagram of a computer system with the signal processor.
 [0015]The invention will now be described below in the context of its use with multiple digital samples of pixel signals form a digital image. However, the invention has applicability in any context employing multiple digital signal samples. Now referring to the drawings, where like reference numeral designate like elements, there is shown in FIG. 2 an exemplary embodiment of the invention employed in an image system 200. System 200 is similar to system 100 and shares several common parts. For example, both systems 100 and 200 utilize the same pixel array 101, sampleandhold circuits 102, and buffer 103. In one exemplary embodiment, the pixel array 101 may be a VGA resolution (e.g., 640×480) pixel array and the analogtodigital converter produces 10bit samples. System 200, however, utilizes a signal processor 204, which is operated differently from that of FIG. 1. Like system 100, system 200 also supports multiple sampling.
 [0016]When performing multiple sampling, each sample is generally at a different, but similar value. The difference in values are caused by noise in system 200. The amount of noise can be characterized by k, which indicates the power of the peak noise level in the system 200 as a number of bits. For example, if performing four times multisampling of a pixel results in sample values (in decimal notation) of 512, 511, 509, and 515, the difference between the highest sample (515) and the lowest sample (509) is 6, which can be encoded by 3 bits. If further sampling confirms that no two samples of the same pixel exceed a difference of 7 then k can be set to 3 because 3bits is the minimum number of bits required to express that difference.
 [0017]The signal processor 204 is capable of calculating a sum of a group of multiple samples without requiring the full resolution of each sample in the group to be transmitted to the signal processor. More specifically, the signal processor 204 requires the first sample of a group of samples to be transmitted to the signal processor at full resolution, while each of the remaining samples only needs to be transmitted using a subset of their least significant bits. The number of least significant bits required to be transmitted is at least a function of the noise level in the system 200, and in one exemplary embodiment is equal to k+2 bits. If the buffer 103 supports data transmission at both full and partial resolutions (i.e., if buffer 103 can be toggled to output different word sizes, one corresponding to the full sample width and at least another corresponding to the k+2 least significant bits of a sample), the subsequent samples can be transmitted using only their k+2 least significant bit portions, thereby decreasing data throughput requirements. For example, if system 100 (FIG. 1) were operated at four times multiple sampling, 10bits per sample, and has a noise level corresponding to k=3 would require 40bits (four samples times 10bits per sample) of communication bandwidth on data path 113. In contrast, a system 200 would require only 25 bits (10bits for the first sample and 5bits for each subsequent sample) to be communicated on data path 213. Using these parameters with the system 200 therefore reduces the required communication bandwidth to approximately 63% of the prior art system 100. Alternatively, buffer 103 may transmit each sample at full sample width and the signal processor 204 can mask out the appropriate set of most significant bits from each of the subsequent samples and process only 25 bits.
 [0018]From a theoretical perspective, signal processor 204 is capable of operating with fewer communicated bits because the signal processor is capable of reconstructing the full resolution of the subsequent samples from just their respective least significant bits. This is because the effect of noise is bounded and the number of least significant bits (i.e., k+2) is a function of at least the noise. More specifically, Table 1 below provides a set of rules for identifying the nontransmitted most significant bits (MSBs) of the subsequent samples. In Table 1, the (k+2)^{th }bit in the first sample is compared against the (k+2)^{th }and (k+1)^{th }bits in a subsequent sample. The MSBs of each of the subsequent samples will be either identical to, one less than, or one greater than, the corresponding MSBs of the first sample.
TABLE 1 (k + 2)^{th }bit in first sample 0 1 (k + 2)^{th }and (k + 1)^{th} 0, 0 The MSBs of the The MSBs of the bits in a subsequent subsequent sample are subsequent sample are equal samples identical to MSBs of the to MSBs of the first sample first sample. plus 1. For example, if the MSB portion of the first (i.e., the full resolution) sample were “10011,” if the (k + 2)^{th }bit in that first sample were equal to 1, and the (k + 2)^{th} and (k + 1)^{th }of a subsequent sample were respectively 0 and 0, the MSB of that subsequent sample would be 10011 + 1 or 10100. 0, 1 The MSBs of the The MSBs of a subsequent subsequent sample are sample are identical to MSBs identical to MSBs of the of the first sample. first sample 1, 0 The MSBs of the The MSBs of a subsequent subsequent sample are sample are identical to MSBs identical to MSBs of the of the first sample. first sample 1, 1 The MSBs of a subsequent The MSBs of a subsequent sample are equal to MSBs sample are identical to MSBs of the first sample minus of the first sample. 1. For example, if the MSB portion of the first (i.e., the full resolution) sample were “10011,” if the (k + 2)^{th }bit in that first sample were equal to 0, and the (k + 2)^{th }and (k + 1)^{th} of a subsequent sample were respectively 1 and 1, the MSB of that subsequent sample would be 10011 − 1 or 10010.  [0019]In multiple sampling systems, one frequently performed mathematical operation is calculation of an average value of a group of samples, which can be performed by calculating a sum of the group of samples and then dividing that sum by the number of samples. If the number of samples is a power of 2, as in one exemplary embodiment, the division step can be performed by shifting the sum by a number of bits equal to log_{2}(N), where N is the number of samples. As noted in the background, the average value calculation for a signal, e.g., a pixel signal, may permit a more accurate indication of a sample value because the effect of noise, a uncorrelated signal, may be at least partially cancelled out in the summing portion of the calculation.
 [0020]The summing operation is traditionally performed using a multibit adder circuit. If the samples each have a 10bit resolution and there are four samples per sample group (i.e., the degree of multiple sampling is 4), an traditional adder capable of summing the samples is required to be at least a 12bit adder, which require a large number of gates. However, by taking advantage of the rules set forth in Table 1, above, simpler circuitry can be used to calculate the sum.
 [0021][0021]FIG. 3 is an illustrate of one implementation of a signal processor 204 which takes advantage of the properties of Table 1. The signal processor 204 is illustrated as having a control circuit 301, a LSB adder 302, an adder 303, a magnitude adder 304, a shifter 305, a shifter 307, and an adder 308. The control circuit 301 includes signal lines 306, 309 which can respectively toggle adders 303, 308 between addition and subtraction modes. The control circuit 301 can be any type of circuit or device capable of asserting control signals to govern the below described processing. For example, the control circuit 301 can be a programmed logic array (PLA), or a microcontroller, or a general purpose microprocessor. The control circuit 301 may be assisted by additional circuits such as a memory controller 301 a for transferring data from the buffer 103.
 [0022]Now also referring to FIG. 4, the processing performed by the signal processor 204 is explained. At step S1, the control circuit 301 causes, t, a sum of the LSBs portion of each of the samples to be computed by the adder 302. In the exemplary embodiment, k=3, so the LSBs portion of each sample is (k+2) or 5bits. In the exemplary embodiment, four times multiple sampling is used. The addition of any four binary values may produce a sum up to 2 bits wider than maximum width of the four operands. Thus, the adder 302 must be able to compute a result equal which includes up to (k+2)+2 or 7bits wide. As described below, the variable t becomes one of the operands to adder 303.
 [0023]At step S2, the control circuit 301 causes the shifter 307 to compute the variable A by twice left shifting (and filling with zeros the newly created least significant bits) the MSB portion of the first sample. In the exemplary embodiment, the sample size n=10, k=3, so the MSB portion size is n(k+2)=5 bits. Thus, in the exemplary embodiment, A is a 7bit number having its 5 most significant bits equal to the MSBs portion of the first sample and its 2 least significant bits equal to “00.”
 [0024]Steps S3S7 correspond to an implementation of the rules of Table 1. At step S3, control circuit 301 examines the (k+2)^{th }bit of the first sample. If the bit is equal to zero, execution continues with steps S4 and S5. If it is equal to one, execution instead continues with steps S6 and S7.
 [0025]At step S4, the (k+2)^{th }bit of the first sample has been found to be 0. The control circuit 301 examines the (k+2)^{th }and (k+1)^{th }bits of each sample and provides to the magnitude adder 304 a single bit magnitude of “0” as an operand if the (k+2)^{th }and (k+1)^{th }bits of the sample is “0,0”, “0,1” or “1,0”. Alternatively, a single bit magnitude of “1” is provided as an operand if the (k+2)^{th }and (k+1)^{th }bits of the sample is “1,1”. In the exemplary embodiment, four times multiple sampling is used, so a total of four single bit magnitude values are provided to the magnitude adder 304. The magnitude adder 304 is a 2bit adder, so any overflow to a third bit is lost. Once the magnitude adder 304 has computed a 2bit sum of each of the singlebit magnitudes as described above, the 2bit sum is provided to the shifter 305, and the control circuit 301 causes the shifter 305 to left shift (and zero fills newly created least significant bits) until a 7bit number with its 2 most significant bits equal to the sum computed by the magnitude adder, and its 5 least significant bits set to 0 is created. The control circuit 301 then causes the adder 303 is to calculate the variable B as being equal to the number created from the magnitude adder minus the variable t.
 [0026]At step S5, the control circuit 301 causes the adder 308 to compute the sum of the four sample as C=A−B. To obtain the average value of each sample, C must be divided by the number of samples, which in the exemplary embodiment is equal to 4, which is equal to right shifting C by 2bits.
 [0027]If at step S3, the (k+2)^{th }bit were found to be 1, then execution continues from step S6. Step S6 is similar to step S4, however, B is computed as the number created from the magnitude adders plus t.
 [0028]Step S7 is also similar to step S5, however, in step S7, C is computed as C=A+B.
 [0029]Thus, the sum of a group of samples can be computed as described above. The variable C (at step S5 or S7) is the sum of the four samples. The variable C may be divided by the number of samples, which can be performed as a shift operation if the number of samples is a power of two.
 [0030]The above description of the invention is based upon applying the rules expressed in Table 1. Thus, it should be evident that the invention may also be practiced by altering the ordering of, or parallelizing the execution of, at least some of the above described steps. As previously noted, Table 1 requires the k+2 bits of LSBs be transmitted per subsequent sample, where k characterizes the power of peak noise level as a number of bits. The above described exemplary embodiment corresponds to an embodiment which might be a typical imaging sensors. However, it should be recognized that a number of variations are possible. For example, the degree of multisampling, size of each sample, the power of peak noise can all be varied with corresponding adjustments to the above described system.
 [0031][0031]FIG. 5 is an illustration of a processor based system 500 which includes an imaging sensor which contains system 200 incorporating the invention as an integrated circuit. The system 500 also includes at least one CPU 501, a memory 502, and one or more I/O devices 503 a503 c. A bus 504 is coupled to the CPU 501, memory 502, image sensor 200, and I/O devices 503 a503 c.
 [0032]From an information theory perspective, the number of least significant bits transmitted in each subsequent sample can even be reduced to k+1 bits. The rules which apply to the transmission of only k+1 least significant bits with the peak noise level corresponding to k^{th}−(k−2)^{th }(for example, if k=3, then the noise level is 2^{3}−2^{1}=6, or if k=4, then the noise level is 2^{4}−2^{2}=12) are described in Table 2, below:
TABLE 2 (k + 1)^{th}, k^{th }bits in the first sample 0, 0 0, 1 1, 0 1, 1 (k + 1)^{th} 0, 0 The MSBs of the The MSBs of the If (k − 1)^{th }bit of the The MSBs of the and k^{th} subsequent sample subsequent sample first sample is 0, subsequent sample bits in the are equal to the are equal to MSBs then MSBs of are equal to MSBs additional MSBs of the first of the first sample. subsequent are of first sample plus sample sample. equal to MSBs of 1. the first sample minus 1. If (k − 1)^{th }bit of the first sample is 1, then MSBs of subsequent are equal to MSBs of the first sample. 0, 1 The MSBs of the The MSBs of the The MSBs of If the (k − 1)^{th }bit subsequent sample subsequent sample subsequent sample of the first sample are equal to the are equal to the are equal to the is 0, then the MSBs of the first MSBs of the first MSBs of the first MSBs of sample. sample. sample. subsequent sample are equal to the MSBs of first sample. If the (k − 1)^{th }bit of the first sample is 1, then the MSBs of subsequent sample are equal to MSBs of the first sample plus 1. 1, 0 If the (k − 1)^{th }bit of The MSBs of the The MSBs of the The MSBs of the the first sample is 0, subsequent sample subsequent sample subsequent sample then the MSBs of are equal to the are equal to the are equal to the the subsequent MSBs of the first MSBs of the first MSBs of the first sample are equal to sample. sample. sample. MSBs of the first sample minus 1. If (k − 1)^{th }bit of the first sample is 1, then MSBs of the subsequent sample are equal to MSBs of first sample. 1, 1 The MSBs of the If (k − 1)^{th }bit of the The MSBs of the The MSBs of the subsequent sample first sample is 0, subsequent sample subsequent sample are equal to MSBs then the MSBs of are equal to the are equal to the of first sample minus the subsequent MSBs of the first MSBs of the first 1. sample is equal to sample. sample. the MSBs of the first sample minus 1. If (k − 1)^{th }bit of the first sample is 1 then the MSBs of the subsequent sample are equal to the MSBs of the first sample  [0033]The set of rules expressed in Table 2 is more complex than the set of rules expressed in Table 1, and would thus require more complex circuitry at the signal processor. For this reason, the transmission of k+2 bits per subsequent sample and the use of signal processor 204 may be preferred. However, if the constraining factor in a system is communications bandwidth, then the use of k+1 bits per subsequent sample can be used to reduce the amount of data transmission. However, this will require that the signal processor 204 use the more complex rules of Table 2.
 [0034]From an information theory perspective, the number of least significant bits transmitted in each subsequent sample can be reduced to (k+1) bits in an environment where the power of peak noise is equal to a kbit signal. For a sequence of samples having an initial sample S1 which is transmitted at full resolution, and at least one subsequent sample S_{i>l }each of which are transmitted with just their (k+1) least significant bits, we can recover the nontransmitted most significant bits of each subsequent sample. The nontransmitted most significant bits of each subsequent sample will either bit equal to, one greater than, or one less than the corresponding most significant bits of the initial sample.
 [0035]The rules for determining which one of the three cases arises is found in Table 3, wherein x represents the (k+1) least significant bit portion of the initial sample S1, y represents the (k+1) least significant bits of a subsequent sample S_{i>l}, and n represents a kbit binary number wherein each one of said kbits is a binary ‘1’. For example, if the k=3, n would be a 3bit number wherein each bit is a ‘1’, or 111 (binary). To use Table 3, we first compute the values of x, y, n, and (yx) and determine which one of the three categories (yx) falls into the table:
TABLE 3 CASE ‘A’ CASE ‘B’ CASE ‘C’ n > (y − x) > −n (y − x) > n −n > (y − x) The MSBs of the subsequent The MSBs of the subsequent The MSBs of the subsequent sample are equal to the MSBs of sample are equal to the MSBs of sample are equal to the MSBs of the first sample. the first sample minus 1. the first sample plus 1.  [0036]As a first example, suppose x=1010_{2 }(10 decimal), y=0100_{2 }(4 decimal), n=111_{2 }(7 decimal). In this case, (yx) is equal to −6, which fits into case ‘A’ since 7>−6>−7. In case ‘A’ situations, the MSBs of the subsequent sample is equal to the corresponding MSBs of the initial sample. Now suppose y is instead 0010_{2 }(2 decimal), while x and n remain unaltered. (yx) is equal to −8, which now fits into case ‘C’ instead of case ‘A’ since −7>−8. The rule for case ‘C’ is that the MSBs of the subsequent sample (S_{i>l}) is equal to one greater than the corresponding MSBs of the initial sample. Finally, suppose x=0110_{2 }(6 decimal), y=1110_{2 }(14 decimal), while n remains 111_{2 }(7 decimal). In this instance, (yx) is equal to 8, which now fits into case ‘B’ since 8>7. The rule for case ‘B’ is that the MSBs of the subsequent sample (S_{i>l}) is equal to one less than the corresponding MSBs of the initial sample (S1).
 [0037]The present invention provides a method and apparatus to take advantage of the ability to characterize the influence of noise on multiple sample values. By knowing the effect of peak noise as a kbit signal, the present invention permits encoding a plurality of sample values by only sending the first one of said plurality of sample values as a hill resolution value, while the remaining values may be sent as a subset of least significant bits. The number of least significant bits required for each remaining sample value is a function of noise. Once the sample values have been received, rules such as those found in Tables 1 or 3 can be used to reconstruct the nontransmitted information content. When the rules of Table 1 is utilized in transmission, the common procedure of summing a plurality of sample values can be performed using relatively simple circuitry, to include an adder for the least significant bits, a shifter for the most significant bit portion of the first sample, and a magnitude adder. The results produced by the adder, shifter, and magnitude adder can be combined as previously described to permit relatively simple circuitry to calculate a sum of multiple samples while maintaining a low communications bandwidth requirement for the signal processor which computes the sum.
 [0038]While the invention has been described in detail in connection with exemplary embodiment, it should be understood that the invention is not limited to the above disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alternations, substitutions, or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.
Claims (45)
1. A method for transmitting a plurality of digital sample values with reduced bandwidth, comprising:
transmitting an entire digital sample value for a first one of said plurality of sample values; and
transmitting a partial digital sample value for each subsequent sample value, each of said partial subsequent digital sample value having at least a predetermined number of least significant bits;
wherein said predetermined number is related to a value of signal noise and is less than the number of bits in said entire digital sample value.
2. The method of claim 1 , wherein each subsequent sample is transmitted using a same number of least significant bits.
3. The method of claim 1 , wherein said required number is equal to k+1 if said noise is equivalent to a signal having kbits.
4. The method of claim 1 , wherein said required number is equal to k+2 if said noise is equivalent to a signal having kbits.
5. A method for receiving a plurality of sample values, comprising:
receiving an entire sample value for a first one of said plurality of sample values; and
receiving at least a required number of least significant bits for each subsequent sample value;
wherein said required number is related to a value of signal noise.
6. The method of claim 5 , wherein each subsequent sample is transmitted using a same number of least significant bits.
7. The method of claim 6 , wherein each subsequent sample is transmitted using the required number of least significant bits.
8. The method of claim 5 , wherein said required number is equal to k+1 if said noise is equivalent to a signal having kbits.
9. The method of claim 5 , wherein said required number is equal to k+2 if said noise is equivalent to a signal having kbits.
10. The method of claim 5 , further comprising: for each one of the subsequent plurality of samples, recovering an untransmitted plurality of most significant bits.
11. A method for recovering information represented by a plurality of untransmitted most significant bits in a subsequent sample of a group of samples where the first transmitted sample of the group is transmitted with full bit resolution and a noise value in the group of samples is equivalent to a k bit signal, said method comprising:
if a (k+2)bit and a (k+1)bit of the subsequent sample are respectively equal to 0 and 0, and if the (k+2)bit of a first one of the plurality of samples is equal to 1, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples plus one;
otherwise if the (k+2)bit and (k+1)bit of the subsequent sample are respectively equal to 1 and 1, and if the (k+2)bit of the first one of the plurality of samples is equal to 0, setting said untransmitted plurality of most significant bits to be equal the corresponding set of most significant bits in said plurality of samples minus one; and
otherwise setting said untransmitted plurality of most significant bits to be equal to the corresponding set of most significant bits in said first one of the plurality of samples.
12. A method for recovering information represented by a plurality of untransmitted most significant bits in a subsequent sample of a group of samples where the first transmitted sample of the group is transmitted with fill bit resolution and a noise value in the group of samples is equivalent to a kbit signal, said method comprising:
if a (k+1)bit and a kbit of the subsequent sample are respectively equal to 0 and 0, and if a (k+1)bit and kbit of a first sample are respectively equal to 1,1, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples plus 1;
otherwise if the (k+1)bit and the kbit of the subsequent sample are respectively equal to 0 and 1, and if the (k+1)bit, kbit, and (k−1)bit are respectively equal to 1, 1, and 1, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples plus 1;
otherwise if the (k+1)bit and the kbit of the subsequent sample are respectively equal to 1 and 0, and if the (k+1)bit, kbit, and (k−1)bit are respectively equal to 0, 0, and 0, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples minus 1;
otherwise if the (k+1)bit and the kbit of the subsequent sample are respectively equal to 1 and 1, and if the (k+1)bit, and kbit are respectively equal to 0 and 0, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples minus 1;
otherwise if the (k+1)bit and the kbit of the subsequent sample are respectively equal to 1 and 1, and if the (k+1)bit, kbit, and (k−1)bit are respectively equal to 0, 1, and 0, setting said untransmitted plurality of most significant bits to be equal to a corresponding set of most significant bits in said first one of the plurality of samples minus 1; and
otherwise setting said untransmitted plurality of most significant bits to be equal to the corresponding set of most significant bits in said first one of the plurality of samples.
13. A method for computing the sum of a plurality of sample values, comprising:
calculating a sum of only a same number of least significant bits of each sample value;
calculating a magnitude from a subset of bits of said plurality of sample values;
shifting and zerofilling said magnitude;
combining said sum and said magnitude to produce a least significant bits portion of a result; shifting and zerofilling a most significant bits portion of a first one of said plurality of samples to produce a most significant bits portion of the result; and
forming said sum of a plurality of sample values using said least significant bits portion of the result with said most significant bits portion of the result.
14. The method of claim 13 , wherein said same number is equal to k+2, wherein a peak noise of the signal samples can be characterized by a kbit signal.
15. The method of claim 14 , wherein said same number is equal to 5.
16. The method of claim 13 , wherein the number of samples is 4.
17. The method of claim 13 , wherein each sample is a 10bit sample.
18. The method of claim 13 , wherein said step of calculating a magnitude comprises: setting an intermediate result to zero;
for each sample,
if a (k+2)bit of a first one of said plurality of samples is equal to 0, and if the (k+2)bit and (k+1) bit are respectively 1 and 1, summing said intermediate result and 1 and storing said sum in said intermediate result; and
setting said magnitude to said intermediate result.
19. The method of claim 13 , wherein said magnitude is left shifted and zero filled until said magnitude is 7 bits wide.
20. The method of claim 13 , where said step of combining comprises:
if a (k+2)bit of a first of said plurality of samples is equal to 0, subtracting said sum of said same number of least significant bits from magnitude after said shifting and zerofilling; or
if the (k+2)bit of said first of said plurality of samples is equal to 1, summing said sum of said same number of least significant bits with said magnitude after said shifting and zerofilling.
21. A signal processor, comprising:
a control circuit, wherein
said control circuit receives a transmission of a plurality of samples, said transmission being in a format such that
each bit of a first one of said plurality of samples is in the transmission,
only a least significant bits portion of each subsequent one of said plurality of samples is in the transmission, and said least significant bits portion of each subsequent sample has a same number of least significant bits, said same number being a function of a noise component of said plurality of samples.
22. The signal processor of claim 21 , wherein said same number is equal to k+1, wherein peak noise power can be represented as a kbit signal.
23. The signal processor of claim 21 , wherein said same number is equal to k+2, wherein peak noise power can be represented as a kbit signal.
24. The signal processor of claim 21 , said signal processor further comprises:
a least significant bits adder, coupled to and controlled by said control circuit;
a magnitude adder, coupled to and controlled by said control circuit;
an intermediate adder, coupled to and controlled by said control circuit; and
a final adder, coupled to and controlled by said control circuit.
25. The signal processor of claim 24 , wherein said control circuit causes said least significant bits adder to compute a least significant bits sum as a sum of said least significant bits portion.
26. The signal processor of claim 24 , wherein said control circuit compares the least significant bits portion of said first one of said plurality of samples with the least significant bits portion of each one of said plurality of samples, and produces a magnitude bit for each one of said plurality of samples, and causes said magnitude adder to produce a magnitude sum by summing each of said magnitude bits.
27. The signal processor of claim 26 , wherein said controller causes one of said at least one shifter to produce a shifted magnitude sum by shifting and zero filling least significant bits of said magnitude sum.
28. The signal processor of claim 27 , wherein said intermediate adder is used to produce a first intermediate result from said shifted magnitude sum and said least significant bits sum.
29. The signal processor of claim 28 , wherein said control circuit causes one of said at least one shifter to produce a second intermediate result by shifting and zero filling least significant bits of a most significant bits portion of said first of said plurality of samples.
30. The signal processor of claim 29 , wherein said control circuit causes said final adder to produce a sum of said plurality of samples from said first intermediate result and said second intermediate result.
31. An imaging system comprising:
a pixel array that receives an image and provides output signals indicating pixel values resulting from the image;
a sampleandhold circuit that receives and stores output signals from the pixel array;
an analogtodigital converter, that receives stored output signals from the sampleandhold circuit and obtains, for each output signal, a digital value;
a buffer that receives and stores digital values from the analogtodigital converter; and
a signal processor, including a control circuit which receives digital value from said buffer, in a format wherein each bit of a first one of said plurality of samples is in the transmission, only a least significant bits portion of each subsequent one of said plurality of samples is in the transmission, and said least significant bits portion of each subsequent sample has a same number of least significant bits, said same number being a function of noise within said stored digital values.
32. The imaging system of claim 31 , wherein said same number is equal to k+1, wherein peak noise power can be represented as a kbit signal.
33. The imaging system of claim 31 , wherein said same number is equal to k+2, wherein peak noise power can be represented as a kbit signal.
34. The imaging system of claim 31 , wherein said signal processor further comprises,
a least significant bits adder, coupled to and controlled by said control circuit;
a magnitude adder, coupled to and controlled by said control circuit;
an intermediate adder, coupled to and controlled by said control circuit; and
a final adder, coupled to and controlled by said control circuit.
35. The imaging system of claim 34 , wherein said control circuit causes said least significant bits adder to compute a least significant bits sum as a sum of said least significant bits portion.
36. The imaging system of claim 35 , wherein said control circuit compares the least significant bits portion of said first one of said plurality of samples with the least significant bits portion of each one of said plurality of samples, and produces a magnitude bit for each one of said plurality of samples, and causes said magnitude adder to produce a magnitude sum by summing each of said magnitude bits.
37. The imaging system of claim 36 , wherein said controller causes one of said at least one shifter to produce a shifted magnitude sum by shifting and zero filling least significant bits of said magnitude sum.
38. The imaging system of claim 37 , wherein said intermediate adder is used to produce a first intermediate result from said shifted magnitude sum and said least significant bits sum.
39. The imaging system of claim 38 , wherein said control circuit causes one of said at least one shifter to produce a second intermediate result by shifting and zero filling least significant bits of a most significant bits portion of said first of said plurality of samples.
40. The imaging system of claim 39 , wherein said control circuit causes said final adder to produce a sum of said plurality of samples from said first intermediate result and said second intermediate result.
41. The imaging system of claim 41 , wherein said imaging system is embodied on a single integrated circuit.
42. The imaging system of claim 36 , wherein said imaging system is embodied as part of a peripheral device.
43. A method for sampling a plurality of values, each having N bits, the values indicating a sensed input, comprising:
sampling all N bits of a first value; for a subsequent value, sampling M least significant bits where M is less than N; and combining the N bits of the first value with the M bits of the subsequent value to obtain an average value for the sensed input.
44. A method for processing multiple digital samples of a pixel signal, said method comprising:
receiving all bits of one of said multiple digital samples;
receiving a predetermined number of least significant bits of the remaining ones of said multiple digital samples, said predetermined number being related to the magnitude of signal difference among said multiple digital samples; and
processing said received bits to produce a digital signal representing a combination of said multiple digital samples.
45. A method for recovering information represented by a plurality of untransmitted most significant bits in a subsequent sample of a group of samples where the first transmitted sample of the group is transmitted with full bit resolution and a noise value in the group of samples is equivalent to a kbit signal, said method comprising:
subtracting from the transmitted portion of a subsequent sample a corresponding portion of the first transmitted sample to arrive at an intermediate result;
recovering the untransmitted portion of the subsequent sample as being equal to the corresponding portion of the first transmitted sample if the intermediate result is less than the maximum value of a kbit signal and greater than the minimum value of negative one times the maximum value of a kbit signal;
recovering the untransmitted portion of the subsequent sample as being equal to the corresponding portion of the first transmitted sample minus one if the intermediate result is greater than the maximum value of a kbit signal; and
recovering the untransmitted portion of the subsequent sample as being equal to the corresponding portion of the first transmitted sample plus one if the intermediate result is less than negative one times the maximum value of a kbit signal.
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