US20040210854A1 - Parellel electronic design automation: shared simultaneous editing - Google Patents

Parellel electronic design automation: shared simultaneous editing Download PDF

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Publication number
US20040210854A1
US20040210854A1 US10/780,902 US78090204A US2004210854A1 US 20040210854 A1 US20040210854 A1 US 20040210854A1 US 78090204 A US78090204 A US 78090204A US 2004210854 A1 US2004210854 A1 US 2004210854A1
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edit
pcb
master design
client
clients
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Abandoned
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US10/780,902
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Charles Pfeil
Edwin Smith
Vladimir Petunin
Henry Potts
Venkat Natarajan
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Mentor Graphics Corp
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Mentor Graphics Corp
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Priority to US34103701P priority Critical
Priority to US10/269,614 priority patent/US6708313B2/en
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Priority to US10/780,902 priority patent/US20040210854A1/en
Priority claimed from US10/869,923 external-priority patent/US7587695B2/en
Priority claimed from US10/870,497 external-priority patent/US7516435B2/en
Publication of US20040210854A1 publication Critical patent/US20040210854A1/en
Assigned to MENTOR GRAPHICS CORPORATION reassignment MENTOR GRAPHICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: POTTS, HENRY, NATARAJAN, VENKAT, PETUNIN, VLADIMIR, PFEIL, CHARLES, SMITH, EDWIN FRANKLIN
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/74Symbolic schematics

Abstract

A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 10/269,614, filed Oct. 10, 2002 and titled “Parallel Electronic Design Automation: Shared Simultaneous Editing,” now U.S. Pat. No. ______(which application is entitled to the benefit of U.S. Provisional Application Ser. No. 60/341,037, filed Dec. 10, 2001) and incorporated by reference herein.[0001]
  • COPYRIGHT NOTICE
  • A portion of the disclosure of this patent document may contain material which is subject to copyright protection. To the extent that it does, the copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright © 2002, Mentor Graphics Corp., All Rights Reserved. [0002]
  • FIELD OF THE INVENTION
  • This invention relates to the field of electronic design automation tools, and more specifically, to a mechanism for giving users a shared environment for parallel printed circuit board (PCB) design. [0003]
  • BACKGROUND OF THE INVENTION
  • A PCB starts out as a schematic design in which the PCB functionality is laid out as a logical diagram of symbolic representations. When the schematic is finished, the schematic is interpreted, or captured, into a virtual PCB of physical components that make up the PCB functionality as detailed in the schematics. The PCB design can then be used to manufacture an electrical circuit in the form of a printed circuit board. [0004]
  • During the PCB layout process, many users may work on the schematic design to create the virtual PCB. Traditionally, this has been accomplished via a design splitting mechanism whereby each user can check out a corresponding (assigned) piece of the design to make edits to the PCB layout. [0005]
  • To see how edits affect the most current edits to the remainder of the board, and vice versa, the edits are merged back into the original database where the master design is updated with the edits. However, this approach is restrictive in that the user is limited to viewing only areas of the design that are opened by each individual. Consequently, the user cannot see edits that are made to the rest of the board while the user's edits are being made. [0006]
  • Furthermore, there is currently no known mechanism that allows users to simultaneously work in shared areas of a PCB design while maintaining the integrity of the PCB design. [0007]
  • SUMMARY OF THE INVENTION
  • In one aspect of the invention is a method for simultaneously allowing multiple users to edit in shared areas of a master design. The method includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.[0008]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: [0009]
  • FIG. 1 is a block diagram illustrating a prior art system for PCB design, where individual sections of a master design are checked out by users. [0010]
  • FIG. 2 is a block diagram illustrating a general embodiment of the invention, where users are given parallel access to a master design for editing. [0011]
  • FIG. 3 is an entity diagram illustrating a general embodiment of the invention. [0012]
  • FIG. 4 is a block diagram illustrating a first embodiment of the invention, where parallel access is implemented by giving users concurrent editing access to shared areas of a master design. [0013]
  • FIG. 5 is an entity diagram illustrating interaction between a client and a server in accordance with general embodiments of the invention. [0014]
  • FIG. 6 is an entity diagram illustrating interaction between a client and a server in accordance with a first embodiment of the invention. [0015]
  • FIG. 7 is a block diagram illustrating a first conflict prevention mechanism. [0016]
  • FIG. 8 is a block diagram illustrating a second conflict prevention mechanism. [0017]
  • FIG. 9 is a block diagram illustrating a second embodiment of the invention, where parallel access is implemented by giving users editing access to corresponding areas of a master design, and read-only access to other areas of the master design. [0018]
  • FIG. 10 is a block diagram illustrating partitioning. [0019]
  • FIG. 11 is a block diagram illustrating a partitioned master design. [0020]
  • FIG. 12 is a block diagram illustrating netline connectivity when partitioning is implemented. [0021]
  • FIG. 13 is a block diagram illustrating the use of force field widths in netline connectivity. [0022]
  • FIG. 14 is a flowchart illustrating a method in accordance with general embodiments of the invention.[0023]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In one aspect of the invention is a method for allowing a user to edit a PCB design concurrently with allowing the user to view edits to the PCB design by other users. Generally, the method displays a PCB design to a plurality of users. While a first user makes edits to an arbitrary section of the PCB design, a second user makes edits to an arbitrary section of the PCB design while preserving the integrity of the master design. In one embodiment of the invention, arbitrary sections may overlap, allowing each user to edit shared areas of the master design. In another embodiment of the invention, arbitrary sections are mutually exclusive, such that each user edits unshared, exclusive areas of the master design. [0024]
  • The present invention includes various operations, which will be described below. The operations of the present invention may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software. [0025]
  • The present invention may be provided as a computer program product which may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to the present invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), and magneto-optical disks, ROMs (Read Only Memories), RAMs (Random Access Memories), EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electromagnetic Erasable Programmable Read Only Memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. [0026]
  • Moreover, the present invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine-readable medium. [0027]
  • Introduction [0028]
  • A printed circuit board design transitions through many phases before it becomes an electrical circuit. In accordance with a set of specifications, an electrical engineer creates a diagram of the circuit which maps out the functionality of the circuit using symbols. For example, a zig-zag line is used to represent a resistor. The diagram is referred to as a schematic. [0029]
  • In order to manufacture a printed circuit board, it is necessary to take the schematic and change it into a form of artwork that makes a pattern of components and wires, which is used in photographic imaging techniques to manufacture the PCB. The artwork is called a PCB design, and one who works on the PCB design is hereinafter referred to as a user. A user may comprise a designer who edits the PCB concurrently with other users. A user may alternatively comprise any automated program, such as an autoplacement tool, simulation tool, or an autorouter that automatically routes components on a PCB in accordance with netlines defined by a schematic. In still other embodiments of the invention, a user may comprise both a designer and an automated program. In this latter embodiment, any one or more of the users may comprise an automated program that coexists with designers for designing a board. [0030]
  • FIG. 1 is a block diagram that illustrates a prior art system for designing a PCB. The system comprises a plurality of clients [0031] 102, 104, 106 and a server 100, where the server 100 comprises a database 108 to store a master PCB design 116 (hereinafter “master design”), and each of the clients 102, 104, 106 enables users connected thereto to request edits to the master design 116. As used herein, a master design refers to a PCB design which can be edited by the users. Under the illustrated prior art, each user opens a unique piece 110, 112, 114 of the master design 116 to work on. A user may open a corresponding piece 110, 112, 114 of the design 116 from the database 108 and make edits to the corresponding piece 110, 112, 114 of the design 116. However, the user cannot see what edits are being made to the master design 116 by other users, and how edits to the other areas of the master design 116 affect the user's corresponding area. For example, user on client 102 edits and only sees piece 110 of the master design; user on client 104 edits and only sees piece 112 of the master design; and user on client 106 edits and only sees piece 114 of the master design.
  • Upon completion, or at the user's request, the corresponding piece [0032] 110, 112, 114 may be checked back into the database 108. At a later time, any of the users can check out a corresponding piece 110, 112, 114 of the master design 116 to see how the compiled, totality of edits made by all users up to that point affect the user's corresponding piece.
  • FIG. 2 is a block diagram that illustrates a system for parallel PCB design in accordance with general embodiments of the invention. It comprises a plurality of clients [0033] 202, 204, 206, a server 200, where the server 200 has a database 208 for maintaining a master design 116.
  • Each client [0034] 202, 204, 206 enables users to request edits to the master design 116 in parallel with one another while viewing edits made to the master design 116 by other users. Master design 116 comprises the version on the server 200 database 208 which incorporates edit requests from clients that are accepted by the server 200, and may also be referred to as the compiled master design. Master design 216 comprises the version that is edited by a user on a given client 202, 204, 206.
  • When a PCB design is displayed (i.e., master design [0035] 216), it may comprise the entire PCB design, or it may comprise a partial PCB design. For instance, the master design 116 may be distributed amongst several user groups, and embodiments of the invention may be applicable to each user group, such that for a given user group, only their sections are displayed, thereby displaying only a partial PCB design. However, the sections displayed for that user group may comprise shared and exclusive areas as described herein.
  • A user on client [0036] 206, for example, may request edits to the master design 116, and the edit requests are submitted to the server 200. The server 200 processes the edit requests and either accepts the edit requests or rejects them. Rejected edit requests are reported back to the requesting client 206. Accepted edit requests are applied to the master design 116. Clients 202, 204, 206 can then be synchronized with master design 116.
  • In embodiments of the invention, parallel PCB design gives users the ability to view a compiled master design [0037] 116 while requesting edits to the master design 116. In one embodiment, one user may simultaneously edit shared areas of the master design with another user while viewing the master design 116 (shared PCB design). In another embodiment, one user may simultaneously edit unshared, exclusive areas of the master design 116 (distributed PCB design) with another user while viewing the master design 116.
  • An edit request may comprise a list of one or more objects and corresponding commands made by the particular user. Objects include routes, components, traces, vias, text, and drawing objects, for example; and commands include move left, move right, delete, or add, for example. [0038]
  • FIG. 3 illustrates an entity diagram. It comprises n clients [0039] 202, 204, and 206, and a server 200. A compiled master design is presented to the users. A user connected to a given client 204 makes an edit request 300 to edit the master design. If the client 204 has resources for conflict checking and resolution 302 (to be discussed), then the task is performed by the client. If client conflict checking and resolution passes, or if client conflict checking and resolution does not exist, then the edit request 300 is submitted to the server 304. If client conflict checking and resolution does not pass, then the edit request is rejected and another edit request 300 may be made.
  • Once an edit request [0040] 300 is submitted to the server 304, the edit request 300 is placed in a request queue 306 of the server. The request queue may comprise a FIFO (first-in-first-out) queue where edit requests submitted first are processed first; or a priority queue, where certain edit requests (i.e., types of requests, or requests from certain clients) are given priority over other edit requests, for example. When the edit request is eventually taken off the request queue, server conflict checking and resolution 308 (to be discussed) are performed on the edit request. If server conflict checking and resolution passes, then the edit is accepted and the master design is updated 310. The clients can then be synchronized with the master design 312.
  • The following comprise examples of how edits can be detected: [0041]
  • When a user moves an object, he selects it, moves it, and then releases it. An edit is detected once the object has been released. [0042]
  • When a user deletes an object, he selects it, and selects a delete command. An edit is detected when the delete command is selected. (The delete command may embody many variations. For example, a delete button may be selected, or the object to be deleted may be placed in a recycle bin.) [0043]
  • When a user adds an object, an object to be added is selected, placed on the master design, and then released. An edit is detected when the object to be added is released. [0044]
  • The user submits object names and commands. [0045]
  • Shared PCB Design [0046]
  • In one embodiment of the invention is a shared editing system, as illustrated in FIG. 4, where a plurality of users [0047] 202, 204, 206 may simultaneously edit shared area 410 of a PCB design 116, giving each of the users shared access to the PCB design. In embodiments of the invention, shared areas comprise areas of the master design that can be accessed and edited by multiple users. On the other hand, exclusive areas are partitioned and assigned to individual users. Exclusive areas are discussed in further detail in the section entitled “Distributed PCB Design”.
  • For purposes of illustration, it is assumed that the entire board comprises shared areas such that each of the users on the clients [0048] 202, 204, 206 can simultaneously edit and view objects in the entire master design 116, subject to access rights, discussed below. It is also contemplated that shared areas may comprise a subset of areas on a master design 116, such that the master design 116 comprises both shared and exclusive areas. In this latter scenario, edits to the master design 116 in exclusive areas are validated by a corresponding client conflict checking and resolution module; and edits to the master design 116 in shared areas may be validated by a corresponding client conflict checking and resolution module, a server conflict checking and resolution module, or both.
  • In FIG. 5, a client [0049] 202 (only one shown) corresponds to a given user and comprises a processor 500 and an optional memory space 502. The server 200 comprises a processor 504 as well. While illustrated as a one-to-one client-server, and user-client relationship, it should be understood by one of ordinary skill in the art that the configuration is not to be so limited. It should be understood that any single client is merely a portal that allows a user to edit the master design 116 simultaneously with other users. Furthermore, the server 200 should be understood as an appliance for coordinating and managing the edits to the master design 116.
  • In one embodiment, the master design [0050] 216 comprises master design 116 on a client, such as on a thin client (i.e., client having minimal processing resources), where all edit requests are submitted to the server 200. In this embodiment, the server 200 performs all conflict checking and resolution operations to determine whether the edit requests are acceptable, to be discussed.
  • In another embodiment, master design [0051] 216 comprises a copy of the master design 116 in a client's memory space. In this embodiment, conflict checking and resolution operations may be performed by a processor 504 on the server 200 alone, on a processor 500 by the client 202 alone, or may be distributed in various proportions between the respective processors of a given client 202, 204, 206, and the server 200. These are described in more detail below.
  • Access Rights [0052]
  • In general embodiments of the invention, each user has access to the same aspects of the master design as any other user, subject to assignment restrictions (discussed below in “Distributed PCB Design”). In one embodiment, all users have the same access rights. For example, a first user may request edits to the same objects and commands as a second user. In another embodiment, access rights of each user may differ. For example, a first user may only request edits to components, and a second user may only request edits to routes. [0053]
  • Conflict Checking and Resolution [0054]
  • When an edit request is received, conflict checking and resolution operations are performed. Conflict checking comprises checking to prevent edits that violate one or more design rules. Design rules ensure that the design adheres to a predetermined set of rules in order to minimize the probability of fabrication defects. A design rule checker may check for spacing violations, geometry violations, and connectivity violations, for example. For example, when two traces are placed next to each other that are closer than a spacing rule, a design rule violation occurs. [0055]
  • Conflict resolution comprises detecting edits that may conflict, but which may be resolved. For example, if two traces are too close and violate a design rule, then one trace can be moved to resolve the conflict. [0056]
  • As illustrated in FIG. 6, client conflict checking and resolution and server conflict checking and resolution may coexist, or they may exist in isolation. When they coexist, a client conflict checker and resolution module [0057] 600 of a client 202 determines if the master design 216 on the client has any conflicts. If there is a conflict, it is determined if the conflict can be resolved.
  • If the conflict can be resolved, or if there are no conflicts, then the client conflict checker and resolution module [0058] 600 sends the edit request to the server conflict checker and resolution module 602 of the server 200 to determine if any conflicts exist with the master design 116 on the server.
  • If conflicts exist, then the server conflict resolution module [0059] 602 may determine if the conflicts may be resolved. If no conflicts exist, then the edit requests are accepted, and a merger unit 604 of the server 100 applies the edit requests into the master design data structure.
  • A synchronizer [0060] 606 of the server 200 then synchronizes the one or more clients 202, 204, 206 with the compiled master design 116. Synchronizing may comprise, for example, sending master design 116 to a single client upon request from the client; broadcasting master design 116 to all or multiple clients upon request from multiple clients; automatically swapping out a client copy of the master design data structure 216 on each of the clients 202, 204, 206 for the updated master design data structure 116 on the server 200 upon updating the master design; or automatically updating the clients' 202, 204, 206 displays upon updating the master design 116. Of course, these examples do not comprise an exhaustive list.
  • When conflict checking and resolution exist in isolation, either the server performs all conflict checking and resolution; or each client performs all conflict checking and resolution. The server may perform all conflict checking and resolution operations when, for example, clients are thin clients (i.e., clients having minimal processing resources), and the master design [0061] 216 on client comprises master design 116, where edit requests are submitted to the server 200. Clients may perform all conflict checking and resolution when, for example, a master design is partitioned and assigned to individual users such that no inter-client conflicts arise during editing (to be discussed in Distributed PCB Design). In this latter scenario, where edits are made in their respective exclusive areas, if any conflicts still exist after those edits are made (residual conflicts), the server may perform conflict checking and resolution operations. However, this is not necessary, as the residual conflicts may be taken care of after the edits have been applied.
  • When a server performs conflict checking and resolution, in cooperation with the client, or in isolation, the server may implement optimization functions to minimize its workload. For example, it may keep track of which client made the previous edit request that was merged so that if the next edit request comes from the same client, the server knows that it can eliminate certain conflict checking and resolution functions. [0062]
  • Conflict Prevention [0063]
  • To avoid conflicts from occurring in the first place, a number of conflict prevention mechanisms may be employed. One mechanism that can be used to prevent conflicts is the use of protection boundaries as illustrated in FIG. 7. A protection boundary [0064] 700 allows a user to draw a protection border around the user's workspace that temporarily reserves the area for the particular user. The protection border is broadcasted to all clients, and enables a user to edit the master design without encountering conflicts. The protection border may be removed at the user's request. If another user attempts to edit in an area contained in a protected border, a conflict checker prevents it and reports it as an error to the client on which the edit is being attempted.
  • As illustrated in FIG. 8, another mechanism for preventing conflicts is the use of force field widths [0065] 800, 802 along the boundaries of a user's working area to automatically provide a reasonable clearance around the working area. In one embodiment, the user's working area comprises the cursor, where a force field width is applied to the area around the cursor. In other embodiments, the working area may comprise an object closest to the cursor, where a force field width is applied to the area around the object. If another user attempts to edit within the boundaries of a working area protected by force fields, the conflict checker prevents it and reports it as an error to the client on which the edit is being attempted.
  • Another mechanism that can be used is object locking. Object locking entails marking an object as reserved for the client that performs the locking operation and not editable by other clients. Still another mechanism that can be used for conflict prevention is the assignment of netlines to autorouters. Assigning netlines to autorouters prevents one autorouter from routing the same netline differently. [0066]
  • Distributed PCB Design [0067]
  • FIG. 9 is a block diagram of a distributed editing system in accordance with another embodiment of the invention. The system comprises a plurality of clients [0068] 202, 204, 206, and a server 200 having a database 208 to store the master design 116. The master design comprises exclusive areas 910, 912, 914, where each exclusive area 910, 912, 914 may be viewed by all users, but edited by a single user.
  • Like prior art systems, each user is assigned a unique piece [0069] 910, 912, 914 of the master design 116 to work on. However, unlike prior art systems, a user can view the edits to the other pieces of the design being performed by other users concurrently with the user's editing session. For example, exclusive area 910 may correspond to a user on client 202, such that user on client 202 may edit exclusive area 910. User on client 202 is able to edit exclusive area 910, and is also able to view exclusive areas 912, 914 to view the compiled master design.
  • Partitioning [0070]
  • Partitioning is the process whereby a design is segregated into a plurality of areas. Partitioned areas may then be assigned to users, such that only an assigned user may edit that area. An exclusive area, with respect to a given user who is assigned to the exclusive area, can only be edited by the given user. The exclusive area with respect to any other user can only be viewed (i.e., is read-only) by other users. [0071]
  • The area boundaries may be arbitrary, and are not bound to the schematic boundaries. Partitioning may be performed by specific drawing tools that create polygons and can assign attributes such as a name, an owner, etc. to each exclusive area. [0072]
  • In embodiments of the invention, an owner of a design partitions a design into a plurality of sections. For example, as illustrated in FIG. 10, arcs [0073] 1000 and lines 1002 may be used to partition a single layer 1004 of the design 116, or even multiple layers 1006 of the design 116. Sections may be defined by specifying a type of area (i.e., circle, rectangle, polygon); assigning one or more layers to the area; and assigning the section. Each section is then available for editing by a single user. An owner of a design may also be a user.
  • When a section is assigned to a user, the section becomes an exclusive area. An exclusive area is not available for editing by other users, but is available for viewing by other users. An exclusive area may be explicitly assigned whereby the owner of the design specifically assigns a given area to a specific user, or an exclusive area may be implicitly assigned whereby any area that is not explicitly assigned is assigned to the owner of the design by default. Alternatively, each area may be assigned an arbitrary name, and users may reserve areas by checking out exclusive areas on demand. [0074]
  • For purposes of illustration, it is assumed that the whole board is exclusive such that users on the clients [0075] 202, 204, 206 can simultaneously edit in assigned areas while viewing the compiled master design 116, subject to access rights, discussed supra. It is also contemplated that exclusive areas may comprise a subset of areas on a master design 116, such that the master design 116 comprises shared and exclusive areas. In this latter scenario, edits to the master design 116 in exclusive areas are validated by a corresponding client conflict checking and resolution module; and edits to the master design 116 in shared areas may be validated by a corresponding client conflict checking and resolution module, a server conflict checking and resolution module, or both.
  • Editing [0076]
  • As illustrated in FIG. 11, when a user opens a design [0077] 116, all sections corresponding to the user 1100 (i.e., exclusive areas that are assigned to or checked out by the user), as well as shared areas, if any, are available to the user for editing, and all other non-corresponding, exclusive areas 1102, 1104 are available for viewing. In embodiments of the invention, the user may be given an option to display only the parts and routes inside the exclusive areas for the specified user. Other items such as PCB objects, drawing objects, and netlines can be displayed normally.
  • Any objects inside a corresponding exclusive area are available for editing, and any objects outside of a corresponding exclusive area are locked and not available for editing, but are read-only. Objects include but are not limited to routes, components, traces, vias, text, and drawing objects, for example. [0078]
  • Placement Rules [0079]
  • Placement rules help prevent conflicts that may arise during design of a section. For example, since exclusive areas may have layer restrictions, it is possible for a via, a thruhole pin, or a part to exist in multiple exclusive areas. Any object that exists in multiple areas should be locked. An object that would traverse multiple areas (by existing on multiple layers that are assigned to different users) should be prevented from being added. [0080]
  • Furthermore, as illustrated in FIG. 12 (assuming area [0081] 1210 is an exclusive area), netlines 1200, 1202 that start inside an exclusive area, and finish inside an exclusive area may be completely routed; netlines 1204 that start inside an exclusive area, but that finish outside the exclusive area may be routed to the edge of the exclusive area. Once the netline is routed to the edge of one exclusive area, the owner of the adjacent exclusive area (or any user, if it is a shared area) may continue routing the netline in their own area. Netlines 1206 that do not start or end in an exclusive area may be restricted from routing, or may be routed with limitations. In this example, netline 1206 may be routed if its endpoints are on the edge of the exclusive area.
  • Spacing violations may occur when traces are placed too closely to one another. (See Conflict Checking and Resolution, discussed supra.) Spacing violations are likely to occur along the boundary of two sections, or within an exclusive area. As illustrated in FIG. 13, one way to deal with spacing violations that occur along the boundary of two sections, is to allow force field widths [0082] 1300, 1302 (discussed, supra) along the boundaries. Force field widths automatically provide a reasonable clearance between objects along the boundaries, and allow users to design to the edge of an exclusive area without facing potential spacing violations.
  • There are various other possibilities for placement rules that are well known in the art and are not further discussed herein. The examples provided are for illustrative purposes only and are not intended to be limiting on embodiments of the invention. [0083]
  • Flowcharts [0084]
  • FIG. 14 is a flowchart illustrating a method in accordance with general embodiments of the invention as discussed above. It begins at block [0085] 1400 and continues to block 1402 where a master design is displayed to a plurality of clients. In one embodiment, each client views the master design from the server database. In another embodiment, each client maintains a copy of the master design in the client's own memory space.
  • At block [0086] 1404, one or more edit requests are received from multiple users. At block 1406, a given edit request is processed. In one embodiment, an edit request is processed by subjecting the edit request to client conflict checking and resolution, prior to submitting the edit request to the server for server conflict checking and resolution, if needed. In another embodiment, the edit request is directly submitted to the server for server conflict checking and resolution.
  • At block [0087] 1408, it is determined if the edit request has been accepted. If the edit request passes conflict checking and resolution, then it is accepted. Otherwise, the edit request is rejected. If the edit request is accepted, then at block 1412, the master design is updated, and clients are synchronized with master design at block 1414. If the edit request is rejected, it is reported as an error to the appropriate client at block 1410. The method ends at block 1416.
  • CONCLUSION
  • In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. [0088]
  • For example, a master design [0089] 116 may be partitioned into areas, and the areas may then be designated as shared or exclusive, such that both shared and exclusive areas comprise sections.

Claims (38)

1. A method for simultaneous editing of at least a portion of a printed circuit board (PCB) design by multiple users, comprising:
transmitting the PCB design portion to first and second clients for graphical display at each of the clients;
transmitting, for display at each of the clients, a protection boundary associated with a PCB design object being edited at the first client; and
rejecting a request from the second client to edit an object within a region bounded by the protection boundary.
2. The method of claim 1, wherein the protection boundary comprises the object being edited at the first client.
3. A method for editing a printed circuit board (PCB) master design during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, comprising:
transmitting the PCB master design portion to the first and second users at respective first and second clients for graphical display on each of said clients, the graphical displays including representations of PCB artwork corresponding to the PCB master design portion;
receiving, during the editing session, a first edit request from the first client and a second edit request from the second client;
applying the first and second edit requests to the PCB master design; and
transmitting synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the first and second edits.
4. The method of claim 3, further comprising:
receiving a subsequent edit request from the first client to edit an object in the PCB master design portion; and
locking the object so as to prevent editing of the object based on a request received from the second client.
5. The method of claim 3, wherein:
at least one of the edit requests is automatically generated in response to selection of an object and a command,
the object is at least one of a route, a component, a trace, a via, text, and a drawing object, and
the command is at least one of move left, move right, delete and add.
6. The method of claim 3, further comprising:
placing the first and second edit requests in a queue; and
applying the first and second edit requests on a first-in-first-out (FIFO) basis.
7. The method of claim 3, wherein the PCB master design portion comprises an entire PCB design.
8. The method of claim 3, further comprising:
determining if the first edit request conflicts with the second edit request.
9. The method of claim 8, wherein said determining if the first edit request conflicts with the second edit request comprises at least one of:
determining whether acceptance of both the first and second edit requests will violate a spacing rule,
determining whether acceptance of both the first and second edit requests will violate a geometry rule, and
determining whether acceptance of both the first and second edit requests will violate a connectivity rule.
10. The method of claim 3, wherein:
one of the edit requests is automatically generated in response to the first or second user selecting, moving, and then releasing a first object, and
another of the edit requests is automatically generated in response to the first or second user selecting a second object and then moving the second object to a graphically represented deletion area.
11. A method for editing a printed circuit board (PCB) master design during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, comprising:
transmitting the PCB master design portion to the first and second users at respective first and second clients for graphical display on each of said clients, the graphical displays including representations of PCB artwork corresponding to the PCB master design portion;
receiving, during the editing session, a first edit request from the first client and a second edit request from the second client;
applying the first edit request to the PCB master design;
transmitting synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the application of the first edit request;
determining if the first edit request conflicts with the second edit request; and
reporting a conflict between the first and second edit requests to the second client.
12. A server for receiving and processing requests to edit a printed circuit board (PCB) master design during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, comprising:
a database for maintaining the master design;
connections to first and second clients; and
a processor configured to:
transmit the PCB design portion to first and second clients for graphical display at each of the clients,
transmit, for display at each of the clients, a protection boundary associated with a PCB design object being edited at the first client, and
reject a request from the second client to edit an object within a region bounded by the protection boundary.
13. The server of claim 12, wherein the protection boundary comprises the object being edited at the first client.
14. A server for receiving and processing requests to edit a printed circuit board (PCB) master design during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, comprising:
a database for maintaining the master design;
connections to first and second clients; and
a processor configured to:
transmit the PCB master design portion to the first and second users at the respective first and second clients for graphical display on each of said clients, the graphical displays including representations of PCB artwork corresponding to the PCB master design portion,
receive, during the editing session, a first edit request from the first client and a second edit request from the second client,
apply the first and second edit requests to the PCB master design, and
transmit synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the first and second edits.
15. The server of claim 14, wherein the processor is further configured to:
receive a subsequent edit request from the first client to edit an object in the PCB master design portion, and
lock the object so as to prevent editing of the object based on a request received from the second client.
16. The server of claim 14, wherein:
at least one of the edit requests is automatically generated in response to selection of an object and a command,
the object is at least one of a route, a component, a trace, a via, text, and a drawing object, and
the command is at least one of move left, move right, delete and add.
17. The server of claim 14, wherein the processor is further configured to:
place the first and second edit requests in a queue; and
apply the first and second edit requests on a first-in-first-out (FIFO) basis.
18. The server of claim 14, wherein the PCB master design portion comprises an entire PCB design.
19. The server of claim 14, wherein the processor is further configured to:
determine if the first edit request conflicts with the second edit request.
20. The server of claim 19, wherein the processor is configured to determine if the first edit request conflicts with the second edit request by:
determining whether acceptance of both the first and second edit requests will violate a spacing rule,
determining whether acceptance of both the first and second edit requests will violate a geometry rule, and
determining whether acceptance of both the first and second edit requests will violate a connectivity rule.
21. The server of claim 14, wherein:
one of the edit requests is automatically generated in response to the first or second user selecting, moving, and then releasing a first object, and
another of the edit requests is automatically generated in response to the first or second user selecting a second object and then moving the second object to a graphically represented deletion area.
22. A server for receiving and processing requests to edit a printed circuit board (PCB) master design during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, comprising:
a database for maintaining the master design;
connections to first and second clients; and
a processor configured to:
transmit the PCB master design portion to the first and second users at respective first and second clients for graphical display on each of said clients, the graphical displays including representations of PCB artwork corresponding to the PCB master design portion,
receive, during the editing session, a first edit request from the first client and a second edit request from the second client,
apply the first edit request to the PCB master design,
transmit synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the application of the first edit request,
determine if the first edit request conflicts with the second edit request, and
report a conflict between the first and second edit requests to the second client.
23. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform steps comprising:
transmitting a printed circuit board (PCB) design portion to first and second clients for graphical display at each of the clients;
transmitting, for display at each of the clients, a protection boundary associated with a PCB design object being edited at the first client; and
rejecting a request from the second client to edit an object within a region bounded by the protection boundary.
24. The machine-readable medium of claim 23, wherein the protection boundary comprises the object being edited at the first client.
25. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform steps comprising:
transmitting a PCB master design portion during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, wherein:
the PCB master design portion is transmitted to the first and second users at respective first and second clients for graphical display on each of said clients, and
the graphical displays include representations of PCB artwork corresponding to the PCB master design portion;
receiving, during the editing session, a first edit request from the first client and a second edit request from the second client;
applying the first and second edit requests to the PCB master design; and
transmitting synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the first and second edits.
26. The machine readable medium of claim 25, comprising further instructions for performing steps comprising:
receiving a subsequent edit request from the first client to edit an object in the PCB master design portion; and
locking the object so as to prevent editing of the object based on a request received from the second client.
27. The machine readable medium of claim 25, wherein:
at least one of the edit requests is automatically generated in response to selection of an object and a command,
the object is at least one of a route, a component, a trace, a via, text, and a drawing object, and
the command is at least one of move left, move right, delete and add.
28. The machine readable medium of claim 25, comprising further instructions for performing steps comprising:
placing the first and second edit requests in a queue; and
accepting the first and second edit requests on a first-in-first-out (FIFO) basis.
29. The machine readable medium of claim 25, wherein the PCB master design portion comprises an entire PCB design.
30. The machine readable medium of claim 25, comprising further instructions for performing steps comprising:
determining if the first edit request conflicts with the second edit request.
31. The machine readable medium of claim 30, wherein said determining if the first edit request conflicts with the second edit request comprises at least one of:
determining whether acceptance of both the first and second edit requests will violate a spacing rule,
determining whether acceptance of both the first and second edit requests will violate a geometry rule, and
determining whether acceptance of both the first and second edit requests will violate a connectivity rule.
32. The machine readable medium of claim 25, wherein:
one of the edit requests is automatically generated in response to the first or second user selecting, moving, and then releasing a first object, and
another of the edit requests is automatically generated in response to the first or second user selecting a second object and then moving the second object to a graphically represented deletion area.
33. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a processor, cause the processor to perform steps comprising:
transmitting a PCB master design portion during an editing session throughout which each of first and second users may edit a PCB master design portion and view edits made to the same PCB master design portion by the other of the first and second users during the editing session, wherein:
the PCB master design portion is transmitted to the first and second users at respective first and second clients for graphical display on each of said clients, and
the graphical displays include representations of PCB artwork corresponding to the PCB master design portion;
receiving, during the editing session, a first edit request from the first client and a second edit request from the second client;
applying the first edit request to the PCB master design;
transmitting synchronization data to the first and second clients, the synchronization data permitting update of the graphical displays on the first and second clients during the editing session to reflect the application of the first edit request;
determining if the first edit request conflicts with the second edit request; and
reporting a conflict between the first and second edit requests to the second client.
34. A method for editing a printed circuit board (PCB) master design, comprising:
displaying on first and second clients a graphical representation of PCB artwork corresponding to a PCB master design portion;
editing the PCB master design portion from the first client during an editing session throughout which each of first and second users at the respective first and second clients may edit the PCB master design portion and view edits made to the PCB master design portion by the other of the first and second users during the editing session;
editing the PCB master design portion from the second client during the editing session;
updating the display of the first client, during the editing session, to reflect one or more edits made from the second client during the editing session; and
updating the display of the second client, during the editing session, to reflect one or more edits made from the first client during the editing session.
35. The method of claim 34, further comprising:
locking an object within the PCB master design portion upon selection of said object at the first client; and
preventing, based on said selection, editing of the object from the second client.
36. The method of claim 34, wherein:
at least one of the edits is automatically generated in response to selection of an object and a command,
the object is at least one of a route, a component, a trace, a via, text, and a drawing object, and
the command is at least one of move left, move right, delete and add.
37. The method of claim 34, further comprising:
receiving at one of the first and second clients a report of a conflict between third and fourth edits respectively attempted from the first and second clients.
38. The method of claim 34, wherein the PCB master design portion comprises the entire PCB master design.
US10/780,902 2001-12-10 2004-02-19 Parellel electronic design automation: shared simultaneous editing Abandoned US20040210854A1 (en)

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US34103701P true 2001-12-10 2001-12-10
US10/269,614 US6708313B2 (en) 2001-12-10 2002-10-10 Parallel electronic design automation: shared simultaneous editing
US10/780,902 US20040210854A1 (en) 2001-12-10 2004-02-19 Parellel electronic design automation: shared simultaneous editing

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US10/780,902 US20040210854A1 (en) 2001-12-10 2004-02-19 Parellel electronic design automation: shared simultaneous editing
US10/869,923 US7587695B2 (en) 2001-12-10 2004-06-18 Protection boundaries in a parallel printed circuit board design environment
US10/870,497 US7516435B2 (en) 2001-12-10 2004-06-18 Reservation of design elements in a parallel printed circuit board design environment
US11/931,660 US20080059932A1 (en) 2001-12-10 2007-10-31 Parallel Electronic Design Automation: Shared Simultaneous Editing
US12/754,850 US7949990B2 (en) 2001-12-10 2010-04-06 Parallel electronic design automation: shared simultaneous editing

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US10/870,497 Continuation-In-Part US7516435B2 (en) 2001-12-10 2004-06-18 Reservation of design elements in a parallel printed circuit board design environment
US11/931,660 Division US20080059932A1 (en) 2001-12-10 2007-10-31 Parallel Electronic Design Automation: Shared Simultaneous Editing

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050044518A1 (en) * 2001-12-10 2005-02-24 Mentor Graphics Corporation Reservation of design elements in a parallel printed circuit board design environment
US20050114865A1 (en) * 2003-11-21 2005-05-26 Mentor Graphics Corporation Integrating multiple electronic design applications
US20050114821A1 (en) * 2003-11-21 2005-05-26 Mentor Graphics Corporation Distributed autorouting of conductive paths
US20060095882A1 (en) * 2004-09-08 2006-05-04 Mentor Graphics Corporation Distributed electronic design automation environment
US20060101368A1 (en) * 2004-09-08 2006-05-11 Mentor Graphics Corporation Distributed electronic design automation environment
US20070073809A1 (en) * 2005-09-13 2007-03-29 Mentor Graphics Corporation Distributed electronic design automation architecture
US20080059932A1 (en) * 2001-12-10 2008-03-06 Mentor Graphics Corporation Parallel Electronic Design Automation: Shared Simultaneous Editing
US20080301613A1 (en) * 2007-06-01 2008-12-04 Simon Edward Holdsworth Designing wiring harnesses
US20090157209A1 (en) * 2007-12-14 2009-06-18 Simon Edward Holdsworth Wire option expressions in wiring harness designs
US20090172623A1 (en) * 2007-12-26 2009-07-02 Cadence Design Systems, Inc. Method and system for implementing efficient locking to facilitate parallel processing of ic designs
US7735044B2 (en) 2007-06-05 2010-06-08 Simon Edward Holdsworth Combination of ground devices in wiring harness designs
US7823060B2 (en) * 2002-06-07 2010-10-26 Microsoft Corporation Undo/redo architecture across multiple files
US20140222919A1 (en) * 2013-02-05 2014-08-07 Brigham Young University System and methods for multi-user cax editing conflict management

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587695B2 (en) * 2001-12-10 2009-09-08 Mentor Graphics Corporation Protection boundaries in a parallel printed circuit board design environment
US7076757B2 (en) * 2003-02-27 2006-07-11 Nec Electronics Corporation Semiconductor integrated device and apparatus for designing the same
US9710508B2 (en) * 2006-03-09 2017-07-18 Quickbase, Inc. Method and system for managing data in a workflow process
US7937663B2 (en) * 2007-06-29 2011-05-03 Microsoft Corporation Integrated collaborative user interface for a document editor program
US8516399B2 (en) * 2009-02-18 2013-08-20 Mentor Graphics Corporation Collaborative environment for physical verification of microdevice designs
US9542010B2 (en) * 2009-09-15 2017-01-10 Palo Alto Research Center Incorporated System for interacting with objects in a virtual environment
US8201094B2 (en) 2009-09-25 2012-06-12 Nokia Corporation Method and apparatus for collaborative graphical creation
EP2770449A4 (en) * 2011-10-20 2015-10-21 Zuken Inc Multi-board design device, multi-board design method, program and computer-readable recording medium
US20150199307A1 (en) * 2012-08-08 2015-07-16 Google Inc. Pluggable Architecture For Optimizing Versioned Rendering of Collaborative Documents
US9779184B2 (en) * 2013-03-15 2017-10-03 Brigham Young University Scalable multi-user CAD system and apparatus
JP6234180B2 (en) * 2013-11-13 2017-11-22 株式会社図研 Parallel editing system, concurrent editing method, program, and memory medium
US20150161306A1 (en) * 2013-12-06 2015-06-11 Synopsys, Inc. Fault insertion for system verification
JP2016139273A (en) * 2015-01-27 2016-08-04 富士通株式会社 Cooperation system, cooperation program, and cooperation method

Citations (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107443A (en) * 1988-09-07 1992-04-21 Xerox Corporation Private regions within a shared workspace
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5295081A (en) * 1992-10-30 1994-03-15 International Business Machines Corporation Concurrent interactive wire editing
US5333312A (en) * 1990-06-21 1994-07-26 International Business Machines Corp. Synchronous and asynchronous copying of a document into a folder in a target library
US5333315A (en) * 1991-06-27 1994-07-26 Digital Equipment Corporation System of device independent file directories using a tag between the directories and file descriptors that migrate with the files
US5333316A (en) * 1991-08-16 1994-07-26 International Business Machines Corporation Locking and row by row modification of a database stored in a single master table and multiple virtual tables of a plurality of concurrent users
US5339388A (en) * 1991-12-31 1994-08-16 International Business Machines Corporation Cursor lock region
US5392400A (en) * 1992-07-02 1995-02-21 International Business Machines Corporation Collaborative computing system using pseudo server process to allow input from different server processes individually and sequence number map for maintaining received data sequence
US5452218A (en) * 1994-02-03 1995-09-19 Texas Instruments System and method for determining quality analysis on fabrication and/or assembly design using shop capability data
US5544067A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5555388A (en) * 1992-08-20 1996-09-10 Borland International, Inc. Multi-user system and methods providing improved file management by reading
US5583993A (en) * 1994-01-31 1996-12-10 Apple Computer, Inc. Method and apparatus for synchronously sharing data among computer
US5604680A (en) * 1994-08-15 1997-02-18 Cadence Design Systems, Inc. Virtual interface representation of hierarchical symbolic layouts
US5745747A (en) * 1995-02-06 1998-04-28 International Business Machines Corporation Method and system of lock request management in a data processing system having multiple processes per transaction
US5806058A (en) * 1995-06-26 1998-09-08 Hitachi, Ltd. Index managing method in database managing system
US5809240A (en) * 1993-05-18 1998-09-15 Fujitsu Limited System for segmenting graphic data installed in respective terminal into areas corresponding to terminals and each area is to be manipulated by its respective terminal
US5826265A (en) * 1996-12-06 1998-10-20 International Business Machines Corporation Data management system having shared libraries
US5892900A (en) * 1996-08-30 1999-04-06 Intertrust Technologies Corp. Systems and methods for secure transaction management and electronic rights protection
US5902240A (en) * 1996-02-21 1999-05-11 Sekisui Kagaku Kogyo Kabushiki Kaisya Method and apparatus for osteoporosis diagnosis
US5950201A (en) * 1996-12-06 1999-09-07 International Business Machines Corporation Computerized design automation method using a single logical PFVL paradigm
US5966707A (en) * 1997-12-02 1999-10-12 International Business Machines Corporation Method for managing a plurality of data processes residing in heterogeneous data repositories
US5983277A (en) * 1996-10-28 1999-11-09 Altera Corporation Work group computing for electronic design automation
US6023565A (en) * 1996-03-29 2000-02-08 Xilinx, Inc. Method for configuring circuits over a data communications link
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6094654A (en) * 1996-12-06 2000-07-25 International Business Machines Corporation Data management system for file and database management
US6094658A (en) * 1992-02-27 2000-07-25 Toyota Jidosha Kabushiki Kaisha Teamwork CAD system and process for teamwork designing
US6110213A (en) * 1997-11-06 2000-08-29 Vlt Coporation Fabrication rules based automated design and manufacturing system and method
US6182115B1 (en) * 1998-03-06 2001-01-30 International Business Machines Corp. Method and system for interactive sharing of text in a networked environment
US6240414B1 (en) * 1997-09-28 2001-05-29 Eisolutions, Inc. Method of resolving data conflicts in a shared data environment
US6289254B1 (en) * 1997-01-24 2001-09-11 Canon Kabushiki Kaisha Parts selection apparatus and parts selection system with CAD function
US6327594B1 (en) * 1999-01-29 2001-12-04 International Business Machines Corporation Methods for shared data management in a pervasive computing environment
US6356796B1 (en) * 1998-12-17 2002-03-12 Antrim Design Systems, Inc. Language controlled design flow for electronic circuits
US20020059054A1 (en) * 2000-06-02 2002-05-16 Bade Stephen L. Method and system for virtual prototyping
US20020069220A1 (en) * 1996-12-17 2002-06-06 Tran Bao Q. Remote data access and management system utilizing handwriting input
US6424959B1 (en) * 1999-06-17 2002-07-23 John R. Koza Method and apparatus for automatic synthesis, placement and routing of complex structures
US6442570B1 (en) * 1997-10-27 2002-08-27 Microsoft Corporation Object identification and data communication during an object synchronization process
US20020120858A1 (en) * 1996-09-09 2002-08-29 Jack Edward Porter Method and apparatus for document management utilizing a messaging system
US20020144212A1 (en) * 2001-03-28 2002-10-03 Lev Lavi A. System, method and computer program product for web-based integrated circuit design
US6484177B1 (en) * 2000-01-13 2002-11-19 International Business Machines Corporation Data management interoperability methods for heterogeneous directory structures
US20020188910A1 (en) * 2001-06-08 2002-12-12 Cadence Design Systems, Inc. Method and system for chip design using remotely located resources
US20030009727A1 (en) * 2000-11-09 2003-01-09 Fujitsu Limited Circuit designing apparatus, circuit designing method and timing distribution apparatus
US6530065B1 (en) * 2000-03-14 2003-03-04 Transim Technology Corporation Client-server simulator, such as an electrical circuit simulator provided by a web server over the internet
US20030101425A1 (en) * 2001-11-29 2003-05-29 Makinen Bruce Allan Systems and methods for linking a graphical display and an n-dimensional data structure in a graphical user interface
US6594799B1 (en) * 2000-02-28 2003-07-15 Cadence Design Systems, Inc. Method and system for facilitating electronic circuit and chip design using remotely located resources
US6654747B1 (en) * 1997-12-02 2003-11-25 International Business Machines Corporation Modular scalable system for managing data in a heterogeneous environment with generic structure for control repository access transactions
US6671699B1 (en) * 2000-05-20 2003-12-30 Equipe Communications Corporation Shared database usage in network devices
US6678877B1 (en) * 2001-08-15 2004-01-13 National Semiconductor Corporation Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas
US6678876B2 (en) * 2001-08-24 2004-01-13 Formfactor, Inc. Process and apparatus for finding paths through a routing space
US6684379B2 (en) * 2000-10-18 2004-01-27 Chipworks Design analysis workstation for analyzing integrated circuits
US6687710B1 (en) * 1999-12-03 2004-02-03 Synchronicity Software, Inc. Intellectual property library management system
US6711718B2 (en) * 2001-12-10 2004-03-23 Charles Pfeil Parallel electronic design automation: distributed simultaneous editing
US6721922B1 (en) * 2000-09-27 2004-04-13 Cadence Design Systems, Inc. System for electronic circuit characterization, analysis, modeling and plan development
US20040093397A1 (en) * 2002-06-06 2004-05-13 Chiroglazov Anatoli G. Isolated working chamber associated with a secure inter-company collaboration environment
US6751781B2 (en) * 2002-01-18 2004-06-15 Advanced Semiconductor Engineering, Inc. Thermal data automatic service system
US6782511B1 (en) * 1999-05-26 2004-08-24 Cadence Design Systems, Inc. Behavioral-synthesis electronic design automation tool business-to-business application service provider
US20040199891A1 (en) * 2003-02-19 2004-10-07 Bentley Stanley Loren Apparatus, system, method, and program for facilitating the design of bare circuit boards
US20040225988A1 (en) * 2001-12-10 2004-11-11 Mentor Graphics Corporation Protection boundaries in a parallel printed circuit board design environment
US20040268283A1 (en) * 2003-06-24 2004-12-30 National Semiconductor Corporation Method for creating, modifying, and simulating electrical circuits over the internet
US6851100B1 (en) * 2002-03-11 2005-02-01 Samsung Electronics Co., Ltd. Management system for automated wire bonding process
US6851094B1 (en) * 2000-02-28 2005-02-01 Cadence Design Systems, Inc. Automated method and system for selecting and procuring electronic components used in circuit and chip designs
US20050044518A1 (en) * 2001-12-10 2005-02-24 Mentor Graphics Corporation Reservation of design elements in a parallel printed circuit board design environment
US20050108663A1 (en) * 2003-02-19 2005-05-19 Bentley Stanley L. Apparatus, system, method, and program for facilitating the design of electronic assemblies
US20050131783A1 (en) * 2002-03-12 2005-06-16 Myoung Jin System, method, and computer program product for network-based part management system
US6931369B1 (en) * 2001-05-01 2005-08-16 National Semiconductor Corporation Method to perform thermal simulation of an electronic circuit on a network
US6983232B2 (en) * 2000-06-01 2006-01-03 Siemens Dematic Electronic Assembly Systems Inc. Electronics assembly systems customer benefit modeling tools and methods
US20060059054A1 (en) * 2004-09-16 2006-03-16 Kaushie Adiseshan Apparel size service
US7020853B2 (en) * 2000-10-18 2006-03-28 Chipworks Design analysis workstation for analyzing integrated circuits
US7024433B2 (en) * 2001-10-25 2006-04-04 Ricoh Company, Ltd. Parts design change supporting system, program, and recording medium
US7036101B2 (en) * 2001-02-26 2006-04-25 Cadence Design Systems, Inc. Method and apparatus for scalable interconnect solution
US7039892B2 (en) * 2001-07-24 2006-05-02 Hewlett-Packard Development Company, L.P. Systems and methods for ensuring correct connectivity between circuit designs
US7076491B2 (en) * 2001-11-09 2006-07-11 Wuxi Evermore Upward and downward compatible data processing system
US7134096B2 (en) * 2002-02-22 2006-11-07 Flextronics International Usa, Inc. System and method for design, procurement and manufacturing collaboration
US7143341B1 (en) * 2002-06-20 2006-11-28 Cadence Design Systems Method and apparatus for concurrent engineering and design synchronization of multiple tools
US7143134B2 (en) * 2000-06-02 2006-11-28 Virtual Ink Corporation System and method for integrating electronic transcription systems
US7219311B2 (en) * 2002-04-17 2007-05-15 Fujitsu Limited Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device
US7240309B2 (en) * 2003-01-20 2007-07-03 Matsushita Electric Industrial Co., Ltd. Design check system, design check method and design check program
US7246055B1 (en) * 2000-08-28 2007-07-17 Cadence Design Systems, Inc. Open system for simulation engines to communicate across multiple sites using a portal methodology
US20080034342A1 (en) * 2003-11-21 2008-02-07 Mentor Graphics Corporation Distributed Autorouting of Conductive Paths
US7337093B2 (en) * 2001-09-07 2008-02-26 Purdue Research Foundation Systems and methods for collaborative shape and design
US20080059932A1 (en) * 2001-12-10 2008-03-06 Mentor Graphics Corporation Parallel Electronic Design Automation: Shared Simultaneous Editing

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8516054D0 (en) 1985-06-25 1985-07-31 Ciba Geigy Ag Photographic material
JPH0248774A (en) 1988-08-10 1990-02-19 Hitachi Comput Eng Corp Ltd Data controlling method for cad system
JPH0256070A (en) 1988-08-20 1990-02-26 Fujitsu Ltd Design data managing system
JPH02245865A (en) 1989-03-20 1990-10-01 Fujitsu Ltd Synergetic intelligent work backup system
JPH03278274A (en) 1990-03-28 1991-12-09 Nec Corp Method for determining wiring order or wiring board and wiring method
JP3002242B2 (en) 1990-07-10 2000-01-24 日立コンピュータエンジニアリング株式会社 Cad system
JPH04115369A (en) 1990-09-06 1992-04-16 Nec Corp Interactive wiring system
US5128878A (en) * 1990-11-28 1992-07-07 Micron Technology, Inc. Remote plotting of integrated circuit layout in a network computer-aided design system
JPH04362783A (en) 1991-06-10 1992-12-15 Toshiba Corp Cad system having simultaneous concurrent processing function at plural terminals
JPH0574942A (en) 1991-09-11 1993-03-26 Mitsubishi Electric Corp Cad device for designing layout pattern
JPH0573630A (en) 1991-09-13 1993-03-26 Hitachi Ltd Distributed design support method/system
US5515491A (en) * 1992-12-31 1996-05-07 International Business Machines Corporation Method and system for managing communications within a collaborative data processing system
JP3278274B2 (en) 1993-12-20 2002-04-30 キヤノン株式会社 Bookbinding apparatus
JPH07175842A (en) * 1993-12-20 1995-07-14 Melco:Kk Cad device, cad managing device, and processing method for cad data
US5751597A (en) * 1994-08-15 1998-05-12 Fujitsu Limited CAD apparatus for LSI or printed circuit board
US6134549A (en) * 1995-03-31 2000-10-17 Showcase Corporation Client/server computer system having personalizable and securable views of database data
US6035297A (en) * 1996-12-06 2000-03-07 International Business Machines Machine Data management system for concurrent engineering
US5920873A (en) * 1996-12-06 1999-07-06 International Business Machines Corporation Data management control system for file and database
US6553555B1 (en) * 1999-08-27 2003-04-22 Dell Products L.P. Maintaining signal guard bands when routing through a field of obstacles
US6418552B1 (en) * 1999-12-10 2002-07-09 Hewlett-Packard Company Method and apparatus for optimizing trace lengths to maximize the speed of a clocked bus
US6460170B1 (en) * 2000-04-29 2002-10-01 Hewlett Packard Company Connection block for interfacing a plurality of printed circuit boards
US6611848B1 (en) * 2000-09-13 2003-08-26 Radiant Data Corporation Methods for maintaining data and attribute coherency in instances of sharable files
US20020091587A1 (en) * 2001-01-11 2002-07-11 Frank Kenna Electronic communication display system
US7143094B2 (en) * 2001-07-18 2006-11-28 International Business Machines Corporation Method and apparatus for ensuring data consistency amongst a plurality of disparate systems having multiple consumer channels
US6708313B2 (en) * 2001-12-10 2004-03-16 Charles Pfeil Parallel electronic design automation: shared simultaneous editing
JP2003186914A (en) 2001-12-18 2003-07-04 Stella Corp Team format designing/editing system
US20040093997A1 (en) * 2002-11-15 2004-05-20 Huang Li Shiu Tool extension with a screw attraction structure
US6983434B1 (en) * 2003-02-13 2006-01-03 Hewlett-Packard Development Company, L.P. Differential via pair impedance adjustment tool
US20050125763A1 (en) * 2003-06-30 2005-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for the online design of a reticle field layout
JP4115369B2 (en) 2003-09-22 2008-07-09 株式会社フルヤ金属 Ni-base superalloy
US7103434B2 (en) * 2003-10-14 2006-09-05 Chernyak Alex H PLM-supportive CAD-CAM tool for interoperative electrical and mechanical design for hardware electrical systems
US7590963B2 (en) * 2003-11-21 2009-09-15 Mentor Graphics Corporation Integrating multiple electronic design applications
US7661101B2 (en) * 2004-01-15 2010-02-09 Parametric Technology Corporation Synchronous and asynchronous collaboration between heterogeneous applications
US20050237776A1 (en) * 2004-03-19 2005-10-27 Adrian Gropper System and method for patient controlled communication of DICOM protected health information
US20050246672A1 (en) * 2004-04-29 2005-11-03 Bois Karl J Differential trace pair coupling verification tool
US20060101368A1 (en) * 2004-09-08 2006-05-11 Mentor Graphics Corporation Distributed electronic design automation environment
US7546571B2 (en) * 2004-09-08 2009-06-09 Mentor Graphics Corporation Distributed electronic design automation environment

Patent Citations (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107443A (en) * 1988-09-07 1992-04-21 Xerox Corporation Private regions within a shared workspace
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5544067A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5333312A (en) * 1990-06-21 1994-07-26 International Business Machines Corp. Synchronous and asynchronous copying of a document into a folder in a target library
US5333315A (en) * 1991-06-27 1994-07-26 Digital Equipment Corporation System of device independent file directories using a tag between the directories and file descriptors that migrate with the files
US5333316A (en) * 1991-08-16 1994-07-26 International Business Machines Corporation Locking and row by row modification of a database stored in a single master table and multiple virtual tables of a plurality of concurrent users
US5339388A (en) * 1991-12-31 1994-08-16 International Business Machines Corporation Cursor lock region
US6094658A (en) * 1992-02-27 2000-07-25 Toyota Jidosha Kabushiki Kaisha Teamwork CAD system and process for teamwork designing
US5392400A (en) * 1992-07-02 1995-02-21 International Business Machines Corporation Collaborative computing system using pseudo server process to allow input from different server processes individually and sequence number map for maintaining received data sequence
US5555388A (en) * 1992-08-20 1996-09-10 Borland International, Inc. Multi-user system and methods providing improved file management by reading
US5295081A (en) * 1992-10-30 1994-03-15 International Business Machines Corporation Concurrent interactive wire editing
US5809240A (en) * 1993-05-18 1998-09-15 Fujitsu Limited System for segmenting graphic data installed in respective terminal into areas corresponding to terminals and each area is to be manipulated by its respective terminal
US5583993A (en) * 1994-01-31 1996-12-10 Apple Computer, Inc. Method and apparatus for synchronously sharing data among computer
US5452218A (en) * 1994-02-03 1995-09-19 Texas Instruments System and method for determining quality analysis on fabrication and/or assembly design using shop capability data
US5604680A (en) * 1994-08-15 1997-02-18 Cadence Design Systems, Inc. Virtual interface representation of hierarchical symbolic layouts
US5745747A (en) * 1995-02-06 1998-04-28 International Business Machines Corporation Method and system of lock request management in a data processing system having multiple processes per transaction
US5806058A (en) * 1995-06-26 1998-09-08 Hitachi, Ltd. Index managing method in database managing system
US5902240A (en) * 1996-02-21 1999-05-11 Sekisui Kagaku Kogyo Kabushiki Kaisya Method and apparatus for osteoporosis diagnosis
US6023565A (en) * 1996-03-29 2000-02-08 Xilinx, Inc. Method for configuring circuits over a data communications link
US5892900A (en) * 1996-08-30 1999-04-06 Intertrust Technologies Corp. Systems and methods for secure transaction management and electronic rights protection
US20020120858A1 (en) * 1996-09-09 2002-08-29 Jack Edward Porter Method and apparatus for document management utilizing a messaging system
US6110223A (en) * 1996-10-28 2000-08-29 Altera Corporation Graphic editor for block diagram level design of circuits
US5983277A (en) * 1996-10-28 1999-11-09 Altera Corporation Work group computing for electronic design automation
US6134705A (en) * 1996-10-28 2000-10-17 Altera Corporation Generation of sub-netlists for use in incremental compilation
US5826265A (en) * 1996-12-06 1998-10-20 International Business Machines Corporation Data management system having shared libraries
US6094654A (en) * 1996-12-06 2000-07-25 International Business Machines Corporation Data management system for file and database management
US5950201A (en) * 1996-12-06 1999-09-07 International Business Machines Corporation Computerized design automation method using a single logical PFVL paradigm
US20020069220A1 (en) * 1996-12-17 2002-06-06 Tran Bao Q. Remote data access and management system utilizing handwriting input
US6289254B1 (en) * 1997-01-24 2001-09-11 Canon Kabushiki Kaisha Parts selection apparatus and parts selection system with CAD function
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6240414B1 (en) * 1997-09-28 2001-05-29 Eisolutions, Inc. Method of resolving data conflicts in a shared data environment
US6442570B1 (en) * 1997-10-27 2002-08-27 Microsoft Corporation Object identification and data communication during an object synchronization process
US6110213A (en) * 1997-11-06 2000-08-29 Vlt Coporation Fabrication rules based automated design and manufacturing system and method
US6654747B1 (en) * 1997-12-02 2003-11-25 International Business Machines Corporation Modular scalable system for managing data in a heterogeneous environment with generic structure for control repository access transactions
US5966707A (en) * 1997-12-02 1999-10-12 International Business Machines Corporation Method for managing a plurality of data processes residing in heterogeneous data repositories
US6182115B1 (en) * 1998-03-06 2001-01-30 International Business Machines Corp. Method and system for interactive sharing of text in a networked environment
US6356796B1 (en) * 1998-12-17 2002-03-12 Antrim Design Systems, Inc. Language controlled design flow for electronic circuits
US6327594B1 (en) * 1999-01-29 2001-12-04 International Business Machines Corporation Methods for shared data management in a pervasive computing environment
US6782511B1 (en) * 1999-05-26 2004-08-24 Cadence Design Systems, Inc. Behavioral-synthesis electronic design automation tool business-to-business application service provider
US6424959B1 (en) * 1999-06-17 2002-07-23 John R. Koza Method and apparatus for automatic synthesis, placement and routing of complex structures
US6687710B1 (en) * 1999-12-03 2004-02-03 Synchronicity Software, Inc. Intellectual property library management system
US6484177B1 (en) * 2000-01-13 2002-11-19 International Business Machines Corporation Data management interoperability methods for heterogeneous directory structures
US6851094B1 (en) * 2000-02-28 2005-02-01 Cadence Design Systems, Inc. Automated method and system for selecting and procuring electronic components used in circuit and chip designs
US6594799B1 (en) * 2000-02-28 2003-07-15 Cadence Design Systems, Inc. Method and system for facilitating electronic circuit and chip design using remotely located resources
US6530065B1 (en) * 2000-03-14 2003-03-04 Transim Technology Corporation Client-server simulator, such as an electrical circuit simulator provided by a web server over the internet
US6671699B1 (en) * 2000-05-20 2003-12-30 Equipe Communications Corporation Shared database usage in network devices
US6983232B2 (en) * 2000-06-01 2006-01-03 Siemens Dematic Electronic Assembly Systems Inc. Electronics assembly systems customer benefit modeling tools and methods
US20020059054A1 (en) * 2000-06-02 2002-05-16 Bade Stephen L. Method and system for virtual prototyping
US7143134B2 (en) * 2000-06-02 2006-11-28 Virtual Ink Corporation System and method for integrating electronic transcription systems
US7246055B1 (en) * 2000-08-28 2007-07-17 Cadence Design Systems, Inc. Open system for simulation engines to communicate across multiple sites using a portal methodology
US6721922B1 (en) * 2000-09-27 2004-04-13 Cadence Design Systems, Inc. System for electronic circuit characterization, analysis, modeling and plan development
US7020853B2 (en) * 2000-10-18 2006-03-28 Chipworks Design analysis workstation for analyzing integrated circuits
US6684379B2 (en) * 2000-10-18 2004-01-27 Chipworks Design analysis workstation for analyzing integrated circuits
US6678871B2 (en) * 2000-11-09 2004-01-13 Fujitsu Limited Circuit designing apparatus, circuit designing method and timing distribution apparatus
US20030009727A1 (en) * 2000-11-09 2003-01-09 Fujitsu Limited Circuit designing apparatus, circuit designing method and timing distribution apparatus
US7036101B2 (en) * 2001-02-26 2006-04-25 Cadence Design Systems, Inc. Method and apparatus for scalable interconnect solution
US20020144212A1 (en) * 2001-03-28 2002-10-03 Lev Lavi A. System, method and computer program product for web-based integrated circuit design
US6931369B1 (en) * 2001-05-01 2005-08-16 National Semiconductor Corporation Method to perform thermal simulation of an electronic circuit on a network
US20020188910A1 (en) * 2001-06-08 2002-12-12 Cadence Design Systems, Inc. Method and system for chip design using remotely located resources
US6578174B2 (en) * 2001-06-08 2003-06-10 Cadence Design Systems, Inc. Method and system for chip design using remotely located resources
US7039892B2 (en) * 2001-07-24 2006-05-02 Hewlett-Packard Development Company, L.P. Systems and methods for ensuring correct connectivity between circuit designs
US6678877B1 (en) * 2001-08-15 2004-01-13 National Semiconductor Corporation Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas
US6678876B2 (en) * 2001-08-24 2004-01-13 Formfactor, Inc. Process and apparatus for finding paths through a routing space
US7337093B2 (en) * 2001-09-07 2008-02-26 Purdue Research Foundation Systems and methods for collaborative shape and design
US7024433B2 (en) * 2001-10-25 2006-04-04 Ricoh Company, Ltd. Parts design change supporting system, program, and recording medium
US7076491B2 (en) * 2001-11-09 2006-07-11 Wuxi Evermore Upward and downward compatible data processing system
US20030101425A1 (en) * 2001-11-29 2003-05-29 Makinen Bruce Allan Systems and methods for linking a graphical display and an n-dimensional data structure in a graphical user interface
US20050044518A1 (en) * 2001-12-10 2005-02-24 Mentor Graphics Corporation Reservation of design elements in a parallel printed circuit board design environment
US6711718B2 (en) * 2001-12-10 2004-03-23 Charles Pfeil Parallel electronic design automation: distributed simultaneous editing
US20040225988A1 (en) * 2001-12-10 2004-11-11 Mentor Graphics Corporation Protection boundaries in a parallel printed circuit board design environment
US20080059932A1 (en) * 2001-12-10 2008-03-06 Mentor Graphics Corporation Parallel Electronic Design Automation: Shared Simultaneous Editing
US6751781B2 (en) * 2002-01-18 2004-06-15 Advanced Semiconductor Engineering, Inc. Thermal data automatic service system
US7134096B2 (en) * 2002-02-22 2006-11-07 Flextronics International Usa, Inc. System and method for design, procurement and manufacturing collaboration
US6851100B1 (en) * 2002-03-11 2005-02-01 Samsung Electronics Co., Ltd. Management system for automated wire bonding process
US20050131783A1 (en) * 2002-03-12 2005-06-16 Myoung Jin System, method, and computer program product for network-based part management system
US7219311B2 (en) * 2002-04-17 2007-05-15 Fujitsu Limited Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device
US20040093397A1 (en) * 2002-06-06 2004-05-13 Chiroglazov Anatoli G. Isolated working chamber associated with a secure inter-company collaboration environment
US7143341B1 (en) * 2002-06-20 2006-11-28 Cadence Design Systems Method and apparatus for concurrent engineering and design synchronization of multiple tools
US7240309B2 (en) * 2003-01-20 2007-07-03 Matsushita Electric Industrial Co., Ltd. Design check system, design check method and design check program
US20050108663A1 (en) * 2003-02-19 2005-05-19 Bentley Stanley L. Apparatus, system, method, and program for facilitating the design of electronic assemblies
US20040199891A1 (en) * 2003-02-19 2004-10-07 Bentley Stanley Loren Apparatus, system, method, and program for facilitating the design of bare circuit boards
US20040268283A1 (en) * 2003-06-24 2004-12-30 National Semiconductor Corporation Method for creating, modifying, and simulating electrical circuits over the internet
US20080034342A1 (en) * 2003-11-21 2008-02-07 Mentor Graphics Corporation Distributed Autorouting of Conductive Paths
US20060059054A1 (en) * 2004-09-16 2006-03-16 Kaushie Adiseshan Apparel size service

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080059932A1 (en) * 2001-12-10 2008-03-06 Mentor Graphics Corporation Parallel Electronic Design Automation: Shared Simultaneous Editing
US20100199240A1 (en) * 2001-12-10 2010-08-05 Mentor Graphics Corporation Parallel Electronic Design Automation: Shared Simultaneous Editing
US20050044518A1 (en) * 2001-12-10 2005-02-24 Mentor Graphics Corporation Reservation of design elements in a parallel printed circuit board design environment
US7949990B2 (en) 2001-12-10 2011-05-24 Mentor Graphics Corporation Parallel electronic design automation: shared simultaneous editing
US7516435B2 (en) 2001-12-10 2009-04-07 Mentor Graphics Corporation Reservation of design elements in a parallel printed circuit board design environment
US7823060B2 (en) * 2002-06-07 2010-10-26 Microsoft Corporation Undo/redo architecture across multiple files
US20110035727A1 (en) * 2002-06-07 2011-02-10 Microsoft Corporation Undo/redo architecture across multiple files
US7590963B2 (en) 2003-11-21 2009-09-15 Mentor Graphics Corporation Integrating multiple electronic design applications
US20050114865A1 (en) * 2003-11-21 2005-05-26 Mentor Graphics Corporation Integrating multiple electronic design applications
US7788622B2 (en) 2003-11-21 2010-08-31 Mentor Graphics Corporation Distributed autorouting of conductive paths
US20050114821A1 (en) * 2003-11-21 2005-05-26 Mentor Graphics Corporation Distributed autorouting of conductive paths
US7305648B2 (en) 2003-11-21 2007-12-04 Mentor Graphics Corporation Distributed autorouting of conductive paths in printed circuit boards
US7546571B2 (en) 2004-09-08 2009-06-09 Mentor Graphics Corporation Distributed electronic design automation environment
US20060095882A1 (en) * 2004-09-08 2006-05-04 Mentor Graphics Corporation Distributed electronic design automation environment
US20060101368A1 (en) * 2004-09-08 2006-05-11 Mentor Graphics Corporation Distributed electronic design automation environment
US8326926B2 (en) * 2005-09-13 2012-12-04 Mentor Graphics Corporation Distributed electronic design automation architecture
US20070073809A1 (en) * 2005-09-13 2007-03-29 Mentor Graphics Corporation Distributed electronic design automation architecture
US20080301613A1 (en) * 2007-06-01 2008-12-04 Simon Edward Holdsworth Designing wiring harnesses
US8694952B2 (en) 2007-06-01 2014-04-08 Mentor Graphics Corporation Designing wiring harnesses
US20100223589A1 (en) * 2007-06-05 2010-09-02 Simon Edward Holdsworth Combination of ground devices in wiring harness designs
US7735044B2 (en) 2007-06-05 2010-06-08 Simon Edward Holdsworth Combination of ground devices in wiring harness designs
US8271927B2 (en) 2007-06-05 2012-09-18 Mentor Graphics Corporation Combination of ground devices in wiring harness designs
US20090157209A1 (en) * 2007-12-14 2009-06-18 Simon Edward Holdsworth Wire option expressions in wiring harness designs
US8010917B2 (en) 2007-12-26 2011-08-30 Cadence Design Systems, Inc. Method and system for implementing efficient locking to facilitate parallel processing of IC designs
US20090172623A1 (en) * 2007-12-26 2009-07-02 Cadence Design Systems, Inc. Method and system for implementing efficient locking to facilitate parallel processing of ic designs
US8438512B2 (en) 2007-12-26 2013-05-07 Cadence Design Systems, Inc. Method and system for implementing efficient locking to facilitate parallel processing of IC designs
US20140222919A1 (en) * 2013-02-05 2014-08-07 Brigham Young University System and methods for multi-user cax editing conflict management
US9648059B2 (en) * 2013-02-05 2017-05-09 Brigham Young University System and methods for multi-user CAx editing conflict management

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