US20040163947A1 - Substrate plating apparatus - Google Patents

Substrate plating apparatus Download PDF

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US20040163947A1
US20040163947A1 US10786110 US78611004A US2004163947A1 US 20040163947 A1 US20040163947 A1 US 20040163947A1 US 10786110 US10786110 US 10786110 US 78611004 A US78611004 A US 78611004A US 2004163947 A1 US2004163947 A1 US 2004163947A1
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plating
substrate
unit
cleaning
area
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Akihisa Hongo
Naoaki Ogure
Hiroaki Inoue
Norio Kimura
Fumio Kuriyama
Manabu Tsujimura
Kenichi Suzuki
Atsushi Chono
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Akihisa Hongo
Naoaki Ogure
Hiroaki Inoue
Norio Kimura
Fumio Kuriyama
Manabu Tsujimura
Kenichi Suzuki
Atsushi Chono
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for plating wafers, e.g. semiconductors, solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67028Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67051Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/6723Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one plating chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67126Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S134/00Cleaning and liquid contact with solids
    • Y10S134/902Semiconductor wafer

Abstract

A substrate plating apparatus forms an interconnection layer on an interconnection region composed of a fine groove and/or a fine hole defined in a substrate. The substrate plating apparatus includes a plating unit for forming a plated layer on a surface of the substrate including the interconnection region, a chemical mechanical polishing unit for chemically mechanically polishing the substrate to remove the plated layer from the surface of the substrate leaving a portion of the plated layer in the interconnection region, a cleaning unit for cleaning the substrate after the plated layer is formed or the substrate is chemically mechanically polished, a drying unit for drying the substrate after the substrate is cleaned, and a substrate transfer unit for transferring the substrate to and from each of the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, and the drying unit. The first plating unit, the first chemical mechanical polishing unit, the cleaning unit, the drying unit, and the substrate transfer unit are combined into a unitary arrangement.

Description

  • This application is a divisional of U.S. patent application Ser. No. 09/945,711, filed Sep. 5, 2001, which is a divisional of U.S. patent application Ser. No. 09/154,895, filed Sep. 17, 1998, and now U.S. Pat. No. 6,294,059.[0001]
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to a substrate plating apparatus for plating a substrate, and more particularly to a substrate plating apparatus for forming a metal interconnection layer in an interconnection region composed of a fine groove and/or a fine hole defined in a substrate such as a semiconductor wafer or the like. [0003]
  • 2. Description of the Related Art [0004]
  • For forming an interconnection circuit on a semiconductor substrate, it has been customary to deposit a conductive film on a surface of the semiconductor substrate by sputtering or the like, and remove unwanted areas of the conductive film by chemical dry etching using a pattern mask such as a resist or the like. [0005]
  • The material of the interconnection circuit has generally been aluminum (Al) or aluminum alloy. Highly integrated semiconductor circuits have thinner interconnections, which result in increased current densities that are responsible for increased thermal stresses and temperature rises. As aluminum films become thinner due to stress migration or electromigration, these problems manifest themselves to the point where interconnections tend to be broken down or short-circuited. [0006]
  • Thus, there is a greater demand for using conductive materials such as copper (Cu) for forming these interconnections, in order to realize lower conductivity and to avoid electromigrations due to currents flowing therethrough. However, since it is difficult to remove copper or its alloy by dry etching, the conventional process of depositing a copper film and then patterning the copper film by dry etching cannot be relied upon for producing interconnections on substrates. One solution is to form a desired pattern of interconnection grooves in a substrate surface, and then fill the interconnection grooves with copper or its alloy. This process does not require any etching process to remove unwanted copper or its alloy. Instead, surface irregularities or steps are removed from the substrate surface by a polishing process. The process is also advantageous in that interconnection holes for interconnecting vertical circuit layers can also be formed simultaneously. [0007]
  • However, as the width of interconnections becomes thinner, those interconnection grooves or holes have a higher aspect ratio, i.e., a higher ratio of their depth to their diameter or width, and cannot uniformly be filled with copper or its alloy by performing a sputtering operation. [0008]
  • Chemical vapor deposition (CVD) is widely used for forming films of various materials. Nevertheless, the application of CVD for the formation of films of copper or its alloy is not promising because it is difficult to prepare a suitable gaseous material as a source of copper or its alloy. If an organic material is used, carbon (C) tends to be introduced from the organic material into a deposited film, resulting in greater electrical resistivity. [0009]
  • There has been proposed a plating process for depositing a copper film on a substrate. According to the proposed plating process, a substrate is immersed in a plating solution to plate the substrate with copper, i.e. an electroless plating or electroplating procedure, and then unwanted areas of the plated copper layer is removed by chemical mechanical polishing (CMP). The plating process makes it possible to fill interconnection grooves of high aspect ratios uniformly with a highly conductive copper metal. When the plating process is continuously carried out within a clean atmosphere in a semiconductor fabrication facility, however, chemicals or solutions used in a pretreatment process and the plating process are spread as a chemical mist or gas, which tends to be attached to clean substrates that have been processed in the semiconductor fabrication facility. This problem arises even if the pretreatment process and the plating process are performed in a sealed processing chamber. Specifically, since the sealed processing chamber has to be opened for loading and unloading substrates, the chemical mist or gas generated in the plating bath or pretreatment bath or chamber cannot be prevented from spreading into the semiconductor fabrication facility. [0010]
  • It has been desired to develop a single apparatus or chamber for forming a plated copper layer on a surface of a semiconductor wafer including interconnection regions, which are composed of fine grooves and fine holes, by performing an electroless plating or electroplating operation, and then removing unwanted copper layer portions by performing a chemical mechanical polishing operation, thereby leaving the plated copper layer only in the interconnection regions. However, such a single apparatus or chamber has not been put to practical use. [0011]
  • If a substrate plating apparatus and a chemical mechanical polishing apparatus are separate from each other, then a semiconductor wafer plated with a copper layer has to be dried and unloaded from the substrate plating apparatus, and then a dried semiconductor wafer is loaded into the chemical mechanical polishing apparatus for removing unwanted copper portions. Therefore, two separate drying apparatuses or chambers are necessary. In some applications, a protective plated layer is deposited on a plated copper interconnection layer for protecting its surface. However, since the substrate plating apparatus is separate from the chemical mechanical polishing apparatus, the surface of the protective plated layer tends to be oxidized during the wafer transfer from the substrate plating apparatus to the chemical mechanical polishing apparatus. [0012]
  • The substrate plating apparatus generally comprises a loading and unloading area for transferring cassettes, which store substrates, a plating area for plating substrates, and a cleaning and drying area for cleaning and drying plated substrates. If the substrate plating apparatus, i.e., a wet processing bath which is accommodated in a chamber, is placed in a clean room for semiconductor fabrication facilities, then it is necessary to prevent particles, mists and gasses generated from a plating solution or a cleaning solution from being applied to semiconductor wafers which have already been processed and dried. Stated otherwise, when processed semiconductor wafers are unloaded from the substrate plating apparatus and transferred to a next processing stage, the particles, mists and gasses from the plating solution or the cleaning solution should not be spread into the clean room, where other manufacturing processes are carried out. [0013]
  • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a substrate plating apparatus which is free of the various conventional problems even when placed in a clean room accommodating semiconductor fabrication facilities. A second object of the present invention is to provide a substrate plating apparatus which is capable of performing, with a unitary arrangement, various processing operations including forming a plated layer on a surface of a substrate including interconnection regions composed of fine interconnection grooves and fine interconnection holes, and removing unwanted layer portions from the substrate, thereby leaving the plated layer in the interconnection regions as an interconnection layer on the substrate. [0014]
  • Another object of the present invention is to provide a substrate plating apparatus which is effective to prevent particles, mists and gasses of a plating solution and a cleaning solution from spreading into a clean room as plated semiconductor wafers are transferred in the clean room from the plating apparatus to further processing equipment. These particles, mists and gasses are also prevented from spreading. [0015]
  • According to the present invention, there is provided a substrate plating apparatus for forming an interconnection layer on an interconnection region composed of a fine groove and/or a fine hole defined in a substrate, comprising: a first plating unit for forming a layer on a surface of the substrate including the interconnection region; a first chemical mechanical polishing unit for chemically mechanically polishing the substrate to remove unwanted portions of the layer from the surface of the substrate; a cleaning unit for cleaning the substrate after the layer has been formed or after the substrate has been chemically mechanically polished; a drying unit for drying the substrate after the substrate has been cleaned; and a substrate transfer device for transferring the substrate to and from each of the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, and the drying unit, wherein the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, the drying unit, and the substrate transfer devices are combined into a unitary arrangement. [0016]
  • The substrate plating apparatus may further comprise a second plating unit for forming a protective layer over the first layer in the interconnection region after the unwanted portions have been removed by chemical mechanical polishing from the surface of the substrate, wherein the second plating unit is part of the unitary arrangement. [0017]
  • The substrate plating apparatus may further comprise a second chemical mechanical polishing unit for chemically mechanically polishing the substrate to remove unwanted portions of the protective layer formed over the first layer in the interconnection region, wherein the second chemical mechanical polishing unit is part of the unitary arrangement. [0018]
  • The substrate plating apparatus may further comprise a discharging facility for discharging a cleaning solution used by the cleaning unit to clean the substrate, wherein the discharging facility is part of the unitary arrangement. [0019]
  • The substrate transfer device may comprise a robot having an arm, with the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, and the drying unit being accessible to the arm. [0020]
  • The substrate plating apparatus may further comprise concentration analyzing devices for analyzing the concentrations of components of a plating solution used by the first plating unit to form the first layer, and plating solution preparing devices for preparing a plating solution based on the analyzed concentrations, wherein the concentration analyzing devices and the plating solution preparing devices are part of the unitary arrangement. [0021]
  • Since at least the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, the drying unit, and the substrate transfer device are combined into a unitary arrangement, the substrate plating apparatus offers the following advantages: [0022]
  • 1. The steps of forming a first layer on a surface of a semiconductor substrate which includes an interconnection region composed of a fine groove and a fine hole, and removing unwanted portions of the first layer from the surface of the semiconductor substrate, can be carried out without multiple drying steps by the substrate plating apparatus. [0023]
  • If the first plating unit and the chemical mechanical polishing unit were independent of each other, a plurality of different drying units would be required to dry substrates in association with these units. The substrate plating apparatus of the unitary arrangement does not need such different drying units. [0024]
  • 2. Down time can be shortened. For example, a substrate can be chemically mechanically polished immediately after plating by a plating solution bath. Consequently, a first layer is prevented from being naturally oxidized, and particles are prevented from being excessively applied to the first layer between such plating and polishing steps. [0025]
  • There is also provided a substrate plating apparatus for plating a substrate comprising: a loading and unloading area for transferring a cassette which stores a substrate; a plating area for plating a substrate; and a cleaning and drying area for cleaning and drying a plated substrate; wherein, the cleaning and drying area is disposed between the loading and unloading area and the plating area, a first partition is disposed between the loading and unloading area and the cleaning and drying area and has a passage defined therein for transferring a substrate between the loading and unloading area and the cleaning and drying area, and a second partition is disposed between the cleaning and drying area and the plating area and has a passage defined therein for transferring a substrate between the cleaning and drying area and the plating area. [0026]
  • The substrate plating apparatus may further comprise a first shutter movably mounted for opening and closing the passage defined in the first partition, and a second shutter movably mounted for opening and closing the passage defined in the second partition. [0027]
  • As described above, the cleaning and drying area is disposed between the loading and unloading area and the plating area. The first partition is disposed between the loading and unloading area and the cleaning and drying area, and the second partition is disposed between the cleaning and drying area and the plating area. Therefore, a substrate loaded in a dry state is plated and cleaned in the substrate plating apparatus and the substrate cleaning apparatus, and unloaded in a dry state from the substrate plating apparatus. Consequently, even if the substrate plating apparatus is installed in a clean room, the clean room is prevented from being contaminated with particles and mists from the plating apparatus and the cleaning apparatus. [0028]
  • When the substrate plating apparatus is installed in a clean room, pressures in the loading and unloading area, the plating area, and the cleaning and drying area are selected such that the pressure in the loading and unloading area is higher than the pressure in the cleaning and drying area, which in turn is higher than the pressure in the plating area, and wherein the pressure in the loading and unloading area is lower than a pressure in the clean room. [0029]
  • Because the pressure in the loading and unloading area is higher than the pressure in the cleaning and drying area, which in turn is higher than the pressure in the plating area, and because the pressure in the loading and unloading area is lower than the pressure in the clean room, air flows in the substrate plating apparatus are prevented from leaking into the clean room, and hence from contaminating the clean room. [0030]
  • The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.[0031]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a first embodiment of the present invention; [0032]
  • FIGS. 2A and 2B are fragmentary cross-sectional views illustrative of an interconnection plating process carried out by the substrate plating apparatus shown in FIG. 1; [0033]
  • FIG. 3 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a second embodiment of the present invention; [0034]
  • FIGS. 4A through 4D are fragmentary cross-sectional views illustrative of an interconnection plating process carried out by the substrate plating apparatus shown in FIG. 3; [0035]
  • FIG. 5 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a third embodiment of the present invention; [0036]
  • FIG. 6 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a fourth embodiment of the present invention; [0037]
  • FIG. 7 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a fifth embodiment of the present invention; [0038]
  • FIG. 8 is a schematic view showing airflow in the substrate plating apparatus shown in FIG. 7; [0039]
  • FIG. 9 is a cross-sectional view showing airflows among areas in the substrate plating apparatus shown in FIG. 7; [0040]
  • FIG. 10 is a perspective view of the substrate plating apparatus shown in FIG. 7, which is placed in a clean room; [0041]
  • FIG. 11 is a plan view of a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a sixth embodiment of the present invention; [0042]
  • FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11; [0043]
  • FIG. 13 is a plan view of a loading stage and a roughly cleaning chamber of the substrate plating apparatus shown in FIG. 11; [0044]
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 13; and [0045]
  • FIG. 15 is a cross-sectional view taken along line XV-XV of FIG. 13.[0046]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • As shown in FIG. 1, a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a first embodiment of the present invention generally comprises a loading unit [0047] 1 for loading a semiconductor wafer, a copper plating chamber 2 for plating a semiconductor wafer with copper, a pair of water cleaning chambers 3, 4 for cleaning a semiconductor wafer with water, a chemical mechanical polishing unit 5 for chemically and mechanically polishing a semiconductor wafer, a pair of water cleaning chambers 6, 7 for cleaning a semiconductor wafer with water, a drying chamber 8 for drying a semiconductor wafer, and an unloading unit 9 for unloading a semiconductor wafer with an interconnection layer thereon. The substrate plating apparatus also has a wafer transfer mechanism (not shown) for transferring semiconductor wafers to the chambers 2, 3, 4, the chemical mechanical polishing unit 5, the chambers 6, 7, 8, and the unloading unit 9. The loading unit 1, the chambers 2, 3, 4, the chemical mechanical polishing unit 5, the chambers 6, 7, 8, and the unloading unit 9 are combined into a unitary arrangement.
  • The substrate plating apparatus operates as follows: The wafer transfer mechanism transfers a semiconductor wafer W, on which an interconnection layer has not yet been formed, from a wafer cassette [0048] 1-1 placed in the loading unit 1 to the copper plating chamber 2. In the copper plating chamber 2, as shown in FIG. 2A, a copper layer 103 is formed on a surface of the semiconductor wafer W having an interconnection region composed of an interconnection groove 101 and an interconnection hole (contact hole) 102.
  • After the copper layer [0049] 103 is formed on the semiconductor wafer W in the copper plating chamber 2, the semiconductor wafer W is transferred to the water cleaning chambers 3, 4 by the wafer transfer mechanism, and cleaned by water in the water cleaning chambers 3, 4. The cleaned semiconductor wafer W is transferred to the chemical mechanical polishing unit 5 by the wafer transfer mechanism. As shown in FIG. 2B, the chemical mechanical polishing unit 5 removes unwanted portions of the copper layer 103 from the surface of the semiconductor wafer W, thereby leaving a portion of the plated copper layer 103 in the interconnection groove 101 and the interconnection hole 102. In FIGS. 2A and 2B, a barrier layer 104 made of tin or the like is formed on the surface of the semiconductor wafer W, including the inner surfaces of the interconnection groove 101 and the interconnection hole 102, before the copper layer 103 is deposited.
  • Then, the semiconductor wafer W with the remaining copper layer [0050] 103 is transferred to the water cleaning chambers 6, 7 by the wafer transfer mechanism, and cleaned by water in the water cleaning chambers 6, 7. The cleaned semiconductor wafer W is then dried in the drying chamber 8, after which the dried semiconductor wafer W with the remaining copper layer 103, serving as an interconnection layer, is placed into a wafer, cassette 9-1 in the unloading unit 9.
  • FIG. 3 shows in plan a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a second embodiment of the present invention. The substrate plating apparatus shown in FIG. 3 differs from the substrate plating apparatus shown in FIG. 1 in that it additionally includes a copper plating chamber [0051] 2′, a water cleaning chamber 10, a pretreatment chamber 11, and a protective layer plating chamber 12 for forming a protective layer on a copper layer on a semiconductor wafer. The loading unit 1, the chambers 2, 2′, 3, 4, the chemical mechanical polishing unit 5, the chambers 6, 7, 8, 10, 11, 12, and the unloading unit 9 are combined into a unitary arrangement. Those parts shown in FIGS. 3 and 4A through 4D which are identical to those shown in FIGS. 1 and 2A, 2B are denoted by identical reference numerals, and will not be described in detail below.
  • The substrate plating apparatus shown in FIG. 3 operates as follows: A semiconductor wafer W is supplied from the wafer cassette [0052] 1-1, placed in the loading unit 1, successively to the copper plating chambers 2, 2′. In the copper plating chamber 2, 2′, as shown in FIG. 4A, a copper layer 103 is formed on a surface of a semiconductor wafer W having an interconnection region composed of an interconnection groove 101 and an interconnection hole (contact hole) 102. The two copper plating chambers 2-, 2′ are employed to allow the semiconductor wafer W to be plated with a copper layer for a long period of time. Specifically, the semiconductor wafer W may be plated with a primary copper layer by electroplating in the copper plating chamber 2, and then plated with a secondary copper layer by electroless plating in the copper plating chamber 2′. The substrate plating apparatus may have more than two copper plating chambers.
  • The semiconductor wafer W with the copper layer [0053] 103 formed thereon is cleaned by water in the water cleaning chambers 3, 4. Then, as shown in FIG. 4B, the chemical mechanical polishing unit 5 removes unwanted portions of the copper layer 103 from the surface of the semiconductor wafer W, thereby leaving a portion of the copper layer 103 in the interconnection groove 101 and the interconnection hole 102.
  • Thereafter, the semiconductor wafer W with the remaining copper layer [0054] 103 is transferred to the water cleaning chamber 10, in which the semiconductor wafer W is cleaned with water. Then, the semiconductor wafer W is transferred to the pretreatment chamber 11, and pretreated therein for the deposition of a protective layer. The pretreated semiconductor wafer W is transferred to the protective layer-plating chamber 12. In the protective layer plating chamber 12, as shown in FIG. 4C, a protective layer 105 is formed on the copper layer 103 in the interconnection region on the semiconductor wafer W. For example, the protective layer 105 is formed with an alloy of nickel (Ni) and boron (B) by electroless plating. After the protective layer 105 is deposited, the semiconductor wafer W is cleaned by water in the water cleaning chambers 6, 7, dried in the drying chamber 8, and then transferred to the wafer cassette 9-1 in the unloading unit 9.
  • FIG. 5 shows in plan a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a third embodiment of the present invention. The substrate plating apparatus shown in FIG. 5 differs from the substrate plating apparatus shown in FIG. 3 in that it additionally includes a chemical mechanical polishing unit [0055] 15, and water cleaning chambers 13, 14. The loading unit 1, the chambers 2, 2′, 3, 4, 14, the chemical mechanical polishing unit 5, 15, the chambers 6, 7, 8, 10, 11, 12, 13, and the unloading unit 9 are combined into a unitary arrangement. Those parts shown in FIG. 5 which are identical to those shown in FIG. 3 are denoted by identical reference numerals, and will not be described in detail below.
  • In the chemical mechanical polishing unit [0056] 15, an upper portion of the protective layer 105 deposited on the copper layer 103 is polished off to planarize the protective layer 105, as shown in FIG. 4D. The water cleaning chambers 13, 14 additionally clean the semiconductor wafer W with water.
  • FIG. 6 shows in plan a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a fourth embodiment of the present invention. As shown in FIG. 6, the substrate plating apparatus includes a robot [0057] 16 at its center which has a robot arm 16-1, and also has a copper plating chamber 2, a pair of water cleaning chambers 3, 4 a chemical mechanical polishing unit 5, a pretreatment chamber 11, a protective layer plating chamber 12, a drying chamber 8, and a loading and unloading station 17, which are disposed around the robot 16 and positioned within the reach of the robot arm 16-1. A loading unit 1 for loading semiconductor wafers and an unloading unit 9 for unloading semiconductor wafers is disposed adjacent to the loading and unloading station 17. The robot 16, the chambers 2, 3, 4, the chemical mechanical polishing unit 5, the chambers 8, 11, 12, the loading and unloading station 17, the loading unit 1, and the unloading unit 9 are combined into a unitary arrangement.
  • The substrate plating apparatus shown in FIG. 6 operates as follows: [0058]
  • A semiconductor wafer to be plated is transferred from the loading unit [0059] 1 to the loading and unloading station 17, from which the semiconductor wafer is received by the robot arm 16-1 and transferred thereby to the copper plating chamber 2. In the copper plating chamber 2, as shown in FIG. 4A, a copper layer 103 is formed on a surface of the semiconductor wafer which has an interconnection region composed of an interconnection groove 101 and an interconnection hole 102. The semiconductor wafer with the copper layer 103 formed thereon is transferred by the robot arm 16-1 to the chemical mechanical polishing unit 5. In the chemical mechanical polishing unit 5, as shown in FIG. 4B, unwanted portions of the copper layer 103 are removed from the surface of the semiconductor wafer W, thereby leaving a portion of the copper layer 103 in the interconnection groove 101 and the interconnection hole 102.
  • The semiconductor wafer is then transferred by the robot arm [0060] 16-1 to the water-cleaning chamber 4, in which the semiconductor wafer is cleaned by water. Thereafter, the semiconductor wafer is transferred by the robot arm 16-1 to the pretreatment chamber 11, in which the semiconductor wafer is pretreated therein for the deposition of a protective layer. The pretreated semiconductor wafer is transferred by the robot arm 16-1 to the protective layer plating chamber 12. In the protective layer plating chamber 12, a protective layer 105 is formed on the copper layer 103 in the interconnection region on the semiconductor wafer W, as shown in FIG. 4C. The semiconductor wafer with the protective layer 105 formed thereon is transferred by the robot arm 16-1 to the water cleaning chamber 4, in which the semiconductor wafer is cleaned by water. The cleaned semiconductor wafer is transferred by the robot arm 16-1 to the drying chamber 8, in which the semiconductor wafer is dried. The dried semiconductor wafer is transferred by the robot arm 16-1 to the loading and unloading station 17, from which the plated semiconductor wafer is transferred to the unloading unit 9.
  • If the copper plating chambers [0061] 2, 2′ of the substrate plating apparatus shown in FIGS. 1, 3, 5, 6 are copper electroplating chambers, then the substrate plating apparatus may have a copper ion concentration analyzer, an oxygen concentration analyzer, a plating additive concentration analyzer, and a plating solution preparing unit for preparing a plating solution based on analyzed results from the analyzers. These analyzers and the plating solution preparing unit may be integrally combined with the other components of the substrate plating apparatus into a unitary arrangement. The substrate plating apparatus may have only some of the above analyzers, rather than all of them.
  • If the copper plating chambers [0062] 2, 2′ are copper electroless plating chambers, then the substrate plating apparatus may have a copper ion concentration analyzer, an oxidizing agent concentration analyzer, a reducing agent concentration analyzer, and a pH measuring unit, along with a plating solution preparing unit for preparing a plating solution based on analyzed results from the analyzers and a pH measured by the pH measuring unit. These analyzers, the pH-measuring unit, and the plating solution preparing unit may be integrally combined with the other components of the substrate plating apparatus into a unitary arrangement. The substrate plating apparatus may have only some of the above analyzers and the pH measuring unit, rather than all of them.
  • If the protective layer plating chamber [0063] 12 is an Ni—B electroless plating chamber, then the substrate plating apparatus may have a nickel ion concentration analyzer, an oxidizing agent concentration analyzer, a reducing agent concentration analyzer, and a pH measuring unit, along with a plating solution preparing unit for preparing a plating solution based on analyzed results from the analyzers and a pH measured by the pH measuring unit. These analyzers, the pH-measuring unit, and the plating solution preparing unit may be integrally combined with the other components of the substrate plating apparatus into a unitary arrangement. The substrate plating apparatus may have only some of the above analyzers and the pH measuring unit, rather than all of them.
  • The substrate plating apparatus may have an ion-exchange tower for ion recovery, an activated carbon extraction tower for organic material recovery, a scrubber for processing exhaust gasses, and a solidifier for solidifying and discarding discharged liquids. The towers, the scrubber, and the solidifier may be integrally combined with the other components of the substrate plating apparatus into a unitary arrangement. [0064]
  • The numbers of the plating chambers, water cleaning chambers, and the pretreatment chambers in the substrate plating apparatus shown in FIGS. 1, 3, [0065] 5, 6 are illustrative only, and these chambers are not limited to the illustrated numbers.
  • The chemical mechanical polishing unit may be associated with a slurry supply unit, a discharged liquid processing unit, and a constant-temperature chamber, which may be integrally combined with the chemical mechanical polishing unit into a unitary arrangement. [0066]
  • If any one of the illustrated substrate plating apparatus is installed in a clean room, then it is necessary that processed and dried semiconductor wafers be unloaded and transferred to a next process without exposure to mists, particles of the plating solution or the cleaning solution contained in the apparatus. Therefore, particles and mists in a plating area and a cleaning and drying area of the substrate plating apparatus should not be applied to processed and dried semiconductor wafers that are stored in a cassette placed in an unloading area of the substrate plating apparatus. [0067]
  • FIG. 7 shows in plan a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a fifth embodiment of the present invention. The substrate plating apparatus shown in FIG. 7 generally comprises a loading and unloading area [0068] 20 for transferring wafer cassettes which store semiconductor wafers, a plating area 30 for plating semiconductor wafers, and a cleaning and drying area 40 for cleaning and drying plated semiconductor wafers. The cleaning and drying area 40 is positioned between the loading and unloading area 20 and the plating area 30. A partition 21 is disposed between the loading and unloading area 20 and the cleaning and drying area 40, and a partition 23 is disposed between the cleaning and drying area 40 and the plating area 30.
  • The partition [0069] 21 has a passage (not shown) defined therein for transferring semiconductor wafers therethrough between the loading and unloading area 20 and the cleaning and drying area 40, and supports a shutter 22 for opening and closing the passage. The partition 23 has a passage (not shown) defined therein for transferring semiconductor wafers therethrough between the cleaning and drying area 40 and the plating area 30, and supports a shutter 24 for opening and closing the passage. The cleaning and drying area 40 and the plating area 30 can independently be supplied with discharge air.
  • The substrate plating apparatus shown in FIG. 7 is placed in a clean room, which accommodates semiconductor fabrication facilities. The pressures in the loading and unloading area [0070] 20, the plating area 30, and the cleaning and drying area 40 are selected as follows:
  • The pressure in the loading and unloading area [0071] 20 is greater than the pressure in the cleaning and drying area 40 which in turn is greater than the pressure in the plating area 30.
  • The pressure in the loading and unloading area [0072] 20 is lower than the pressure in the clean room. Therefore, air does not flow from the plating area 30 into the cleaning and drying area 40, and air does not flow from the cleaning and drying area 40 into the loading and unloading area 20. Furthermore, air does not flow from the loading and unloading area 20 into the clean room.
  • The loading and unloading area [0073] 20 houses a loading unit 20 a and an unloading unit 20 b, each accommodating a wafer cassette for storing semiconductor wafers. The cleaning and drying area 40 houses two water cleaning units 41 for cleaning plated semiconductor wafers with water, and two drying units 42 for drying plated semiconductor wafers. Each of the water cleaning units 41 may comprise a pencil-shaped cleaner with a sponge layer mounted on a front end thereof, or a roller with a sponge layer mounted on an outer circumferential surface thereof. Each of the drying units 42 may comprise a drier for spinning a semiconductor wafer at a high speed to dehydrate and dry it. The cleaning and drying area 40 also has a transfer unit (transfer robot) 43 for transferring semiconductor wafers.
  • The plating area [0074] 30 houses a plurality of pretreatment chambers 31 for pretreating semiconductor wafers prior to being plated, and a plurality of plating chambers 32 for plating semiconductor wafers with copper. Each of the pretreatment chambers 31 contains a pretreatment solution bath including sulfuric acid. A semiconductor wafer can be pretreated when it is immersed in the pretreatment solution bath in the pretreatment chamber 31. Each of the plating chambers 32 contains a plating solution bath including copper sulfate. A semiconductor wafer can be plated with copper when it is immersed in the plating solution bath in the plating chamber 32. The plating area 30 also has a transfer unit (transfer robot) for transferring semiconductor wafers.
  • FIG. 8 shows in side elevation air flows in the substrate plating apparatus. As shown in FIG. 8, fresh air is introduced from the exterior through a duct [0075] 46 and forced through high-performance filters 44 by fans from a ceiling 40 a into the cleaning and drying area 40 as downward clean air flows around the water cleaning units 41 and the drying units 42. Most of the supplied clean air is returned from a floor 40 b through a circulation duct 45 to the ceiling 40 a, from which the clean air is forced again through the filters 44 by the fans into the cleaning and drying area 40. Part of the clean air is discharged from the water cleaning units 41 and the drying units 42 through a duct 52 out of the cleaning and drying area 40.
  • In the plating area [0076] 30 which accommodates the pretreatment chambers 31 and the plating chambers 32, particles are not allowed to be applied to the surfaces of semiconductor wafers even though the plating area 30 is a wet zone. To prevent particles from being applied to semiconductor wafers, downward clean air flows around the pretreatment chambers 31 and the plating chambers 32. Fresh air is introduced from the exterior through a duct 39 and forced through high-performance filters 33 by fans from a ceiling 30 a into the plating area 30.
  • If the entire amount of clean air as downward clean air flows introduced into the plating area [0077] 30 were always supplied from the exterior, then a large amount of air would be required to be introduced into and discharged from the plating area 30 at all times. According to this embodiment, air is discharged from the plating area 30 through a duct 53 at a rate sufficient to keep the pressure in the plating area 30 lower than the pressure in the cleaning and drying area 40, and most of the downward clean air introduced into the plating area 30 is circulated through circulation ducts 34, 35. The circulation duct 34 extends from the cleaning and drying area 40 and is connected to the filters 33 over the ceiling 30 a. The circulation duct 35 is disposed in the cleaning and drying area 40 and connected to the pipe 34 in the cleaning and drying area 40.
  • The circulating air that has passed around the pretreatment chambers [0078] 31 and the plating chambers 32 contains a chemical mist and gasses from solution bathes. The chemical mist and gasses are removed from the circulating air by a scrubber 36 and mist separators 37, 38 which are disposed in the pipe 34 that is connected to the pipe 35. The air which circulates from the cleaning and drying area 40 through the scrubber 36 and the mist separators 37, 38 back into the circulation duct 34 over the ceiling 30 a is free of any chemical mist and gasses. The clean air is then forced through the filters 33 by the fans to circulate back into the plating area 30.
  • Part of the air is discharged from the plating area [0079] 30 through the duct 53 connected to a floor 30 b of the plating area 30. Air containing a chemical mist and gasses is also discharged from a plating solution circulating tank 50 and an H2SO4 circulating tank 51 in the plating area 30, through the duct 53. An amount of fresh air which is commensurate with the amount of air discharged through the duct 53 is supplied from the duct 39 into the plating chamber 30 under the negative pressure developed therein with respect to the pressure in the clean room.
  • As described above, the pressure in the loading and unloading area [0080] 20 is higher than the pressure in the cleaning and drying area 40 which is higher than the pressure in the plating area 30. When the shutters 22, 24 (see FIG. 7) are opened, therefore, air flows successively through the loading and unloading area 20, the cleaning and drying area 40, and the plating area 30, as shown in FIG. 9. Air discharged from the cleaning and drying area 40 and the plating area 30 flows through the ducts 52, 53 into a common duct 54 (see FIG. 10) which extends out of the clean room.
  • FIG. 10 shows in perspective the substrate plating apparatus shown in FIG. 7, which is placed in the clean room. The loading and unloading area [0081] 20 includes a side wall which has a cassette transfer port 55 defined therein and a control panel 56, and which is exposed to a working zone 58 that is compartmented in the clean room by a partition wall 57. The partition wall 57 also compartments a utility zone 59 in the clean room in which the substrate plating apparatus is installed. Other sidewalls of the substrate plating apparatus are exposed to the utility zone 59 whose air cleanliness is lower than the air cleanliness in the working zone 58.
  • As described above, the cleaning and drying area [0082] 40 is disposed between the loading and unloading area 20 and the plating area 30. The partition 21 is disposed between the loading and unloading area 20 and the cleaning and drying area 40, and the partition 23 is disposed between the cleaning and drying area 40 and the plating area 30. A dry semiconductor wafer is loaded from the working zone 58 through the cassette transfer port 55 into the substrate plating apparatus, and then plated in the substrate plating apparatus. The plated semiconductor wafer is cleaned and dried, and then unloaded from the substrate plating apparatus through the cassette transfer port 55 into the working zone 58. Consequently, no particles and mist are applied to the surface of the semiconductor wafer, and the working zone 58 which has higher air cleanliness than the utility zone 57 is prevented from being contaminated by particles, chemical mists, and cleaning solution mists.
  • In the fifth embodiment shown in FIGS. 7 and 8, the substrate plating apparatus has the loading and unloading area [0083] 20, the cleaning and drying area 40, and the plating area 30. However, an area accommodating a chemical mechanical polishing unit may be disposed in or adjacent to the plating area 30, and the cleaning and drying area 40 may be disposed in the plating area 30 or between the area accommodating the chemical mechanical polishing unit and the loading and unloading area 20. Any of various other suitable area and unit layouts may be employed insofar as a dry semiconductor wafer can be loaded into the substrate plating apparatus, and a plated semiconductor wafer can be cleaned and dried, and thereafter unloaded from the substrate plating apparatus.
  • FIGS. 11 through 15 show a substrate plating apparatus for forming interconnections on a semiconductor wafer according to a sixth embodiment of the present invention. [0084]
  • As shown in FIG. 11, the substrate plating apparatus, generally denoted by [0085] 110, has a contaminated zone 112 and a clean zone 113 divided by a partition 111. The contaminated zone 112 and the clean zone 113 can independently be supplied with and discharge air. The pressure in the clean zone 113 is higher than the pressure in the contaminated zone 112.
  • The clean zone [0086] 113 accommodates a loading unit 114 a, an unloading unit 114 b, two water cleaning and drying units 160 for cleaning and drying plated semiconductor wafers, and a transfer unit (transfer robot) 161 for transferring semiconductor wafers. The contaminated zone 112 accommodates two pretreatment chambers 118 for pretreating semiconductor wafers by pretreating solution baths, a plurality of plating chambers 119 for plating semiconductor wafers with copper by plating solution baths, and a transfer unit (transfer robot) 162 for transferring semiconductor wafers.
  • The pretreatment chambers [0087] 118 and the plating chambers 119 are similar in structure and operation to those according the previous embodiments.
  • As shown in FIG. 12, the transfer unit [0088] 162 disposed in the contaminated zone 112 comprises a six-axis robot, for example, having a plurality of interconnected arms 163 with an openable and closable grip hand 164 mounted on a tip end of the arms 163. The grip hand 164 is in the form of a ring having a plurality of rotatable rollers 163 165 mounted on an inner circumferential surface thereof.
  • As shown in FIGS. 11 and 13, a loading stage [0089] 167 having a plurality (four in the illustrated embodiment) of support bases 166 is mounted in the clean zone 113 adjacent to the partition 111. The transfer unit 161 in the clean zone 113 holds a semiconductor wafer W to be plated and places the semiconductor wafer W onto the support bases 166 of the loading stage 167, and then the transfer unit 162 in the contaminated zone 112 picks up the semiconductor wafer W from the support bases 166.
  • As shown in FIG. 13, a partition wall [0090] 170 is disposed between the loading stage 167 and the partition 111. The partition wall 170 has an opening 170 a defined therein for passage of the grip hand 164 of the transfer unit 162 therethrough and a shutter 172 actuatable by a cylinder 171 for opening and closing the opening 170 a. The partition 111 also has an opening 111 a defined therein for passage of the grip hand 164 of the transfer unit 162 therethrough.
  • A roughly cleaning chamber [0091] 183 is positioned adjacent to the partition 111 in juxtaposed relation to the loading stage 167. The roughly cleaning chamber 183 is defined as a box by a rear partition wall 180 contiguous to the partition wall 170, a front partition wall 181 of a substantially C-shape joined to the rear partition wall 180, and a ceiling 182 (see FIG. 15). The roughly cleaning chamber 183 accommodates an unloading stage 185 having a plurality of (four in the illustrated embodiment) support bases 184. The unloading stage 185 is identical in structure to the loading stage 167.
  • As shown in FIG. 15, two vertically spaced arrays of ejection nozzles [0092] 186 for ejecting a cleaning solution are disposed in the roughly cleaning chamber 183.
  • As shown in FIGS. 13 and 15, the rear partition wall [0093] 180 has an opening 180 a defined therein for passage of the grip hand 164 of the transfer unit 162 in the contaminated zone 112 therethrough and a shutter 188 actuatable by a cylinder 187 for opening and closing the opening 180 a. The front partition wall 181 has an opening 181 a defined therein for passage of a grip hand of the transfer unit 161 in the clean zone 113 therethrough and a shutter 190 actuatable by a cylinder 189 for opening and closing the opening 181 a. The opening 11 a in the partition 111 extends from a position behind the loading stage 167 all the way to a position behind the roughly cleaning chamber 183 for allowing the grip hand 164 of the transfer unit 162 to move freely toward and away from the openings 170 a, 180 a.
  • As shown in FIG. 14, the shutter [0094] 188 has a recess 188 a defined in an upper edge thereof for passage therethrough of only the arms 163 of the transfer unit 162.
  • The grip hand [0095] 164 of the transfer unit 162 in the contaminated zone 112 can be inserted through the recess 188 a into the roughly cleaning chamber 183. Therefore, the grip hand 164 and a plated semiconductor wafer W gripped thereby can be roughly cleaned in the roughly cleaning chamber 183. After the grip hand 164 and the plated semiconductor wafer W gripped thereby are roughly cleaned, the grip hand 164 places the semiconductor wafer W onto the support bases 184 of the unloading stage 185. The semiconductor wafer W placed on the support bases 184 is roughly cleaned again, and thereafter picked up by the transfer unit 161 in the clean zone 113.
  • More specifically, the shutter [0096] 188 is opened by being lowered by the cylinder 187, and a plated semiconductor wafer W gripped by the grip hand 164 of the transfer unit 162 is introduced into the roughly cleaning chamber 183. The shutter 188 is then lifted, and with the arms 163 of the transfer unit 162 being inserted through the recess 188 a, the ejection nozzles 186 eject a cleaning solution to the semiconductor wafer W for thereby roughly cleaning the grip hand 164 and the semiconductor wafer W. Thereafter, the roughly cleaned semiconductor wafer W is placed onto the support bases 184, and the grip hand 164 is retracted out of the roughly cleaning chamber 183. Then, the shutter 188 is fully closed.
  • Then, the ejection nozzles [0097] 186 eject a cleaning solution again to the semiconductor wafer W on the support bases 184 for roughly cleaning the semiconductor wafer W again. Thereafter, the shutter 190 is opened, and the grip hand of the transfer unit 161 in the clean zone 113 is inserted into the roughly cleaning chamber 183. After the grip hand of the transfer unit 161 picks up the semiconductor wafer W and removes the semiconductor wafer W from the roughly cleaning chamber 183, the shutter 190 is closed.
  • Because the grip hand [0098] 164 of the transfer unit 162 in the contaminated zone 112 is roughly cleaned together with the plated semiconductor wafer W, the plating solution is prevented from being applied to and deposited on the grip hand 164. Consequently, the grip hand 164 does not transfer any substantial contamination to the transfer unit 161 in the clean zone 113.
  • In the illustrated sixth embodiment, the clean zone [0099] 113 accommodates the loading stage 167 and the roughly cleaning chamber 183, which houses the unloading stage 185. However, the loading stage 167 and the roughly cleaning chamber 183 which houses the unloading stage 185 may be disposed in the contaminated zone 112.
  • In the illustrated embodiments, the present invention is applied to the substrate plating apparatus for plating a semiconductor wafer. However, the principles of the present invention are also applicable to a substrate plating apparatus for plating a substrate other than a semiconductor wafer. Furthermore, a region on a substrate plated by the substrate plating apparatus is not limited to an interconnection region on the substrate. The substrate plating apparatus may be used to plate substrates with a metal other than copper. [0100]
  • Although certain preferred embodiments of the present invention have been shown and described in detail, it should be understood that various changes and modifications may be made therein without departing from the scope of the appended claims. [0101]

Claims (1)

    What is claimed is:
  1. 1. A substrate plating apparatus for plating a substrate, comprising:
    a plating unit including at least one plating chamber for containing a plating solution for plating a metal layer onto a semiconductor substrate;
    a concentration analyzing device to analyze concentrations of the plating solution, wherein said concentration analyzing device includes a metal ion concentration analyzer and a plating additive concentration analyzer; and
    a plating solution preparing unit for preparing the plating solution based on results from said concentration analyzing device.
US10786110 1997-09-17 2004-02-26 Substrate plating apparatus Abandoned US20040163947A1 (en)

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JP27049397 1997-09-17
JP270493/1997 1997-09-17
JP7137098 1998-03-05
JP71370/1998 1998-03-05
JP9697498A JP3830272B2 (en) 1998-03-05 1998-03-26 Plating apparatus of the substrate
JP96974/1998 1998-03-26
JP205138/1998 1998-07-21
JP20513898A JPH11154653A (en) 1997-09-17 1998-07-21 Apparatus for plating substrates
US09154895 US6294059B1 (en) 1997-09-17 1998-09-17 Substrate plating apparatus
US09945711 US6929722B2 (en) 1997-09-17 2001-09-05 Substrate plating apparatus
US10786110 US20040163947A1 (en) 1997-09-17 2004-02-26 Substrate plating apparatus

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