US20040126548A1 - ULSI wiring and method of manufacturing the same - Google Patents

ULSI wiring and method of manufacturing the same Download PDF

Info

Publication number
US20040126548A1
US20040126548A1 US10/694,172 US69417203A US2004126548A1 US 20040126548 A1 US20040126548 A1 US 20040126548A1 US 69417203 A US69417203 A US 69417203A US 2004126548 A1 US2004126548 A1 US 2004126548A1
Authority
US
United States
Prior art keywords
layer
wiring
nickel
ulsi
diffusion prevention
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/694,172
Inventor
Kazuyoshi Ueno
Tetsuya Osaka
Nao Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Waseda University
NEC Electronics Corp
NEC Corp
Original Assignee
Waseda University
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2001158513 priority Critical
Priority to JP2001-158513 priority
Priority to JP2001277602A priority patent/JP3654354B2/en
Priority to JP2001-277602 priority
Priority to US10/154,812 priority patent/US20030008075A1/en
Application filed by Waseda University, NEC Corp filed Critical Waseda University
Priority to US10/694,172 priority patent/US20040126548A1/en
Assigned to WASEDA UNIVERSITY, NEC CORPORATION reassignment WASEDA UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OSAKA, TETSUYA, TAKANO, NAO, UENO, KAZUYOSHI
Publication of US20040126548A1 publication Critical patent/US20040126548A1/en
Assigned to NEC CORPORATION, WASEDA UNIVERSITY reassignment NEC CORPORATION CORRECTED ASSIGNMENT TO CORRECT THE ADDRESS OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 014951 FRAME 0987. Assignors: OSAKA, TETSUYA, TAKANO, NAO, UENO, KAZUYOSHI
Assigned to NEC ELECTRONICS CORPORATION, WASEDA UNIVERSITY reassignment NEC ELECTRONICS CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNEE'S ADDRESSES PREVIOUSLY ON REEL 014951, FRAME 0987. Assignors: OSAKA, TETSUYA, TAKANO, NAO, UENO, KAZUYOSHI
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18Pretreatment of the material to be coated
    • C23C18/1851Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
    • C23C18/1872Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
    • C23C18/1886Multistep pretreatment
    • C23C18/1893Multistep pretreatment with use of organic or inorganic compounds other than metals, first
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • C23C18/1651Two or more layers only obtained by electroless plating
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/31504Composite [nonstructural laminate]
    • Y10T428/31652Of asbestos
    • Y10T428/31663As siloxane, silicone or silane

Abstract

A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, an SiO2 surface on which the insulating interlayer portion is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. Furthermore, a capping layer is formed on the wiring layer by electroless plating. Consequently, the diffusion prevention layer having good adhesive properties can all be formed through a simple process by wet processes, and further, the wiring layer can directly be formed on this diffusion prevention layer by the wet process. In addition, the capping layer can directly be formed on this wiring layer by electroless plating.

Description

  • This is a Continuation-In-Part of application Ser. No. 10/154,812 filed May 28, 2002, the disclosure of which is incorporated herein by reference.[0001]
  • BACKGROUND OF THE INVENTION
  • (i) Field of the Invention [0002]
  • The present invention relates to ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO[0003] 2, and a method of manufacturing the same.
  • (ii) Description of the Related Art [0004]
  • In ULSI wiring, attendant upon the requirements of an increase in capacity of ULSI and a decrease in cost of manufacture, it is desired to decrease in size of wiring structure and simplify the manufacturing process. From these points, as fabrication techniques for ULSI wiring structures, at present, dual damascene processes are mainstream (hereinafter referred to as prior art 1). [0005]
  • In ULSI wiring according to the prior art 1, in case that a wiring layer is made of Cu (copper), Cu constituting the wiring layer diffuses into an insulating interlayer so that it may bring about bad insulation. Therefore, it is indispensable to interpose a diffusion prevention layer between the wiring layer and the insulating interlayer and thereby prevent Cu from diffusing into the insulating interlayer. [0006]
  • Conventionally, for this diffusion prevention layer, use is made of TaN, TiN, or the like, formed mainly through a sputtering process. Besides, in case that the wiring layer is formed on this diffusion prevention layer by electroplating, in particular, with copper, since the diffusion prevention layer of TaN, TiN, or the like, as described above, is inferior in electrical conductivity, a Cu seed layer or the like as a conductive layer is required. [0007]
  • Although, in dual damascene processes, simplification of process and a decrease in cost by application of wet processes are considered to be advantageous, it is hard to say that the use of dry processes, such as sputtering upon fabrication of the diffusion prevention layer and the conductive layer, is the best technique. [0008]
  • So, a technique is first thinkable in which the diffusion prevention layer is fabricated through an electroless plating process as a wet process. A method of forming such a diffusion prevention layer by electroless plating is reported in, e.g., Electrochimica Acta, vol. 44 (1999), pp. 3639-3649 (hereinafter referred to as prior art 2). For forming a diffusion prevention layer by electroless plating, it is indispensable to give catalysis to the surface of an insulating interlayer. However in the above report, for forming a diffusion prevention layer of COWP, a Co layer is formed as a catalyst layer by sputtering to give catalysis. In this way, in the case of forming the catalyst layer by sputtering, a thickness to some extent is required for keeping adhesive properties between the diffusion prevention layer and the insulating interlayer, and the uniformity of the diffusion prevention layer. Therefore, by this method, further fineness of the ULSI wiring structure is difficult. [0009]
  • Besides, in the above-described process, many steps are required till the fabrication of the wiring layer. In addition, two processes different in phase, such as sputtering and CVD as dry processes, and electroplating as a wet process, must be performed. Therefore, the process is complicated and it is disadvantageous in cost. [0010]
  • Further, a layer of SiN or the like higher in dielectric constant than SiO[0011] 2, as a capping layer (cap insulating layer), is formed on the wiring layer by chemical vapor deposition (CVD) or the like. In this case, a thickness to some extent is required for keeping the adhesive properties with the wiring layer, and the uniformity and thermal stability of the capping layer. Therefore, the wiring capacity is increased, and further fineness of the wiring structure is difficult.
  • SUMMARY OF THE INVENTION
  • The present invention has been made in view of the above circumstances. [0012]
  • It is an object of the present invention to provide a method of manufacturing ULSI wiring, which makes it possible to perform all the formations of the diffusion prevention layer and further the wiring layer and the capping layer through wet processes, and in which the diffusion prevention layer good in adhesion, and further the wiring layer and the capping layer, can be formed through a simple process. [0013]
  • It is another object of the present invention to provide ULSI wiring in which a capping layer good in adhesion, uniformity, and thermal stability is formed as a plating film on the wiring layer. [0014]
  • According to one aspect of the present invention, there is provided a method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO[0015] 2. The method comprises the steps of treating, with a silane compound, an SiO2 surface on which the insulating interlayer portion is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. According to this aspect of the present invention, the diffusion prevention layer having high thermal stability and barrier properties.
  • In the aspect of the present invention, the formation of the diffusion prevention layer by the electroless plating preferably is accomplished by a step of forming metallic cores by use of a neutral or acid electroless plating bath, and a step of forming the diffusion prevention layer by use of an alkaline electroless plating bath. In consequence, even by using the alkaline electroless plating bath, the diffusion prevention layer can be formed without damaging SiO[0016] 2 and the organic silane layer.
  • In the aspect of the present invention, when the wiring layer is formed by electroless plating, the diffusion prevention layer formed by the above method plays the role of a catalyst. Hence, it is possible to directly form the wiring layer on the diffusion prevention layer by the electroless plating without performing a treatment such as the catalyzation treatment. In addition, if a metallic film having a low specific resistance is used as the diffusion prevention layer, the wiring layer can also be formed by electroplating. Furthermore, if a capping layer is directly formed on this wiring layer by the electroless plating, the ULSI wiring can be manufactured through all wet processes. [0017]
  • According to another aspect of the present invention, there is provided a manufacturing method of ULSI wiring which comprises the step of directly forming a capping layer on a wiring layer by electroless plating. Here, in the case of this aspect of the present invention, for forming the capping layer, an electroless plating bath as will be described below in detail is preferably used, besides, in case that the wiring layer is made of copper, it preferably comprises the step of removing copper oxide rubbish before electroless plating. As the copper oxide rubbish removing step before electroless plating, it is a wet treatment or the like with an acid aqueous solution without damaging an insulating interlayer, more specifically, a wet treatment with an acid electroless nickel plating bath using a boron-base reducing agent is preferable. By treatment with the acid electroless nickel plating bath using this boron-base reducing agent, preferably not only the removal of the copper oxide layer but also uniform reaction core formation onto the wiring layer is performed at the same time. In this case, it is preferable that the step of forming the capping layer is performed in two stages of the copper oxide layer removal and reaction core formation step with the electroless nickel plating bath using the boron-base reducing agent, and then the step of forming the capping layer by alkaline electroless plating; or it is also preferable that the copper oxide layer removal and reaction core formation step with the electroless nickel plating bath using the boron-base reducing agent, and the step of forming the capping layer are performed in one stage; or it is preferable that the step of forming the capping layer is performed in two stages of the copper oxide layer removal and the step of forming the capping layer by alkaline electroless plating containing no alkali metal. [0018]
  • According to still another aspect of the present invention, there is provided ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO[0019] 2 and a capping layer is formed on the wiring layers. In the ULSI wiring, the capping layer is made of a nickel-tungsten-phosphorus, nickel-rhenium-phosphorus, or nickel-boron plating film. In this case, the capping layer is preferably formed by nickel-tungsten-phosphorus electroless plating, nickel-rhenium-phosphorus electroless plating, or nickel-boron electroless plating. According to this aspect of the present invention, this capping layer is good in adhesion, uniformity, and thermal stability.
  • According to yet another aspect of the present invention, there is provided a method of manufacturing ULSI wiring which comprises the step of applying nickel-tungsten-phosphorus electroless plating, nickel-rhenium-phosphorus electroless plating, or nickel-boron electroless plating to wiring layers of ULSI wiring in which the wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO[0020] 2, thereby forming a capping layer on the wiring layers.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a conceptional view illustrating one example of ULSI wiring manufactured through a conventional dual damascene process; [0021]
  • FIG. 2 is a conceptional view illustrating another example of ULSI wiring manufactured through a conventional dual damascene process; [0022]
  • FIG. 3 is a conceptional view illustrating ULSI wiring manufactured by a manufacturing method according to one embodiment of the present invention; [0023]
  • FIG. 4 is a conceptional view illustrating ULSI wiring manufactured by a manufacturing method according to another embodiment of the present invention; [0024]
  • FIG. 5 is a graph showing the thermal stability valuation of a nickel-rhenium-phosphorus diffusion prevention layer; [0025]
  • FIG. 6 is a graph showing the thermal stability valuation of a nickel-boron capping layer; and [0026]
  • FIG. 7 is a graph showing the thermal stability valuation of a nickel-boron capping layer fabricated with an electroless plating bath containing no alkali metal.[0027]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Before describing embodiments of the present invention, for making the understanding of the present invention easy, manufacturing methods of ULSI wiring according to prior arts will be described with reference to FIGS. 1 and 2. [0028]
  • As illustrated in FIG. 1, in ULSI wiring according to the prior art [0029] 1, particularly in case that a wiring layer 11 is made of Cu (copper), if Cu constituting the wiring layer 11 diffuses into an insulating interlayer 13, it may bring about bad insulation. Therefore, it is indispensable to interpose a diffusion prevention layer 15 between the wiring layer 11 and the insulating interlayer 13 and thereby prevent Cu from diffusing into the insulating interlayer 2.
  • Conventionally, for this diffusion prevention layer [0030] 15, use is made of TaN, TiN, or the like, formed mainly through a sputtering process. In case that the wiring layer 11 is formed on this diffusion prevention layer 15 by electroplating, in particular, with copper, the diffusion prevention layer 15 of TaN, TiN, or the like, as described above, is inferior in electrical conductivity. Accordingly, a Cu seed layer or the like as a conductive layer 17 is required. Note that reference numeral 19 in the figure denotes an etching stop, and reference numeral 21 in the figure denotes a cap insulating layer (SiN).
  • Although, in dual damascene processes, simplification of process and a decrease in cost by application of wet processes are considered to be advantageous, it is hard to say that the use of dry processes such as sputtering upon fabrication of the diffusion prevention layer and the conductive layer is the best technique. [0031]
  • So, as illustrated in FIG. 2, a technique in which the diffusion prevention layer is fabricated through an electroless plating process as a wet process has been thought out in the prior art 2. [0032]
  • Referring to FIG. 2, for forming a diffusion prevention layer by electroless plating according to the prior art 2, although it is indispensable to give catalysis to the surface of the insulating interlayer [0033] 13, in one according to the prior art 2, for forming the diffusion prevention layer 15 of COWP, as a catalyst layer 25, a Co layer is formed by sputtering to give catalysis. In this way, in the case of forming the catalyst layer 15 by sputtering, for keeping the adhesive properties between the diffusion prevention layer and the insulating interlayer and the uniformity of the diffusion prevention layer, a thickness to some extent is required. Therefore, by this method, further fineness of the ULSI wiring structure is difficult.
  • In the above-described process, many steps are required till the fabrication of the wiring layer. In addition, two processes different in phase, such as sputtering and CVD as dry processes, and electroplating as a wet process, must be performed. Therefore, the process is complicated and it is disadvantageous in cost. [0034]
  • Further, a layer of SiN or the like higher in dielectric constant than SiO[0035] 2, as a capping layer (cap insulating layer), is formed on the wiring layer by chemical vapor deposition (CVD) or the like. In this case, a thickness to some extent is required for keeping the adhesive properties with the wiring layer, and the uniformity and thermal stability of the capping layer. Therefore, it has disadvantages that the wiring capacity is increased and further fineness of the wiring structure is difficult.
  • Now, preferred embodiments of the present invention will be described with reference to FIGS. [0036] 3 to 9.
  • Methods of manufacturing ULSI wiring according to the embodiments of the present invention are based on a dual damascene process. [0037]
  • As illustrated in FIG. 3, in an embodiment of the present invention, first, the surface of the insulating interlayer [0038] 13 made of SiO2 is treated with an organic silane compound. By this, an adhesion layer 27 preferably made of a monomolecular layer of the organic silane compound.
  • In this case, as the organic silane compound, although, for example, silane coupling agents such as silane having amino groups and alkoxy groups such as N-(2-aminoethyl)-3-aminopropyl trimethoxy silane, 3-aminopropyl trimethoxy silane, 2-(trimethoxysilyl)ethyl-2-pyridine, (aminoethyl)-phenethyl trimethoxy silane, or the like, and further silane having epoxy groups and alkoxy groups such as γ-glycidyl propyl trimethoxy silane or the like, can be mentioned, particularly from the points of adhesive properties and catalysis giving properties, a silane coupling agent having amino groups and alkoxy groups is preferable. [0039]
  • The above organic silane compound is used as a solution in which it is dissolved in a solvent, and treated by dipping the substrate having the insulating interlayer made of the above SiO[0040] 2 in this. In this case, as the solvent, although an alcoholic solvent such as methanol, ethanol, or the like, a hydrocarbonic solvent such as toluene or the like, are used, preferably, an alcoholic solvent, in particular, ethanol is preferable.
  • Although depending upon the time in which the substrate is dipped, the concentration of the above organic silane is preferably 0.2-2 vol. %, particularly, about 1 vol. % is preferable. [0041]
  • Besides, this solution is used in the temperature range of, preferably, 20-90° C., particularly, 40-70° C., more particularly, 50-60° C. Note that the dipping time is preferably 30 minutes to 10 hours, particularly, 1-6 hours, more particularly, 2-6 hours. [0042]
  • In the present invention, next, the SiO[0043] 2 surface is catalyzed with a solution containing a palladium (Pd) compound. In this way, by dipping the substrate in a silane compound, particularly, a silane compound solution having amino groups in particular, preferably, a self-organizing monomolecular layer in chemical bond with the SiO2 surface is formed on the SiO2 surface of the substrate, and further, by dipping this substrate in an aqueous solution containing a palladic salt, amino groups catch Pd, and it enables catalyzation of the SiO2 surface. That is, although the surface that the monomolecular layer constituted by the silane compound, in particular, silane molecules having amino groups, on SiO2 of the substrate, has good smoothness, by dipping in the aqueous solution containing the palladic salt, catalyzation of the surface becomes possible.
  • Here, as the aqueous solution (catalysis giving liquid) containing a palladium compound, an acid aqueous solution containing a water-soluble palladium compound such as PdCl[0044] 2, Na2PdCl4, or the like, is suitably used. In this case, the concentration of the palladium compound is preferably 0.01-0.5 g/L, particularly, 0.04-0.1 g/L, more particularly, 0.04-0.05 g/L, as palladium. In this catalysis giving liquid, at need, a buffer such as 2-morpholinoethane sulfonic acid or the like can be added, or a stabilizer such as NaCl or the like can be added. Besides, pH of this catalysis giving liquid is preferably set at 2-6, particularly, 4-6, more particularly, about 5.
  • Although the catalyzation treatment using the above catalysis giving liquid is performed in the temperature range of, preferably, 10-40° C., particularly, 20-30° C., more particularly, 20-25° C., usually the room temperature suffices. Note that the dipping time is preferably 1-60 minutes, particularly, 10-30 minutes. [0045]
  • Next, on SiO[0046] 2 to which the above catalyzation treatment has been applied, as illustrated in FIG. 3, a diffusion prevention layer 15 is formed by electroless plating.
  • Here, in case that an adhesion layer [0047] 27 is formed onto SiO2 by the organic silane monomolecular layer, if an alkaline electroless plating bath is directly used in the subsequent electroless plating process, since, by the SiO2 surface being damaged, the adhesion layer 27 is also damaged. Therefore, an electroless plating bath not more than neutrality must be used.
  • However, when formation of a metallic film effective as the diffusion prevention layer [0048] 15 is considered, such a restriction is very disadvantageous.
  • So, in the present invention, it is preferable to adopt a method in which, first, as the first step, metal cores are formed with a neutral or acid electroless plating bath, and then, as the second step, formation of the diffusion prevention layer using an alkaline electroless plating bath is performed by the use of self-catalysis functions of the metal cores themselves. If this process is used, even using the highly alkaline electroless plating bath in the second step, there is no damage on the adhesion layer, and fabrication of the diffusion prevention layer exhibiting good adhesive properties becomes possible. In this way, by forming the metal cores in the first step, since the restriction of the electroless plating bath used upon diffusion prevention layer formation, it can be said that this is a very effective technique. [0049]
  • Here, as the above neutral or acid electroless plating bath, use is suitably made of electroless nickel plating bath using, as a reducing agent, hypophosphite, such as sodium hypophosphite or the like, amine borane, such as dimethylamine borane or the like, or the like, at pH of 4-7, particularly, 4-5, 5, more particularly, 4.4-5. As this neutral or acid electroless nickel plating bath, one having a known composition is used, and a commercial item can be used. [0050]
  • Besides, plating conditions using this neutral or acid electroless nickel plating bath can be a normal method according to this plating bath, though being properly selected, for example, the plating temperature is 70-95° C., particularly at 70-92° C., plating is preferably performed for 5-60 seconds, particularly, for 10-30 seconds, more particularly, for 10-15 seconds, and the film thickness of the plating film by this plating is preferably set at 5-25 nm, particularly, 5-15 nm. [0051]
  • On the other hand, as the alkaline electroless plating bath, it is preferable to use an electroless nickel-tungsten-phosphorus bath, an electroless nickel-rhenium-phosphorus bath, an electroless nickel-boron bath, or the like. In this way, the substrate to which the above catalyzation has been applied is (a) by dipping in the neutral or acid electroless nickel plating bath, after deposition cores of nickel are formed, (b) by dipping in the alkaline electroless nickel-tungsten-phosphorus bath, electroless nickel-rhenium-phosphorus bath, or electroless nickel-boron bath, fabrication of a nickel alloy layer as the diffusion prevention layer is suitable. In this case, by performing the step of (a), as described above, metal film formation from such an alkaline electroless plating bath as (b) becomes possible, if the alkaline plating bath is used without performing the step of (a), since the substrate is damaged by the alkaline aqueous solution, the organic silane monomolecular layer is also damaged, and there is a fear of hindering the subsequent electroless plating process. A nickel-tungsten-phosphorus or nickel-rhenium-phosphorus thin film fabricated by the above step exhibits good adhesion, and by the subsequent anneal treatment, the adhesive properties are further improved. [0052]
  • Note that the plating layer formed with the above electroless nickel-tungsten-phosphorus bath or electroless nickel-rhenium-phosphorus bath is, from the point of diffusion prevention effect or the like, preferably one in which the tungsten or rhenium content is 40-80 wt. %, the phosphorus content is 0.1-1.0 wt. %, and the residual is nickel. Besides, the plating layer formed with the electroless nickel-boron bath is preferably one in which the boron content is 5-10 wt. % and the residual is nickel. [0053]
  • Here, as the electroless nickel-tungsten-phosphorus bath or electroless nickel-rhenium-phosphorus bath, one is preferable which contains 0.02-0.1 mole/L, particularly, about 0.075 mole/L of a water-soluble nickel salt, e.g., nickel sulfate or the like, 0.005-0.2 mole/L, particularly, 0.030-0.106 mole/L of a water-soluble tungstate or rhenate, such as sodium tungstate, ammonium perrhenate, or the like, and 0.09-0.1 mole/L, particularly, 0.094-0.1 mole/L of a hypophosphite, such as sodium hypophosphite or the like, as a reducing agent. As the electroless nickel-boron bath, one is preferable which contains 0.05-0.2 mole/L, particularly, about 0.1 mole/L of a water-soluble nickel salt, e.g., nickel sulfate or the like, and 0.025-0.1 mole/L, particularly, about 0.05 mole/L of amine borane such as dimethylamine borane or the like, as a reducing agent. Besides, these electroless plating baths preferably further contain 0.034-0.4 mole/L, particularly, 0.135-0.2 mole/L of a complexing agent such as carboxylic acid such as citric acid, tartaric acid, succinic acid, malonic acid, malic acid, gluconic acid, or the like, or its salt, or an ammonium salt such as ammonium sulfate or the like. In the baths, at need, a pH-conditioner, a buffer, a stabilizer, or the like, may be added. [0054]
  • pH of the above plating baths can be set in the range of 7.4-10, particularly, 8.5-9.5. [0055]
  • Although plating conditions are properly selected, plating can be performed at 80-90° C., particularly, about 90° C., for 1-30 minutes, particularly, 3-15 minutes, more particularly, 3-8 minutes, and the thickness of the diffusion prevention layer is preferably set at 50-100 nm, particularly, about 50 nm. [0056]
  • Note that the present invention preferably adopts a two-stage plating method in which, after plating with a neutral or acid electroless plating bath, plating is performed with an alkaline electroless plating bath. However, it is not limited to this. The diffusion prevention layer can be formed by a single-stage plating method using a neutral or acid electroless plating bath. Particularly, in case that a neutral or acid bath (pH=4-7) is used as the above nickel-tungsten-phosphorus bath, nickel-rhenium-phosphorus bath, or nickel-boron bath, the diffusion prevention layer can be formed by a single-stage plating method with this plating bath. [0057]
  • Note that, after forming the diffusion prevention layer as described above, it is preferable to apply a heating treatment at 300-450° C., particularly, 300-350° C., for 10-30 minutes, particularly, 25-30 minutes, and thereby the adhesive properties can be further improved. However, since a heating step is always included in ULSI wiring manufacturing process, even if no heating treatment step is performed here, finally, the improvement of the adhesive properties can be intended. [0058]
  • In a process of manufacturing ULSI wiring before the diffusion prevention layer is formed on the organic silane layer and after the organic silane layer is deposited on the first insulation layer, the organic silane layer is subjected to heat-decomposition by heating of the process at a temperature, for example 300° C. or more in the process to form an adhesion layer containing at least one of silicon (Si) and carbon (C). [0059]
  • Furthermore, in a process of manufacturing ULSI wiring after the diffusion prevention is formed on the organic silane layer, the adhesion layer heat-decomposed at the temperature, for example 300° C. or more in the process from the organic silane layer to form silicon (Si) and carbon (C) and which Si and C are further diffused into the diffusion prevention layer by heating to form a diffusion prevention layer containing at least one of Si and C. [0060]
  • In the present invention, after forming the diffusion prevention layer in this way, a wiring layer [0061] 11 can be formed directly on this as illustrated in FIG. 3. In this case, the wiring layer 11 is preferably formed by electroless copper plating or electroplating with copper (note that, in FIG. 3, reference numeral 19 denotes an etching stop made of SiN or the like, and reference numeral 21 is a cap insulating layer made of SiN). That is, the diffusion prevention layer fabricated by an electroless plating method as described above has catalyst activity to another electroless plating bath. Therefore, in FIG. 4, the step of forming a conductive layer for copper plating layer fabrication denoted by reference numeral 15 is eliminated, and subsequently, fabrication of the copper wiring layer 11 becomes possible by electroless copper plating. Further, if the diffusion prevention layer 15 is a metallic film low in specific resistance, fabrication of the copper wiring layer becomes possible not only by electroless plating but also electroplating with copper, and it can achieve the manufacture of the ULSI wiring layer by all wet processes.
  • Here, as electroless copper plating, using a known electroless copper plating bath in which formalin, hypophosphite, further, dimethylamine borane, NaBH[0062] 4, or the like is used as a reducing agent, plating can be performed under known conditions in accordance with the kind of the plating bath. Besides, as for electroplating with copper, using known electro-copper-plating bath, such as a copper-sulfate bath, a copper-borofluoride bath, a copper-pyrophosphate bath, or the like, plating can be performed under known conditions in accordance with the kind of the plating bath, and the wiring layer 11 can be formed by a normal method.
  • Further, in the present invention, after forming the wiring layer [0063] 11 as described above, as illustrated in FIG. 4, further, a metallic plating thin film can be formed on this as a capping layer 29 like the diffusion prevention layer using an electroless plating bath, such as the above electroless nickel-tungsten-phosphorus bath, electroless nickel-rhenium-phosphorus bath, electroless nickel-boron bath, or the like. In the present invention, a step of forming a metallic plating thin film on the substrate by no use of forming the catalyst layer and with contacting to the substrate will be referred to as “direct forming the metallic plating film on the substrate”. By this, without performing film formation of the cap insulating layer as shown by reference numeral 21 in FIG. 3, although film formation of an insulating interlayer in the upper layer can be performed as illustrated in FIG. 4, the wiring layer 11 forming the capping layer 29 by the above method is not limited to one formed by the above-described method, and also applicable is to form on the wiring layer 11 of the ULSI wiring formed by a conventionally known method.
  • Note that, since the film thickness of the capping layer [0064] 29 of FIG. 4 is thin, the step with the upper surface of the insulating interlayer 13 of the middle step is little and it is substantially flat. For further flattening, a structure may be in which the wiring layer upper surface is formed somewhat lower than the upper surface of the insulating interlayer 13 of the middle step. Furthermore, the structure may be in which the capping layer 29 is formed on this so that its upper surface is at the same height as the insulating interlayer 13 of the middle step. However, the structure is not limited to these.
  • At this time, in the case of using an alkaline electroless plating bath, it is preferable to first treat with the acid electroless nickel-boron bath. Note that, in this case, its pH is preferably 4-6, particularly, 4-5. Since this electroless nickel-boron bath is acid, with removing oxide rubbish on the copper surface, it becomes possible to form reaction cores of electroless nickel-tungsten-phosphorus plating, electroless nickel-rhenium-phosphorus plating, or electroless nickel-boron plating, which will be performed subsequently. In the report in the above-mentioned Electrochimica Acta and a report in IBM Journal Research and Development, vol. 42 (1998), pp. 607-620, although a treatment with a Pd aqueous solution is performed when the capping layer [0065] 29 is formed on Cu by electroless plating, in the process according to the present invention, it becomes possible to decrease one stage of the treatment with the Pd aqueous solution which is considered to be desirable that it is omitted in the semiconductor process as far as possible. In the case of using acid electroless nickel-boron plating for forming the capping layer 29, it has the above-mentioned advantage, and also the plating process can be performed in one stage. In the report of Electrochimica Acta, although the copper wiring layer 11 surface fabricated by electroless plating is treated with fluoric acid and a palladium chloride aqueous solution, in the present invention, also the fluoric acid treatment which is considered to damage the insulating interlayer 13 can be eliminated.
  • In the case of forming the capping layer [0066] 29 with the electroless nickel-tungsten-phosphorus plating bath or electroless nickel-rhenium-phosphorus plating bath, a two-stage process is preferable in which, after the treatment with the acid electroless nickel-boron plating bath as described above, plating is performed with the alkaline electroless nickel-tungsten-phosphorus plating bath or alkaline electroless nickel-rhenium-phosphorus plating bath. However, it is not limited to this. The capping layer 29 can be formed through a single-stage process by the use of an electroless plating bath containing dimethylamine borane or the like which is acid and has activity on the copper surface as a reducing agent.
  • Besides, as the method for forming the capping layer [0067] 29, a method also can be used in which oxide rubbish on the copper surface is removed with an acid aqueous solution such as sulfuric acid or the like, and then the capping layer 29 is formed with an electroless plating bath. In this case, as the electroless plating bath, an alkaline electroless plating bath, in particular, an alkaline electroless nickel-boron plating bath, is preferable, and further, the plating bath preferably contain no alkali metal such as sodium, potassium, or the like. If a plating bath containing alkali metal is used, the gate insulating film made of SiO2 is contaminated with the alkali metal and there is a case that it causes deterioration of transistor characteristics. Note that, in this case, pH of the plating bath can be controlled with a base containing no alkali metal, such as TMAH (tetramethylammonium hydroxide).
  • Note that, as for the electroless plating bath in the case of forming the capping layer [0068] 29, as the electroless nickel-tungsten-phosphorus bath or electroless nickel-rhenium-phosphorus bath, one is preferable which contains 0.02-0.1 mole/L, particularly, about 0.075 mole/L of a water-soluble nickel salt, e.g., nickel sulfate or the like, 0.005-0.2 mole/L, particularly, 0.030-0.106 mole/L of a water-soluble tungstate or rhenate such as sodium tungstate, ammonium perrhenate, or the like, and 0.09-0.1 mole/L, particularly, 0.094-0.1 mole/L of a hypophosphite such as sodium hypophosphite or the like, as a reducing agent.
  • As the electroless nickel-boron bath, one is preferable which contains 0.05-0.2 mole/L, particularly, about 0.1 mole/L of a water-soluble nickel salt, e.g., nickel sulfate or the like, and 0.025-0.1 mole/L, particularly, about 0.05 mole/L of amine borane such as dimethylamine borane or the like, as a reducing agent. Besides, these electroless plating baths preferably further contain 0.034-0.4 mole/L, particularly, 0.135-0.2 mole/L of a complexing agent such as carboxylic acid such as citric acid, tartaric acid, succinic acid, malonic acid, malic acid, gluconic acid, or the like, or its salt, or an ammonium salt such as ammonium sulfate or the like. In the baths, at need, a pH-conditioner, a buffer, a stabilizer, or the like, may be added. [0069]
  • pH of the above plating baths can be set in the range of 7.4-10, particularly, 8.5-9.5. [0070]
  • Although plating conditions are properly selected, plating can be performed at 80-90° C., particularly, about 90° C., for 1-30 minutes, particularly, 3-15 minutes, more particularly, 3-8 minutes, and the thickness of the capping layer [0071] 29 is preferably set at 5-100 nm, particularly, about 20 nm.
  • The capping layer [0072] 29 obtained by the above method is, from the point of thermal stability or the like, in the case of nickel-tungsten-phosphorus or nickel-rhenium-phosphorus, preferably one in which the tungsten or rhenium content is 40-80 wt. %, the phosphorus content is 0.1-1.0 wt. %, and the residual is nickel. On the other hand, in the case of nickel-boron, it is preferably one in which the boron content is 0.1-10 wt. % and the residual is nickel.
  • Well, although specific examples of the present invention will be described, the present invention is not limited by this. [0073]
  • EXAMPLES 1-3
  • By washing an SiO[0074] 2 (film thickness: 30 nm)/Si substrate by an SPM treatment [H2SO4:H2O2=4:1 (volume ratio), 80° C., 10 minutes], and dipping this substrate in an N-(2-aminoethyl)-3-aminopropyl trimethoxy silane ethanol solution having the composition shown in Table 1, at 50° C. for four hours, an organic silane monomolecular layer was formed. Next, by dipping it in ethanol, removing surplus organic silane molecules by supersonic washing, and subsequently, dipping it in an aqueous solution containing Na2PdCl4 at the component concentration shown in the below Table 2, at the room temperature for 10-30 minutes, the surface was catalyzed. The substrate pulled up from the above solution was washed with ultrapure water and kept in ultrapure water.
  • Next, as the first step, this substrate was dipped in an electroless plating bath whose pH had been controlled to 4.5 and which had the composition shown in Table 3, at 70-90° C. for 10-15 seconds to form nickel cores on the surface. Subsequently, as the second step, this substrate was dipped in an electroless plating bath whose pH had been controlled to 9.0 and which had the component concentration shown in Table 4, for 3-8 minutes. As a result, a diffusion prevention layer was obtained. The whole surface of the substrate obtained had uniform metallic luster. [0075]
    TABLE 1
    Content (ml/100 ml)
    N-(2-aminoethyl)-3-aminopropyl 1.0
    trimethoxy silane
    Ethanol 99.0
  • [0076]
    TABLE 2
    Component Conc. (g/L)
    NaCl 0.5844
    2-Morpholinoethane sulfonic acid 2.132
    Na2PdCl4 0.1140
    pH (adjusted with NaOH) 5.0
  • [0077]
    TABLE 3
    Component Conc. (mol/L)
    NaH2PO2 .H2O 0.15
    (NH4)2SO4 0.50
    Sodium citrate 0.20
    NiSO4 .6H2O 0.10
  • [0078]
    TABLE 4
    Component Conc. (mol/L) Example 1 Example 2 Example 3
    (NH4)2SO4 0.227
    Sodium citrate 0.135 0.400 0.2
    NiSO4 0.027 0.0750 0.1
    Na2WO4 0.106
    (NH4)2ReO4 0.0300
    NaH2PO2 0.100 0.100
    Dimethylamine borane 0.05
    pH (adjusted with NaOH) 9.0 9.0 9.0
  • Note that, in the above example, if the first step was omitted and the second step was performed, it resulted in either that the metal deposition from the alkaline electroless plating bath of the above Table 4 became partial or that no deposition was observed. [0079]
  • Besides, as shown in FIG. 5, the nickel-rhenium-phosphorus diffusion prevention layer fabricated on SiO[0080] 2 exhibited good thermal stability to 400° C., and it was recognized to have a sufficient performance as the diffusion prevention layer.
  • After the above alkaline electroless plating, copper plating was performed using the electroless copper plating bath having the composition shown in the below Table 5, or the electroless steel plating bath having the composition shown in the below Table 6. In either case, good plating could be directly performed, and it was recognized to be able to form a wiring layer by direct copper plating. [0081]
    TABLE 5
    Component Conc.
    CuSO4 .5H2O 2 (g/dm3)
    EDTA 6 (g/dm3)
    DMAB 4 (g/dm3)
  • [0082]
    TABLE 6
    Component Conc.
    CuSO4 .5H2O 0.24 (mol/L)
    H2SO4  1.8 (mol/L)
    CL-   50 (mol/L)
    Polyethylene glycol  300 (mol/L)
    Bis(3-sulfopropyl) disulfide  1.0 (mol/L)
    Janus Green B  1.0 (mol/L)
  • After the above copper plating, with alcohol, such as ethanol, isopropyl alcohol, or the like, organic matter pollution on the copper surface was washed. Then, by the use of one in which pH of the electroless nickel-boron plating bath shown in the above Table 4 had been controlled to be acid (pH 5.0), reaction cores were formed for removal of oxide rubbish on the copper surface and electroless nickel-tungsten-phosphorus plating or electroless nickel-rhenium-phosphorus plating. By these treatments, the copper surface became pure and reaction active. Subsequently, when the above alkaline electroless plating was performed and fabrication of a capping layer [0083] 29 was performed, it exhibited good thermal stability to 450° C., and it was made clear to have a sufficient performance as the capping layer 29. Besides, after the above organic manner pollution washing step, using one in which pH of the electroless nickel-boron plating bath shown in the above Table 4 had been controlled to be acid, also in the case of performing removal of oxide rubbish on the copper surface and fabrication of the capping layer in a single stage, it exhibited good thermal stability to 400° C., and it was made clear to have a sufficient performance as the capping layer 29.
  • Besides, after the above-described copper plating, with alcohol such as ethanol, isopropyl alcohol, or the like, organic matter pollution on the copper surface was washed. Then, oxide rubbish on the copper surface was removed by dipping it in 10% sulfuric acid aqueous solution. By the use of the electroless nickel-boron plating bath shown in the above Table 4, fabrication of the capping layer [0084] 29 was performed by electroless plating. As shown in FIG. 6, the capping layer exhibited good thermal stability to 450° C., and it was made clear to have a sufficient performance as the capping layer 29.
  • Further, after the above-described copper plating, the above organic matter pollution washing and oxide rubbish removal step on the copper surface was applied. By the use of the electroless nickel-boron plating bath containing no alkali metal shown in Table 7, fabrication of the capping layer [0085] 29 was performed by electroless plating. As shown in FIG. 7, the capping layer 29 exhibited good thermal stability to 400° C., and it was made clear to have a sufficient performance as the capping layer 29.
    TABLE 7
    Component Conc. (mol/L)
    Citrate 0.2
    NiSO4 0.1
    DMAB 0.05
    pH (adjusted by TMAH) 9.0
  • As described above, according to the present invention, the diffusion prevention layer having good adhesive properties can all be formed through a simple process by wet processes, and further, the wiring layer can be formed on this diffusion prevention layer directly by the wet process. The capping layer can directly be formed on this wiring layer by the wet process. However, in the case of attaching the capping layer onto the wiring layer, the diffusion prevention layer of the lower layer is not limited to formation by the wet process. [0086]
  • In the above-embodiment, use is made of a silicon dioxide (SiO[0087] 2) layer, as the first and the second insulating internal layers. Furthermore, as the first and the second insulating internal layers, use may be made of a low dielectric layer, such as a hydrogen silsesquiozane layer (HSQ), a silicon oxycarbide (SiOC) layer, and the like.
  • Furthermore, in the above-embodiment, use is made of a plating film, such as a nickel-tungsten-phosphorus plating film, a nickel-rhenium-phosphorus plating film, and a nickel-boron film as the diffusion protection film and the capping layer. In place of the plating films as the diffusion protection film, use may be made of a conventional plating film, such as a cobalt-tungsten-phosphorus film, a cobalt-tungsten-boron film, and a cobalt metal film. [0088]

Claims (17)

What is claimed is:
1. ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO2 and a capping layer is formed on the wiring layers, wherein the capping layer is made of one plating film selected from the group consisting of nickel-tungsten-phosphorus, nickel-rhenium-phosphorus, and nickel-boron.
2. The ULSI wiring as claimed in claim 1, wherein said nickel-boron plating film contains a boron content of between about 0.1-10 wt. % and a nickel content of between about 90-99.9 wt. %.
3. The ULSI wiring as claimed in claim 1, wherein said nickel-tungsten-phosphorus plating film contains a tungsten content of between about 40-80 wt. %, a phosphorus content of between about 0.1-1.0 wt. %, and a residual of nickel.
4. The ULSI wiring as claimed in claim 1, wherein said nickel-rhenium-phosphorus plating film contains a rhenium content of between about 40-80 wt. %, a phosphorus content of between about 0.1-1.0 wt. %, and a residual of nickel.
5. The ULSI wiring as claimed in claim 1, wherein the wiring layer is separately formed via a diffusion prevention layer with the first insulating layer.
6. The ULSI wiring as claimed in claim 1, wherein the second insulating interlayer is also formed on at least a portion of said first insulating interlayer.
7. Ultra-Large Scale Integrated (ULSI) wiring comprising a first insulating interlayer having at least one of trench and via formed on the surface of the first insulating layer, a diffusion prevention layer formed above an inner surface of the at least one of trench and via with a space therein, a wiring layer formed in the space of the diffusion prevention layer, and a second insulating layer covered over at least the wiring layer,
wherein the diffusion prevention layer is made of a plating film selected from the group consisting of a nickel-tungsten-phosphorus plating film, a nickel-rhenium-phosphorus plating film, a nickel-boron film, a cobalt-tungsten-phosphorus film, a cobalt-tungsten-boron film, and a cobalt metal film.
8. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 7, wherein said diffusion prevention layer contains at least one of silicon and carbon.
9. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 7, further comprising an adhesion layer containing at least one of silicon and carbon between said first insulating layer and said diffusion prevention layer.
10. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 9, wherein said adhesion layer is substantially made of silane compound layer.
11. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 10, wherein said silane compound layer is a monomolecular layer containing an amino group.
12. Ultra-Large Scale Integrated (ULSI) wiring comprising a first insulating interlayer having at least one of trench and via formed on the surface of the first insulating layer, a diffusion prevention layer formed above an inner surface of the at least one of trench and via with a space therein, a wiring layer formed in the space of the diffusion prevention layer, a capping layer formed directly on the wiring layer and the diffusion protecting layer, and a second insulating layer covered over the capping layer,
wherein at least one of the diffusion prevention layer and the capping layer is made of a plating film selected from the group consisting of a nickel-tungsten-phosphorus plating film, a nickel-rhenium-phosphorus plating film, a nickel-boron film, a cobalt-tungsten-phosphorus film, a cobalt-tungsten-boron film, and a cobalt metal film.
13. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 12, wherein said diffusion prevention layer contains at least one of silicon and carbon.
14. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 12, further comprising an adhesion layer containing at least one of silicon and carbon between said first insulating layer and said diffusion prevention layer.
15. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 14, wherein said adhesion layer is substantially made of silane compound layer.
16. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 15, wherein said adhesion layer contains carbon more than silicon in an amount.
17. Ultra-Large Scale Integrated (ULSI) wiring as claimed in claim 12, wherein said silane compound layer is a monomolecular layer containing an amino group.
US10/694,172 2001-05-28 2003-10-28 ULSI wiring and method of manufacturing the same Abandoned US20040126548A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2001158513 2001-05-28
JP2001-158513 2001-05-28
JP2001277602A JP3654354B2 (en) 2001-05-28 2001-09-13 Ultra lsi wiring board and its manufacturing method
JP2001-277602 2001-09-13
US10/154,812 US20030008075A1 (en) 2001-05-28 2002-05-28 ULSI wiring and method of manufacturing the same
US10/694,172 US20040126548A1 (en) 2001-05-28 2003-10-28 ULSI wiring and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/694,172 US20040126548A1 (en) 2001-05-28 2003-10-28 ULSI wiring and method of manufacturing the same
US12/565,448 US8784931B2 (en) 2001-05-28 2009-09-23 ULSI wiring and method of manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/154,812 Continuation-In-Part US20030008075A1 (en) 2001-05-28 2002-05-28 ULSI wiring and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/565,448 Division US8784931B2 (en) 2001-05-28 2009-09-23 ULSI wiring and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20040126548A1 true US20040126548A1 (en) 2004-07-01

Family

ID=46300227

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/694,172 Abandoned US20040126548A1 (en) 2001-05-28 2003-10-28 ULSI wiring and method of manufacturing the same
US12/565,448 Active 2022-08-16 US8784931B2 (en) 2001-05-28 2009-09-23 ULSI wiring and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/565,448 Active 2022-08-16 US8784931B2 (en) 2001-05-28 2009-09-23 ULSI wiring and method of manufacturing the same

Country Status (1)

Country Link
US (2) US20040126548A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040108136A1 (en) * 2002-12-04 2004-06-10 International Business Machines Corporation Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel
US20040238960A1 (en) * 2003-05-29 2004-12-02 Lsi Logic Corporation Interconnect integration
US20080079154A1 (en) * 2006-09-29 2008-04-03 Waseda University Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof
US20080217617A1 (en) * 2005-07-05 2008-09-11 Zeon Corporation Thin Film Transistor, Wiring Board and Methods of Manufacturing the Same
US20090004851A1 (en) * 2007-06-29 2009-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Salicidation process using electroless plating to deposit metal and introduce dopant impurities
US7784531B1 (en) * 2004-04-13 2010-08-31 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Nanoengineered thermal materials based on carbon nanotube array composites
US8241948B2 (en) 2005-06-30 2012-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US20140009875A1 (en) * 2012-07-03 2014-01-09 Seiko Epson Corporation Base substrate, electronic device, and electronic apparatus
US9847355B2 (en) 2002-05-17 2017-12-19 Semiconductor Energy Laboratory Co., Ltd. Silicon nitride film, and semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1978128A2 (en) * 2007-03-29 2008-10-08 Ebara Corporation Electroless plating bath and method for producing high-temperature apparatus member using the bath
WO2010108116A1 (en) * 2009-03-20 2010-09-23 Antares Pharma, Inc. Hazardous agent injection system

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3485597A (en) * 1964-10-30 1969-12-23 Us Army Electroless deposition of nickel-phosphorus based alloys
US4424805A (en) * 1978-04-10 1984-01-10 Neary Michael P Solar energy system and method of use
US4503131A (en) * 1982-01-18 1985-03-05 Richardson Chemical Company Electrical contact materials
US4636255A (en) * 1984-05-24 1987-01-13 Aisin Seiki Kabushiki Kaisha Electroless plating bath for forming a nickel alloy coating having a high phosphorus content
US4990462A (en) * 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5235139A (en) * 1990-09-12 1993-08-10 Macdermid, Incorprated Method for fabricating printed circuits
US5330088A (en) * 1993-04-30 1994-07-19 Eaton Corporation Electrical contact containing a braze diffusion barrier
US5357808A (en) * 1991-03-28 1994-10-25 The Foxboro Company Overpressure-protected, differential pressure sensor
US5369309A (en) * 1991-10-30 1994-11-29 Harris Corporation Analog-to-digital converter and method of fabrication
US5821158A (en) * 1995-08-28 1998-10-13 Nec Corporation Substrate surface treatment method capable of removing a spontaneous oxide film at a relatively low temperature
US6060176A (en) * 1995-11-30 2000-05-09 International Business Machines Corporation Corrosion protection for metallic features
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US6180523B1 (en) * 1998-10-13 2001-01-30 Industrial Technology Research Institute Copper metallization of USLI by electroless process
US6184061B1 (en) * 1998-04-24 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Electrode of semiconductor device, method of manufacturing thereof, and the semicondutor device
US6335104B1 (en) * 2000-02-22 2002-01-01 International Business Machines Corporation Method for preparing a conductive pad for electrical connection and conductive pad formed
US6344309B2 (en) * 1998-10-22 2002-02-05 Shin-Etsu Chemical Co., Ltd. Polysilane composition for forming a coating suitable for bearing a metal pattern, metal pattern forming method, wiring board preparing method
US6479384B2 (en) * 2000-02-18 2002-11-12 Sony Corporation Process for fabricating a semiconductor device
US20030124255A1 (en) * 2001-05-28 2003-07-03 Nec Corporation ULSI wiring and method of manufacturing the same
US20050056828A1 (en) * 2002-07-02 2005-03-17 Masaru Wada Semiconductor device and method for manufacturing same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473950A (en) * 1967-07-25 1969-10-21 Owens Corning Fiberglass Corp High strength fibrous glass
US3949141A (en) * 1974-05-06 1976-04-06 Owens-Corning Fiberglas Corporation Fiber reinforced elastomers
DE2847298C2 (en) * 1978-10-27 1989-10-05 Schering Ag, 1000 Berlin Und 4709 Bergkamen, De
JP2866486B2 (en) 1991-03-26 1999-03-08 学校法人早稲田大学 Electroless Ni-Re-P alloy thin-film resistor
US6156413A (en) * 1996-10-25 2000-12-05 Canon Kabushiki Kaisha Glass circuit substrate and fabrication method thereof
JP2001020077A (en) * 1999-07-07 2001-01-23 Sony Corp Electroless plating method and electroless plating liquid
JP2001323381A (en) 2000-05-16 2001-11-22 Sony Corp Plating method and plated structure
EP1182709A1 (en) * 2000-08-14 2002-02-27 Bp Solar Limited A process for depositing metal contacts on a buried grid solar cell and a solar cell obtained by the process

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3485597A (en) * 1964-10-30 1969-12-23 Us Army Electroless deposition of nickel-phosphorus based alloys
US4424805A (en) * 1978-04-10 1984-01-10 Neary Michael P Solar energy system and method of use
US4503131A (en) * 1982-01-18 1985-03-05 Richardson Chemical Company Electrical contact materials
US4636255A (en) * 1984-05-24 1987-01-13 Aisin Seiki Kabushiki Kaisha Electroless plating bath for forming a nickel alloy coating having a high phosphorus content
US4990462A (en) * 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5235139A (en) * 1990-09-12 1993-08-10 Macdermid, Incorprated Method for fabricating printed circuits
US5357808A (en) * 1991-03-28 1994-10-25 The Foxboro Company Overpressure-protected, differential pressure sensor
US5369309A (en) * 1991-10-30 1994-11-29 Harris Corporation Analog-to-digital converter and method of fabrication
US5330088A (en) * 1993-04-30 1994-07-19 Eaton Corporation Electrical contact containing a braze diffusion barrier
US5821158A (en) * 1995-08-28 1998-10-13 Nec Corporation Substrate surface treatment method capable of removing a spontaneous oxide film at a relatively low temperature
US6060176A (en) * 1995-11-30 2000-05-09 International Business Machines Corporation Corrosion protection for metallic features
US6184061B1 (en) * 1998-04-24 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Electrode of semiconductor device, method of manufacturing thereof, and the semicondutor device
US6180523B1 (en) * 1998-10-13 2001-01-30 Industrial Technology Research Institute Copper metallization of USLI by electroless process
US6344309B2 (en) * 1998-10-22 2002-02-05 Shin-Etsu Chemical Co., Ltd. Polysilane composition for forming a coating suitable for bearing a metal pattern, metal pattern forming method, wiring board preparing method
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US6479384B2 (en) * 2000-02-18 2002-11-12 Sony Corporation Process for fabricating a semiconductor device
US6335104B1 (en) * 2000-02-22 2002-01-01 International Business Machines Corporation Method for preparing a conductive pad for electrical connection and conductive pad formed
US20030124255A1 (en) * 2001-05-28 2003-07-03 Nec Corporation ULSI wiring and method of manufacturing the same
US20030124263A1 (en) * 2001-05-28 2003-07-03 Nec Corporation ULSI wiring and method of manufacturing the same
US20050056828A1 (en) * 2002-07-02 2005-03-17 Masaru Wada Semiconductor device and method for manufacturing same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9847355B2 (en) 2002-05-17 2017-12-19 Semiconductor Energy Laboratory Co., Ltd. Silicon nitride film, and semiconductor device
US20040108136A1 (en) * 2002-12-04 2004-06-10 International Business Machines Corporation Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel
US20080237053A1 (en) * 2002-12-04 2008-10-02 International Business Machines Corporation Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel
US20040238960A1 (en) * 2003-05-29 2004-12-02 Lsi Logic Corporation Interconnect integration
US7784531B1 (en) * 2004-04-13 2010-08-31 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Nanoengineered thermal materials based on carbon nanotube array composites
US8241948B2 (en) 2005-06-30 2012-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US8558227B2 (en) 2005-06-30 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US20080217617A1 (en) * 2005-07-05 2008-09-11 Zeon Corporation Thin Film Transistor, Wiring Board and Methods of Manufacturing the Same
US7547972B2 (en) 2006-09-29 2009-06-16 Waseda University Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof
US20080079154A1 (en) * 2006-09-29 2008-04-03 Waseda University Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof
US20090004851A1 (en) * 2007-06-29 2009-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Salicidation process using electroless plating to deposit metal and introduce dopant impurities
US20140009875A1 (en) * 2012-07-03 2014-01-09 Seiko Epson Corporation Base substrate, electronic device, and electronic apparatus

Also Published As

Publication number Publication date
US8784931B2 (en) 2014-07-22
US20100006326A1 (en) 2010-01-14

Similar Documents

Publication Publication Date Title
US5917244A (en) Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel containing conductor layer
US4154877A (en) Electroless deposition of gold
US6605549B2 (en) Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US20010011638A1 (en) Method of forming a metal seed layer for subsequent plating
US6638410B2 (en) Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US20020094673A1 (en) Method for making interconnects and diffusion barriers in integrated circuits
US6528409B1 (en) Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US7659203B2 (en) Electroless deposition process on a silicon contact
US20040084773A1 (en) Forming a copper diffusion barrier
US7405154B2 (en) Structure and method of forming electrodeposited contacts
US8241701B2 (en) Processes and systems for engineering a barrier surface for copper deposition
US20020123220A1 (en) Method for forming Co-W-P-Au films
Shacham-Diamand et al. High aspect ratio quarter-micron electroless copper integrated technology: Invited lecture
US6660625B2 (en) Method of electroless plating copper on nitride barrier
US7135098B2 (en) Copper interconnect seed layer treatment methods and apparatuses for treating the same
EP1451858B1 (en) Interconnects with improved barrier layer adhesion
US7728436B2 (en) Method for selective deposition of a thin self-assembled monolayer
US6958547B2 (en) Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
US20070099422A1 (en) Process for electroless copper deposition
JP3979791B2 (en) Semiconductor device and manufacturing method thereof
US6962873B1 (en) Nitridation of electrolessly deposited cobalt
US20070108404A1 (en) Method of selectively depositing a thin film material at a semiconductor interface
US6878632B2 (en) Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof
US5674787A (en) Selective electroless copper deposited interconnect plugs for ULSI applications
US6624070B2 (en) Plating catalysts

Legal Events

Date Code Title Description
AS Assignment

Owner name: WASEDA UNIVERSITY, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:014951/0987

Effective date: 20031209

Owner name: NEC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:014951/0987

Effective date: 20031209

AS Assignment

Owner name: WASEDA UNIVERSITY, JAPAN

Free format text: CORRECTED ASSIGNMENT TO CORRECT THE ADDRESS OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 014951 FRAME 0987;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:015967/0172

Effective date: 20031209

Owner name: NEC CORPORATION, JAPAN

Free format text: CORRECTED ASSIGNMENT TO CORRECT THE ADDRESS OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 014951 FRAME 0987;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:015967/0172

Effective date: 20031209

AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNEE'S ADDRESSES PREVIOUSLY ON REEL 014951, FRAME 0987;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:016292/0379

Effective date: 20031209

Owner name: WASEDA UNIVERSITY, JAPAN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNEE'S ADDRESSES PREVIOUSLY ON REEL 014951, FRAME 0987;ASSIGNORS:UENO, KAZUYOSHI;OSAKA, TETSUYA;TAKANO, NAO;REEL/FRAME:016292/0379

Effective date: 20031209

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION