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US20040100302A1 - Adaptive algorithm for electrical fuse programming - Google Patents

Adaptive algorithm for electrical fuse programming Download PDF

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Publication number
US20040100302A1
US20040100302A1 US10301986 US30198602A US2004100302A1 US 20040100302 A1 US20040100302 A1 US 20040100302A1 US 10301986 US10301986 US 10301986 US 30198602 A US30198602 A US 30198602A US 2004100302 A1 US2004100302 A1 US 2004100302A1
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Prior art keywords
efuse
programming
array
data
state
Prior art date
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US10301986
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US6747481B1 (en )
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Robert Pitts
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Texas Instruments Inc
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Texas Instruments Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18Auxiliary circuits, e.g. for writing into memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

Description

    TECHNICAL FIELD OF THE INVENTION
  • [0001]
    The technical field of this invention is integrated circuit programming by selective activation of electrical fuses.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Programmable devices have made a great impact on integrated circuit devices. The possibility of programming a device to do a specific task efficiently has made modest cost ‘special purpose processors’ a reality. Programmable devices are available from a wide variety manufacturers having mass production capability for the parent device. Programmation most often depends on a reliable methodology for ‘customizing’ a device in a repeatable, non-complex manner. ‘Fusing’ of the connections within the programmable logic is the most common process of programmation. Many fusible interconnect links are constructed of materials such as doped polysilicon.
  • [0003]
    These electrical fuses (eFuses) in VLSI silicon devices have been programmed conventionally by applying a large amount of power to the fuse body to melt and separate the fuse body material. This changes the fuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: unblown or blown. As process technology has progressed to smaller and smaller geometry the maximum operating voltages have also scaled downward, making it more difficult to get massive power to the eFuses. Also, it is always desirable to minimize the amount of current the programming operation requires so that metallization power buses that deliver the current to the eFuses do not have to be large.
  • [0004]
    One of the common difficulties encountered in programming eFuses in sub-nanometer technologies for example, where there are significant voltage limitations, is that of providing enough power to reliably blow the fuse in a single programming pulse. It has been shown that multiple programming pulses may be employed to achieve the desired resistance.
  • [0005]
    eFuse Implementation
  • [0006]
    The eFuse for a conventional programmable device application is normally configured as a linear array or two dimensional array containing sometimes hundreds of eFuses and supporting logic. Several definitions will be helpful in clarifying the descriptions of eFuse implementation to follow.
  • [0007]
    1. The ‘eFuse’ itself is a circuit element, which has a natural un-programmed state, but may be permanently programmed to the opposite state.
  • [0008]
    2. An ‘eFuse element’ is comprised of an eFuse along with its programming and sensing circuits.
  • [0009]
    3. An ‘eFuse cell’ is comprised of an eFuse element plus the local logic required to integrate it into an eFuse array.
  • [0010]
    4. An ‘eFuse array’ is a collection of one or more eFuse cells connected in series or arrays. An eFuse controller is comprised of the control logic designed to access the eFuse arrays.
  • [0011]
    5. An un-programmed eFuse is defined as having a pre-defined maximum ‘low’ resistance value.
  • [0012]
    6. A programmed eFuse is defined as having a pre-defined minimum ‘high’ resistance value.
  • [0013]
    The eFuse array is programmed by loading the desired ‘fused state’ and ‘non-fused state’ locations into a ‘programming database’ containing a record for the individual elements of the entire array. Then programming those values into each eFuse sequentially can commence.
  • [0014]
    Because several pulses may be required to successfully blow eFuses, a normal approach is to experiment with applying the eFuse programming data set to program the desired eFuses in a array multiple times to attempt to increase the yield. Due to the physical properties of the fuse body four possible results are observed, two desirable and two undesirable.
  • [0015]
    Desired Result Possibilities
  • [0016]
    1. The eFuse was not desired to be programmed and it stayed low resistance after completion of the programming process.
  • [0017]
    2. The eFuse blew to an acceptable high value of resistance after the pulses were applied.
  • [0018]
    Undesired Result Possibilities
  • [0019]
    3. The eFuse blew to an acceptably high resistance after some of the pulses, but degraded after the completion of all of the pulses, and the resistance had become lower than acceptable.
  • [0020]
    4. The eFuse never blew to an acceptably high resistance, and caused the programming process to incur yield loss.
  • [0021]
    Case 3 above represents a most significant problem area, which can be mitigated by a special programming algorithm, the focus of this invention. Putting a high enough electrical field across a blown eFuse can cause it to heat the body enough to allow the material to re-melt and grow back creating an unacceptably lower resistance. Good eFuses can in this manner become bad after successive programming pulses. The focus of this invention is a solution to the problem of fuses growing back into an un-fused condition.
  • [0022]
    [0022]FIG. 1 illustrates the conventional eFuse cell circuit configuration, which is comprised of an eFuse element 101 plus the local logic required to integrate it into an eFuse array. This logic includes a CData flip-flop 103 that is clocked by the Enable Clock 108 and stores cell data in the array and a PData flip-flop 102 that is clocked by the Data Clock 106 and latches program data being passed into the eFuse cell.
  • [0023]
    In the ‘program’ mode, incoming PData In 107 is latched into the PData flip-flop 102 and programmed into the eFuse element on the occurrence of one or more program pulses initiated at Program input 110. PData passes to the eFuse cell via path 115. In the ‘program’ mode also, PData Out is passed through multiplexers 104 and 105 and is latched into the CData flip-flop 102. VPP 109 is the input for the programming power source. Program data is passed serially to the next cell in the array at PData Out line 115.
  • [0024]
    In the ‘test’ mode, the CData flip-flop latches the data from the present cell and passes it to Cell Data Out 116. This data from the present cell is passed through multiplexer 104 and multiplexer 105 as directed by the Test input 111.
  • [0025]
    Initz input 112 acts to initialize all flip-flops in the cell array prior to the programming cycle. Margin input 114 allows adjustment to the reference input for a differential amplifier so that the desired ‘high’ resistance values for a program element may be modified.
  • [0026]
    [0026]FIG. 2 illustrates a simplified view of a conventional eFuse system having an eFuse controller 200, a number of series-connected eFuse cells represented at the input and output ends of the array by 201 and 210 Each cell 201 and 210 have the local logic of FIG. 1 for integrating the cells into an eFuse array. At the last stage of the array 210 PData Out 208 and CData Out 209 are passed back to the controller as required in the ‘program’ and ‘test’ modes.
  • SUMMARY OF THE INVENTION
  • [0027]
    This invention describes a means for preventing the opportunity for eFuses to become lower resistance due to successive programming pulses after being successfully blown by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become lower resistance.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0028]
    These and other aspects of this invention are illustrated in the drawings, in which:
  • [0029]
    [0029]FIG. 1 illustrates the conventional eFuse cell circuit configuration, which is comprised of an eFuse element plus the local logic required to integrate it into an eFuse array (Prior Art);
  • [0030]
    [0030]FIG. 2 illustrates a simple conventional eFuse system having an effuse controller and a number of series-connected eFuse cells integrated into an eFuse array (Prior Art); and
  • [0031]
    [0031]FIG. 3 illustrates the flow chart for the adaptive algorithm eFuse programming method described in this invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0032]
    The solution to preventing eFuses from growing back by the time the complete set of pulses had been applied was solved by developing an adaptive programming algorithm for blowing the eFuses. The adaptive algorithm works as illustrated in the flow chart of FIG. 3. Also a description of the individual process steps follows with references to FIG. 3.
  • [0033]
    Main Sequence
  • [0034]
    1. Determine the data to be programmed into the eFuse array. Read desired programmation data into database. [301]
  • [0035]
    2. Load the array with the desired data [302] and apply a program pulse to the appropriate eFuses desired to be blown [303]
  • [0036]
    3. Read and determine the result on the eFuses, which should have been blown [304].
  • [0037]
    Adaptive Loop
  • [0038]
    4. Perform overall test [305] on array elements and proceed to programming complete [308] {Yes, results are correct} or proceed return loop [306] {No, results are not correct}.
  • [0039]
    5. Regenerate the data [306] to include only eFuses which were supposed to be blown, but which did not successfully blow (this is the adaptive part of the routine). Successfully blown fuses are assigned a ‘0’ input on the next pass, just as the ‘don't-blow’ cells.
  • [0040]
    6. Reapply the ‘load desired data’ 302 and ‘apply programming pulse’ 303 sequence for a prescribed number of times until desired array results are attained
  • [0041]
    In the adaptive algorithm of FIG. 3, once a high enough resistance on a blown eFuse has been attained it will not receive another programming pulse, which could cause it to degrade from the ‘high resistance’ state and become a measurably lower resistance link. This adaptive algorithm has allowed programming yields on eFuse arrays to be maximized.
  • [0042]
    Table 1 illustrates an example of the adaptive eFuse programmation algorithm for a sixteen-element eFuse array. Row 1 of the table shows that the initial values for all eFuses in the array are in a virgin state before programming and thus are all zeros. Row 2 (which matches the desired programmation in Row 8) shows programmation data desired which will be attempted in full on the first pass. A ‘1’ loaded at a given position blows that eFuse. Row 3 shows the results read after the first pass. Four eFuses of the eFuses targeted by a ‘1’ did not blow. Row 4 the programmation data for the second pass, modified to blow only those four eFuses not successfully blown on the first pass. Row 5 shows the results read after the second pass. Two eFuses of those targeted by a ‘1’ in the second pass did not blow. Row 6 shows the programmation data for the third pass, modified to blow only those two eFuses not successfully blown on the second pass. Row 7 shows the results read after the third pass. All eFuses of those targeted by a ‘1’ in the original programmation data are now blown. Thus the programmation data for each pass and the results on the state of the eFuse array after each pass is shown in successive pairs of rows in the table. The desired state, successfully achieved on the third pass, is shown on row 8 at the bottom of the table.
    TABLE 1
    Read Values of Each eFuse in the Array
    eFuse Array State Programmation Data
    Read Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    Values
    Fuse blow 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 0
    data (first pass)
    Read eFuse array 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0
    (first pass)
    Fuse blow data 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0
    (second pass)
    Read eFuse array 0 0 1 0 0 1 0 1 1 1 0 0 1 1 1 0
    (second pass)
    Fuse blow data 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0
    (third pass)
    Read eFuse array 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 0
    (third pass)
    Desired eFuse 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 0
    array state
  • [0043]
    The advantages of this solution to the programming process may be summarized as follows. The adaptive programming algorithm:
  • [0044]
    1. Is able to achieve the highest programming yield (percentage of correctly programmed devices);
  • [0045]
    2. May allow the use of lower voltages for programming, which reduces reliability concerns in the eFuse implementation;
  • [0046]
    3. May allow the use of lower currents for programming, which reduces the power bus width requirements and results in a Silicon area savings; and
  • [0047]
    4. May reduce required test time and thereby lowers programming cost.
  • [0048]
    Future applications for the adaptive programming algorithm include its use in newer technologies as they are introduced. Other possibilities include yield enhancement in advent of the introduction of newer eFuse body composition. The eFuse body is not limited to polysilicon. Programmable contacts or metallization methodologies could also be used and this algorithm would still be applicable. However, efforts to improve eFuse programming yields using new composition approaches may have more and more limitations as voltages continue to decline. The method of this invention is also easily extended to programming of ‘anti-fuses’, which are high resistance in the un-programmed state and ‘low’ resistance in the programmed state.

Claims (4)

    What is claimed is:
  1. 1. A method of programming electrical fuses comprising the steps of:
    reading the desired data for a array of fuses to be programmed from a programmation source;
    programming the array of fuses by applying a programmation pulse to fuses where a corresponding bit of the desired data has a first digital state, and applying no programmation pulse to fuses where a corresponding bit in the desired data has a second digital state; and
    repeating the sequence of
    reading the programmation of the fuses,
    programming the array of fuses by applying a programmation pulse to fuses where a corresponding bit of the desired data has a first digital state and the read state of the fuse fails to match the corresponding bit of the desired state, applying no programmation pulse to fuses where a corresponding bit in the desired data has a second digital state, and applying no programmation pulse to fuses where a corresponding bit of the desired data has a first digital state and the read state of the fuse fails to match the corresponding bit of the desired state,
    until all fuses match the corresponding bit of the desired state.
  2. 2. The method of claim 1 wherein:
    all electrical fuses initially have a low resistance and some fuses after programmation have a desired state of a high resistance.
  3. 3. The method of claim 1 wherein:
    all electrical fuses initially have a high resistance and some fuses after programmation have a desired state of a low resistance.
  4. 4. The method of claim 1 wherein:
    said step of programming the array of fuses includes arranging input programmation data where data bits representing fuses in desired state have a second digital state and data bits representing fuses not in the desired state have a first digital state, and applying a programming pulse only to fuses having data of the first digital state and no programming pulse to fuses having the second digital state.
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EP20030104325 EP1437743A3 (en) 2002-11-22 2003-11-21 Adaptive algorithm for electrical fuse programming

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834659B1 (en) * 2008-03-05 2010-11-16 Xilinx, Inc. Multi-step programming of E fuse cells
US20110047892A1 (en) * 2009-08-25 2011-03-03 Martin Engineering Company Roof Edge Cable Raceway and Method of Forming Same
US9556973B2 (en) 2009-08-25 2017-01-31 Hot Edge, LLC System securing a cable to a roof

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3881641B2 (en) * 2003-08-08 2007-02-14 株式会社東芝 Fuse circuit
US7162825B2 (en) * 2004-05-18 2007-01-16 Calculations Made Simple Method and means for adjusting the scope of a firearm
US7308598B2 (en) * 2004-11-04 2007-12-11 International Business Machines Corporation Algorithm to encode and compress array redundancy data
US7295057B2 (en) * 2005-01-18 2007-11-13 International Business Machines Corporation Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit
US7624080B1 (en) 2005-02-25 2009-11-24 The United States Of America As Represented By The Secretary Of The Navy Smart sensor continuously adapting to a data stream in real time using both permanent and temporary knowledge bases to recognize sensor measurements
US7373573B2 (en) * 2005-06-06 2008-05-13 International Business Machines Corporation Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing
US7759226B1 (en) 2005-08-30 2010-07-20 Altera Corporation Electrical fuse with sacrificial contact
US7345943B2 (en) * 2006-06-28 2008-03-18 International Business Machines Corporation Unclocked eFUSE circuit
KR100729368B1 (en) * 2006-06-30 2007-06-11 삼성전자주식회사 Apparatus for electrical fuse option in semiconductor integrated circuit
KR100827664B1 (en) * 2006-12-26 2008-05-07 삼성전자주식회사 Electrical fuse, semiconductor device having the same, and programming and reading method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367207A (en) * 1990-12-04 1994-11-22 Xilinx, Inc. Structure and method for programming antifuses in an integrated circuit array
US5544070A (en) * 1991-07-31 1996-08-06 Quicklogic Corporation Programmed programmable device and method for programming antifuses of a programmable device
US6188242B1 (en) * 1999-06-30 2001-02-13 Quicklogic Corporation Virtual programmable device and method of programming
US6339559B1 (en) * 2001-02-12 2002-01-15 International Business Machines Corporation Decode scheme for programming antifuses arranged in banks

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748535A (en) * 1994-10-26 1998-05-05 Macronix International Co., Ltd. Advanced program verify for page mode flash memory
GB2314953B (en) * 1996-06-29 2000-07-05 Hyundai Electronics Ind Program circuit
JP2002217295A (en) * 2001-01-12 2002-08-02 Toshiba Corp Semiconductor device
US6373771B1 (en) * 2001-01-17 2002-04-16 International Business Machines Corporation Integrated fuse latch and shift register for efficient programming and fuse readout

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367207A (en) * 1990-12-04 1994-11-22 Xilinx, Inc. Structure and method for programming antifuses in an integrated circuit array
US5544070A (en) * 1991-07-31 1996-08-06 Quicklogic Corporation Programmed programmable device and method for programming antifuses of a programmable device
US6188242B1 (en) * 1999-06-30 2001-02-13 Quicklogic Corporation Virtual programmable device and method of programming
US6339559B1 (en) * 2001-02-12 2002-01-15 International Business Machines Corporation Decode scheme for programming antifuses arranged in banks

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834659B1 (en) * 2008-03-05 2010-11-16 Xilinx, Inc. Multi-step programming of E fuse cells
US20110047892A1 (en) * 2009-08-25 2011-03-03 Martin Engineering Company Roof Edge Cable Raceway and Method of Forming Same
US9556973B2 (en) 2009-08-25 2017-01-31 Hot Edge, LLC System securing a cable to a roof

Also Published As

Publication number Publication date Type
EP1437743A3 (en) 2009-03-11 application
EP1437743A2 (en) 2004-07-14 application
US6747481B1 (en) 2004-06-08 grant
JP2004185613A (en) 2004-07-02 application

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