US20030113987A1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- US20030113987A1 US20030113987A1 US10/141,922 US14192202A US2003113987A1 US 20030113987 A1 US20030113987 A1 US 20030113987A1 US 14192202 A US14192202 A US 14192202A US 2003113987 A1 US2003113987 A1 US 2003113987A1
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- film
- gate electrode
- polysilicon film
- insulating film
- polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
Definitions
- the present invention relates to a method of manufacturing a semiconductor device provided with a fine gate electrode.
- FIGS. 3A to 3 E a conventional method of manufacturing a semiconductor device is briefly described.
- FIGS. 3A to 3 E are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode.
- a gate insulating film 2 is formed on a silicon substrate 1 .
- a polysilicon film 3 is formed on the gate electrode 2 . It will be noted here that part of the thus formed polysilicon film 3 becomes a gate electrode in a subsequent step.
- a photoresist 4 is applied onto the polysilicon film 3 .
- a desired resist pattern 4 a is formed on the polysilicon film 3 according to photolithography.
- an exposed portion of the polysilicon film 3 which is not covered with the resist pattern 4 a , is etched via a mask of the resist pattern 4 a . Moreover, the resist pattern 4 a is removed to form a polysilicon film 3 a serving as a gate electrode on the gate insulating film 2 .
- the scale down of the gate electrode relies on the resolution in a lithographic technique. More particularly, the gate length of the gate electrode becomes substantially same as the line width of the resist pattern formed according to the photolithography. This entails that a possible minimum gate length depends just on the resolution of an exposure equipment used in the photolithography.
- the resolution of an exposure equipment is proportional to a wavelength of light from a light source.
- it is essential to use an exposure equipment having a shorter wavelength light source. Nevertheless, certain limitation is placed on the realization of such a shorter wavelength of a light source, so that it has been difficult to form a fine gate electrode at a level below resolution.
- a gate insulating film, a first polysilicon film, a nitride film and a second polysilicon film are successively formed on a semiconductor substrate, followed by forming a pattern of the second polysilicon according to photolithography. Thereafter, the second polysilicon pattern is thermally oxidized on the surface thereof, and the resulting thermal oxidization film is removed to form a finer second polysilicon film.
- the method of manufacturing a semiconductor device as stated hereinabove has the problem that although a fine gate electrode can be formed irrespective of the resolution of photolithography, a number of the manufacturing steps are used and complicated.
- the present invention is provided in order to solve the above-stated problem and contemplates to provide a method of manufacturing a semiconductor device wherein a fine gate electrode can be relatively simply formed without resorting to the resolution in a photolithographic technique.
- the method comprises these steps below.
- a gate insulating film is formed on a substrate, a polysilicon film is formed on the gate insulating film, a resist pattern is formed on the polysilicon film and subsequently an exposed portion of the polysilicon film which is not covered with the resist pattern is removed.
- the surface of the polysilicon film left after the step of removing the exposed portion of the polysilicon film is thermally oxidized to simultaneously form a gate electrode and an insulating film on the surface of the gate electrode.
- the insulating film on the surface of the gate electrode may be formed with a hole at part thereof.
- the method comprises these steps below.
- a gate insulating film is formed on a substrate, a polysilicon film is formed on the gate insulating film, and a nitride film is formed on the polysilicon film.
- a resist pattern is formed on the nitride film and subsequently an exposed portion of the nitride film which is not covered with the resist pattern is removed, thereby forming a nitride film pattern.
- the exposed portion of the polysilicon film which is not covered with the nitride film pattern is removed.
- the surface of the polysilicon film left after the step of removing the exposed portion of the polysilicon film is thermally oxidized to simultaneously form a gate electrode and an insulating film on side surfaces of the gate electrode.
- a silicide is formed on the upper surface of the gate electrode through the insulating film on side surfaces on the gate electrode used as a mask.
- FIGS. 1A to 1 F are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the first embodiment of the invention
- FIGS. 2A to 2 J are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the second embodiment of the invention.
- FIGS. 3A to 3 E are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a conventional method of manufacturing a semiconductor device.
- FIGS. 1A to 1 F are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the first embodiment of the invention.
- a gate insulating film is formed on a silicon substrate 1 .
- the gate insulating film 2 has a thickness, for example, of 3 nm.
- a polysilicon film 3 is formed on the gate insulating film 2 according to a CVD method. It will be noted that part of the polysilicon film 3 becomes a gate electrode in a subsequent step, with the thickness thereof being, for example, at 20 nm.
- a photoresist film 4 is applied onto the polysilicon film 3 .
- a desired resist pattern 4 a is formed by photolithography.
- an exposed portion of the polysilicon film 3 which is not covered with the resist pattern 4 a , is removed by dry etching through the resist pattern 4 a used as a mask.
- a polysilicon film 3 a is formed as a polysilicon pattern.
- the resist pattern 4 a on the polysilicon film 3 a is removed by ashing.
- the polysilicon film 3 a is thermally oxidized to form a thermal oxide film 5 as an insulating film on the surfaces of the polysilicon pattern (including an upper surface and side surfaces of the polysilicon film 3 a ).
- the inside of the polysilicon pattern does not undergo any thermal oxidation and remains as a polysilicon film 3 b .
- This polysilicon film 3 b serves as a gate electrode.
- the gate electrode 3 b and the insulating film 5 surrounding the electrode are simultaneously formed by the thermal oxidation treatment of the polysilicon film 3 a .
- the polysilicon film 3 b serving as the gate electrode has a width (gate length) which is more reduced by twice the thickness of the thermal oxide film 5 than a width of the polysilicon film 3 a prior to the step of the thermal oxidation treatment.
- the insulating films made of the thermal oxide film 5 and the gate insulating film 2 are formed on the silicon substrate 1 . More particularly, the thermal oxide film 5 serving as an insulating film is not removed in subsequent steps and left, as it is, as an insulating film in the semiconductor device. In other words, according to the method of manufacturing a semiconductor device in the first embodiment of the invention, to leave the thermal oxide film 5 as an insulating film permits a subsequent insulating film-forming step to be omitted.
- the thermal oxide film 5 is formed with a hole at a part of the upper surface thereof so that a part at the upper surface of the polysilicon film 3 b is exposed. Moreover, a plug such as tungsten is formed in the hole. In this way, a transistor of the semiconductor device is formed. It will be noted that the source/drain regions of the transistor are neither particularly shown nor illustrated.
- a fine gate electrode can be formed according to a relatively small number of steps without resorting to the resolution in the photolithographic technique.
- FIGS. 2A to 2 J are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the second embodiment of the invention.
- a gate insulating film 2 is formed on a silicon substrate 1 .
- the thickness of the gate insulating film 2 is, for example, at 3 nm.
- a polysilicon film 3 is formed on the gate insulating film 2 according to a CVD method. It will be noted that part of this polysilicon film 3 becomes a gate electrode in a subsequent step, with the film thickness being, for example, at 20 nm.
- a nitride film is formed on the polysilicon film 3 according to a CVD method.
- the thickness of the nitride film is, for example, at 15 nm.
- a photoresist film 4 is coated onto the nitride film 6 .
- a desired resist pattern 4 a is formed according to photolithography.
- an exposed portion of the nitride film 6 which is not covered with the resist pattern 4 a , is removed by drying etching through a mask of the resist pattern 4 a .
- a nitride film pattern 6 a is formed.
- the resist pattern 4 a on the nitride film pattern 6 a is removed.
- an exposed portion of the polysilicon film 3 which is not covered with the resist pattern 4 a , is removed by dry etching through the resist pattern 6 a used as a mask. In this way, a polysilicon film 3 a is formed as a polysilicon pattern.
- the polysilicon film 3 a is thermally oxidized thereby forming a thermal oxide film 5 , as an insulating film, on the exposed surfaces of the polysilicon pattern (i.e. the side surfaces of the polysilicon film 3 a ).
- the inside of the polysilicon pattern is left as a polysilicon film 3 b , like the above-stated first embodiment, and this polysilicon film 3 b serves as a gate electrode.
- the gate electrode 3 b and the insulating film 5 on the side surfaces of the gate electrode are simultaneously formed through the thermal oxidation treatment of the polysilicon film 3 a.
- a metal film 7 such as cobalt is formed on an exposed surface of each of the gate insulating film 2 , polysilicon film 3 b and thermal oxide film 5 .
- the metal film 7 has a thickness, for example, of 7 nm.
- annealing is carried out, whereupon a silicide 7 a is formed only at a contact portion between the metal film 7 and the polysilicon film 3 b through a mask of the thermal oxide film 5 .
- the other portion of the metal film 7 where no silicide 7 a is formed is removed as shown in FIG. 2J.
- the silicide 7 a formed with the metal film can be selectively formed on the polysilicon film 3 b serving as a fine gate electrode. It will be noted that the silicide 7 a lowers the resistance of the gate electrode thereby improving the performance of a transistor.
- the silicon substrate 1 is formed thereon with the insulating film made of the thermal oxide film 5 and the gate insulating film 2 except for the upper surface of the gate electrode. More particularly, the thermal oxide film 5 formed on the side surfaces of the polysilicon film 3 b serving as an insulating film is left, as it is, as an insulating film in subsequent steps without removal thereof. Moreover, the thermal oxide film 5 formed on the side surfaces of the polysilicon film 3 b serves as a mask, enabling the formation of the silicide 7 a on the upper surface of the polysilicon film 3 b.
- an insulating film is formed on the upper surface of the silicide 7 a or over the entire region of the silicon substrate 1 including the upper surface of the silicide 7 a . Thereafter, the insulating film on the silicide 7 a is formed with a hole in part thereof according to photolithography so that part of the upper surface of the silicide 7 a is exposed. A plug is formed in the hole.
- a fine, low resistance gate electrode can be formed by a relatively small number of steps without resorting to the resolution in a photolithographic technique, like the foregoing first embodiment.
- the invention is so arranged as described hereinbefore and can provide a method of manufacturing a semiconductor device wherein a fine gate electrode can be relatively simply formed without resorting to the resolution in a photolithography.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method of manufacturing a semiconductor device provided with a fine gate electrode.
- 2. Background Art
- In recent years, in order to attain a high degree of integration of a semiconductor device, there is an increasing demand of forming a fine gate electrode of a transistor serving as a semiconductor element.
- In FIGS. 3A to3E, a conventional method of manufacturing a semiconductor device is briefly described. FIGS. 3A to 3E are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode.
- Initially, as shown in FIG. 3A, a
gate insulating film 2 is formed on asilicon substrate 1. - Next, as shown in FIG. 3B, a
polysilicon film 3 is formed on thegate electrode 2. It will be noted here that part of the thus formedpolysilicon film 3 becomes a gate electrode in a subsequent step. - Thereafter, as shown in FIG. 3C, a
photoresist 4 is applied onto thepolysilicon film 3. - As shown in FIG. 3D, a desired
resist pattern 4 a is formed on thepolysilicon film 3 according to photolithography. - Next, as shown in FIG. 3E, an exposed portion of the
polysilicon film 3, which is not covered with theresist pattern 4 a, is etched via a mask of theresist pattern 4 a. Moreover, theresist pattern 4 a is removed to form apolysilicon film 3 a serving as a gate electrode on thegate insulating film 2. - In the above-stated conventional method of manufacturing a semiconductor device, the scale down of the gate electrode relies on the resolution in a lithographic technique. More particularly, the gate length of the gate electrode becomes substantially same as the line width of the resist pattern formed according to the photolithography. This entails that a possible minimum gate length depends just on the resolution of an exposure equipment used in the photolithography.
- The resolution of an exposure equipment is proportional to a wavelength of light from a light source. Hence, for further scale down of the gate electrode, it is essential to use an exposure equipment having a shorter wavelength light source. Nevertheless, certain limitation is placed on the realization of such a shorter wavelength of a light source, so that it has been difficult to form a fine gate electrode at a level below resolution.
- To solve the above problem, the following technique is disclosed, for example, in JP-A No. 2001-237420. More particularly, a gate insulating film, a first polysilicon film, a nitride film and a second polysilicon film are successively formed on a semiconductor substrate, followed by forming a pattern of the second polysilicon according to photolithography. Thereafter, the second polysilicon pattern is thermally oxidized on the surface thereof, and the resulting thermal oxidization film is removed to form a finer second polysilicon film.
- Thereafter, using the fine second polysilicon pattern as a mask, an exposed portion of the underlying nitride film is removed. The exposed portion of the first silicon film and the fine second polysilicon pattern are both removed via a mask of a remaining nitride film, thereby forming a gate electrode made of the fine first polysilicon film.
- The method of manufacturing a semiconductor device as stated hereinabove has the problem that although a fine gate electrode can be formed irrespective of the resolution of photolithography, a number of the manufacturing steps are used and complicated.
- The present invention is provided in order to solve the above-stated problem and contemplates to provide a method of manufacturing a semiconductor device wherein a fine gate electrode can be relatively simply formed without resorting to the resolution in a photolithographic technique.
- In one embodiment of the present invention, the method comprises these steps below. A gate insulating film is formed on a substrate, a polysilicon film is formed on the gate insulating film, a resist pattern is formed on the polysilicon film and subsequently an exposed portion of the polysilicon film which is not covered with the resist pattern is removed. Subsequently, the surface of the polysilicon film left after the step of removing the exposed portion of the polysilicon film is thermally oxidized to simultaneously form a gate electrode and an insulating film on the surface of the gate electrode. After the step of simultaneously forming the gate electrode and the insulating film on the surface of the gate electrode, the insulating film on the surface of the gate electrode may be formed with a hole at part thereof.
- In another embodiment of the present invention, the method comprises these steps below. A gate insulating film is formed on a substrate, a polysilicon film is formed on the gate insulating film, and a nitride film is formed on the polysilicon film. Next a resist pattern is formed on the nitride film and subsequently an exposed portion of the nitride film which is not covered with the resist pattern is removed, thereby forming a nitride film pattern. Next the exposed portion of the polysilicon film which is not covered with the nitride film pattern is removed. The surface of the polysilicon film left after the step of removing the exposed portion of the polysilicon film is thermally oxidized to simultaneously form a gate electrode and an insulating film on side surfaces of the gate electrode. A silicide is formed on the upper surface of the gate electrode through the insulating film on side surfaces on the gate electrode used as a mask.
- Other and further objects, features and advantages of the invention will appear more fully from the following description.
- The present invention will be more apparent from the following detailed description, when taken in conjunction with the accompanying drawings, in which;
- FIGS. 1A to1F are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the first embodiment of the invention;
- FIGS. 2A to2J are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the second embodiment of the invention;
- FIGS. 3A to3E are schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a conventional method of manufacturing a semiconductor device.
- Embodiments of the invention will be described in detail with reference to the accompanying drawings. It will be noted in the figures, the same reference numerals indicate the same members or portions and the repetition of their explanation may be appropriately simplified or may be omitted.
- In FIGS. 1A to1F, a first embodiment of the invention will be described in detail. FIGS. 1A to 1F are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the first embodiment of the invention.
- As shown in FIG. 1A, a gate insulating film is formed on a
silicon substrate 1. Thegate insulating film 2 has a thickness, for example, of 3 nm. - Next, as shown in FIG. 1B, a
polysilicon film 3 is formed on thegate insulating film 2 according to a CVD method. It will be noted that part of thepolysilicon film 3 becomes a gate electrode in a subsequent step, with the thickness thereof being, for example, at 20 nm. - Thereafter, as shown in FIG. 1C, a
photoresist film 4 is applied onto thepolysilicon film 3. - Further, as shown in FIG. 1D, a desired resist
pattern 4 a is formed by photolithography. - Next, as shown in FIG. 1E, an exposed portion of the
polysilicon film 3, which is not covered with the resistpattern 4 a, is removed by dry etching through the resistpattern 4 a used as a mask. In this way, apolysilicon film 3 a is formed as a polysilicon pattern. Moreover, the resistpattern 4 a on thepolysilicon film 3 a is removed by ashing. - As shown in FIG. 1F, the
polysilicon film 3 a is thermally oxidized to form athermal oxide film 5 as an insulating film on the surfaces of the polysilicon pattern (including an upper surface and side surfaces of thepolysilicon film 3 a). At this stage, the inside of the polysilicon pattern does not undergo any thermal oxidation and remains as apolysilicon film 3 b. Thispolysilicon film 3 b serves as a gate electrode. - More particularly, in the first embodiment of the invention, the
gate electrode 3 b and the insulatingfilm 5 surrounding the electrode are simultaneously formed by the thermal oxidation treatment of thepolysilicon film 3 a. Thepolysilicon film 3 b serving as the gate electrode has a width (gate length) which is more reduced by twice the thickness of thethermal oxide film 5 than a width of thepolysilicon film 3 a prior to the step of the thermal oxidation treatment. - As stated hereinabove, the insulating films made of the
thermal oxide film 5 and thegate insulating film 2 are formed on thesilicon substrate 1. More particularly, thethermal oxide film 5 serving as an insulating film is not removed in subsequent steps and left, as it is, as an insulating film in the semiconductor device. In other words, according to the method of manufacturing a semiconductor device in the first embodiment of the invention, to leave thethermal oxide film 5 as an insulating film permits a subsequent insulating film-forming step to be omitted. - Although not shown in the figures, after the steps described above, the
thermal oxide film 5 is formed with a hole at a part of the upper surface thereof so that a part at the upper surface of thepolysilicon film 3 b is exposed. Moreover, a plug such as tungsten is formed in the hole. In this way, a transistor of the semiconductor device is formed. It will be noted that the source/drain regions of the transistor are neither particularly shown nor illustrated. - As set forth hereinabove, in the method of manufacturing the semiconductor device in the first embodiment of the invention, a fine gate electrode can be formed according to a relatively small number of steps without resorting to the resolution in the photolithographic technique.
- Second Embodiment
- With reference to FIGS. 2A to2J, the second embodiment of the invention will be described in detail. FIGS. 2A to 2J are, respectively, schematic sectional views showing a semiconductor device in the respective steps of forming a gate electrode in a method of manufacturing the semiconductor device according to the second embodiment of the invention.
- Initially, as shown in FIG. 2A, a
gate insulating film 2 is formed on asilicon substrate 1. The thickness of thegate insulating film 2 is, for example, at 3 nm. - Next, as shown in FIG. 2B, a
polysilicon film 3 is formed on thegate insulating film 2 according to a CVD method. It will be noted that part of thispolysilicon film 3 becomes a gate electrode in a subsequent step, with the film thickness being, for example, at 20 nm. - As shown in FIG. 2C, a nitride film is formed on the
polysilicon film 3 according to a CVD method. The thickness of the nitride film is, for example, at 15 nm. - Thereafter, as shown in FIG. 2D, a
photoresist film 4 is coated onto thenitride film 6. - As shown in FIG. 2E, a desired resist
pattern 4 a is formed according to photolithography. - Next, as shown in FIG. 2F, an exposed portion of the
nitride film 6, which is not covered with the resistpattern 4 a, is removed by drying etching through a mask of the resistpattern 4 a. As a result, anitride film pattern 6 a is formed. Moreover, the resistpattern 4 a on thenitride film pattern 6 a is removed. - Next, as shown in FIG. 2G, an exposed portion of the
polysilicon film 3, which is not covered with the resistpattern 4 a, is removed by dry etching through the resistpattern 6 a used as a mask. In this way, apolysilicon film 3 a is formed as a polysilicon pattern. - As shown in FIG. 2H, the
polysilicon film 3 a is thermally oxidized thereby forming athermal oxide film 5, as an insulating film, on the exposed surfaces of the polysilicon pattern (i.e. the side surfaces of thepolysilicon film 3 a). At this stage, the inside of the polysilicon pattern is left as apolysilicon film 3 b, like the above-stated first embodiment, and thispolysilicon film 3 b serves as a gate electrode. - More particularly, in the second embodiment, the
gate electrode 3 b and the insulatingfilm 5 on the side surfaces of the gate electrode are simultaneously formed through the thermal oxidation treatment of thepolysilicon film 3 a. - Next, as shown in FIG. 2I, after removal of the
nitride film pattern 6 a on thepolysilicon film 3 b, ametal film 7 such as cobalt is formed on an exposed surface of each of thegate insulating film 2,polysilicon film 3 b andthermal oxide film 5. Themetal film 7 has a thickness, for example, of 7 nm. - Thereafter, annealing is carried out, whereupon a
silicide 7 a is formed only at a contact portion between themetal film 7 and thepolysilicon film 3 b through a mask of thethermal oxide film 5. At the same time, the other portion of themetal film 7 where nosilicide 7 a is formed is removed as shown in FIG. 2J. - In this manner, the
silicide 7 a formed with the metal film can be selectively formed on thepolysilicon film 3 b serving as a fine gate electrode. It will be noted that thesilicide 7 a lowers the resistance of the gate electrode thereby improving the performance of a transistor. - As stated hereinabove, the
silicon substrate 1 is formed thereon with the insulating film made of thethermal oxide film 5 and thegate insulating film 2 except for the upper surface of the gate electrode. More particularly, thethermal oxide film 5 formed on the side surfaces of thepolysilicon film 3 b serving as an insulating film is left, as it is, as an insulating film in subsequent steps without removal thereof. Moreover, thethermal oxide film 5 formed on the side surfaces of thepolysilicon film 3 b serves as a mask, enabling the formation of thesilicide 7 a on the upper surface of thepolysilicon film 3 b. - Although not shown, after the above step, an insulating film is formed on the upper surface of the
silicide 7 a or over the entire region of thesilicon substrate 1 including the upper surface of thesilicide 7 a. Thereafter, the insulating film on thesilicide 7 a is formed with a hole in part thereof according to photolithography so that part of the upper surface of thesilicide 7 a is exposed. A plug is formed in the hole. - As set forth hereinabove, according to the method of manufacturing a semiconductor device in the second embodiment of the invention, a fine, low resistance gate electrode can be formed by a relatively small number of steps without resorting to the resolution in a photolithographic technique, like the foregoing first embodiment.
- It should be noted that the invention should not be construed as limited to these embodiments and appropriate variations and alterations of the embodiments may be possible within the spirit of the technical concept of the invention except those suggested in the embodiments. The number, position, shape and the like of constituting members are not limited to those indicated in the embodiments, but such a number, position and shape may be appropriately determined from the standpoint of carrying out the invention.
- The invention is so arranged as described hereinbefore and can provide a method of manufacturing a semiconductor device wherein a fine gate electrode can be relatively simply formed without resorting to the resolution in a photolithography.
- The entire disclosure of a Japanese Patent Application No. 2001-0383490, filed on Dec. 17, 2001 including specification, claims drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001-383490 | 2001-12-17 | ||
JP2001383490A JP2003188371A (en) | 2001-12-17 | 2001-12-17 | Method of manufacturing semiconductor device and semiconductor device |
Publications (2)
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US20030113987A1 true US20030113987A1 (en) | 2003-06-19 |
US6583036B1 US6583036B1 (en) | 2003-06-24 |
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US10/141,922 Expired - Fee Related US6583036B1 (en) | 2001-12-17 | 2002-05-10 | Method of manufacturing a semiconductor device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070049030A1 (en) * | 2005-09-01 | 2007-03-01 | Sandhu Gurtej S | Pitch multiplication spacers and methods of forming the same |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100575449B1 (en) * | 2004-05-10 | 2006-05-03 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
KR100583609B1 (en) * | 2004-07-05 | 2006-05-26 | 삼성전자주식회사 | Method of manufacturing a gate structure in a semiconductor device and method of manufacturing a cell gate structure in non-volatile memory device using the same |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH07118522B2 (en) * | 1990-10-24 | 1995-12-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Method and semiconductor structure for oxidizing a substrate surface |
KR100275544B1 (en) * | 1995-12-20 | 2001-01-15 | 이계철 | Method for manufacturing super self-aligned bipolar transistor using selective collector growth |
TW332915B (en) * | 1997-06-24 | 1998-06-01 | Ti Acer Co Ltd | The producing method for shallow trench isolation with global planarization |
JPH1145995A (en) * | 1997-07-25 | 1999-02-16 | Nec Kyushu Ltd | Semiconductor device and manufacture thereof |
KR100275540B1 (en) * | 1997-09-23 | 2000-12-15 | 정선종 | Super self-aligned bipolar transistor and its fabrication method |
JP3425581B2 (en) | 2000-02-24 | 2003-07-14 | Necエレクトロニクス株式会社 | Method for forming gate electrode of semiconductor device |
-
2001
- 2001-12-17 JP JP2001383490A patent/JP2003188371A/en not_active Withdrawn
-
2002
- 2002-05-10 US US10/141,922 patent/US6583036B1/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070049030A1 (en) * | 2005-09-01 | 2007-03-01 | Sandhu Gurtej S | Pitch multiplication spacers and methods of forming the same |
KR100967740B1 (en) * | 2005-09-01 | 2010-07-05 | 마이크론 테크놀로지, 인크. | Mask patterns with spacers for pitch multiplication and methods of forming the same |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US20100267240A1 (en) * | 2005-09-01 | 2010-10-21 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US9099314B2 (en) | 2005-09-01 | 2015-08-04 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
Also Published As
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US6583036B1 (en) | 2003-06-24 |
JP2003188371A (en) | 2003-07-04 |
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