US20030105907A1 - System and method for caching DRAM using an egress buffer - Google Patents

System and method for caching DRAM using an egress buffer Download PDF

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Publication number
US20030105907A1
US20030105907A1 US10/273,829 US27382902A US2003105907A1 US 20030105907 A1 US20030105907 A1 US 20030105907A1 US 27382902 A US27382902 A US 27382902A US 2003105907 A1 US2003105907 A1 US 2003105907A1
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data
egress
processor
bus
server
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Leslie Kohn
Michael Wong
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Sun Microsystems Inc
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Sun Microsystems Inc
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Abstract

A system and method includes a server that includes a processor and a memory system coupled that are coupled to a bus system. A network interface is coupled to the processor and an egress buffer is coupled to the processor and the network interface by an egress bus.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims priority from U.S. Provisional Patent Application No. 60/345,315 filed on Oct. 22, 2001 and entitled “High Performance Web Server,” which is incorporated herein by reference in its entirety for all purposes.[0001]
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates generally to microprocessors, and more particularly, to methods and systems for microprocessors to serve data from memory systems. [0003]
  • 2. Description of the Related Art [0004]
  • A typical server computer, such as a web server, has one main memory. A server serves data from the memory to a client computer that requested the data. FIG. 1 shows a typical web server [0005] 102 and client computer 110 that are linked by a network 104, such as the Internet or other network. FIG. 2 is a high-level block diagram of a typical web server 102. As shown, the web server 102 includes a processor 202, a memory system 203 that includes a ROM 204, a main memory DRAM 206 and a mass storage device 210, each connected by a peripheral bus system 208. The peripheral bus system 208 may include one or more buses connected to each other through various bridges, controllers and/or adapters, such as are well known in the art. For example, the peripheral bus system 208 may include a “system bus” that is connected through an adapter to one or more expansion buses, such as a Peripheral Component Interconnect (PCI) bus. Also coupled to the peripheral bus system 208 are a network interface 212, a number (N) of input/output (I/O) devices 216-1 through 216-N and a peripheral cryptographic processor 220. 141 I/O devices 216-1 through 216-N may include, for example, a keyboard, a pointing device, a display device and/or other conventional I/O devices. Mass storage device 210 may include any suitable device for storing large volumes of data, such as a magnetic disk or tape, magneto-optical (MO) storage device, or any of various types of Digital Versatile Disk (DVD) or Compact Disk (CD) based storage.
  • Network interface [0006] 212 provides data communication between the computer system and other computer systems on the network 104. Hence, network interface 212 may be any device suitable for or enabling the web server 102 to communicate data with a remote processing system (e.g., client computer 110) over a data communication link, such as a conventional telephone modem, an Integrated Services Digital Network (ISDN) adapter, a Digital Subscriber Line (DSL) adapter, a cable modem, a satellite transceiver, an Ethernet adapter, or the like. 161 The web server 102 typically processes large quantities of data, for example, streaming data such as streaming video or streaming audio or other types of data or serving a website and other web data. FIG. 3 is a flowchart of the method operations 300 of the web server 102 serving a large volume of data such as a 10 MB data stream. In operation 305, the web server 102 receives a request for the 10 MB data stream from the client 110. If the 10 MB data stream required processing such as being encrypted, then the 10 MB data stream must first be retrieved from the DRAM 206 into the processor 202. In operation 310, the data stream is retrieved from the DRAM 206 and/or other portions of the memory system 203.
  • In operation [0007] 315, the data stream is processed in the processor 202. In operation 320, the processed data stream is stored in the DRAM 206. In operation 325, the data stream is served through the network interface 212 to the network 104 to the client 110.
  • The processed data stream must be stored in the memory system [0008] 203 because the processor 202 and the network interface 212 typically have different data processing rates. By way of example, the processor 202 can process data at a rate of about 2 GHz or even greater. The peripheral bus system 208 typically operates at about 166 MHz, therefore the network interface 212 typically does not operates as fast as 2 GHz and cannot serve the data as fast as the processor can process the data. As a result the processed data must be temporarily stored in the memory system 203 so that the network interface 212 can serve the processed data at the optimal rate for the network interface 212. Alternatively, the network interface 212 may be able to output data faster than the processor can process the data, therefore, the processed data can be built up in the memory system 203 and the network interface 203 can serve the data from the memory system 203 at a high rate.
  • Now, as described in FIG. 3 above, the 10 MB data stream must transfer across the peripheral bus system [0009] 208 between the DRAM 206 and the processor 202 three times. Therefore, a 10 MB data stream being served results in a 30 MB data stream flowing between the DRAM 206 and the processor 202. These multiple passes between the DRAM 206 and the processor 202 consume large portion of the total I/O bandwidth of the processor 202 I/O which can limit the ability of the processor 202 to perform other operations besides serving the 10 MB data stream.
  • What is needed is a system and method to reduce the bandwidth usage of the processor to memory system interface. [0010]
  • SUMMARY OF THE INVENTION
  • Broadly speaking, the present invention fills these needs by providing a system method for caching DRAM to reduce the bandwidth usage of the processor to memory system interface. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below. [0011]
  • One embodiment includes a server that includes a processor and a memory system coupled that are coupled to a bus system. A network interface is coupled to the processor and an egress buffer is coupled to the processor and the network interface by an egress bus. [0012]
  • The processor can also include multiple processors. The multiple processors can be included on a first die or chip. Alternatively, the multiple processors can be included on multiple separate dies or chips. [0013]
  • The egress buffer can include a high-speed random access memory. In one embodiment, the egress buffer includes random access memory that has an operating speed of about 400 MHz. [0014]
  • The egress buffer and the egress bus can have a data throughput rate that is greater than or equal to about twice the amount of a data stream to be served. [0015]
  • The egress buffer can also include a double data rate buffer. [0016]
  • The egress buffer can also include a double data rate buffer. [0017]
  • The egress bus has a bandwidth that is greater than or equal to about twice the amount of a data stream to be served. The egress bus can also include a 32-bit data bus. [0018]
  • One embodiment includes a system and method of serving data that includes receiving a request for data in a processor in a server. The requested data is retrieved. The retrieved data is processed in the processor. The processed data is stored in an egress buffer that is coupled to the processor and a network interface. The stored data is served from the egress buffer through the network interface. [0019]
  • The egress buffer is coupled to the processor and the network interface by an egress bus. [0020]
  • The requested data can include a data stream. [0021]
  • The egress bus has a bandwidth of about twice a bandwidth of the data stream. [0022]
  • The egress bus can include a 32-bit data bus. [0023]
  • The processed data can be stored in the egress buffer substantially simultaneously with the stored data being served from the egress buffer. [0024]
  • Processing the retrieved data in the processor can also include formatting the data, encrypting the data, and decrypting the data among other processes. [0025]
  • Another embodiment includes a system and method of serving a data stream that includes receiving a request for a data stream in a processor in a server. The requested data stream is retrieved. The retrieved data stream is processed in the processor. The processed data stream is stored in an egress buffer that is coupled to the processor and a network interface by an egress bus. The egress bus has a bandwidth that is greater than or equal to about twice the data stream. The stored data stream is served from the egress buffer through the network interface. The data stream can include audio or video or any other streaming media. [0026]
  • Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. [0027]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements. [0028]
  • FIG. 1 shows a typical web server and client computer that are linked by a network, such as the Internet or other network. [0029]
  • FIG. 2 is a high-level block diagram of a typical web server. [0030]
  • FIG. 3 is a flowchart of the method operations of the web server serving a large volume of data such as a 10 MB data stream. [0031]
  • FIG. 4 shows a block diagram of a server in accordance with one embodiment of the present invention. [0032]
  • FIG. 5 is a flow chart of the method operations of serving data using an egress buffer in accordance with one embodiment of the present invention. [0033]
  • FIG. 6 shows a block diagram of a processor according to one embodiment of the present invention. [0034]
  • DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
  • Several exemplary embodiments for caching DRAM to reduce the bandwidth usage of the processor to memory system interface will now be described. It will be apparent to those skilled in the art that the present invention may be practiced without some or all of the specific details set forth herein. [0035]
  • One embodiment of the present invention includes an egress buffer that can be used to temporarily store processed data from the processor that will be served by the network interface. The egress buffer thereby reduces the demand on the bandwidth usage of the processor to memory system interface by about two-thirds. [0036]
  • FIG. 4 shows a block diagram of a server [0037] 400 in accordance with one embodiment of the present invention. The server 400 can be a web server or other type of server. The server 400 includes a bus system 408 that couples a processor 402 and a memory system 404. The processor 402 includes at least one processor core 402A. The server 400 also includes an egress buffer 420 that is coupled to the processor 402 and a network interface 412.
  • The egress buffer [0038] 420 is coupled to the processor 402 and the network interface 412 via a dedicated egress bus 422. The egress bus 422 can be as wide as necessary, for example, the egress bus 422 can be 32-bits (i.e., lines) wide but the egress bus 422 could be narrower or wider such as 16-bits or 64-bits. The egress buffer 420 can be large enough to buffer the desired data throughput of the network interface 412 as will be described in more detail below. Referring to the above example of a 10 gigabit data throughput, the egress buffer 420 would need to be 32 megabytes or possibly larger.
  • In one embodiment, the egress buffer [0039] 420 includes a very high-speed ram such as a fast cycle time RAM (FCRAM) that operates as fast as about 400 MHz or more. The FCRAM allows the egress buffer 420 to serve the data across the egress bus 422 to the network interface 412 at the speed of the network interface 412.
  • In one embodiment, the server [0040] 400 can include multiple processors on multiple processor chips or dies. The egress bus 422 can also couple a single egress buffer 420 to all of the multiple processors. An egress bus controller can be included to manage the data flow between the multiple processors and the egress buffer 420.
  • FIG. 5 is a flow chart of the method operations [0041] 500 of serving data using an egress buffer in accordance with one embodiment of the present invention. In operation 505, a request for data is received in the server 400. The request can be from an application within the server 400 or due to a request received from an external data requester, such as a client computer 110 in FIG. 1 that is linked to the server 400 by a network.
  • The processor [0042] 402 retrieves the requested data, in operation 510. The data can be retrieved from numerous sources such as from the memory system 404 or other sources via the system data bus 408. In operation 515, the processor 402 processes the retrieved data such as packetizing the data or performing some other formatting, encryption, decryption, or other processing to the retrieved data.
  • The processed data is stored in the egress buffer [0043] 420 via the egress bus 422, in operation 520. In operation 525, the network interface 412, 412′ retrieves the processed data from the egress buffer 420, via the egress bus 422 and serves the data to the data requestor.
  • FIG. 6 shows a block diagram of a processor [0044] 402′ according to one embodiment of the present invention. The processor 402′ includes a processor core 402A′ and an integrated network interface 412′. Because the integrated network interface 412′ is included on the processor die 402′ with the processor core 402A′, the network interface 412′ can output data faster than the network interface 412 described in FIG. 4 above.
  • In one embodiment, a dedicated bus [0045] 422A couples the processor core 402A′ to the egress bus 422, through a process data switch 430. The process data switch 430 is also coupled to the network interface 412′ via a bus 422B. Alternatively, the network interface 412′ can be coupled to the egress buffer 420 by a separate, dedicated bus. The process data switch 430 directs the data from the processor core 402A′ to the egress buffer 420 or the memory system 404 and controls the data flow across the egress bus 422 so that the data flows either to the network interface 412′ or from the processor core 402A′.
  • In alternative embodiments, the egress bus [0046] 422 can also link other components on the processor die to the egress buffer 420.
  • In one embodiment, the egress buffer [0047] 420 is an about 400 MHz, double data rate (DDR) buffer. When combined with a 32-bit wide egress bus 422, a 400 MHz DDR buffer produces 800 MHz×32-bit wide egress bus 422 to produce 3.2 GB per second throughput with a relatively small actual buffer of only two or four bits per 32 bit lines of the egress bus 422. 3.2 GB per second throughput of the egress bus 422 and egress buffer 420 equates to slightly more than 24 gigabits per second. A 24 gigabit per second egress buffer 420 can support two 10-gigabit-per-second data streams: A first 10 gigabit data stream is input to the egress buffer 420 while a second 10 gigabit data stream output from the egress buffer 420 to the network interface 412, 412′. The speed of the egress buffer 420 memory must be sufficient to support the network interface 412, 412′ data demand rate.
  • The egress buffer [0048] 420
  • Because the egress buffer [0049] 420 is coupled to the processor core 402A′ by the dedicated egress bus 422, the egress bus 422 can deliver the data much quicker than a shared data bus such as the I/O interface 432 between the memory system 404 and the processor core 402A′. Further, because the egress buffer 420 uses much higher speed type RAM (e.g., FCRAM), the egress buffer 420 can serve the data faster than standard DRAM.
  • The egress buffer [0050] 420 can also substantially smooth out the data interface between the data processing rate of the processor core 402A and the rate the network interface 412 can serve the data. Often the difference in processing rates (i.e., the transient variation) can vary as the processor performs other operations or the network is busy and reduces the rate the network interface 412 can serve the data. The amount of transient variation increases as the size of the egress buffer 420 increases.
  • The egress buffer [0051] 420 FCRAM can operate in any range from about 100 MHz or even slower to about 400 MHz or greater. The higher speed of the egress buffer 420, the greater the efficiency of the processor serving the data to the network interface. Alternatively, lower speed egress buffer 420 FCRAM would also increase the efficiency by reducing the demand across the system bus 408 and specifically across the interface between the memory system 404 and the processor 402.
  • The egress buffer [0052] 420 could be within a single die or chip with the processor 402. However, typically the egress buffer 420 would not be part of the processor die because of the physical size of the memory is relatively large as compared to the size of the microprocessor devices in the processor 402 and therefore including the egress buffer is not an efficient use of the space on processor die.
  • The network interface [0053] 412, 412′ can have any bandwidth such as about a 4 gigabit per second or about a 10 gigabit per second. The network interface 412, 412′ has direct access to the egress buffer 420 via the dedicated egress bus 422.
  • As used herein the term “about” means +/−10%. By way of example, the phrase “about 250” indicates a range of between 225 and 275. [0054]
  • With the above embodiments in mind, it should be understood that the invention might employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. [0055]
  • Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purposes, or it may be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations. [0056]
  • The invention can also be embodied as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. [0057]
  • It will be further appreciated that the instructions represented by the operations in FIG. 5 are not required to be performed in the order illustrated, and that all the processing represented by the operations may not be necessary to practice the invention. Further, the processes described in FIG. 5 can also be implemented in software stored in any one of or combinations of the RAM, the ROM, or the hard disk drive. [0058]
  • Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. [0059]

Claims (19)

What is claimed is:
1. A server comprising:
a processor coupled to a bus system;
a memory system coupled to the bus system;
a network interface coupled to the processor; and
an egress buffer coupled to the processor and the network interface by an egress bus.
2. The server of claim 1, wherein the processor includes a plurality of processors.
3. The server of claim 2, wherein the plurality of processors are included on a first die.
4. The server of claim 2, wherein the plurality of processors are included on a plurality of dies.
5. The server of claim 1, wherein the egress buffer includes high speed random access memory.
6. The server of claim 1, wherein the egress buffer includes random access memory that has an operating speed of about 400 MHz.
7. The server of claim 1, wherein the egress buffer and the egress bus have a data throughput rate that is greater than or equal to about twice the amount of a data stream to be served.
8. The server of claim 1, wherein the egress buffer includes a double data rate buffer.
9. The server of claim 1, wherein the egress bus has a bandwidth that is greater than or equal to about twice the amount of a data stream to be served.
10. The server of claim 1, wherein the egress bus includes a 32-bit data bus.
11. A method of serving data comprising:
receiving a request for data in a processor in a server;
retrieving the requested data;
processing the retrieved data in the processor;
storing the processed data in an egress buffer that is coupled to the processor and a network interface; and
serving the stored data from the egress buffer through the network interface.
12. The method of claim 11, wherein the egress buffer that is coupled to the processor and the network interface by an egress bus.
13. The method of claim 11, wherein the requested data includes a data stream.
14. The method of claim 13, wherein the egress bus has a bandwidth of about twice a bandwidth of the data stream.
15. The method of claim 13, wherein the egress bus includes a 32-bit data bus.
16. The method of claim 11, wherein the processed data is stored in the egress buffer substantially simultaneously with the stored data being served from the egress buffer.
17. The method of claim 11, wherein processing the retrieved data in the processor includes at least one of a group consisting of formatting the data, encrypting the data, and decrypting the data.
18. A method of serving a data stream comprising:
receiving a request for a data stream in a processor in a server;
retrieving the requested data stream;
processing the retrieved data stream in the processor;
storing the processed data stream in an egress buffer that is coupled to the processor and a network interface by an egress bus having a bandwidth that is greater than or equal to about twice the data stream; and
serving the stored data stream from the egress buffer through the network interface.
19. The method of claim 18, wherein the data stream includes at least one of a group consisting of audio and video.
US10/273,829 2001-10-22 2002-10-17 System and method for caching DRAM using an egress buffer Abandoned US20030105907A1 (en)

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US10/272,783 Active 2025-08-22 US7248585B2 (en) 2001-10-22 2002-10-16 Method and apparatus for a packet classifier
US10/272,786 Active 2024-07-24 US7209996B2 (en) 2001-10-22 2002-10-16 Multi-core multi-thread processor
US10/273,829 Abandoned US20030105907A1 (en) 2001-10-22 2002-10-17 System and method for caching DRAM using an egress buffer
US10/273,718 Abandoned US20030084309A1 (en) 2001-10-22 2002-10-18 Stream processor with cryptographic co-processor
US10/273,806 Active 2023-06-18 US6938119B2 (en) 2001-10-22 2002-10-18 DRAM power management
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241457A1 (en) * 1994-12-23 2004-12-02 Saint-Gobain Glass France Glass substrates coated with a stack of thin layers having reflective properties in the infra-red and/or solar ranges
US20060009265A1 (en) * 2004-06-30 2006-01-12 Clapper Edward O Communication blackout feature
US20060136915A1 (en) * 2004-12-17 2006-06-22 Sun Microsystems, Inc. Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline
US20060161760A1 (en) * 2004-12-30 2006-07-20 Sun Microsystems, Inc. Multiple contexts for efficient use of translation lookaside buffer
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US7509484B1 (en) 2004-06-30 2009-03-24 Sun Microsystems, Inc. Handling cache misses by selectively flushing the pipeline
US7519796B1 (en) 2004-06-30 2009-04-14 Sun Microsystems, Inc. Efficient utilization of a store buffer using counters
US7543132B1 (en) 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US9747132B2 (en) 2013-04-18 2017-08-29 Denso Corporation Multi-core processor using former-stage pipeline portions and latter-stage pipeline portions assigned based on decode results in former-stage pipeline portions

Families Citing this family (342)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7600131B1 (en) 1999-07-08 2009-10-06 Broadcom Corporation Distributed processing in a cryptography acceleration chip
AU4964401A (en) * 2000-03-30 2001-10-15 Penn State Res Found Novel compounds for enhancing chemotherapy
US7013302B2 (en) * 2000-12-22 2006-03-14 Nortel Networks Limited Bit field manipulation
US7529242B1 (en) * 2002-02-15 2009-05-05 Symantec Corporation Routing network packets for multi-processor network flow analysis
US7400722B2 (en) * 2002-03-28 2008-07-15 Broadcom Corporation Methods and apparatus for performing hash operations in a cryptography accelerator
US20050108518A1 (en) * 2003-06-10 2005-05-19 Pandya Ashish A. Runtime adaptable security processor
US7487264B2 (en) * 2002-06-11 2009-02-03 Pandya Ashish A High performance IP processor
US7631107B2 (en) * 2002-06-11 2009-12-08 Pandya Ashish A Runtime adaptable protocol processor
US7685254B2 (en) * 2003-06-10 2010-03-23 Pandya Ashish A Runtime adaptable search processor
US7415723B2 (en) * 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
US20040010781A1 (en) * 2002-07-12 2004-01-15 Maly John Warren Parameter parsing system
US20040103248A1 (en) 2002-10-08 2004-05-27 Hass David T. Advanced telecommunications processor
US7467243B2 (en) * 2002-10-08 2008-12-16 Rmi Corporation Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip
US20050033889A1 (en) * 2002-10-08 2005-02-10 Hass David T. Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip
US8478811B2 (en) * 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US7461215B2 (en) * 2002-10-08 2008-12-02 Rmi Corporation Advanced processor with implementation of memory ordering on a ring based data movement network
US7961723B2 (en) * 2002-10-08 2011-06-14 Netlogic Microsystems, Inc. Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
US7334086B2 (en) * 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US20050033831A1 (en) * 2002-10-08 2005-02-10 Abbas Rashid Advanced processor with a thread aware return address stack optimally used across active threads
US7627721B2 (en) * 2002-10-08 2009-12-01 Rmi Corporation Advanced processor with cache coherency
US7984268B2 (en) * 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US8015567B2 (en) * 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US7346757B2 (en) 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US9088474B2 (en) * 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US7924828B2 (en) * 2002-10-08 2011-04-12 Netlogic Microsystems, Inc. Advanced processor with mechanism for fast packet queuing operations
US8176298B2 (en) * 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US20050044324A1 (en) * 2002-10-08 2005-02-24 Abbas Rashid Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
US7461213B2 (en) 2002-10-08 2008-12-02 Rmi Corporation Advanced processor system using request, data, snoop, and response rings
US8037224B2 (en) * 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US7434043B2 (en) 2002-12-18 2008-10-07 Broadcom Corporation Cryptography accelerator data routing unit
US20040123120A1 (en) * 2002-12-18 2004-06-24 Broadcom Corporation Cryptography accelerator input interface data handling
US20040123123A1 (en) * 2002-12-18 2004-06-24 Buer Mark L. Methods and apparatus for accessing security association information in a cryptography accelerator
US7568110B2 (en) * 2002-12-18 2009-07-28 Broadcom Corporation Cryptography accelerator interface decoupling from cryptography processing cores
US7673118B2 (en) * 2003-02-12 2010-03-02 Swarztrauber Paul N System and method for vector-parallel multiprocessor communication
US7392400B2 (en) 2003-04-18 2008-06-24 Via Technologies, Inc. Microprocessor apparatus and method for optimizing block cipher cryptographic functions
US7529367B2 (en) 2003-04-18 2009-05-05 Via Technologies, Inc. Apparatus and method for performing transparent cipher feedback mode cryptographic functions
US7536560B2 (en) 2003-04-18 2009-05-19 Via Technologies, Inc. Microprocessor apparatus and method for providing configurable cryptographic key size
US7925891B2 (en) 2003-04-18 2011-04-12 Via Technologies, Inc. Apparatus and method for employing cryptographic functions to generate a message digest
US7529368B2 (en) 2003-04-18 2009-05-05 Via Technologies, Inc. Apparatus and method for performing transparent output feedback mode cryptographic functions
US7321910B2 (en) 2003-04-18 2008-01-22 Ip-First, Llc Microprocessor apparatus and method for performing block cipher cryptographic functions
US7844053B2 (en) 2003-04-18 2010-11-30 Ip-First, Llc Microprocessor apparatus and method for performing block cipher cryptographic functions
US7519833B2 (en) 2003-04-18 2009-04-14 Via Technologies, Inc. Microprocessor apparatus and method for enabling configurable data block size in a cryptographic engine
US7900055B2 (en) 2003-04-18 2011-03-01 Via Technologies, Inc. Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms
US8060755B2 (en) 2003-04-18 2011-11-15 Via Technologies, Inc Apparatus and method for providing user-generated key schedule in a microprocessor cryptographic engine
US7539876B2 (en) 2003-04-18 2009-05-26 Via Technologies, Inc. Apparatus and method for generating a cryptographic key schedule in a microprocessor
US7532722B2 (en) 2003-04-18 2009-05-12 Ip-First, Llc Apparatus and method for performing transparent block cipher cryptographic functions
US7542566B2 (en) 2003-04-18 2009-06-02 Ip-First, Llc Apparatus and method for performing transparent cipher block chaining mode cryptographic functions
US7502943B2 (en) 2003-04-18 2009-03-10 Via Technologies, Inc. Microprocessor apparatus and method for providing configurable cryptographic block cipher round results
US7392399B2 (en) * 2003-05-05 2008-06-24 Sun Microsystems, Inc. Methods and systems for efficiently integrating a cryptographic co-processor
US20040230813A1 (en) * 2003-05-12 2004-11-18 International Business Machines Corporation Cryptographic coprocessor on a general purpose microprocessor
CA2467140A1 (en) * 2003-05-12 2004-11-12 Auckland Uniservices Limited An integrity mechanism for file transfer in communications networks
US8266379B2 (en) * 2003-06-02 2012-09-11 Infineon Technologies Ag Multithreaded processor with multiple caches
US8730923B2 (en) * 2003-06-11 2014-05-20 Alcatel Lucent Method for controlling resource allocation in a wireless communication system
JP3761544B2 (en) 2003-06-25 2006-03-29 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Setting device, an information processing apparatus, setting method, a program, and a recording medium
US7996839B2 (en) * 2003-07-16 2011-08-09 Hewlett-Packard Development Company, L.P. Heterogeneous processor core systems for improved throughput
CN100498757C (en) 2003-07-25 2009-06-10 Rmi公司 Advanced processor
US20050044320A1 (en) 2003-08-19 2005-02-24 Sun Microsystems, Inc. Cache bank interface unit
US7873785B2 (en) * 2003-08-19 2011-01-18 Oracle America, Inc. Multi-core multi-thread processor
US8463996B2 (en) 2003-08-19 2013-06-11 Oracle America, Inc. Multi-core multi-thread processor crossbar architecture
US7133950B2 (en) 2003-08-19 2006-11-07 Sun Microsystems, Inc. Request arbitration in multi-core processor
EP1522923A3 (en) * 2003-10-08 2011-06-22 STMicroelectronics SA Simultaneous multi-threaded (SMT) processor architecture
US7536692B2 (en) * 2003-11-06 2009-05-19 Intel Corporation Thread-based engine cache partitioning
US7617241B2 (en) * 2003-11-07 2009-11-10 Rmi Corporation Method and apparatus for enhanced hashing
US8516179B2 (en) * 2003-12-03 2013-08-20 Digital Rna, Llc Integrated circuit with coupled processing cores
US7222299B1 (en) * 2003-12-19 2007-05-22 Google, Inc. Detecting quoted text
US7308558B2 (en) * 2004-01-07 2007-12-11 International Business Machines Corporation Multiprocessor data processing system having scalable data interconnect and data routing mechanism
US7007128B2 (en) * 2004-01-07 2006-02-28 International Business Machines Corporation Multiprocessor data processing system having a data routing mechanism regulated through control communication
US7634655B2 (en) * 2004-02-13 2009-12-15 Microsoft Corporation Efficient hash table protection for data transport protocols
US7564381B1 (en) * 2004-02-16 2009-07-21 Cisco Technology, Inc. System and method for code-based compression in a communications environment
US8028164B2 (en) * 2004-03-19 2011-09-27 Nokia Corporation Practical and secure storage encryption
US7292591B2 (en) 2004-03-30 2007-11-06 Extreme Networks, Inc. Packet processing system architecture and method
US7649879B2 (en) * 2004-03-30 2010-01-19 Extreme Networks, Inc. Pipelined packet processor
US7936687B1 (en) * 2004-03-30 2011-05-03 Extreme Networks, Inc. Systems for statistics gathering and sampling in a packet processing system
US7889750B1 (en) 2004-04-28 2011-02-15 Extreme Networks, Inc. Method of extending default fixed number of processing cycles in pipelined packet processor architecture
KR100594755B1 (en) * 2004-05-11 2006-06-30 삼성전자주식회사 The packet classification method through hierarchial rulebase partitioning
US7480302B2 (en) * 2004-05-11 2009-01-20 Samsung Electronics Co., Ltd. Packet classification method through hierarchical rulebase partitioning
US7418582B1 (en) 2004-05-13 2008-08-26 Sun Microsystems, Inc. Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7664810B2 (en) * 2004-05-14 2010-02-16 Via Technologies, Inc. Microprocessor apparatus and method for modular exponentiation
US20060041715A1 (en) * 2004-05-28 2006-02-23 Chrysos George Z Multiprocessor chip having bidirectional ring interconnect
US7369557B1 (en) * 2004-06-03 2008-05-06 Cisco Technology, Inc. Distribution of flows in a flow-based multi-processor system
US20080263324A1 (en) * 2006-08-10 2008-10-23 Sehat Sutardja Dynamic core switching
US7760719B2 (en) 2004-06-30 2010-07-20 Conexant Systems, Inc. Combined pipelined classification and address search method and apparatus for switching environments
US7492763B1 (en) * 2004-07-16 2009-02-17 Applied Micro Circuits Corporation User-specified key creation from attributes independent of encapsulation type
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7389375B2 (en) * 2004-07-30 2008-06-17 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
US7296129B2 (en) * 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US7681105B1 (en) * 2004-08-09 2010-03-16 Bakbone Software, Inc. Method for lock-free clustered erasure coding and recovery of data across a plurality of data stores in a network
DK1794979T3 (en) * 2004-09-10 2017-07-24 Cavium Inc Selective copying data structure
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US7594081B2 (en) * 2004-09-10 2009-09-22 Cavium Networks, Inc. Direct access to low-latency memory
US9626194B2 (en) 2004-09-23 2017-04-18 Intel Corporation Thread livelock unit
US7748001B2 (en) * 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US7788670B2 (en) * 2004-10-26 2010-08-31 Intel Corporation Performance-based workload scheduling in multi-core architectures
US7395476B2 (en) * 2004-10-29 2008-07-01 International Business Machines Corporation System, method and storage medium for providing a high speed test interface to a memory subsystem
US7277988B2 (en) * 2004-10-29 2007-10-02 International Business Machines Corporation System, method and storage medium for providing data caching and data compression in a memory subsystem
US20060095620A1 (en) * 2004-10-29 2006-05-04 International Business Machines Corporation System, method and storage medium for merging bus data in a memory subsystem
US7305574B2 (en) * 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
US7512762B2 (en) * 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7299313B2 (en) * 2004-10-29 2007-11-20 International Business Machines Corporation System, method and storage medium for a memory subsystem command interface
US7331010B2 (en) * 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7441060B2 (en) * 2004-10-29 2008-10-21 International Business Machines Corporation System, method and storage medium for providing a service interface to a memory system
US7356737B2 (en) * 2004-10-29 2008-04-08 International Business Machines Corporation System, method and storage medium for testing a memory module
US7564847B2 (en) * 2004-12-13 2009-07-21 Intel Corporation Flow assignment
US8473750B2 (en) * 2004-12-15 2013-06-25 Nvidia Corporation Chipset security offload engine
EP1801725B1 (en) * 2005-12-14 2009-09-23 Nvidia Corporation Chipset security offload engine
US7920701B1 (en) 2004-12-15 2011-04-05 Nvidia Corporation System and method for digital content protection
US20060136717A1 (en) 2004-12-20 2006-06-22 Mark Buer System and method for authentication via a proximate device
US8295484B2 (en) * 2004-12-21 2012-10-23 Broadcom Corporation System and method for securing data from a remote input device
US7937709B2 (en) 2004-12-29 2011-05-03 Intel Corporation Synchronizing multiple threads efficiently
US7428619B2 (en) * 2005-01-18 2008-09-23 Sony Computer Entertainment Inc. Methods and apparatus for providing synchronization of shared data
US7421598B2 (en) * 2005-02-09 2008-09-02 International Business Machines Corporation Dynamic power management via DIMM read operation limiter
US7426649B2 (en) * 2005-02-09 2008-09-16 International Business Machines Corporation Power management via DIMM read operation limiter
US7769858B2 (en) * 2005-02-23 2010-08-03 International Business Machines Corporation Method for efficiently hashing packet keys into a firewall connection table
US7443878B2 (en) 2005-04-04 2008-10-28 Sun Microsystems, Inc. System for scaling by parallelizing network workload
WO2006128062A2 (en) * 2005-05-25 2006-11-30 Terracotta, Inc. Database caching of queries and stored procedures using database provided facilities for dependency analysis and detected database updates for invalidation
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7639613B1 (en) * 2005-06-24 2009-12-29 Packeteer, Inc. Adaptive, flow-based network traffic measurement and monitoring system
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8719819B2 (en) 2005-06-30 2014-05-06 Intel Corporation Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US20070005899A1 (en) * 2005-06-30 2007-01-04 Sistla Krishnakanth V Processing multicore evictions in a CMP multiprocessor
US8407432B2 (en) * 2005-06-30 2013-03-26 Intel Corporation Cache coherency sequencing implementation and adaptive LLC access priority control for CMP
CN100458757C (en) 2005-07-28 2009-02-04 大唐移动通信设备有限公司 Communication method and apparatus among cores for multi-core processor in embedded real-time operating system
US20070086456A1 (en) * 2005-08-12 2007-04-19 Electronics And Telecommunications Research Institute Integrated layer frame processing device including variable protocol header
KR101303518B1 (en) * 2005-09-02 2013-09-03 구글 인코포레이티드 Methods and apparatus of stacking drams
GB0519981D0 (en) * 2005-09-30 2005-11-09 Ignios Ltd Scheduling in a multicore architecture
US7159082B1 (en) * 2005-10-03 2007-01-02 Hewlett-Packard Development Company, L.P. System and method for throttling memory accesses
US7984180B2 (en) 2005-10-20 2011-07-19 Solarflare Communications, Inc. Hashing algorithm for network receive filtering
US7478259B2 (en) 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US20070124728A1 (en) * 2005-11-28 2007-05-31 Mark Rosenbluth Passing work between threads
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
WO2007067562A2 (en) * 2005-12-06 2007-06-14 Boston Circuits, Inc. Methods and apparatus for multi-core processing with dedicated thread management
US7750915B1 (en) * 2005-12-19 2010-07-06 Nvidia Corporation Concurrent access of data elements stored across multiple banks in a shared memory resource
US20070168377A1 (en) * 2005-12-29 2007-07-19 Arabella Software Ltd. Method and apparatus for classifying Internet Protocol data packets
US7725624B2 (en) * 2005-12-30 2010-05-25 Intel Corporation System and method for cryptography processing units and multiplier
US7900022B2 (en) * 2005-12-30 2011-03-01 Intel Corporation Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction
US7817633B1 (en) 2005-12-30 2010-10-19 Extreme Networks, Inc. Method of providing virtual router functionality through abstracted virtual identifiers
US7894451B2 (en) * 2005-12-30 2011-02-22 Extreme Networks, Inc. Method of providing virtual router functionality
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
US7822033B1 (en) 2005-12-30 2010-10-26 Extreme Networks, Inc. MAC address detection device for virtual routers
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7774590B2 (en) 2006-03-23 2010-08-10 Intel Corporation Resiliently retaining state information of a many-core processor
US7610330B1 (en) * 2006-03-30 2009-10-27 Packeteer, Inc. Multi-dimensional computation distribution in a packet processing device having multiple processing architecture
CN100407705C (en) * 2006-04-12 2008-07-30 华为技术有限公司 One kind of router control method and system
EP2016718B1 (en) 2006-04-21 2014-02-12 Oracle America, Inc. Method and system for scaling by parallelizing network workload
US7852850B2 (en) * 2006-04-26 2010-12-14 Marvell Israel (M.I.S.L.) Ltd. Double-hash lookup mechanism for searching addresses in a network device
US7865694B2 (en) * 2006-05-12 2011-01-04 International Business Machines Corporation Three-dimensional networking structure
EP1858228A1 (en) * 2006-05-16 2007-11-21 THOMSON Licensing Network data storage system with distributed file management
US7636813B2 (en) * 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
US7594055B2 (en) * 2006-05-24 2009-09-22 International Business Machines Corporation Systems and methods for providing distributed technology independent memory controllers
US7640386B2 (en) * 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
DE102006025133A1 (en) * 2006-05-30 2007-12-06 Infineon Technologies Ag Memory and storage communication system
US7584336B2 (en) * 2006-06-08 2009-09-01 International Business Machines Corporation Systems and methods for providing data modification operations in memory subsystems
US7584286B2 (en) 2006-06-28 2009-09-01 Intel Corporation Flexible and extensible receive side scaling
WO2008005793A2 (en) * 2006-06-30 2008-01-10 Symbol Technologies, Inc. Systems and methods for processing data packets using a multi-core abstraction layer (mcal)
US20080002702A1 (en) * 2006-06-30 2008-01-03 Symbol Technologies, Inc. Systems and methods for processing data packets using a multi-core abstraction layer (MCAL)
US20080002681A1 (en) * 2006-06-30 2008-01-03 Symbol Technologies, Inc. Network wireless/RFID switch architecture for multi-core hardware platforms using a multi-core abstraction layer (MCAL)
KR100724527B1 (en) * 2006-07-11 2007-05-28 이평범 Method for manufacturing of agricultural products powder and the system for manufacturing thereof
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US7493439B2 (en) * 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
US7669086B2 (en) 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7581073B2 (en) * 2006-08-09 2009-08-25 International Business Machines Corporation Systems and methods for providing distributed autonomous power management in a memory system
US7587559B2 (en) * 2006-08-10 2009-09-08 International Business Machines Corporation Systems and methods for memory module power management
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
CN100574277C (en) 2006-09-20 2009-12-23 杭州华三通信技术有限公司 Method and apparatus for global statistics in multi-core system
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8006069B2 (en) * 2006-10-05 2011-08-23 Synopsys, Inc. Inter-processor communication method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
CN100452757C (en) 2006-10-12 2009-01-14 杭州华三通信技术有限公司 Message transferring method and device
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7477522B2 (en) * 2006-10-23 2009-01-13 International Business Machines Corporation High density high reliability memory module with a fault tolerant address and command bus
WO2008050248A2 (en) * 2006-10-27 2008-05-02 Nokia Corporation System and method for improved broadband wireless gateway reliability
US8356361B2 (en) * 2006-11-07 2013-01-15 Spansion Llc Secure co-processing memory controller integrated into an embedded memory subsystem
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7996348B2 (en) 2006-12-08 2011-08-09 Pandya Ashish A 100GBPS security and search architecture using programmable intelligent search memory (PRISM) that comprises one or more bit interval counters
US9141557B2 (en) 2006-12-08 2015-09-22 Ashish A. Pandya Dynamic random access memory (DRAM) that comprises a programmable intelligent search memory (PRISM) and a cryptography processing engine
US7721140B2 (en) * 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7603526B2 (en) * 2007-01-29 2009-10-13 International Business Machines Corporation Systems and methods for providing dynamic memory pre-fetch
CN101043446A (en) * 2007-03-08 2007-09-26 华为技术有限公司 Method and apparatus for data transmission process
US8095782B1 (en) 2007-04-05 2012-01-10 Nvidia Corporation Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change
US7979683B1 (en) * 2007-04-05 2011-07-12 Nvidia Corporation Multiple simultaneous context architecture
AT472476T (en) * 2007-05-11 2010-07-15 Sca Hygiene Prod Ab Packaging and supply device for grouping of product objects
US7840821B2 (en) * 2007-05-18 2010-11-23 Globalfoundries Inc. Method and apparatus for monitoring energy consumption of an electronic device
US7552241B2 (en) * 2007-05-18 2009-06-23 Tilera Corporation Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip
CN101350010B (en) 2007-07-20 2011-08-17 迈普通信技术股份有限公司 Operation method of hash table
WO2009018481A1 (en) * 2007-07-31 2009-02-05 Viasat, Inc. Multi-level key manager
US7895463B2 (en) * 2007-08-28 2011-02-22 Cisco Technology, Inc. Redundant application network appliances using a low latency lossless interconnect link
US8082482B2 (en) 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US7861014B2 (en) * 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US7584308B2 (en) * 2007-08-31 2009-09-01 International Business Machines Corporation System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
US7840748B2 (en) * 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US8086936B2 (en) 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US7865674B2 (en) * 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7899983B2 (en) * 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7818497B2 (en) * 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US7558887B2 (en) * 2007-09-05 2009-07-07 International Business Machines Corporation Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel
US8019919B2 (en) 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
KR100899526B1 (en) * 2007-09-07 2009-05-27 삼성네트웍스 주식회사 Apparatus and Method for Processing Packet using Multi-Processor
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7890472B2 (en) 2007-09-18 2011-02-15 Microsoft Corporation Parallel nested transactions in transactional memory
US8560634B2 (en) * 2007-10-17 2013-10-15 Dispersive Networks, Inc. Apparatus, systems and methods utilizing dispersive networking
US8539098B2 (en) 2007-10-17 2013-09-17 Dispersive Networks, Inc. Multiplexed client server (MCS) communications and systems
IL187038D0 (en) * 2007-10-30 2008-02-09 Sandisk Il Ltd Secure data processing for unaligned data
US20090119114A1 (en) * 2007-11-02 2009-05-07 David Alaniz Systems and Methods for Enabling Customer Service
US8838817B1 (en) * 2007-11-07 2014-09-16 Netapp, Inc. Application-controlled network packet classification
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8019970B2 (en) * 2007-11-28 2011-09-13 International Business Machines Corporation Three-dimensional networking design structure
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
CN100580629C (en) 2007-12-21 2010-01-13 上海华为技术有限公司 Method and device of multithread load application version program
CN100596126C (en) 2007-12-29 2010-03-24 华为技术有限公司 A wireless packet domain gateway performance self-adapting method and device
US7793080B2 (en) * 2007-12-31 2010-09-07 Globalfoundries Inc. Processing pipeline having parallel dispatch and method thereof
US8086825B2 (en) * 2007-12-31 2011-12-27 Advanced Micro Devices, Inc. Processing pipeline having stage-specific thread selection and method thereof
US20090172370A1 (en) * 2007-12-31 2009-07-02 Advanced Micro Devices, Inc. Eager execution in a processing pipeline having multiple integer execution units
US8375395B2 (en) * 2008-01-03 2013-02-12 L3 Communications Integrated Systems, L.P. Switch-based parallel distributed cache architecture for memory access on reconfigurable computing platforms
US7930470B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US8140936B2 (en) 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US7930469B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US7925826B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US7925824B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US9596324B2 (en) * 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
JP4621747B2 (en) * 2008-02-15 2011-01-26 株式会社東芝 Communication control device and information processing apparatus
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8510370B2 (en) * 2008-02-26 2013-08-13 Avid Technology, Inc. Array-based distributed storage system with parity
US8566833B1 (en) 2008-03-11 2013-10-22 Netapp, Inc. Combined network and application processing in a multiprocessing environment
US8209493B2 (en) 2008-03-26 2012-06-26 Intel Corporation Systems and methods for scheduling memory requests during memory throttling
KR100976628B1 (en) * 2008-05-09 2010-08-18 한국전자통신연구원 Multi-processor system and multi-processing method in multi-processor system
US8094560B2 (en) * 2008-05-19 2012-01-10 Cisco Technology, Inc. Multi-stage multi-core processing of network packets
US8667556B2 (en) * 2008-05-19 2014-03-04 Cisco Technology, Inc. Method and apparatus for building and managing policies
US8677453B2 (en) * 2008-05-19 2014-03-18 Cisco Technology, Inc. Highly parallel evaluation of XACML policies
US20090288104A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Extensibility framework of a network element
JP5583893B2 (en) 2008-05-28 2014-09-03 富士通株式会社 The method of the arithmetic processing device and a processing unit
JP5832284B2 (en) * 2008-05-30 2015-12-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated Distributed level one cache system and a centralized level 2 shader complex having a cache
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8194582B2 (en) * 2008-06-30 2012-06-05 The Boeing Company Method and apparatus for hosting commercially-derived packet routers on satellite payloads
US8331369B2 (en) 2008-07-10 2012-12-11 At&T Intellectual Property I, L.P. Methods and apparatus to distribute network IP traffic
TWI362596B (en) * 2008-07-23 2012-04-21 Inst Information Industry Intermediary apparatus, intermediary method, computer program product for storing a data in a storage apparatus, and data storage system comprising the same
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US7979671B2 (en) * 2008-07-28 2011-07-12 CacheIQ, Inc. Dual hash indexing system and methodology
JP5395383B2 (en) * 2008-08-21 2014-01-22 株式会社東芝 Control system with a pipeline arithmetic processor
US20100070471A1 (en) * 2008-09-17 2010-03-18 Rohati Systems, Inc. Transactional application events
US8688911B1 (en) 2008-11-25 2014-04-01 Marvell Israel (M.I.S.L) Ltd. Transparent processing core and L2 cache connection
US8484421B1 (en) 2008-11-25 2013-07-09 Marvell Israel (M.I.S.L) Ltd. Cache pre-fetch architecture and method
US8549260B2 (en) * 2009-01-29 2013-10-01 Infineon Technologies Ag Apparatus for processing data and method for generating manipulated and re-manipulated configuration data for processor
CN101799750B (en) * 2009-02-11 2015-05-06 上海芯豪微电子有限公司 Data processing method and device
JP5081847B2 (en) * 2009-02-20 2012-11-28 株式会社日立製作所 Packet processing apparatus and packet processing method according Multiprocessor
US9461930B2 (en) 2009-04-27 2016-10-04 Intel Corporation Modifying data streams without reordering in a multi-thread, multi-flow network processor
US9444757B2 (en) 2009-04-27 2016-09-13 Intel Corporation Dynamic configuration of processing modules in a network communications processor architecture
US8514874B2 (en) * 2010-03-12 2013-08-20 Lsi Corporation Thread synchronization in a multi-thread network communications processor architecture
WO2010144624A1 (en) 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
JP2010288233A (en) * 2009-06-15 2010-12-24 Toshiba Corp Cryptographic processing apparatus
US8565239B2 (en) * 2009-07-14 2013-10-22 Broadcom Corporation Node based path selection randomization
US8503456B2 (en) * 2009-07-14 2013-08-06 Broadcom Corporation Flow based path selection randomization
US8949695B2 (en) * 2009-08-27 2015-02-03 Cleversafe, Inc. Method and apparatus for nested dispersed storage
US8473818B2 (en) * 2009-10-12 2013-06-25 Empire Technology Development Llc Reliable communications in on-chip networks
US8484439B1 (en) 2009-10-27 2013-07-09 Juniper Networks, Inc. Scalable hash tables
US8446824B2 (en) * 2009-12-17 2013-05-21 Intel Corporation NUMA-aware scaling for network devices
US8452835B2 (en) * 2009-12-23 2013-05-28 Citrix Systems, Inc. Systems and methods for object rate limiting in multi-core system
US9367462B2 (en) * 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors
US8295305B2 (en) * 2009-12-30 2012-10-23 International Business Machines Corporation Dual scheduling of work from multiple sources to multiple sinks using source and sink attributes to achieve fairness and processing efficiency
US8532129B2 (en) * 2009-12-30 2013-09-10 International Business Machines Corporation Assigning work from multiple sources to multiple sinks given assignment constraints
US8391305B2 (en) * 2009-12-30 2013-03-05 International Business Machines Corporation Assignment constraint matrix for assigning work from multiple sources to multiple sinks
JP5477112B2 (en) * 2010-03-31 2014-04-23 富士通株式会社 The method of testing network system
US9015441B2 (en) 2010-04-30 2015-04-21 Microsoft Technology Licensing, Llc Memory usage scanning
US8699484B2 (en) 2010-05-24 2014-04-15 At&T Intellectual Property I, L.P. Methods and apparatus to route packets in a network
US9491085B2 (en) * 2010-05-24 2016-11-08 At&T Intellectual Property I, L.P. Methods and apparatus to route control packets based on address partitioning
US8559332B2 (en) * 2010-05-25 2013-10-15 Telefonaktiebolaget L M Ericsson (Publ) Method for enhancing table lookups with exact and wildcards matching for parallel environments
US8381004B2 (en) * 2010-05-26 2013-02-19 International Business Machines Corporation Optimizing energy consumption and application performance in a multi-core multi-threaded processor system
EP2590083A4 (en) * 2010-06-30 2016-04-20 Fujitsu Ltd Data restoration program, data restoration device, and data restoration method
US8681973B2 (en) * 2010-09-15 2014-03-25 At&T Intellectual Property I, L.P. Methods, systems, and computer program products for performing homomorphic encryption and decryption on individual operations
CN102446087B (en) * 2010-10-12 2014-02-26 无锡江南计算技术研究所 Instruction prefetching method and device
GB2485142A (en) * 2010-10-27 2012-05-09 Nds Ltd Secure broadcast/multicast of media content
US8751720B2 (en) 2010-11-08 2014-06-10 Moon J. Kim Computationally-networked unified data bus
KR101153940B1 (en) * 2010-11-09 2012-06-08 아주대학교산학협력단 The packet classification apparatus and method
US8955110B1 (en) 2011-01-14 2015-02-10 Robert W. Twitchell, Jr. IP jamming systems utilizing virtual dispersive networking
US8941659B1 (en) 2011-01-28 2015-01-27 Rescon Ltd Medical symptoms tracking apparatus, methods and systems
US8605732B2 (en) 2011-02-15 2013-12-10 Extreme Networks, Inc. Method of providing virtual router functionality
FR2971872B1 (en) * 2011-02-18 2014-06-20 Bull Sas Programmable integrated circuit cryptography
US9158592B2 (en) 2011-05-02 2015-10-13 Green Hills Software, Inc. System and method for time variant scheduling of affinity groups comprising processor core and address spaces on a synchronized multicore processor
CN102779110B (en) * 2011-05-11 2014-08-06 扬智科技股份有限公司 Multi-core system based on far-end code calling and data access and control method thereof
JP2012243105A (en) * 2011-05-19 2012-12-10 Buffalo Inc File management device and control program thereof
US9996403B2 (en) * 2011-09-30 2018-06-12 Oracle International Corporation System and method for providing message queues for multinode applications in a middleware machine environment
US9612934B2 (en) * 2011-10-28 2017-04-04 Cavium, Inc. Network processor with distributed trace buffers
US9330002B2 (en) * 2011-10-31 2016-05-03 Cavium, Inc. Multi-core interconnect in a network processor
WO2013072773A2 (en) * 2011-11-18 2013-05-23 Marvell World Trade Ltd. Data path acceleration using hw virtualization
WO2013081744A1 (en) * 2011-11-30 2013-06-06 Axis Semiconductor, Inc. Herarchical multi-core processor and method of programming for efficient data processing
US10102124B2 (en) * 2011-12-28 2018-10-16 Intel Corporation High bandwidth full-block write commands
US8850557B2 (en) 2012-02-29 2014-09-30 International Business Machines Corporation Processor and data processing method with non-hierarchical computer security enhancements for context states
US9069912B2 (en) * 2012-03-31 2015-06-30 Qualcomm Technologies, Inc. System and method of distributed initiator-local reorder buffers
US9311228B2 (en) 2012-04-04 2016-04-12 International Business Machines Corporation Power reduction in server memory system
US9420008B1 (en) * 2012-05-10 2016-08-16 Bae Systems Information And Electronic Systems Integration Inc. Method for repurposing of communications cryptographic capabilities
US8910179B2 (en) * 2012-05-15 2014-12-09 Freescale Semiconductor, Inc. Systems and methods for providing semaphore-based protection of system resources
US9514069B1 (en) 2012-05-24 2016-12-06 Schwegman, Lundberg & Woessner, P.A. Enhanced computer processor and memory management architecture
WO2014038582A1 (en) * 2012-09-04 2014-03-13 日本電気株式会社 Packet distribution device, packet distribution method, and packet distribution program
US9164570B2 (en) * 2012-12-13 2015-10-20 Advanced Micro Devices, Inc. Dynamic re-configuration for low power in a data processor
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US9361116B2 (en) 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
US10346195B2 (en) 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
KR101448951B1 (en) * 2013-02-27 2014-10-13 주식회사 시큐아이 Apparatus and method for processing packet
US9237128B2 (en) * 2013-03-15 2016-01-12 International Business Machines Corporation Firewall packet filtering
US8954992B2 (en) * 2013-03-15 2015-02-10 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Distributed and scaled-out network switch and packet processing
CN105229980B (en) * 2013-04-11 2018-11-16 马维尔以色列(M.I.S.L.)有限公司 Method to find an exact match keyword with variable size and equipment
KR101499890B1 (en) * 2013-05-15 2015-03-06 주식회사 코스콤 Low Latency Framework System
US9454196B2 (en) 2013-06-27 2016-09-27 Apple Inc. Active peak power management of a high performance embedded microprocessor cluster
CN104302100A (en) * 2013-07-18 2015-01-21 群联电子股份有限公司 Welding pad structure, printed circuit board employing welding pad structure, and memory storage device
JP5742908B2 (en) * 2013-10-03 2015-07-01 富士通株式会社 Multicore processor system, control method and program
CN104572275B (en) * 2013-10-23 2017-12-29 华为技术有限公司 A process whereby loading method, apparatus and system
US9825857B2 (en) * 2013-11-05 2017-11-21 Cisco Technology, Inc. Method for increasing Layer-3 longest prefix match scale
GB201322883D0 (en) * 2013-12-23 2014-02-12 Bae Systems Plc Data capture
US10122609B2 (en) 2013-12-23 2018-11-06 Bae Systems Plc Data capture
KR20150086718A (en) * 2014-01-20 2015-07-29 삼성전자주식회사 Method and Apparatus for processing data by pipeline using memory
US10078613B1 (en) * 2014-03-05 2018-09-18 Mellanox Technologies, Ltd. Computing in parallel processing environments
US9547331B2 (en) 2014-04-03 2017-01-17 Qualcomm Incorporated Apparatus and method to set the speed of a clock
US20150334008A1 (en) * 2014-05-15 2015-11-19 Samsung Electronics Co., Ltd. Method of distributing data and device supporting the same
US9413783B1 (en) * 2014-06-02 2016-08-09 Amazon Technologies, Inc. Network interface with on-board packet processing
CN105591914A (en) * 2014-10-21 2016-05-18 中兴通讯股份有限公司 Openflow flow table look-up method and device
US10230824B2 (en) * 2014-11-17 2019-03-12 Keysight Technologies Singapore (Holdings) Pte. Lte. Packet classification using memory pointer information
CN104391821A (en) * 2014-11-20 2015-03-04 天津大学 System level model building method of multiple core sharing SIMD coprocessor
DE102015200301A1 (en) 2015-01-13 2016-07-14 Robert Bosch Gmbh A method for classifying a data segment with respect to its further processing
US9830187B1 (en) * 2015-06-05 2017-11-28 Apple Inc. Scheduler and CPU performance controller cooperation
CN105468705A (en) * 2015-11-18 2016-04-06 广东南方通信建设有限公司 Mobile communication background data file importing method
CN106059792B (en) * 2016-05-13 2019-03-29 北京英诺威尔科技股份有限公司 A kind of flow analyzing and processing method of low latency
CN107077390A (en) * 2016-07-29 2017-08-18 华为技术有限公司 Task processing method and network card
US10348506B2 (en) 2016-09-30 2019-07-09 International Business Machines Corporation Determination of state of padding operation
US20180122038A1 (en) * 2016-10-28 2018-05-03 Qualcomm Incorporated Multi-layer fetch during composition

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744078A (en) * 1985-05-13 1988-05-10 Gould Inc. Multiple path multiplexed host to network data communication system
US4777595A (en) * 1982-05-07 1988-10-11 Digital Equipment Corporation Apparatus for transferring blocks of information from one node to a second node in a computer network
US5422654A (en) * 1991-10-17 1995-06-06 Chips And Technologies, Inc. Data stream converter with increased grey levels
US5583561A (en) * 1994-06-07 1996-12-10 Unisys Corporation Multi-cast digital video data server using synchronization groups
US5838603A (en) * 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US5878217A (en) * 1994-11-21 1999-03-02 Cirrus Logic, Inc. Network controller for switching into DMA mode based on anticipated memory overflow and out of DMA mode when the host processor is available
US5905874A (en) * 1996-06-28 1999-05-18 Compaq Computer Corporation Method and system for reducing data transfer latency when transferring data from a network to a computer system
US5923654A (en) * 1996-04-25 1999-07-13 Compaq Computer Corp. Network switch that includes a plurality of shared packet buffers
US5974496A (en) * 1997-01-02 1999-10-26 Ncr Corporation System for transferring diverse data objects between a mass storage device and a network via an internal bus on a network card
US6216205B1 (en) * 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
US20020083344A1 (en) * 2000-12-21 2002-06-27 Vairavan Kannan P. Integrated intelligent inter/intra networking device
US6430626B1 (en) * 1996-12-30 2002-08-06 Compaq Computer Corporation Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses
US20020122419A1 (en) * 2000-06-14 2002-09-05 Bergantino Paul V. Communication packet processor with a look-up engine and content-addressable memory for modifying selectors to retrieve context information for a core processor
US20020184328A1 (en) * 2001-05-29 2002-12-05 Richardson Stephen E. Chip multiprocessor with multiple operating systems
US20020184487A1 (en) * 2001-03-23 2002-12-05 Badamo Michael J. System and method for distributing security processing functions for network applications
US20030046511A1 (en) * 2001-08-30 2003-03-06 Buch Deep K. Multiprocessor-scalable streaming data server arrangement
US20030074388A1 (en) * 2001-10-12 2003-04-17 Duc Pham Load balanced scalable network gateway processor architecture
US6578156B1 (en) * 1999-01-08 2003-06-10 Seiko Epson Corporation Output buffer having a plurality of switching devices being turned on successively at shorter time intervals to achieve increasing drive capability using a predriver
US20030126297A1 (en) * 2001-12-31 2003-07-03 Maxxan Systems, Inc. Network processor interface system
US20040153694A1 (en) * 2002-11-26 2004-08-05 Microsoft Corporation Reliability of diskless network-bootable computers using non-volatile memory cache
US6940814B1 (en) * 1997-06-30 2005-09-06 Sun Microsystems, Inc. System and method for a quality of service in a multi-layer network element

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736569A (en) * 1971-10-13 1973-05-29 Ibm System for controlling power consumption in a computer
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
US4754394A (en) 1984-10-24 1988-06-28 International Business Machines Corporation Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage
US5226171A (en) * 1984-12-03 1993-07-06 Cray Research, Inc. Parallel vector processing system for individual and broadcast distribution of operands and control information
JPS63163912A (en) * 1986-12-26 1988-07-07 Toshiba Corp Microcomputer system
EP0512009A4 (en) * 1990-11-26 1993-10-20 Adaptive Solutions, Inc. Temperature-sensing control system and method for integrated circuits
DE4421640C1 (en) * 1994-06-21 1995-08-03 Siemens Ag Hash addressing and storage for distribution and recovery of data
US5671377A (en) * 1994-07-19 1997-09-23 David Sarnoff Research Center, Inc. System for supplying streams of data to multiple users by distributing a data stream to multiple processors and enabling each user to manipulate supplied data stream
JP3132749B2 (en) 1994-12-05 2001-02-05 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Multi-processor data processing system
JPH096633A (en) 1995-06-07 1997-01-10 Internatl Business Mach Corp <Ibm> Method and system for operation of high performance multiple logical route in data processing system
EP0777182B1 (en) 1995-11-28 2001-07-04 Bull S.A. A memory access limiter for random access dynamic memories
US5802576A (en) * 1996-07-01 1998-09-01 Sun Microsystems, Inc. Speculative cache snoop during DMA line update
US5778243A (en) * 1996-07-03 1998-07-07 International Business Machines Corporation Multi-threaded cell for a memory
DE19630861A1 (en) * 1996-07-31 1998-02-05 Philips Patentverwaltung Data processing means comprising a microprocessor and an additional arithmetic unit
US5828753A (en) * 1996-10-25 1998-10-27 Intel Corporation Circuit and method for ensuring interconnect security within a multi-chip integrated circuit package
US5895487A (en) 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US6088788A (en) 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US5999441A (en) * 1997-02-14 1999-12-07 Advanced Micro Devices, Inc. Random access memory having bit selectable mask for memory writes
US6151681A (en) * 1997-06-25 2000-11-21 Texas Instruments Incorporated Dynamic device power management
US5892966A (en) * 1997-06-27 1999-04-06 Sun Microsystems, Inc. Processor complex for executing multimedia functions
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6272520B1 (en) 1997-12-31 2001-08-07 Intel Corporation Method for detecting thread switch events
FR2775369B1 (en) * 1998-02-26 2001-08-03 Sgs Thomson Microelectronics Implementation Method of relative specific modular multiplication to the method of Montgomery
US6151685A (en) * 1998-05-15 2000-11-21 International Business Machines Corporation System and method for recovering a segment directory for a log structured array
US6021076A (en) * 1998-07-16 2000-02-01 Rambus Inc Apparatus and method for thermal regulation in memory subsystems
US6320964B1 (en) * 1998-08-26 2001-11-20 Intel Corporation Cryptographic accelerator
US6453360B1 (en) * 1999-03-01 2002-09-17 Sun Microsystems, Inc. High performance network interface
US7243133B2 (en) * 1999-03-30 2007-07-10 Sedna Patent Services, Llc Method and apparatus for reducing latency in an interactive information distribution system
US6341347B1 (en) * 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US6938147B1 (en) * 1999-05-11 2005-08-30 Sun Microsystems, Inc. Processor with multiple-thread, vertically-threaded pipeline
JP2001043084A (en) * 1999-05-24 2001-02-16 Toshiba Corp Processor system
US6334180B1 (en) * 1999-06-27 2001-12-25 Sun Microsystems, Inc. Processor coupled by visible register set to modular coprocessor including integrated multimedia unit
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6434662B1 (en) * 1999-11-02 2002-08-13 Juniper Networks, Inc. System and method for searching an associative memory utilizing first and second hash functions
US6950434B1 (en) * 1999-12-07 2005-09-27 Advanced Micro Devices, Inc. Arrangement for searching packet policies using multi-key hash searches in a network switch
TW536672B (en) * 2000-01-12 2003-06-11 Hitachi Ltd IC card and microcomputer
CA2375749A1 (en) * 2000-03-31 2001-10-11 Motorola, Inc. Scalable cryptographic engine
WO2001078309A2 (en) 2000-04-11 2001-10-18 P-Cube Ltd. A method and apparatus for wire-speed application layer classification of data packets
JP2001339383A (en) * 2000-05-29 2001-12-07 Hitachi Ltd Semiconductor device for authentication communication
US6754662B1 (en) * 2000-08-01 2004-06-22 Nortel Networks Limited Method and apparatus for fast and consistent packet classification via efficient hash-caching
US6567900B1 (en) * 2000-08-31 2003-05-20 Hewlett-Packard Development Company, L.P. Efficient address interleaving with simultaneous multiple locality options
US6785783B2 (en) 2000-11-30 2004-08-31 International Business Machines Corporation NUMA system with redundant main memory architecture
US6963977B2 (en) * 2000-12-19 2005-11-08 International Business Machines Corporation Circuits and methods for modular exponentiation
US6463510B1 (en) * 2000-12-29 2002-10-08 Compaq Information Technologies Group, L.P. Apparatus for identifying memory requests originating on remote I/O devices as noncacheable
US6980550B1 (en) * 2001-01-16 2005-12-27 Extreme Networks, Inc Method and apparatus for server load balancing
US6968453B2 (en) * 2001-01-17 2005-11-22 International Business Machines Corporation Secure integrated device with secure, dynamically-selectable capabilities
US6904040B2 (en) * 2001-10-05 2005-06-07 International Business Machines Corporaiton Packet preprocessing interface for multiprocessor network handler

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777595A (en) * 1982-05-07 1988-10-11 Digital Equipment Corporation Apparatus for transferring blocks of information from one node to a second node in a computer network
US4744078A (en) * 1985-05-13 1988-05-10 Gould Inc. Multiple path multiplexed host to network data communication system
US5422654A (en) * 1991-10-17 1995-06-06 Chips And Technologies, Inc. Data stream converter with increased grey levels
US5583561A (en) * 1994-06-07 1996-12-10 Unisys Corporation Multi-cast digital video data server using synchronization groups
US5838603A (en) * 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US5878217A (en) * 1994-11-21 1999-03-02 Cirrus Logic, Inc. Network controller for switching into DMA mode based on anticipated memory overflow and out of DMA mode when the host processor is available
US5923654A (en) * 1996-04-25 1999-07-13 Compaq Computer Corp. Network switch that includes a plurality of shared packet buffers
US5905874A (en) * 1996-06-28 1999-05-18 Compaq Computer Corporation Method and system for reducing data transfer latency when transferring data from a network to a computer system
US6430626B1 (en) * 1996-12-30 2002-08-06 Compaq Computer Corporation Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses
US5974496A (en) * 1997-01-02 1999-10-26 Ncr Corporation System for transferring diverse data objects between a mass storage device and a network via an internal bus on a network card
US6940814B1 (en) * 1997-06-30 2005-09-06 Sun Microsystems, Inc. System and method for a quality of service in a multi-layer network element
US6216205B1 (en) * 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
US6578156B1 (en) * 1999-01-08 2003-06-10 Seiko Epson Corporation Output buffer having a plurality of switching devices being turned on successively at shorter time intervals to achieve increasing drive capability using a predriver
US20020122419A1 (en) * 2000-06-14 2002-09-05 Bergantino Paul V. Communication packet processor with a look-up engine and content-addressable memory for modifying selectors to retrieve context information for a core processor
US20020083344A1 (en) * 2000-12-21 2002-06-27 Vairavan Kannan P. Integrated intelligent inter/intra networking device
US20020184487A1 (en) * 2001-03-23 2002-12-05 Badamo Michael J. System and method for distributing security processing functions for network applications
US20020184328A1 (en) * 2001-05-29 2002-12-05 Richardson Stephen E. Chip multiprocessor with multiple operating systems
US20030046511A1 (en) * 2001-08-30 2003-03-06 Buch Deep K. Multiprocessor-scalable streaming data server arrangement
US20030074388A1 (en) * 2001-10-12 2003-04-17 Duc Pham Load balanced scalable network gateway processor architecture
US20030126297A1 (en) * 2001-12-31 2003-07-03 Maxxan Systems, Inc. Network processor interface system
US20040153694A1 (en) * 2002-11-26 2004-08-05 Microsoft Corporation Reliability of diskless network-bootable computers using non-volatile memory cache

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040241457A1 (en) * 1994-12-23 2004-12-02 Saint-Gobain Glass France Glass substrates coated with a stack of thin layers having reflective properties in the infra-red and/or solar ranges
US20060009265A1 (en) * 2004-06-30 2006-01-12 Clapper Edward O Communication blackout feature
US7519796B1 (en) 2004-06-30 2009-04-14 Sun Microsystems, Inc. Efficient utilization of a store buffer using counters
US7543132B1 (en) 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7509484B1 (en) 2004-06-30 2009-03-24 Sun Microsystems, Inc. Handling cache misses by selectively flushing the pipeline
US20060136915A1 (en) * 2004-12-17 2006-06-22 Sun Microsystems, Inc. Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline
US8756605B2 (en) 2004-12-17 2014-06-17 Oracle America, Inc. Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline
US7430643B2 (en) 2004-12-30 2008-09-30 Sun Microsystems, Inc. Multiple contexts for efficient use of translation lookaside buffer
US20060161760A1 (en) * 2004-12-30 2006-07-20 Sun Microsystems, Inc. Multiple contexts for efficient use of translation lookaside buffer
US9747132B2 (en) 2013-04-18 2017-08-29 Denso Corporation Multi-core processor using former-stage pipeline portions and latter-stage pipeline portions assigned based on decode results in former-stage pipeline portions

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