US20020147969A1 - Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method - Google Patents

Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method Download PDF

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US20020147969A1
US20020147969A1 US09/176,112 US17611298D US2002147969A1 US 20020147969 A1 US20020147969 A1 US 20020147969A1 US 17611298 D US17611298 D US 17611298D US 2002147969 A1 US2002147969 A1 US 2002147969A1
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branch
instructions
compiler
interpreter
code
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US6463582B1 (en
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Richard A. Lethin
Joseph A. Bank
Charles D. Garrett
Mikayo Wada
Mitsuo Sakurai
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Fujitsu Ltd
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Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GARRETT, CHARLES D., SAKURAI, MITSUO, WADA, MIKAYO, BANK, JOSEPH A., LETHIN, RICARD A.
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED CORRECTIVE ASSIGNMENT TO CORRECT CONVEYING PARTY'S NAME. AN ASSIGNMENT PREVIOUSLY RECORDED AT REEL 009714, FRAME 0542. Assignors: GARRETT, CHARLES D., SAKURAI, MITSUO, WADA, MIKAYO, BANK, JOSEPH A., LETHIN, RICHARD A.
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

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  • the size of the converted object code becomes relatively small in comparison with the static converted object code.
  • the conventional dynamic object code conversion method has a problem in that all objects, including seldom used objects, are converted. In other words, the conventional dynamic object code conversion method fails to efficiently recognize objects which are executed plural times and thereby increases the time needed for conversion of the original object code while sacrificing efficiency.
  • FIG. 12 is a schematic diagram illustrating an overall structure of a compiler according to an embodiment of the present invention.
  • FIG. 22 particularly illustrates an example of code generation for the same instruction with different surrounding instructions.
  • trans_master_target_table 1 1000h An array of pointers, one for each page in ASP's address space. For a page that ASP does not use, the pointer is 0. For a page that ASP uses, the pointer points to an array in the dynamically allocated part of the OOCT buffer (see below.) unallocated 41004h A pointer which points to the first unused byte in the dynamically allocated part of the buffer. Only used during initialization. length_left 41008h The number of bytes left in the dynamically allocated part of the buffer. Only used during initialization. num_execs 4100Ch The number of interpreter 110.
  • Branch header table 6 There is one pointer to a BRANCH_RECORD for each estimated branch.
  • SIZE Num execs * 32 * 4 * 24 bytes.
  • OOCT stack 7 A 1 MB stack.
  • Zone memory 2 A percentage of the remaining memory is used for zone memory. Currently 50% of memory is used.
  • Segment memory 3 A percentage of the remaining memory is used for segment memory. Currently 50% of memory is used.
  • compiler 104 When compiler 104 wants to read branch log information, it calls the procedure BRANCH_Get_Record with the address of the branch instruction. This procedure looks up the branch in the branch log and returns a pointer to one of the elements of the BRANCH_RECORD array. Compiler 104 can then see how many times the branch instruction was executed, how many times it branched and how many times it fell through.
  • the TRANS_Get_Entry_Address procedure reads and returns the entry point address of the translation table entry. Note that an entry point address is the address of an target instruction if there is no segment locking, but it is the address of a SEGMENT_GATE data structure if there is segment locking.
  • the fourth transition is from U/L to U/U. It also happens when the interpreter 110 leaves a segment (* 304 ) and goes to the unlock procedure (* 305 ). After this transition occurs, the segment is unlocked and compiler 104 will pass the two tests (* 309 , * 3010 ) and delete the segment (* 3011 ).
  • the interpreter 110 send seed addresses to compiler 104 . They use two message queues to send them. The first one uses the KOI system calls ScMsgSnd and ScMsgRcv to send and receive seeds. The second queue uses a shared memory area in the OOCT buffer. The shared area is called the branch_Seed_Buffer.
  • OOCT gets the advantages of both methods.
  • compiler 104 When compiler 104 is idle, it calls ScMsgRcv to block. In this case, the interpreter 110 sends the next seed with a ScMsgSnd call to wake compiler 104 up.
  • the interpreter 110 sends seeds through the branch_Seed_Buffer area, which is faster. After compiler 104 finishes one compilation, it checks for sch_Seed_Buffer area. If there are any then it compiles them. When it finishes the all seeds, it calls ScMsgRcv again and blocks.
  • the OOCT interpreter code can run in two modes, OOCT_PERFORMANCE_MODE and OOCT_DEBUG_MODE. This documentation describes all of the features of OOCT_PERFORMANCE_MODE and notes where OOCT_DEBUG_MODE is different.
  • Allocate compiler 104 s stack memory. Compiler 104 uses a special large stack that is allocated in the OOCT_buffer.
  • interpreter 110 executes a branch instruction in system code and the OOCT mode bit is set, interpreter 110 calls branch logger 112 through one of the following routines: _declspec(naked) OOCT_Log_Unconditional_Fixed_Branch() Invoked by interpreter with a branch Arguments: ecx: address of branch instruction Returns: Does not return (acts like a jump to IC_FETCHO2) _declspec(naked) OOCT_Log_Unconditional_Non_Fixed_Branch() Invoked by interpreter with a branch Arguments: ecx: address of branch instruction Does not return (acts like a jump to IC_FETCHO2) _declspec(naked) OOCT_Log_Conditional_Fixed_Branch_Taken() Invoked by interpreter with a branch Arguments: ecx: address of branch instruction Returns: Does not return (acts like a jump to IC_FETCHO
  • FIG. 9 particularly illustrates that the variable local_branch_header_table is an array of pointers to lists. Each list contains BRANCH_RECORDs that have the same destination address. When there is no list, the pointer in local_branch_header_table is NULL.
  • branch logger 112 When a branch instruction is executed very frequently, branch logger 112 sends its destination address to compiler 104 . This address is called a ‘seed’ and choosing seeds is a very important part of the OOCT system.
  • the IL used by OOCT (referred to as just the IL from here on) is currently composed of 40 different opcodes listed in Table 6.
  • the instructions fall into three main categories. First, there are functional opcodes such as ADD and LOAD that have a straightforward mapping to standard machine opcodes. Second, there are opcodes that handle control flow such as LABEL and CGOTO. Finally, there are a number of special opcodes that are used as special markers by compiler 104 , which do not directly correspond to code that is generated by the back end. These special marker opcodes are described in a separate section. Since the IL represents a virtual machine, it is straightforward to add other opcodes to the IL if further functionality is required.
  • the IL Since the IL is typed, it is critical to use the correct size pseudoregister with the correct type. For example, to load a 16 bit value into a 32 bit register, first a 16 bit load is done into a 16 bit pseudoregister, and then a CVT operation is used to cast the 16 bit value to a 32 bit value (the LOAD_CVT 32 macro does this).
  • IL is generated for entry points, interrupt checks.
  • each pseudoregister definition compiler 104 keeps track of the instructions which use that definition, and for each pseudoregister use compiler 104 keeps track of its definitions. This information is called use/def information.
  • Compiler 104 uses use/def information in passes such as the Constant Folding pass. When pseudoregisters can alias each other, this requires the use/def computation and compiler 104 passes that use that information to be much more complex.
  • a second problem created by overlapping pseudoregisters is in register allocation. When the register allocator assigns two overlapping pseudoregisters into machine registers at the same time, a modification to one register may require that the other register be invalidated. In general, keeping track of that information is very difficult and creates unneeded complexity.
  • Register allocation is a complex, multi-step process. The steps are described in detail below.
  • the next step is to compute the conflict graph of the REGINFO structures.
  • Two REGINFOs conflict if their live ranges overlap.
  • Two REGINFOs are compatible if they are connected by copy.
  • Conflicting REGINFOs cannot be assigned to the same register, as they are alive at the same time.
  • Two compatible REGINFOs should be assigned to the same register if possible, as doing so eliminates a copy.
  • OC_RegAllocDefWeight Weight placed on definitions, Higher values of OC_RegAllocDefWeight will favor REGINFOs with more different definition IL statements.
  • Code compiled by OOCT is stored within a SEGMENT data structure. There are a number of important issues associated with the management of segments. First, segments have a special memory allocator to handle segment storage. Second, how segments are created and installed into the system is discussed. Third, how segments are deleted is discussed (if this option is turned on). Finally, segment locking, which is used when segment deletion is on, is discussed.
  • the K assembler provides a straightforward mechanism for generating K code from within a C program.
  • Each K opcode has a function used to assemble instructions specifically for that opcode.
  • the individual instructions take as arguments a pointer to memory for where to store the code, a (possibly empty) label name, and an argument for each field used in the instruction.
  • the function simply combines the fields into their correct places and writes the code into the buffer. Since branches to a label may occur before the definition of the label, a second pass over the code is used to resolve branch destination.
  • the interpreter task counts how often a branch instruction jumps to a particular destination address. When this count passes a threshold, the interpreter sends a translation request including the destination address.
  • the threshold value is the critical parameter that is set by the software feedback mechanism. When the threshold is lower than most of the execution counts, the rate of translation requests is high. When the threshold is higher than most of the execution counts, the rate of requests is low. Since the typical size of an execution count varies with the program that is being interpreted, software feedback is an ideal way to set the threshold because it adapts to the behavior of the interpreter automatically.

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