US20020123195A1 - MOS technology power device with low output resistance and low capacity, and related manufacturing process - Google Patents
MOS technology power device with low output resistance and low capacity, and related manufacturing process Download PDFInfo
- Publication number
- US20020123195A1 US20020123195A1 US10/006,778 US677801A US2002123195A1 US 20020123195 A1 US20020123195 A1 US 20020123195A1 US 677801 A US677801 A US 677801A US 2002123195 A1 US2002123195 A1 US 2002123195A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor layer
- lightly doped
- doped semiconductor
- regions
- dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000005516 engineering process Methods 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 210000000746 body region Anatomy 0.000 claims abstract description 46
- 239000002019 doping agent Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims 3
- 239000000463 material Substances 0.000 abstract description 2
- 239000007943 implant Substances 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 210000004027 cell Anatomy 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 210000001316 polygonal cell Anatomy 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Definitions
- MOS-gated power devices include, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices.
- a primary goal of the designers of MOS-gated power devices is to reduce, as far as possible, the output resistance (or “on” resistance) and the various capacitances associated with the power device structure.
- the physical structure of the MOS-gated power devices limits the degree to which the integration density can be increased. These limits can be better understood considering the distinct components of the on resistance of a MOS-gated power device, which are: the channel resistance Rc, which is the component associated with the channel region of the MOS-gated power device; the accumulation region resistance Racc, which is the component associated with the surface region of those portions of the common drain layer (i.e.
- the lightly doped epitaxial layer wherein the elementary functional units are formed disposed between the body regions of the elementary functional units; the JFET resistance Fjfet, which is the component associated with those portions of the common drain layer disposed between the depletion regions of the body regions of the elementary functional units; and the epitaxial layer resistance Repi, which is the component associated with those portions of the common drain layer beneath the body regions of the elementary functional units.
- the channel resistance Rc and the accumulation region resistance Racc can be reduced by scaling down the dimensions of the elementary functional units and by employing photolithographic machines with better optical resolution.
- the JFET resistance Rjfet and the epitaxial layer resistance Repi can be reduced only modifying the physical structure of the MOS-gated power devices. In fact, reducing the distance between the elementary functional units (cells or stripes), causes the Fjfet component to significantly increase, the increase being more pronounced the higher the resistivity of the common drain layer.
- the minimum distance to which the elementary functional units of the MOS-gated power device must be kept increases with the increase of the resistivity of the common drain layer.
- the distance between the elementary functional units can be between 4 ⁇ m and 10 ⁇ m, while in the case of devices designed to operate in higher voltages of about 500 V, wherein the common drain layer is resistive, the distance between 15 ⁇ m and 20 ⁇ m.
- One of the limitations of this technique is that only the JFET component of the on resistance can be reduced, but not the epitaxial layer resistance Repi. Furthermore, an additional mask may be required in the manufacturing process, to prevent the N type dopants from being implanted at the edge of the power MOS device chip.
- a MOS-gated power device comprising a plurality of elementary functional units, each elementary functional unit comprising a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value, wherein a respective lightly doped region of a second conductivity type is respectively disposed under each body region, each respective lightly doped region having a second resistivity value higher than said first resistivity value.
- a MOS-gated power device which, for a given breakdown voltage, has a common drain layer with a lower resistivity than that which would be necessary in a conventional MOS-gated power device with the same breakdown voltage.
- the reduced resistivity of the common drain layer not only provides a decrease of the JFET component Rjfet, but also of the epitaxial layer component Repi of the output resistance of the MOS-gated power device. Furthermore, it is possible to reduce the distance between the elementary functional units without increasing the JFET component, thus reducing the gate-drain capacitance of the MOS-gated power device.
- the structure according to the present invention is particularly suitable for MOS-gated power devices of low voltages (30-200V), in which the dimension of the elementary functional units is comparable with the residual thickness of the epitaxial layer under the body regions.
- FIG. 1 is a cross-sectional view of a MOS-gated power device according to the present invention
- FIGS. 2 to 5 are cross-sectional views similar to FIG. 1 showing intermediate steps of a manufacturing process according to one embodiment of the present invention
- FIG. 5A is a cross-sectional view similar to FIG. 5, illustrating another embodiment of the manufacturing process
- FIG. 6 is a comparative diagram showing doping profiles in the case of a conventional MOS-gated power device and in the case of the present invention.
- FIG. 7 is another comparative diagram showing doping profiles in the regions between elementary functional units of the MOS-gated power device
- FIG. 8 is a comparative diagram showing the electric field distribution in the case of a conventional MOS-gated power device and in the case of the present invention.
- FIGS. 9 to 11 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention.
- FIGS. 12 to 17 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices;
- FIG. 18 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS. 12 to 17 ;
- FIGS. 19 to 24 are cross-sectional views similar to that of FIG. 1 of yet another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices;
- FIG. 25 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS. 19 to 24 .
- a MOS-gated power device chip comprises a heavily doped semiconductor substrate 1 , over which a lightly doped semiconductor layer 2 is formed, for example by means of an epitaxial growth.
- a heavily doped semiconductor substrate 1 over which a lightly doped semiconductor layer 2 is formed, for example by means of an epitaxial growth.
- both the substrate 1 and the epitaxial layer 2 are of the N conductivity type; differently, in a P channel power MOSFET both the substrate 1 and the epitaxial layer 2 would be of the P conductivity type.
- the substrate 1 and the epitaxial layer 2 could be of opposite conductivity types, as in the case of a Insulated Gate Bipolar Transistor (IGBT).
- IGBT Insulated Gate Bipolar Transistor
- the epitaxial layer 2 forms a common drain layer for elementary functional units of the MOS-gated power device.
- Each elementary functional unit comprise a body region 3 of the P conductivity type (or, more generally, of the opposite conductivity type of the epitaxial layer 2 ).
- the body regions 3 can have a polygonal layout (e.g. square or hexagonal), as in the case of “cellular” MOS-gated power devices, or alternatively they can be represented by elongated stripes (in which case FIG. 1 shows a cross-section in a direction transverse to the elongated stripes).
- heavily doped source regions 4 of the N conductivity type i.e. of the same conductivity type as the epitaxial layer 2 ) are provided inside each body region 3 .
- the top surface of the epitaxial layer 2 is covered by an insulated gate layer comprising a thin gate oxide layer 5 and a polysilicon layer 6 . Openings are provided in the insulated gate layer over each body region 3 .
- the insulated gate layer is covered by an insulating material layer 7 in which contact windows are provided over each body region 3 to allow a source metal layer 8 t contact the source regions 4 and the body regions 3 .
- a drain metal layer 9 is also provided on the bottom surface of the substrate 1 .
- region 20 is illustrated as extending through the whole thickness of the epitaxial layer 2 , one skilled in the art will appreciate that region 20 may extend only partially through epitaxial layer 2 .
- a region 20 of the same conductivity type as but having a higher resistivity than the epitaxial layer 2 is provided which extends downwardly substantially for the whole thickness of the epitaxial layer 2 , to the substrate 1 .
- the presence of the regions 20 beneath the body regions 3 it is possible to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage of the MOS-gated power device, because the breakdown voltage of the MOS-gated power device depends on the resistivity and on the thickness of the portions of the common drain layer beneath the body regions, not on the portions of the common drain layer between the body regions.
- the presence of the lightly doped regions 20 under the body regions 3 allows achievement of the desired breakdown voltage even with an epitaxial layer having a lower resistivity than that necessary with conventional devices.
- both the JFET component Fjfet and the epitaxial layer component Repi of the output resistance Ron of the MOS-gated power device are reduced, because the current flux I coming from the source regions and flowing towards the substrate 1 encounter a lower resistance.
- FIG. 6 illustrates the doping profiles of the different semiconductor regions along the direction of arrow x of FIG. 1 beginning at the surface of body region 3 and moving through the depth of the device towards the substrate.
- the dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure.
- the continuous line represents the doping profile of a device in accordance with the present invention.
- FIG. 7 illustrates the doping profiles of the different semiconductor regions along the direction of arrow Y of FIG. 1 beginning at the surface of the lightly doped semiconductor layer 2 and moving through the depth of the device towards the substrate.
- the dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure.
- the continuous line presents the doping profile of a device in accordance with the present invention.
- FIGS. 6 and 7 illustrate depth value for low-voltage MOS-gated power devices.
- the width of the body region 3 can be, for example, approximately 20 ⁇ m and the depth of regions 20 can therefore be approximately 20 ⁇ m.
- FIG. 8 is a diagram showing the profile of the electric field E in the two cases of FIGS. 6 and 7. From FIG. 8, one skilled in the art will appreciate that in the structure of the present invention the breakdown voltage is higher (the area subtended by the curve of the electric field E is higher in the case of the structure of the present invention (continuous line) than in the case of a conventional structure (dash-and-dot line)).
- the lightly doped layer 2 is epitaxially grown over the heavily doped substrate 1 , the thickness of the epitaxial layer 2 depends on the voltage class of the MOS-gated power device to be fabricated; for example, for low voltage devices the epitaxial layer 2 can have a thickness of about 2 or 5 ⁇ m.
- the resistivity of the epitaxial layer is determined on the basic of the desired breakdown voltage of the MOS-gated power device (for example 1 ohm ⁇ cm for a breakdown voltage of 60 V), in the present invention the epitaxial layer 2 has a resistivity which is lower than that necessary to achieve the same desired breakdown voltage (for example 0.6 ohm ⁇ cm).
- a thin oxide layer 5 is formed, for example by means of a thermal growth or, alternatively, a thick field oxide and an active area are formed.
- a polysilicon layer 6 is then deposited over the oxide layer 5 .
- the polysilicon layer 6 and the oxide layer 5 are then selectively removed from the surface of the epitaxial layer 2 to form openings 10 .
- This step involves depositing a photoresist layer 11 , the selectively exposing the photoresist layer 11 to a light source by means of a mask carrying the pattern of the openings 10 , selectively removing the photoresist layer 11 , and eching the polysilicon and oxide layers 5 , 6 where they are not covered by the photoresist layer 11 .
- the openings 10 can have a polygonal layout (for example square or hexagonal, i.e., cellular layout), or they can be elongated stripes.
- the body regions 3 of the elementary functional units of the MOS-gated power device are then formed.
- a P type dopant such as boron is implanted, using the polysilicon and oxide layers 5 , 6 (and if necessary also the photoresist layer 11 ) as a mask, in a dose ranging from 5 ⁇ 10 13 to 5 ⁇ 10 14 atoms/cm 2 , with an implantation energy in the range 80-200 KeV (FIG. 3).
- a subsequent thermal diffusion of the dopants forms the body regions 3 with a surface concentration in the channel region of approximately 10 17 atoms/cm 3 , which is a concentration necessary to achieve the desired threshold voltage of the MOS-gated power device.
- the body regions 3 can be formed by means of two distinct implants of boron in different doses and at different energies, still using the polysilicon and oxide layers 5 , 6 as a mask.
- the first implant can involve a dose of a P type dopant in the range 10 13 -10 14 atoms/cm 2 with an energy of approximately 80 KeV and is used to control the dopant concentration at the surface of the body regions, especially in the channel regions, which sets the desired threshold voltage of the MOS-gated power device.
- the second implant can involve, for example, a dose of P type dopant in the range 10 14 -10 15 atoms/cm 2 with an energy comprised between 200 KeV and 600 KeV (for low-voltage devices, energies in the range 100 KeV-300 KeV are suitable), such that the peak concentration of the dopants can be located at a prescribed depth, namely under the source regions which will be formed in a later step.
- a subsequent thermal diffusion process at a temperature in the range 1050-1100° C. for 0.5 to 2 hours determines the lateral diffusion of the dopant introduced with the first implant, to form the channel regions of the body regions extending over the gate oxide layer.
- the vertical diffusion of the dopant introduced with the second implant does not alter the threshold voltage of the MOS-gated power device, because the dopant ions reach the surface with a concentration lower than the concentration of the dopant introduced with the first implant (in fact, the peak dopant concentration of the dopant introduced with the first implant is located substantially at the surface of the drain layer 2 ).
- the vertical and lateral diffusion of the dopants introduced with the second implant forms the heavily doped deep body portions of the body regions, reducing the resistivity of the body regions under the source regions.
- a dopant of the P conductivity type preferably one having a high diffusivity such as aluminium, is implanted into the epitaxial layer 2 using the polysilicon and oxide layers 5 , 6 (and if necessary the photoresist layer 11 ) as a mask.
- the implant dose is suitable to partially compensate, but not to invert, the N type doping level of the epitaxial layer, so as to substantially increase the resistivity of those portions of the epitaxial layer 2 wherein such a dopant is implanted.
- the implantation energy (ranging from 700 KeV to 1 MeV or more) is such as to locate the peak concentration of the dopant as close as possible to a body-drain junction (1.5-2 ⁇ m from the surface of the epitaxial layer 2 ).
- the implant mask for the high-diffusivity dopant could be formed by another photoresist layer 111 with smaller openings 100 than the openings 10 in the polysilicon and oxide layers 5 , 6 .
- a high dose of a N type dopant (such as arsenic or phosphorus) is then selectively implanted into the body regions 3 to form the source regions 4 .
- the N type dopant is then made to diffuse by means of a thermal process. During such thermal process, the source dopant diffuses for a depth of about 0.4-0.5 ⁇ m in the case of arsenic, or about 0.6-0.7 ⁇ m in the case of phosphorus.
- the high-diffusivity dopant diffuses for a depth of about 1.5-2 ⁇ m, distributing in a controlled manner under all the body regions 3 substantially to the substrate 1 , modifying the doping profile of the epitaxial layer 2 under the body regions 3 to increase the resistivity of the epitaxial layer 2 in these regions.
- the following process steps involve forming a layer of insulating material 7 over the whole surface of the chip, openings contact windows in the insulating layer 7 over the body regions 3 , and forming a source metal layer 8 and a drain metal layer 9 .
- the budget of the thermal diffusion process used to diffuse the source dopant is not sufficient to completely diffuse the high-voltage devices with a thick epitaxial layer, it is possible to modify the thermal diffusion process of the source dopant, or to invert the described sequence of steps, for example implanting the high-diffusivity dopant before the step of formation of the body regions 3 , to exploit the thermal diffusion process of the body regions.
- FIGS. 9 to 11 show three steps of another embodiment of the manufacturing process of the invention.
- an N ⁇ epitaxial layer 2 grown over substrate 1 has a resistivity value suitable for sustaining the desired breakdown voltage, i.e. 2-5 ohm/cm for a device rated for 30-200V.
- an N type dopant is implanted into the epitaxial layer 2 in regions thereof that will lie between the body regions.
- the dose and energy of the implanted dopant is chosen so to form N ⁇ regions less resistive than the N ⁇ layer 2 .
- a suitable dose is for example 10 12 -10 13 atoms/cm 2 .
- N ⁇ regions are formed in the N ⁇ layer which have a resistivity of 0.5-5 ⁇ /cm depending on the devices's voltage ratings.
- FIG. 11 similarly to what is shown in FIG. 3, a p type dopant is implanted to form the body regions 3 between the N ⁇ regions.
- FIGS. 12 to 18 and 19 to 25 show, in cross-sectional views similar to that of FIG. 1, the main steps of two further alternative embodiments of a manufacturing process according to the present invention.
- Such embodiments are particularly suitable for manufacturing high-voltage devices, capable of sustaining voltages of 400 to 1000 V or more.
- a unique aspect of these devices is that, in order to sustain such voltage values, the thickness of the drain layer has to be in the range 30 to 80 ⁇ m or even more.
- a first lightly doped epitaxial layer 21 of the N conductivity type is formed over the N+ substrate 1 .
- Epitaxial layer 21 has a thickness X 1 approximately equal to the size of the elementary functional units, be they cells or stripes, i.e., for example, 5 to 15 ⁇ m.
- the thickness X 1 of epitaxial layer 21 is much lower, e.g. one third or less, than the overall thickness of the drain layer of the final device.
- the doping level of epitaxial layer 21 is higher than that required for assuring that the device keeps the desired high voltage.
- a doping level of 5-9*10 14 atoms/cm 3 (5-10 ohm/cm) is suitable.
- an oxide layer 24 is then formed over the top surface of epitaxial layer 21 .
- the oxide layer 24 is then selectively removed from the areas wherein the elementary cells or stripes will be formed.
- the size L of the openings in the oxide layer 24 is slightly less than the size of the memory cells or stripes.
- a photoresist layer can be used instead of the oxide layer 24 .
- a P type dopant such as boron or aluminum is then selectively implanted into the epitaxial layer 21 , using the oxide layer 24 as a mask or, alternatively, the photoresist layer.
- a suitable implantation energy must be higher that 200 KeV, for example in the range 200 to 500 KeV.
- the implant dose is chosen in such a way that, after the thermal diffusion processes that will follow, the implanted P type dopant partially compensates, but does not invert, the N type doping of the epitaxial layer 21 .
- a suitable dose ranges from 1*10 12 to 1*10 13 atoms/cm 2 .
- the oxide layer 24 is then completely removed and then a second lightly doped epitaxial layer 22 of the N conductivity type is formed over the first epitaxial layer 21 .
- the thickness X 2 of the second epitaxial layer 22 and its dopant concentration are respectively similar to the thickness X 1 and dopant concentration of the first epitaxial layer 21 .
- the P type dopant previously implanted diffuses into the first and second epitaxial layers 21 , 22 , thus forming N ⁇ regions 201 having dopant concentration approximately lower than or equal to 10 13 atoms/cm 3 .
- another oxide layer 25 is then formed over the second epitaxial layer 22 .
- the oxide layer 25 is then selectively removed using the same photolithographic mask previously used to remove oxide layer 24 .
- a P type dopant such as boron or aluminum is then selectively implanted using the oxide layer 25 as a mask, as in the step depicted in FIG. 11. The implantation dose and energy are chosen in the same way as before.
- the oxide layer 25 is then completely removed, and a third lightly doped epitaxial layer 23 of the N conductivity type is formed over the second epitaxial layer 22 .
- the thickness X 3 and the dopant concentration of the third epitaxial layer 23 are respectively similar to the thickness X 2 and the dopant concentration of the second epitaxial layer 22 .
- the P type dopant previously implanted diffuses into the second and third epitaxial layers 22 , 23 , to form N ⁇ regions 202 , and also regions 202 further diffuse vertically. In this way, N ⁇ regions 202 and N ⁇ regions 201 merge, forming columns of stacked N ⁇ regions 202 , 201 .
- the dopant concentration of N ⁇ regions 202 and 201 is suitable to sustain the desired high voltage.
- each implant of the succession is performed with a respective energy, so as to locate the peak dopant concentration at a respective depth.
- the dose of these implants ranges form 5*10 11 to 1*10 13 atoms/cm 2 , and the energies range from 200 KeV to 900 KeV or more.
- the implanted dopant is boran
- three implants at 300 KeV, 600 KeV and 900 KeV or more can be performed, so as to have peak dopant concentrations located at a depth of 0.7 ⁇ m, 1.2 ⁇ m and 1.7 ⁇ m, respectively.
- FIGS. 19 to 25 Another manufacturing process particularly suitable for high-voltage devices is depicted in FIGS. 19 to 25 .
- a first lightly doped epitaxial layer 21 of the N type and thickness X 1 is formed over the N+ substrate 1 .
- the dopant concentration of the first epitaxial layer 201 is that required for making the final device capable of sustaining the high voltage (that is, by comparison with the process depicted in FIGS. 12 to 18 , the dopant concentration of layer 21 is similar to the dopant concentration of N ⁇ regions 201 and 202 , i.e. 3-5*10 13 atoms/cm 3 (80-150 ohms/cm).
- an oxide layer 26 is formed over the first epitaxial layer 21 .
- the oxide layer 26 is then selectively removed from the regions of layer 21 which will lie between the body regions of the elementary functional units of the device.
- the size L D of the openings in the oxide layer is slightly lower than the distance between the elementary functional units to be formed later on.
- a photoresist layer can be used instead of the oxide layer 26 .
- an N type dopant is implanted into the first epitaxial layer 21 using the oxide layer 26 (or alternatively the photoresist layer) as a mask.
- Suitable implantation dose and energy are respectively 1*10 12 -10 13 atoms/cm 2 and more than 200 KeV (e.g. 200-500 KeV).
- the oxide layer 26 is then completely removed, and a second epitaxial layer 22 is formed over the first epitaxial layer 21 .
- the thickness X 2 and dopant concentration of the second epitaxial layer 22 are respectively similar to the thickness X 1 and dopant concentration of the first epitaxial layer 21 .
- the N type dopant previously implanted diffuses into the first epitaxial layer 21 and the second epitaxial layer 22 , to form enriched N ⁇ regions 300 having a higher dopant concentration than the N ⁇ epitaxial layers 21 and 22 , for example 5-9*10 14 atoms/cm 3 (5-10 ohms/cm).
- oxide layer 27 is then formed over the second epitaxial layer 22 .
- Oxide layer 27 is then selectively removed by means of the same mask used to selectively removed oxide layer 26 .
- An N type dopant is then selectively implanted into the second epitaxial layer 22 using oxide layer 27 as a mask.
- the oxide layer 27 is then completely removed, and a third lightly doped epitaxial layer 23 of the N conductivity type is formed over the second epitaxial layer 22 .
- the thickness X 3 and dopant concentration of the third epitaxial layer 23 are respectively similar to the thickness X 2 and dopant concentration of the second epitaxial layer.
- the implanted N type dopant diffuses into the second and third epitaxial layers 22 , 23 , to form enriched N ⁇ regions 301 over the enriched N ⁇ regions 300 previously formed.
- first and second epitaxial layers 21 , 22 also diffuse further into the first and second epitaxial layers 21 , 22 , so that at the end regions 301 merge with regions 300 .
- stacked enriched N ⁇ regions 300 , 301 are formed in the first, second and third epitaxial layers 21 , 22 , 23 in the regions thereof comprised between the elementary functional units which will be formed later on.
- the body regions of the elementary functional units are to be formed in the third epitaxial layer 23 in the regions thereof between the N ⁇ regions 300 , 301 , as shown in FIG. 25.
- the number of stacked epitaxial layers can be different from three.
- the number of epitaxial layers to be formed depends on the overall thickness of the drain layer of the final device, i.e., on the voltage to be sustained by the power device.
Abstract
A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
Description
- This application is a continuation-in-part of application Ser. No. 08/740,713 filed on Nov. 4, 1996, entitled MOS TECHNOLOGY POWER DEVICE WITH LOW OUTPUT RESISTANCE AND LOW CAPACITANCE, AND RELATED MANUFACTURING PROCESS, which prior application is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a MOS-gated power device with low output resistance and low capacitance, and to a related manufacturing process. MOS-gated power devices include, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices.
- 2. Discussion of the Related Art
- A primary goal of the designers of MOS-gated power devices is to reduce, as far as possible, the output resistance (or “on” resistance) and the various capacitances associated with the power device structure.
- These parameters can be reduced by increasing the integration density of the elementary functional units (polygonal cells or stripes), which constitute a MOS-gated power device, by exploiting photolitographic techniques and manufacturing processes more and more similar to those used in Very Large Scale of Integration (VLSI) technologies.
- However, the physical structure of the MOS-gated power devices limits the degree to which the integration density can be increased. These limits can be better understood considering the distinct components of the on resistance of a MOS-gated power device, which are: the channel resistance Rc, which is the component associated with the channel region of the MOS-gated power device; the accumulation region resistance Racc, which is the component associated with the surface region of those portions of the common drain layer (i.e. the lightly doped epitaxial layer wherein the elementary functional units are formed) disposed between the body regions of the elementary functional units; the JFET resistance Fjfet, which is the component associated with those portions of the common drain layer disposed between the depletion regions of the body regions of the elementary functional units; and the epitaxial layer resistance Repi, which is the component associated with those portions of the common drain layer beneath the body regions of the elementary functional units.
- The channel resistance Rc and the accumulation region resistance Racc (both associated with regions near the surface of the common drain layer) can be reduced by scaling down the dimensions of the elementary functional units and by employing photolithographic machines with better optical resolution. Differently, the JFET resistance Rjfet and the epitaxial layer resistance Repi can be reduced only modifying the physical structure of the MOS-gated power devices. In fact, reducing the distance between the elementary functional units (cells or stripes), causes the Fjfet component to significantly increase, the increase being more pronounced the higher the resistivity of the common drain layer.
- This means that in order to prevent the on resistance from significantly increasing, the minimum distance to which the elementary functional units of the MOS-gated power device must be kept increases with the increase of the resistivity of the common drain layer. By way of example, in devices designed to operated in a voltage range of approximately 60 V, the distance between the elementary functional units can be between 4 μm and 10 μm, while in the case of devices designed to operate in higher voltages of about 500 V, wherein the common drain layer is resistive, the distance between 15 μm and 20 μm.
- Therefore, if in the attempt to increase the integration density it is desired to reduce the distance between the elementary functional units (cells or stripes), so that the gate-drain (or feedback) capacitance can be reduced, without however increasing the output resistance of the MOS-gated power device, it is necessary to increase the doping concentration of the common drain layer. This however reduces the breakdown voltage of the MOS-gated power device.
- One known technique to overcome this drawback is described in the U.S. Pat. No. 4,376,286: the doping concentration in the portions of the common drain layer between the elementary functional units is increased by means of an implant of N type dopants, without affecting the doping concentration of the common drain layer beneath the body regions of the elementary functional units. In this way, it is possible to reduce the distance between the elementary functional units (and consequently reducing the feedback capacitance of the MOS-gated power device), without increasing the Fjfet component of the on resistance.
- One of the limitations of this technique is that only the JFET component of the on resistance can be reduced, but not the epitaxial layer resistance Repi. Furthermore, an additional mask may be required in the manufacturing process, to prevent the N type dopants from being implanted at the edge of the power MOS device chip.
- In view of the state of the art described, it is an object of the present invention to provide a MOS-gated power device with a low output resistance and low capacitance, without negatively affecting the breakdown voltage.
- According to the present invention, this and other objects are achieved in a MOS-gated power device comprising a plurality of elementary functional units, each elementary functional unit comprising a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value, wherein a respective lightly doped region of a second conductivity type is respectively disposed under each body region, each respective lightly doped region having a second resistivity value higher than said first resistivity value.
- As a result of the present invention, and specifically due to the presence of the lightly doped regions under the body regions of the elementary functional units, a MOS-gated power device is provided which, for a given breakdown voltage, has a common drain layer with a lower resistivity than that which would be necessary in a conventional MOS-gated power device with the same breakdown voltage. The reduced resistivity of the common drain layer not only provides a decrease of the JFET component Rjfet, but also of the epitaxial layer component Repi of the output resistance of the MOS-gated power device. Furthermore, it is possible to reduce the distance between the elementary functional units without increasing the JFET component, thus reducing the gate-drain capacitance of the MOS-gated power device.
- The structure according to the present invention is particularly suitable for MOS-gated power devices of low voltages (30-200V), in which the dimension of the elementary functional units is comparable with the residual thickness of the epitaxial layer under the body regions.
- These and other features of the present invention will be made more evident by the following detailed description of one particular embodiment, illustrated as a non limiting example in the annexed drawings, wherein:
- FIG. 1 is a cross-sectional view of a MOS-gated power device according to the present invention;
- FIGS.2 to 5 are cross-sectional views similar to FIG. 1 showing intermediate steps of a manufacturing process according to one embodiment of the present invention;
- FIG. 5A is a cross-sectional view similar to FIG. 5, illustrating another embodiment of the manufacturing process;
- FIG. 6 is a comparative diagram showing doping profiles in the case of a conventional MOS-gated power device and in the case of the present invention;
- FIG. 7 is another comparative diagram showing doping profiles in the regions between elementary functional units of the MOS-gated power device;
- FIG. 8 is a comparative diagram showing the electric field distribution in the case of a conventional MOS-gated power device and in the case of the present invention;
- FIGS.9 to 11 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention;
- FIGS.12 to 17 are cross-sectional views similar to that of FIG. 1 of another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices;
- FIG. 18 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS.12 to 17;
- FIGS.19 to 24 are cross-sectional views similar to that of FIG. 1 of yet another embodiment of a manufacturing process according to the invention, particularly suitable for the manufacturing of high-voltage MOS-gated power devices; and
- FIG. 25 shows in cross-section the high-voltage MOS-gated power device obtained by the process of FIGS.19 to 24.
- With reference to the drawings, and specifically to FIG. 1, a MOS-gated power device chip according to the present invention comprises a heavily doped
semiconductor substrate 1, over which a lightly dopedsemiconductor layer 2 is formed, for example by means of an epitaxial growth. In the example shown, referring to the case of an N channel power MOSFET, both thesubstrate 1 and theepitaxial layer 2 are of the N conductivity type; differently, in a P channel power MOSFET both thesubstrate 1 and theepitaxial layer 2 would be of the P conductivity type. Also, thesubstrate 1 and theepitaxial layer 2 could be of opposite conductivity types, as in the case of a Insulated Gate Bipolar Transistor (IGBT). - The
epitaxial layer 2 forms a common drain layer for elementary functional units of the MOS-gated power device. Each elementary functional unit comprise a body region 3 of the P conductivity type (or, more generally, of the opposite conductivity type of the epitaxial layer 2). The body regions 3 can have a polygonal layout (e.g. square or hexagonal), as in the case of “cellular” MOS-gated power devices, or alternatively they can be represented by elongated stripes (in which case FIG. 1 shows a cross-section in a direction transverse to the elongated stripes). Inside each body region 3, heavily doped source regions 4 of the N conductivity type (i.e. of the same conductivity type as the epitaxial layer 2) are provided. - The top surface of the
epitaxial layer 2 is covered by an insulated gate layer comprising a thingate oxide layer 5 and apolysilicon layer 6. Openings are provided in the insulated gate layer over each body region 3. The insulated gate layer is covered by an insulating material layer 7 in which contact windows are provided over each body region 3 to allow a source metal layer 8 t contact the source regions 4 and the body regions 3. A drain metal layer 9 is also provided on the bottom surface of thesubstrate 1. Althoughregion 20 is illustrated as extending through the whole thickness of theepitaxial layer 2, one skilled in the art will appreciate thatregion 20 may extend only partially throughepitaxial layer 2. - In the
epitaxial layer 2, beneath each body region 3, aregion 20 of the same conductivity type as but having a higher resistivity than theepitaxial layer 2 is provided which extends downwardly substantially for the whole thickness of theepitaxial layer 2, to thesubstrate 1. - As a result of the presence of the
regions 20 beneath the body regions 3, it is possible to reduce the resistivity of theepitaxial layer 2 without decreasing the breakdown voltage of the MOS-gated power device, because the breakdown voltage of the MOS-gated power device depends on the resistivity and on the thickness of the portions of the common drain layer beneath the body regions, not on the portions of the common drain layer between the body regions. In other words, the presence of the lightly dopedregions 20 under the body regions 3 allows achievement of the desired breakdown voltage even with an epitaxial layer having a lower resistivity than that necessary with conventional devices. - As a consequence of the decreased resistivity of the
epitaxial layer 2, both the JFET component Fjfet and the epitaxial layer component Repi of the output resistance Ron of the MOS-gated power device are reduced, because the current flux I coming from the source regions and flowing towards thesubstrate 1 encounter a lower resistance. - Also, it is possible to reduce the distance d (FIG. 1) between adjacent elementary functional units without the drawback of an increase of the Rjfet component of the output resistance of the MOS-gated power device.
- FIG. 6 illustrates the doping profiles of the different semiconductor regions along the direction of arrow x of FIG. 1 beginning at the surface of body region3 and moving through the depth of the device towards the substrate. The dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure. The continuous line represents the doping profile of a device in accordance with the present invention.
- FIG. 7 illustrates the doping profiles of the different semiconductor regions along the direction of arrow Y of FIG. 1 beginning at the surface of the lightly doped
semiconductor layer 2 and moving through the depth of the device towards the substrate. The dash-and-dot line represents the doping profile of a conventional MOS-gated power device structure. The continuous line presents the doping profile of a device in accordance with the present invention. - FIGS. 6 and 7 illustrate depth value for low-voltage MOS-gated power devices. For high-voltage MOS-gated power devices, the width of the body region3 can be, for example, approximately 20 μm and the depth of
regions 20 can therefore be approximately 20 μm. - FIG. 8 is a diagram showing the profile of the electric field E in the two cases of FIGS. 6 and 7. From FIG. 8, one skilled in the art will appreciate that in the structure of the present invention the breakdown voltage is higher (the area subtended by the curve of the electric field E is higher in the case of the structure of the present invention (continuous line) than in the case of a conventional structure (dash-and-dot line)).
- A manufacturing process according to the invention will now be described with reference to FIGS.2-5A. Referring to FIG. 2, the lightly doped
layer 2 is epitaxially grown over the heavily dopedsubstrate 1, the thickness of theepitaxial layer 2 depends on the voltage class of the MOS-gated power device to be fabricated; for example, for low voltage devices theepitaxial layer 2 can have a thickness of about 2 or 5 μm. However, in conventional devices the resistivity of the epitaxial layer is determined on the basic of the desired breakdown voltage of the MOS-gated power device (for example 1 ohm×cm for a breakdown voltage of 60 V), in the present invention theepitaxial layer 2 has a resistivity which is lower than that necessary to achieve the same desired breakdown voltage (for example 0.6 ohm×cm). - Over the surface of the epitaxial layer2 a
thin oxide layer 5 is formed, for example by means of a thermal growth or, alternatively, a thick field oxide and an active area are formed. Apolysilicon layer 6 is then deposited over theoxide layer 5. - As illustrated in FIG. 3, the
polysilicon layer 6 and theoxide layer 5 are then selectively removed from the surface of theepitaxial layer 2 to formopenings 10. This step involves depositing aphotoresist layer 11, the selectively exposing thephotoresist layer 11 to a light source by means of a mask carrying the pattern of theopenings 10, selectively removing thephotoresist layer 11, and eching the polysilicon andoxide layers photoresist layer 11. Theopenings 10 can have a polygonal layout (for example square or hexagonal, i.e., cellular layout), or they can be elongated stripes. - The body regions3 of the elementary functional units of the MOS-gated power device are then formed. To this purpose, a P type dopant such as boron is implanted, using the polysilicon and
oxide layers 5, 6 (and if necessary also the photoresist layer 11) as a mask, in a dose ranging from 5×1013 to 5×1014 atoms/cm2, with an implantation energy in the range 80-200 KeV (FIG. 3). As illustrated in FIG. 4, a subsequent thermal diffusion of the dopants forms the body regions 3 with a surface concentration in the channel region of approximately 1017 atoms/cm3, which is a concentration necessary to achieve the desired threshold voltage of the MOS-gated power device. - Alternatively, the body regions3 can be formed by means of two distinct implants of boron in different doses and at different energies, still using the polysilicon and
oxide layers - For example, the first implant can involve a dose of a P type dopant in the range 1013-1014 atoms/cm2 with an energy of approximately 80 KeV and is used to control the dopant concentration at the surface of the body regions, especially in the channel regions, which sets the desired threshold voltage of the MOS-gated power device. The second implant can involve, for example, a dose of P type dopant in the range 1014-1015 atoms/cm2 with an energy comprised between 200 KeV and 600 KeV (for low-voltage devices, energies in the
range 100 KeV-300 KeV are suitable), such that the peak concentration of the dopants can be located at a prescribed depth, namely under the source regions which will be formed in a later step. A subsequent thermal diffusion process at a temperature in the range 1050-1100° C. for 0.5 to 2 hours determines the lateral diffusion of the dopant introduced with the first implant, to form the channel regions of the body regions extending over the gate oxide layer. The vertical diffusion of the dopant introduced with the second implant does not alter the threshold voltage of the MOS-gated power device, because the dopant ions reach the surface with a concentration lower than the concentration of the dopant introduced with the first implant (in fact, the peak dopant concentration of the dopant introduced with the first implant is located substantially at the surface of the drain layer 2). The vertical and lateral diffusion of the dopants introduced with the second implant forms the heavily doped deep body portions of the body regions, reducing the resistivity of the body regions under the source regions. - As illustrated in FIG. 5, a dopant of the P conductivity type, preferably one having a high diffusivity such as aluminium, is implanted into the
epitaxial layer 2 using the polysilicon andoxide layers 5, 6 (and if necessary the photoresist layer 11) as a mask. The implant dose is suitable to partially compensate, but not to invert, the N type doping level of the epitaxial layer, so as to substantially increase the resistivity of those portions of theepitaxial layer 2 wherein such a dopant is implanted. The implantation energy (ranging from 700 KeV to 1 MeV or more) is such as to locate the peak concentration of the dopant as close as possible to a body-drain junction (1.5-2 μm from the surface of the epitaxial layer 2). - Alternatively, as shown in FIG. 5A, the implant mask for the high-diffusivity dopant could be formed by another
photoresist layer 111 withsmaller openings 100 than theopenings 10 in the polysilicon andoxide layers - Subsequently, a high dose of a N type dopant (such as arsenic or phosphorus) is then selectively implanted into the body regions3 to form the source regions 4. The N type dopant is then made to diffuse by means of a thermal process. During such thermal process, the source dopant diffuses for a depth of about 0.4-0.5 μm in the case of arsenic, or about 0.6-0.7 μm in the case of phosphorus. During the same thermal process, the high-diffusivity dopant diffuses for a depth of about 1.5-2 μm, distributing in a controlled manner under all the body regions 3 substantially to the
substrate 1, modifying the doping profile of theepitaxial layer 2 under the body regions 3 to increase the resistivity of theepitaxial layer 2 in these regions. - The following process steps involve forming a layer of insulating material7 over the whole surface of the chip, openings contact windows in the insulating layer 7 over the body regions 3, and forming a
source metal layer 8 and a drain metal layer 9. - If the budget of the thermal diffusion process used to diffuse the source dopant is not sufficient to completely diffuse the high-voltage devices with a thick epitaxial layer, it is possible to modify the thermal diffusion process of the source dopant, or to invert the described sequence of steps, for example implanting the high-diffusivity dopant before the step of formation of the body regions3, to exploit the thermal diffusion process of the body regions.
- FIGS.9 to 11 show three steps of another embodiment of the manufacturing process of the invention. In this embodiment, an N−
epitaxial layer 2 grown oversubstrate 1 has a resistivity value suitable for sustaining the desired breakdown voltage, i.e. 2-5 ohm/cm for a device rated for 30-200V. - Then, by means of a mask70 (FIG. 10), an N type dopant is implanted into the
epitaxial layer 2 in regions thereof that will lie between the body regions. The dose and energy of the implanted dopant is chosen so to form N− regions less resistive than the N−layer 2. A suitable dose is for example 1012-1013 atoms/cm2. In this way, N− regions are formed in the N− layer which have a resistivity of 0.5-5 Ω/cm depending on the devices's voltage ratings. Then (FIG. 11), similarly to what is shown in FIG. 3, a p type dopant is implanted to form the body regions 3 between the N− regions. - FIGS.12 to 18 and 19 to 25 show, in cross-sectional views similar to that of FIG. 1, the main steps of two further alternative embodiments of a manufacturing process according to the present invention. Such embodiments are particularly suitable for manufacturing high-voltage devices, capable of sustaining voltages of 400 to 1000 V or more. A unique aspect of these devices is that, in order to sustain such voltage values, the thickness of the drain layer has to be in the
range 30 to 80 μm or even more. The size of the elementary functional units, be they cells or stripes, varies instead from 5 to 15 μm. - Clearly, in view of the substantial thickness of the drain layer, the manufacturing processes previously described, providing for a single implantation from the front of the device, could prove not suitable for forming N− regions extending sufficiently in the drain layer under the body regions.
- The two embodiments which will be now described overcome the above problem.
- Referring to FIG. 12, a first lightly doped
epitaxial layer 21 of the N conductivity type is formed over theN+ substrate 1.Epitaxial layer 21 has a thickness X1 approximately equal to the size of the elementary functional units, be they cells or stripes, i.e., for example, 5 to 15 μm. The thickness X1 ofepitaxial layer 21 is much lower, e.g. one third or less, than the overall thickness of the drain layer of the final device. The doping level ofepitaxial layer 21 is higher than that required for assuring that the device keeps the desired high voltage. A doping level of 5-9*1014 atoms/cm3 (5-10 ohm/cm) is suitable. - Referring to FIG. 13, an
oxide layer 24 is then formed over the top surface ofepitaxial layer 21. Theoxide layer 24 is then selectively removed from the areas wherein the elementary cells or stripes will be formed. The size L of the openings in theoxide layer 24 is slightly less than the size of the memory cells or stripes. Alternatively, a photoresist layer can be used instead of theoxide layer 24. - Referring to FIG. 14, a P type dopant such as boron or aluminum is then selectively implanted into the
epitaxial layer 21, using theoxide layer 24 as a mask or, alternatively, the photoresist layer. A suitable implantation energy must be higher that 200 KeV, for example in the range 200 to 500 KeV. The implant dose is chosen in such a way that, after the thermal diffusion processes that will follow, the implanted P type dopant partially compensates, but does not invert, the N type doping of theepitaxial layer 21. A suitable dose ranges from 1*1012 to 1*1013 atoms/cm2. - Referring to FIG. 15, the
oxide layer 24 is then completely removed and then a second lightly dopedepitaxial layer 22 of the N conductivity type is formed over thefirst epitaxial layer 21. Preferably, the thickness X2 of thesecond epitaxial layer 22 and its dopant concentration are respectively similar to the thickness X1 and dopant concentration of thefirst epitaxial layer 21. During the growth of thesecond epitaxial layer 22, that as known involves a thermal process, the P type dopant previously implanted diffuses into the first and second epitaxial layers 21, 22, thus forming N−regions 201 having dopant concentration approximately lower than or equal to 1013 atoms/cm3. - Referring to FIG. 16, another oxide layer25 is then formed over the
second epitaxial layer 22. The oxide layer 25 is then selectively removed using the same photolithographic mask previously used to removeoxide layer 24. A P type dopant such as boron or aluminum is then selectively implanted using the oxide layer 25 as a mask, as in the step depicted in FIG. 11. The implantation dose and energy are chosen in the same way as before. - Referring to FIG. 17, the oxide layer25 is then completely removed, and a third lightly doped
epitaxial layer 23 of the N conductivity type is formed over thesecond epitaxial layer 22. Preferably, the thickness X3 and the dopant concentration of thethird epitaxial layer 23 are respectively similar to the thickness X2 and the dopant concentration of thesecond epitaxial layer 22. During the growth of thethird epitaxial layer 23, that involves a thermal process, the P type dopant previously implanted diffuses into the second and third epitaxial layers 22, 23, to form N− regions 202, and also regions 202 further diffuse vertically. In this way, N− regions 202 and N−regions 201 merge, forming columns of stacked N−regions 202, 201. The dopant concentration of N−regions 202 and 201 is suitable to sustain the desired high voltage. - The subsequent steps are similar to those of the processes according to the first two embodiments described. Clearly, the body regions of the elementary functional units will have to be formed in the
third epitaxial layer 23 over the stacked N−regions 201 and 202, as shown in FIG. 18. - As an alternative, instead of performing into each of the
epitaxial layers 21 and 22 a single implant, several implants can be performed in succession into each of theepitaxial layers form 5*1011 to 1*1013 atoms/cm2, and the energies range from 200 KeV to 900 KeV or more. For example, where the implanted dopant is boran, three implants at 300 KeV, 600 KeV and 900 KeV or more can be performed, so as to have peak dopant concentrations located at a depth of 0.7 μm, 1.2 μm and 1.7 μm, respectively. - In this way, “box” shaped concentration profiles are obtained.
- Another manufacturing process particularly suitable for high-voltage devices is depicted in FIGS.19 to 25.
- Referring to FIG. 19, as in the last-described process, a first lightly doped
epitaxial layer 21 of the N type and thickness X1 is formed over theN+ substrate 1. The dopant concentration of thefirst epitaxial layer 201 is that required for making the final device capable of sustaining the high voltage (that is, by comparison with the process depicted in FIGS. 12 to 18, the dopant concentration oflayer 21 is similar to the dopant concentration of N−regions 201 and 202, i.e. 3-5*1013 atoms/cm3 (80-150 ohms/cm). - Referring to FIG. 20, an
oxide layer 26 is formed over thefirst epitaxial layer 21. Theoxide layer 26 is then selectively removed from the regions oflayer 21 which will lie between the body regions of the elementary functional units of the device. The size LD of the openings in the oxide layer is slightly lower than the distance between the elementary functional units to be formed later on. Alternatively, a photoresist layer can be used instead of theoxide layer 26. - Then, referring to FIG. 21, an N type dopant is implanted into the
first epitaxial layer 21 using the oxide layer 26 (or alternatively the photoresist layer) as a mask. Suitable implantation dose and energy are respectively 1*1012-1013 atoms/cm2 and more than 200 KeV (e.g. 200-500 KeV). - Referring to FIG. 22, the
oxide layer 26 is then completely removed, and asecond epitaxial layer 22 is formed over thefirst epitaxial layer 21. Preferably, the thickness X2 and dopant concentration of thesecond epitaxial layer 22 are respectively similar to the thickness X1 and dopant concentration of thefirst epitaxial layer 21. During the thermal process involved in the epitaxial growth of thesecond epitaxial layer 22, the N type dopant previously implanted diffuses into thefirst epitaxial layer 21 and thesecond epitaxial layer 22, to form enriched N−regions 300 having a higher dopant concentration than the N−epitaxial layers - Referring to FIG. 23, another
oxide layer 27 is then formed over thesecond epitaxial layer 22.Oxide layer 27 is then selectively removed by means of the same mask used to selectively removedoxide layer 26. An N type dopant is then selectively implanted into thesecond epitaxial layer 22 usingoxide layer 27 as a mask. - Referring to FIG. 24, the
oxide layer 27 is then completely removed, and a third lightly dopedepitaxial layer 23 of the N conductivity type is formed over thesecond epitaxial layer 22. Preferably, the thickness X3 and dopant concentration of thethird epitaxial layer 23 are respectively similar to the thickness X2 and dopant concentration of the second epitaxial layer. During the thermal process involved in the epitaxial growth of thethird epitaxial layer 23, the implanted N type dopant diffuses into the second and third epitaxial layers 22, 23, to form enriched N−regions 301 over the enriched N−regions 300 previously formed. The latter also diffuse further into the first and second epitaxial layers 21, 22, so that at theend regions 301 merge withregions 300. In this way, stacked enriched N−regions - The following steps are completely similar to those of the first two processes described. Clearly, the body regions of the elementary functional units, be they cells or stripes, are to be formed in the
third epitaxial layer 23 in the regions thereof between the N−regions - Clearly, in both of the two embodiments just described, the number of stacked epitaxial layers can be different from three. The number of epitaxial layers to be formed depends on the overall thickness of the drain layer of the final device, i.e., on the voltage to be sustained by the power device.
- Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.
Claims (19)
1. A process for the manufacturing of a MOS-gated power device, comprising the steps of:
a) forming a heavily doped semiconductor substrate;
b) forming a semiconductor layer of a first conductivity type and with a first resistivity value;
c) selectively introducing into the semiconductor layer a dopant suitable for forming first regions of the first conductivity type and with a second resistivity value, intercalated by second regions of the first conductivity type with the first resistivity value;
d) forming on the semiconductor layer a conductive insulated gate layer;
e) selectively removing the conductive insulated gate layer to open windows over selected portions of a surface of the semiconductor layer, said selected portions of the surface being located over those among the first regions and the second regions which have a higher resistivity value;
f) forming at said selected portions of the surface of the semiconductor layer body regions of a second conductivity type;
g) forming in the body regions source regions of the first conductivity type.
2. The process according to claim 1 , wherein said dopant is of the first conductivity type, and it is introduced into the semiconductor layer in a dose suitable to make the second resistivity value lower than said first resistivity value, the windows in the insulated gate layer being located over said second region.
3. The process of claim 1 , providing for:
a) forming the heavily doped semiconductor substrate;
b) forming a lightly doped semiconductor layer of a first conductivity type and with a first resistivity value;
c) selectively introducing into the lightly doped semiconductor layer a dopant suitable for forming first regions of the first conductivity type and with a second resistivity value, intercalated by second regions of the first conductivity type with the first resistivity value;
d) forming on the lightly doped semiconductor layer a top lightly doped semiconductor layer of the first conductivity type and having substantially the first resistivity value;
e) forming on the top lightly doped layer a conductive insulated gate layer;
f) selectively removing the conductive insulated gate layer to open windows over selected portions of a surface of the semiconductor layer, said selected portions of the surface being located over those among the first regions and the second regions which have a higher resistivity value;
g) forming at said selected portions of the surface of the top lightly doped semiconductor layer body regions of a second conductivity type;
h) forming in the body regions source regions of the first conductivity type.
4. The process according to claim 3 , wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer in a dose suitable to compensate, but not to invert, a concentration of dopant of the first conductivity type of the lightly doped semiconductor layer, so that said second resistivity value is higher than said first resistivity value, the windows in the insulated gate layer being located over said first regions.
5. The process of claim 4 , wherein said lightly doped semiconductor layer has a concentration of dopant of approximately 5-9*1014 atoms/cm3, corresponding to a resistivity of 5-10 ohms/cm.
6. The process of claim 5 , wherein said top lightly doped semiconductor layer has a concentration of dopant of approximately equal to that of the lightly doped semiconductor layer.
7. The process of claim 6 , wherein said dopant is introduced by ion implantation, in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 100 KeV.
8. The process of claim 3 , wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer in a dose suitable to make the second resistivity value lower than the first resistivity value, the windows in the insulated gate layer being located over said second regions.
9. The process of claim 8 , wherein said lightly doped semiconductor layer has a dopant concentration of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
10. The process of claim 9 , wherein said top lightly doped semiconductor layer has a dopant concentration of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
11. The process of claim 10 , wherein said dopant is introduced by ion implantation, in a dose of 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200 KeV.
12. The process of claim 3 , further providing for repeating steps b) and c) at least one time, for forming over the lightly doped semiconductor layer of the first conductivity type and with the first resistivity value at least one intermediate lightly doped layer of the first resistivity type and with the first resistivity value, and for selectively introducing into the at least one intermediate lightly doped semiconductor layer a dopant suitable for forming third regions of the first conductivity type and with the second resistivity value, intercalated by fourth regions of the first conductivity type with the first resistivity value, said third regions and fourth regions being disposed over the first regions and the second regions, respectively.
13. The process of claim 12 , wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have approximately similar thickness.
14. The process of claim 13 , wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have similar dopant concentrations of approximately 5-9*1014 atoms/cm3, corresponding to a resistivity of 5-10 ohms/cm.
15. The process of claim 14 , wherein said dopant is of the second conductivity type, and it is introduced into the lightly doped semiconductor layer and the intermediate lightly doped semiconductor layer in a dose suitable to compensate, but not to invert, a concentration of dopant of the first conductivity type of the lightly doped semiconductor layer and the intermediate lightly doped semiconductor layer, so that said second resistivity value is higher than said first resistivity value, the windows in the insulated gate layer being located over said first regions.
16. The process of claim 15 , wherein said dopant is introduced into the lightly doped semiconductor layer and into the intermediate lightly doped semiconductor layer by ion implantation, in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200 KeV.
17. The process of claim 13 wherein the lightly doped semiconductor layer, the intermediate lightly doped semiconductor layer and the top lightly doped semiconductor layer have similar dopant concentrations of approximately 3-5*1013 atoms/cm3, corresponding to a resistivity of 80-150 ohms/cm.
18. The process of claim 17 , wherein said dopant is of the first conductivity type, and it is introduced into the lightly doped semiconductor layer and into the intermediate lightly doped semiconductor layer in a dose suitable to make the second resistivity value lower than the first resistivity value, the windows in the insulated gate layer being located over said second regions.
19. The process of claim 18 , wherein said dopant is introduced into the lightly doped semiconductor layer and into the intermediate semiconductor layer in a dose of approximately 1*1012 to 1*1013 atoms/cm2 and with an energy higher than 200.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/006,778 US20020123195A1 (en) | 1995-11-06 | 2001-11-05 | MOS technology power device with low output resistance and low capacity, and related manufacturing process |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95830468.5 | 1995-11-06 | ||
EP95830468A EP0772244B1 (en) | 1995-11-06 | 1995-11-06 | MOS technology power device with low output resistance and low capacity and related manufacturing process |
US08/740,713 US5900662A (en) | 1995-11-06 | 1996-11-04 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
US09/235,067 US6228719B1 (en) | 1995-11-06 | 1999-01-21 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
US80008101A | 2001-03-05 | 2001-03-05 | |
US10/006,778 US20020123195A1 (en) | 1995-11-06 | 2001-11-05 | MOS technology power device with low output resistance and low capacity, and related manufacturing process |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/740,713 Continuation-In-Part US5900662A (en) | 1995-11-06 | 1996-11-04 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
US80008101A Continuation | 1995-11-06 | 2001-03-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020123195A1 true US20020123195A1 (en) | 2002-09-05 |
Family
ID=26140767
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/235,067 Expired - Lifetime US6228719B1 (en) | 1995-11-06 | 1999-01-21 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
US10/006,778 Abandoned US20020123195A1 (en) | 1995-11-06 | 2001-11-05 | MOS technology power device with low output resistance and low capacity, and related manufacturing process |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/235,067 Expired - Lifetime US6228719B1 (en) | 1995-11-06 | 1999-01-21 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
Country Status (1)
Country | Link |
---|---|
US (2) | US6228719B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030181010A1 (en) * | 2002-03-21 | 2003-09-25 | Blanchard Richard A. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US7060567B1 (en) * | 2005-07-26 | 2006-06-13 | Episil Technologies Inc. | Method for fabricating trench power MOSFET |
US20100084583A1 (en) * | 2008-10-06 | 2010-04-08 | Hatem Christopher R | Reduced implant voltage during ion implantation |
US20120135587A1 (en) * | 2009-04-08 | 2012-05-31 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69534919T2 (en) | 1995-10-30 | 2007-01-25 | Stmicroelectronics S.R.L., Agrate Brianza | Power device in MOS technology with a single critical size |
EP0772241B1 (en) | 1995-10-30 | 2004-06-09 | STMicroelectronics S.r.l. | High density MOS technology power device |
DE19922187C2 (en) * | 1999-05-12 | 2001-04-26 | Siemens Ag | Low-resistance VDMOS semiconductor component and method for its production |
US6461918B1 (en) * | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
US6346463B1 (en) * | 2000-05-05 | 2002-02-12 | Advanced Micro Devices, Inc. | Method for forming a semiconductor device with a tailored well profile |
US6969909B2 (en) * | 2002-12-20 | 2005-11-29 | Vlt, Inc. | Flip chip FET device |
US7038917B2 (en) * | 2002-12-27 | 2006-05-02 | Vlt, Inc. | Low loss, high density array interconnection |
EP1710843B1 (en) * | 2005-04-04 | 2012-09-19 | STMicroelectronics Srl | Integrated power device |
US8304311B2 (en) | 2006-04-11 | 2012-11-06 | Stmicroelectronics S.R.L. | Process for manufacturing a semiconductor power device comprising charge-balance column structures and respective device |
WO2007122646A1 (en) | 2006-04-21 | 2007-11-01 | Stmicroelectronics S.R.L. | Process for manufacturing a power semiconductor device and corresponding power semiconductor device |
US7944035B2 (en) * | 2006-05-22 | 2011-05-17 | International Rectifier Corporation | Double sided semiconduction device with edge contact and package therefor |
EP1873837B1 (en) | 2006-06-28 | 2013-03-27 | STMicroelectronics Srl | Semiconductor power device having an edge-termination structure and manufacturing method thereof |
US7687891B2 (en) * | 2007-05-14 | 2010-03-30 | Infineon Technologies Ag | Diode having one or more zones of a first conductivity type and one or more zones of a second conductivity type each located within a layer of the second conductivity type |
EP2058862B1 (en) * | 2007-11-09 | 2018-09-19 | ams AG | Field-effect transistor and method for producing a field-effect transistor. |
KR100960475B1 (en) * | 2008-05-28 | 2010-06-01 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
CN101630683B (en) | 2008-07-15 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Integrated electrostatic discharge device |
KR101578931B1 (en) * | 2008-12-05 | 2015-12-21 | 주식회사 동부하이텍 | Semiconductor device |
IT1397574B1 (en) | 2008-12-29 | 2013-01-16 | St Microelectronics Rousset | MULTI-DRAIN TYPE POWER SEMICONDUCTOR DEVICE AND RELATIVE ON-BOARD TERMINATION STRUCTURE |
US20110049638A1 (en) * | 2009-09-01 | 2011-03-03 | Stmicroelectronics S.R.L. | Structure for high voltage device and corresponding integration process |
US8901652B2 (en) * | 2009-09-01 | 2014-12-02 | Stmicroelectronics S.R.L. | Power MOSFET comprising a plurality of columnar structures defining the charge balancing region |
WO2012020290A2 (en) | 2010-07-26 | 2012-02-16 | Stmicroelectronics S.R.L. | Process for filling deep trenches in a semiconductor material body, and semiconductor device resulting from the same process |
US9685523B2 (en) * | 2014-12-17 | 2017-06-20 | Alpha And Omega Semiconductor Incorporated | Diode structures with controlled injection efficiency for fast switching |
US9070765B2 (en) | 2013-02-06 | 2015-06-30 | Infineon Technologies Ag | Semiconductor device with low on resistance and high breakdown voltage |
ITTO20130410A1 (en) | 2013-05-22 | 2014-11-23 | St Microelectronics Srl | SUPER-JUNCTION POWER DEVICE AND ITS MANUFACTURING PROCEDURE |
US9899508B1 (en) | 2016-10-10 | 2018-02-20 | Stmicroelectronics S.R.L. | Super junction semiconductor device for RF applications, linear region operation and related manufacturing process |
IT201700113926A1 (en) | 2017-10-10 | 2019-04-10 | St Microelectronics Srl | POWER MOSFET DEVICE AND ITS MANUFACTURING PROCEDURE |
IT201800006323A1 (en) | 2018-06-14 | 2019-12-14 | SEMICONDUCTOR DEVICE OF THE CHARGE BALANCING TYPE, IN PARTICULAR FOR HIGH EFFICIENCY RF APPLICATIONS, AND RELATED MANUFACTURING PROCESS | |
US11728422B2 (en) * | 2019-11-14 | 2023-08-15 | Stmicroelectronics S.R.L. | Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof |
IT202000015076A1 (en) | 2020-06-23 | 2021-12-23 | St Microelectronics Srl | ELECTRONIC DEVICE IN 4H-SIC WITH IMPROVED SHORT-CIRCUIT PERFORMANCE, AND RELATED MANUFACTURING METHOD |
Family Cites Families (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5144388B2 (en) | 1974-08-20 | 1976-11-27 | ||
JPS5148981A (en) | 1974-10-25 | 1976-04-27 | Nippon Electric Co | ZETSUENGEETOGATADENKAIKOKAHANDOTAISOCHI |
US4015278A (en) | 1974-11-26 | 1977-03-29 | Fujitsu Ltd. | Field effect semiconductor device |
JPS5185381A (en) | 1975-01-24 | 1976-07-26 | Hitachi Ltd | |
JPS5265943A (en) | 1975-11-27 | 1977-05-31 | Nippon Kokan Kk | Method and boat for burying earth and sand |
JPS52132684A (en) | 1976-04-29 | 1977-11-07 | Sony Corp | Insulating gate type field effect transistor |
JPS5366181A (en) | 1976-11-26 | 1978-06-13 | Hitachi Ltd | High dielectric strength mis type transistor |
US4055884A (en) | 1976-12-13 | 1977-11-01 | International Business Machines Corporation | Fabrication of power field effect transistors and the resulting structures |
JPS5374385A (en) | 1976-12-15 | 1978-07-01 | Hitachi Ltd | Manufacture of field effect semiconductor device |
JPS53135284A (en) | 1977-04-30 | 1978-11-25 | Nec Corp | Production of field effect transistor |
JPS5553462A (en) | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
DK157272C (en) | 1978-10-13 | 1990-04-30 | Int Rectifier Corp | MOSPHET WITH HIGH POWER |
US5191396B1 (en) | 1978-10-13 | 1995-12-26 | Int Rectifier Corp | High power mosfet with low on-resistance and high breakdown voltage |
US4705759B1 (en) | 1978-10-13 | 1995-02-14 | Int Rectifier Corp | High power mosfet with low on-resistance and high breakdown voltage |
US5008725C2 (en) | 1979-05-14 | 2001-05-01 | Internat Rectifer Corp | Plural polygon source pattern for mosfet |
US5130767C1 (en) | 1979-05-14 | 2001-08-14 | Int Rectifier Corp | Plural polygon source pattern for mosfet |
JPS55163877A (en) | 1979-06-06 | 1980-12-20 | Toshiba Corp | Semiconductor integrated circuit device |
US4344081A (en) | 1980-04-14 | 1982-08-10 | Supertex, Inc. | Combined DMOS and a vertical bipolar transistor device and fabrication method therefor |
US4345265A (en) | 1980-04-14 | 1982-08-17 | Supertex, Inc. | MOS Power transistor with improved high-voltage capability |
US4593302B1 (en) | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
US4680853A (en) | 1980-08-18 | 1987-07-21 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4399449A (en) | 1980-11-17 | 1983-08-16 | International Rectifier Corporation | Composite metal and polysilicon field plate structure for high voltage semiconductor devices |
US4412242A (en) | 1980-11-17 | 1983-10-25 | International Rectifier Corporation | Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions |
US4414560A (en) | 1980-11-17 | 1983-11-08 | International Rectifier Corporation | Floating guard region and process of manufacture for semiconductor reverse conducting switching device using spaced MOS transistors having a common drain region |
JPS58206174A (en) | 1982-05-26 | 1983-12-01 | Toshiba Corp | Mesa type semiconductor device and manufacture thereof |
US4974059A (en) | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
EP0119400B1 (en) | 1983-02-17 | 1987-08-05 | Nissan Motor Co., Ltd. | A vertical-type mosfet and method of fabricating the same |
US5286984A (en) | 1984-05-30 | 1994-02-15 | Kabushiki Kaisha Toshiba | Conductivity modulated MOSFET |
US4605948A (en) | 1984-08-02 | 1986-08-12 | Rca Corporation | Semiconductor structure for electric field distribution |
EP0211972A1 (en) | 1985-08-07 | 1987-03-04 | Eaton Corporation | Raised gate efet |
JPS6247162A (en) | 1985-08-27 | 1987-02-28 | Matsushita Electric Works Ltd | Manufacture of insulated gate field effect transistor |
US4798810A (en) | 1986-03-10 | 1989-01-17 | Siliconix Incorporated | Method for manufacturing a power MOS transistor |
US4816882A (en) | 1986-03-10 | 1989-03-28 | Siliconix Incorporated | Power MOS transistor with equipotential ring |
JPH0758782B2 (en) | 1986-03-19 | 1995-06-21 | 株式会社東芝 | Semiconductor device |
US4716126A (en) | 1986-06-05 | 1987-12-29 | Siliconix Incorporated | Fabrication of double diffused metal oxide semiconductor transistor |
JPH07120794B2 (en) | 1986-07-09 | 1995-12-20 | 株式会社東芝 | MOS semiconductor device |
EP0279403A3 (en) | 1987-02-16 | 1988-12-07 | Nec Corporation | Vertical mos field effect transistor having a high withstand voltage and a high switching speed |
JPH01272163A (en) | 1987-08-07 | 1989-10-31 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
JPS6445173A (en) | 1987-08-13 | 1989-02-17 | Fuji Electric Co Ltd | Conductive modulation type mosfet |
JPH0766968B2 (en) | 1987-08-24 | 1995-07-19 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
DE3902300C3 (en) | 1988-01-30 | 1995-02-09 | Toshiba Kawasaki Kk | Shutdown thyristor |
US5418179A (en) | 1988-05-31 | 1995-05-23 | Yamaha Corporation | Process of fabricating complementary inverter circuit having multi-level interconnection |
JPH0783119B2 (en) | 1988-08-25 | 1995-09-06 | 日本電気株式会社 | Field effect transistor |
US4901127A (en) | 1988-10-07 | 1990-02-13 | General Electric Company | Circuit including a combined insulated gate bipolar transistor/MOSFET |
JPH02143566A (en) | 1988-11-25 | 1990-06-01 | Toshiba Corp | Double diffusion type insulated gate field effect transistor |
JPH0834312B2 (en) | 1988-12-06 | 1996-03-29 | 富士電機株式会社 | Vertical field effect transistor |
JP2787921B2 (en) | 1989-01-06 | 1998-08-20 | 三菱電機株式会社 | Insulated gate bipolar transistor |
JPH02239670A (en) | 1989-03-14 | 1990-09-21 | Fujitsu Ltd | Semiconductor device |
US4998151A (en) | 1989-04-13 | 1991-03-05 | General Electric Company | Power field effect devices having small cell size and low contact resistance |
JPH077750B2 (en) | 1989-05-15 | 1995-01-30 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPH02312280A (en) | 1989-05-26 | 1990-12-27 | Mitsubishi Electric Corp | Insulated gate bipolar transistor |
US4927772A (en) | 1989-05-30 | 1990-05-22 | General Electric Company | Method of making high breakdown voltage semiconductor device |
US5208471A (en) | 1989-06-12 | 1993-05-04 | Hitachi, Ltd. | Semiconductor device and manufacturing method therefor |
JP2689703B2 (en) | 1989-08-03 | 1997-12-10 | 富士電機株式会社 | MOS type semiconductor device |
US5119153A (en) | 1989-09-05 | 1992-06-02 | General Electric Company | Small cell low contact resistance rugged power field effect devices and method of fabrication |
US4931408A (en) | 1989-10-13 | 1990-06-05 | Siliconix Incorporated | Method of fabricating a short-channel low voltage DMOS transistor |
JPH03185737A (en) | 1989-12-14 | 1991-08-13 | Toshiba Corp | Manufacture of semiconductor device |
JP2573736B2 (en) | 1990-09-18 | 1997-01-22 | 三菱電機株式会社 | High breakdown voltage low resistance semiconductor device and method of manufacturing the same |
DE69029942T2 (en) | 1990-10-16 | 1997-08-28 | Sgs Thomson Microelectronics | Method of manufacturing vertical current MOS power transistors |
JPH04256367A (en) | 1991-02-08 | 1992-09-11 | Hitachi Ltd | Semiconductor element |
JPH04349660A (en) | 1991-05-28 | 1992-12-04 | Toshiba Corp | Semiconductor devicce and its manufacture |
JP3156300B2 (en) | 1991-10-07 | 2001-04-16 | 株式会社デンソー | Vertical semiconductor device |
JPH05206470A (en) | 1991-11-20 | 1993-08-13 | Nec Corp | Insulated gate field effect transistor |
GB9207849D0 (en) | 1992-04-09 | 1992-05-27 | Philips Electronics Uk Ltd | A semiconductor device |
FR2698486B1 (en) | 1992-11-24 | 1995-03-10 | Sgs Thomson Microelectronics | Direct overvoltage protection structure for vertical semiconductor component. |
US5317184A (en) | 1992-11-09 | 1994-05-31 | Harris Corporation | Device and method for improving current carrying capability in a semiconductor device |
DE69325645T2 (en) | 1993-04-21 | 1999-12-09 | Cons Ric Microelettronica | Integrated protection circuit structure for the protection of logic MOS power semiconductor components from electrostatic discharges |
JPH06342914A (en) | 1993-06-01 | 1994-12-13 | Nec Corp | Manufacture of semiconductor device |
DE69331052T2 (en) | 1993-07-01 | 2002-06-06 | Cons Ric Microelettronica | Integrated edge structure for high-voltage semiconductor devices and the associated manufacturing process |
JP2870402B2 (en) | 1994-03-10 | 1999-03-17 | 株式会社デンソー | Insulated gate field effect transistor |
US5539232A (en) | 1994-05-31 | 1996-07-23 | Kabushiki Kaisha Toshiba | MOS composite type semiconductor device |
EP0696054B1 (en) | 1994-07-04 | 2002-02-20 | STMicroelectronics S.r.l. | Process for the manufacturing of high-density MOS-technology power devices |
DE69428894T2 (en) | 1994-08-02 | 2002-04-25 | St Microelectronics Srl | Bipolar transistor with isolated control electrode |
US5795793A (en) | 1994-09-01 | 1998-08-18 | International Rectifier Corporation | Process for manufacture of MOS gated device with reduced mask count |
US5798554A (en) | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
DE69534919T2 (en) * | 1995-10-30 | 2007-01-25 | Stmicroelectronics S.R.L., Agrate Brianza | Power device in MOS technology with a single critical size |
EP0782201B1 (en) | 1995-12-28 | 2000-08-30 | STMicroelectronics S.r.l. | MOS-technology power device integrated structure |
-
1999
- 1999-01-21 US US09/235,067 patent/US6228719B1/en not_active Expired - Lifetime
-
2001
- 2001-11-05 US US10/006,778 patent/US20020123195A1/en not_active Abandoned
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030181010A1 (en) * | 2002-03-21 | 2003-09-25 | Blanchard Richard A. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US6686244B2 (en) * | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US20040157384A1 (en) * | 2002-03-21 | 2004-08-12 | Blanchard Richard A. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US7084455B2 (en) | 2002-03-21 | 2006-08-01 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer |
US20060267083A1 (en) * | 2002-03-21 | 2006-11-30 | Blanchard Richard A | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US7586148B2 (en) | 2002-03-21 | 2009-09-08 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed by terraced trenches |
US7060567B1 (en) * | 2005-07-26 | 2006-06-13 | Episil Technologies Inc. | Method for fabricating trench power MOSFET |
US20100084583A1 (en) * | 2008-10-06 | 2010-04-08 | Hatem Christopher R | Reduced implant voltage during ion implantation |
US20120135587A1 (en) * | 2009-04-08 | 2012-05-31 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
US8343863B2 (en) * | 2009-04-08 | 2013-01-01 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
US8476152B2 (en) | 2009-04-08 | 2013-07-02 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
US8642431B2 (en) | 2009-04-08 | 2014-02-04 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
Also Published As
Publication number | Publication date |
---|---|
US6228719B1 (en) | 2001-05-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6228719B1 (en) | MOS technology power device with low output resistance and low capacitance, and related manufacturing process | |
US5900662A (en) | MOS technology power device with low output resistance and low capacitance, and related manufacturing process | |
US7084034B2 (en) | High voltage MOS-gated power device and related manufacturing process | |
US5981998A (en) | Single feature size MOS technology power device | |
US5637898A (en) | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance | |
CN1163973C (en) | Trench DMOS transistor structure having low resistance path to drain contact located on upper surface | |
US7161208B2 (en) | Trench mosfet with field relief feature | |
EP0693773B1 (en) | VDMOS power device and manufacturing process thereof | |
JP2005505921A (en) | Semiconductor power device having a floating island voltage sustaining layer | |
US6030870A (en) | High density MOS technology power device | |
US6784488B2 (en) | Trench-gate semiconductor devices and the manufacture thereof | |
US6040212A (en) | Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage | |
US6221719B1 (en) | Process for the manufacturing of a DMOS-technology transistor providing for a single thermal process for the formation of source and body regions | |
JP3895110B2 (en) | Method for manufacturing body region of vertical MOS transistor device with reduced intrinsic switch-on resistance | |
KR0149705B1 (en) | A structure of the insulated gate bipolar transistor and manufacturing method of the same | |
US5970343A (en) | Fabrication of conductivity enhanced MOS-gated semiconductor devices | |
US20230142541A1 (en) | Superjunction semiconductor device and method for manufacturing same | |
KR20040065224A (en) | Trench-gate semiconductor devices and the manufacture thereof | |
US6285056B1 (en) | Conductivity enhanced MOS-gated semiconductor devices | |
KR20150108485A (en) | Method for reducing on resistance of Power MOSFET JFET area by double implanting ion |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |