US20020098643A1 - Method of manufacturing SOI element having body contact - Google Patents

Method of manufacturing SOI element having body contact Download PDF

Info

Publication number
US20020098643A1
US20020098643A1 US10/107,657 US10765702A US2002098643A1 US 20020098643 A1 US20020098643 A1 US 20020098643A1 US 10765702 A US10765702 A US 10765702A US 2002098643 A1 US2002098643 A1 US 2002098643A1
Authority
US
United States
Prior art keywords
region
body contact
insulator
formed
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/107,657
Inventor
Shigeru Kawanaka
Takashi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP9-046688 priority Critical
Priority to JP04668897A priority patent/JP3441330B2/en
Priority to US3221498A priority
Priority to US09/956,575 priority patent/US6403405B1/en
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to US10/107,657 priority patent/US20020098643A1/en
Publication of US20020098643A1 publication Critical patent/US20020098643A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact

Abstract

A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application is a continuation of co-pending U.S. patent application Ser. No. 09/032,214, filed on Feb. 27, 1998, priority of which is hereby claimed under 35 U.S.C. § 120. The present application also claims priority under 35 U.S.C. § 119 and Rule 55 to Japanese patent Application No. 9-046688, filed on Feb. 28, 1997. All of these applications are expressly incorporated herein by reference as though fully set forth in full.[0001]
  • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a SOI (Silicon On Insulator) type semiconductor device and a method of manufacturing the same. [0002]
  • As the reduction in power consumption of semiconductor integrated circuits and the enhancement in mounting density thereof are furthered, the miniaturization of the individual elements constituting the integrated circuits and the lowering in operating voltages thereof are strongly desired. In the case of a conventional bulk planar type elements, as a result of the miniaturization of the elements and the reduction in channel length thereof, a short-channel effect is actualized; and, in order to prevent it, technical measures such as the enhancement of the impurity density in the substrate, the thinning of the gate insulator, etc. have been taken in accordance with several element size-reduction rules. However, as a matter of fact, as the elements are further and further miniaturized, the existence of some physical limits is encountered; and thus, in order to achieve a further miniaturization, some novel element structures have come to be proposed. As one such novel element structure, there can be pointed out a SOI element which has an insulator under an active region thereof. [0003]
  • Next, typical examples of the structure of an SOI element and the method of the manufacturing the same will be described below. First, FIG. 1 shows a sectional view taken along the direction of the channel length of the SOI element. On a monocrystalline silicon (Si) semiconductor substrate [0004] 1, a monocrystalline silicon (Si) active layer 3 is formed through, e.g. a silicon oxide layer (SiO2) 2, and further, a gate electrode 9 is formed through, e.g. a silicon oxide layer (SiO2) 8 which is to be used as a gate insulator. Further, a source region 4-1 and a drain region 4-2 are formed by introducing, by the use of ion implantation method, an impurity of the conductivity type opposite to that of a silicon active layer 4-3 which is to be used as a channel region.
  • However, the SOI element which has thus been formed is advantageous, in view of improving the element characteristics thereof, in that the film thickness of the active layer can be reduced, but on the other hand, due to the fact that the source and drain diffusion layers or the depletion layer extending from the source and drain diffusion layers reach even the insulator lying under the active layer, it is it is structurally difficult to control the potential in the body region so easily as in the case of a conventional bulk planar type element. As a result, there takes place the phenomenon that the potential in the body region floats during the operation of the element, thus posing problems such as the problem that, during the operation of the element, the threshold voltage of the element changes. [0005]
  • As countermeasures to these problems, attempts have been made to control the potential in the channel region of the thin-film SOI element. [0006]
  • For instance, in Japanese Patent Publication (KOKAI) No. 61-34978, it is proposed to form an electrode, between the isolation region and the buried insulator thereunder, for providing a potential to the channel region from outside. According to this method, however, the isolation insulator is formed in such a manner that the isolation region is previously oxidized into a thin film by selectively controlling the amount thereof, and further, the thicknesses of the contact portion to the channel region and the isolation region are controlled simultaneously and repeatedly again to form the isolation dielectric. Thus, the method has the problem or defect that it is very difficult to control the amount of the SOI layer at the respective manufacturing steps for the reduction in thickness of the SOI layer intended in view of improving the performances, and at the same time, the increase in the necessary area occupied by the element is increased. [0007]
  • As described above, mainly in the case of a conventional thin-film SOI element, there are problems or defects such as the defect that the manufacturing steps thereof become complicated as compared with the formation of a conventional bulk planar type element, and further, the area occupied by the element is substantially increased. [0008]
  • BRIEF SUMMARY OF THE INVENTION
  • It is the object of the present invention to provide, mainly, a SOI type semiconductor device and a method of manufacturing the semiconductor device, according to which the miniaturization of the semiconductor device, the enhancement in operating speed thereof, and the reduction in power consumption thereof can be realized. [0009]
  • To achieve the above subject, according to the present invention, the following means are employed. [0010]
  • The main point of the present invention lies in that, in the step of forming the isolation region, the isolation width thereof and the formation condition thereof are varied, whereby, in a desired area, a region in which an isolation layer formed from the surface of a channel layer does not extend as far as an insulator positioned under an active layer which lies under the isolation layer is formed in a self-aligning manner, and, through the region, a region for controlling the potential in a body region is formed. [0011]
  • The semiconductor device according to the present invention comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region. In connection with this, it is preferable that the gate electrode is formed on the second region and the fourth region. Further, it is effective that the gate electrode is electrically conductive to the fourth region, and the gate electrode is formed on the fourth region through a fourth insulator. [0012]
  • The above-mentioned method of manufacturing a semiconductor device according to the present invention comprises the step of forming the third insulator simultaneously with the formation of the isolation region by making the interval between the second region and the fourth region narrower than the width of the isolation region at the time of forming the isolation region so as to extend as far as the first insulator in order to isolate the semiconductor channel region. [0013]
  • Further, the method of manufacturing a semiconductor device, which comprises a semiconductor substrate having a first insulator and a semiconductor channel region formed on the first insulator, the semiconductor channel region including at least two first regions of a first conductivity type, a second region provided between the first regions and having the conductivity type opposite to the first conductivity type, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region and being electrically conductive to the second region, a third insulator formed on the third region, and a fourth region having the same conductivity type as that of the third region and being electrically conductive to the third region, according to the present invention comprises the step of forming the third insulator simultaneously with the formation of the isolation region by narrowing the interval between the second region and the fourth region than the width of the isolation region at the time of forming the isolation region so as to extend as far as the first insulator in order to isolate the semiconductor channel region. In connection with this, it is preferable that the gate electrode is formed on the second region and the fourth region. Further, it is effective that the gate electrode is electrically conductive to the fourth region, and the gate electrode is formed on the fourth region through a fourth insulator. [0014]
  • By using the above-mentioned method, the electrode for controlling the potential in the body region can be formed without complicating the manufacturing steps as compared with the conventional bulk planar type element and by suppressing the increase of the area required. As a result, the problem pertaining to the floating effect of the body potential can be eliminated, and further, the body potentials of the individual elements can be arbitrarily controlled, so that a circuit operation etc. which could not be realized through the conventional bulk planar type elements can be achieved. [0015]
  • As mentioned above, according to the present invention, it is made possible, by controlling the width and film thickness of the isolation region, to form a thin-film SOI element in which the body potential can be controlled without increasing the number of manufacturing steps, complicating the structure of the element or increasing the area occupied by the element. [0016]
  • Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.[0017]
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which: [0018]
  • FIG. 1 is a sectional view showing a conventional semiconductor device; [0019]
  • FIG. 2 is a sectional view of the semiconductor device, after the first manufacturing step, according to a first embodiment of the present invention; [0020]
  • FIGS. 3A and 3B are respectively a plan view and a sectional view taken along the line [0021] 3B-3B in FIG. 3A of the semiconductor device after the second manufacturing step according to the first embodiment of the present invention;
  • FIG. 4 is a sectional view of the semiconductor device after the third manufacturing step according to the first embodiment of the present invention; [0022]
  • FIGS. 5A and 5B are respectively a plan view and a sectional view taken along the line [0023] 5B-5B in FIG. 5A, of the semiconductor device after the fourth manufacturing step of the first embodiment of the present invention;
  • FIG. 6 is a sectional view of the semiconductor device according to the first embodiment of the present invention; [0024]
  • FIG. 7 is a sectional view of the semiconductor device according to a second embodiment of the present invention; [0025]
  • FIG. 8 is a graph showing the characteristic of the semiconductor device according to the second embodiment of the present invention; and [0026]
  • FIGS. 9A and 9B are respectively a plan view and a sectional view taken along the line [0027] 9B-9B in FIG. 9A, of the semiconductor device according to a third embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention will now be described referring to the drawings. [0028]
  • FIGS. [0029] 2 to 6 are schematic diagrams showing the manufacturing steps for explaining the first embodiment of the method of manufacturing a semiconductor device according to the present invention.
  • First, as shown in FIG. 2, a SOI layer [0030] 3 formed through, e.g. an oxide layer 2 on a semiconductor substrate 1 by means of SIMOX or wafer bonding is thinned into a layer having a desired thickness of, e.g. about 150 nm by the use of the thermal oxidation method and an etching method using NH4F.
  • Next, as shown in FIGS. 3A and 3B, an isolation region [0031] 6 is formed in a desired area in order to separate the SOI layer 3 into an channel region 4 and a body contact region 5. In this case, the isolation width L between the channel region 4 and the body contact region 5 is arranged so as to become narrower than the other isolation widths. By selecting this isolation width L so as to be narrower than the other isolation widths, it is ensured that, even in case the isolation region is formed at the same time as according to the present invention, the portion of the isolation region lying between the channel region 4 and the body contact region 5 is not oxidized as far as the oxide layer 2 unlike in the case of the other portions of the isolation region. The isolation width L is determined by means of, e.g. simulation. The isolation region is formed by the use of, e.g. the LOCOS method, in which case the insulator, which is rendered into the isolation region is formed by oxidizing mainly the SOI layer. In this case, the amount of oxidation of the SOI layer is controlled, whereby, in the wider portion of the isolation region, the whole SOI layer is oxidized.
  • Here, it should be noted that, in the case of the portion of the isolation region which lies between the channel region [0032] 4 and the body contact reason 5 and has the isolation width L narrower than the widths of the other portions of the isolation region, it never happens that the whole SOI region is oxidized as far as the oxide layer 2, so that, as shown in FIG. 4, a region 7 connecting the channel region 4 and the body contact region 5 to each other can be formed beneath the element isolation insulating film.
  • Next, desired impurities are injected into the channel region [0033] 4, the body contact region 5 and the region 7 which connects them together by the use of the ion implantation method, and thereafter, as shown in FIGS. 5A and 5B, a gate electrode 9 is formed through a gate insulator 8 on the isolation region 6 and the SOI layer 3 excepting the body contact region 5.
  • Next, the body contact region [0034] 5 is masked by the use of, e.g. a resist (not shown), a desired impurity is introduced for the formation of the source and drain regions 4-1 and 4-2 of the element. After this, an annealing treatment is carried out using a thermal step such as, e.g. the RTA (Rapid Thermal Annealing) method for activation of the impurity introduced by the use of the ion implantation method.
  • Thereafter, the step of forming a wiring for providing contacts [0035] 11 and 12 (the source contact and the drain contact being not shown) respectively to the source and drain regions 4-1 and 4-2, the gate electrode 9, and the body contact region 5 through an interlevel dielectric 10 is performed, whereby a desired SOI type semiconductor device shown in FIG. 6 is completed.
  • In the case of the thin-film SOI element formed in accordance with the first embodiment of the present invention, the abnormal operation due to float the potential in the body region can be suppressed by controlling the body potential in spite of the fact that the method of manufacturing the SOI element is approximately the same as the conventional method. [0036]
  • Further, in the case of the element according to the present invention, when the element operates, the channel inversion layer through which the current flowing between the source and drain passes and the body potential contact region can be isolated from each other by the isolation region, so that, between the source, the drain and the channel inversion layer and the body potential control contact, no high-density pn-junction is formed, so that the leakage current from the body contact region can be structurally reduced. [0037]
  • FIG. 7 is a schematic diagram showing a second embodiment of the semiconductor device according to the present invention, wherein the same portions as those shown in the drawings pertaining to the first embodiment shown are denoted by the same reference numerals, whereby the repetition of the description thereof is omitted. [0038]
  • The above-described first embodiment is of the structure constructed in such a manner that the channel potential is given from outside, but even if the thin-film SOI element is formed, for instance, in such a manner that, after the element isolation [0039] 6 is formed and then, on the channel region 4 and the body contact region 5, the gate insulator (not shown) is formed, and thereafter, the insulator on the body contact region 5 is selectively removed to form the gate electrode as shown in FIG. 7, it is also possible to control the potential of the body contact region 5 like the gate potential.
  • In case the above-mentioned structure is employed, a very good cut-off characteristic is exhibited as shown in FIG. 8 due to the substrate bias effect of the element in case, particularly, the operating voltage range is below the built-in potential induced at the pn-junction between the source and drain diffusion layer and the body region. Thus, according to the second embodiment of the present invention, a semiconductor device having a very good cutoff characteristic can be realized without being followed by an increase of unnecessary leakage current and without increasing the manufacturing steps and the area occupied by the element. [0040]
  • FIGS. 9A and 9B are schematic diagrams showing a third embodiment of the semiconductor device according to the present invention. In these drawings, the same portions as those shown in the drawings pertaining to the first embodiment are denoted by the same reference numerals, whereby the repetition of the description thereof is omitted. [0041]
  • The semiconductor device shown in FIGS. 9A and 9B is constructed in such a manner that, with the formation, between the contact region for controlling the body potential and the gate electrode [0042] 9 formed of for instance a polycrystalline semiconductor, of an insulator similar to that of the channel region, the portion of the gate electrode 9 lying on the body contact region 5 is rendered into the conductivity type same as that of the body contact region. Portion of the gate electrode 9 lying on the channel region 4, and further, a material such as for instance tungsten polycide or the like is provided in such a manner as to extend over the portions of the polycrystalline semiconductor gate electrode 9 lying on the body contact region 5 and the channel region 4, respectively, to thereby make the portions electrically conductive to each other. By adopting such a structure, it is ensured that, in case the gate voltage is transiently applied in operating the semiconductor device, the body potential can be changed, as in the case of the second embodiment, by the capacitive coupling formed in the body contact region 5. In particular, this third embodiment has the advantage that, in the circuit operating at high frequency, preventing the leakage current from the electrode which provides a body potential, the body bias effect due to capacitive coupling can be effectively utilized.
  • The present invention is not limited only to the foregoing embodiments. According to the present invention, for instance as the monocrystalline layer formed on the insulator, not only the SOI substrate formed by the use of the above-mentioned SIMOX method or the wafer bonding method, but also a monocrystalline layer stuck on an insulation substrate and an SOS (Silicon On Sapphire) can be used. [0043]
  • It is a matter of course that the present invention can be variously modified within the technical scope of the present invention. [0044]
  • Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the present invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [0045]

Claims (9)

1. A method of manufacturing a semiconductor device, which comprises: a semiconductor substrate having a first insulator and a semiconductor layer formed on said first insulator, said semiconductor layer including a plurality of active regions each including at least two source-drain regions of a first conductivity type, a channel region provided between said source-drain regions and having a second conductivity type opposite to said first conductivity type, a gate insulator formed on said channel region, a gate electrode formed on said gate insulator, a channel-body contact connection region having the same conductivity type as that of said channel region and being electrically conductive to said channel region, a second insulator formed on said channel-body contact connection region, and a body contact region having the same conductivity type as that of said channel-body contact connection region and being electrically conductive to said channel-body contact connection region, and an isolation region which electrically isolates said plurality of active regions, said method comprising the step of:
forming said second insulator simultaneously with the formation of an isolation region without varying thickness of said semiconductor layer, whereby a distance between said channel region and said body contact region is narrower than the width of said isolation region at the time of forming said isolation region, said isolation region formed so as to extend as far as said first insulator in order to isolate said semiconductor layer.
2. A method of manufacturing the semiconductor device according to claim 1, wherein said gate electrode is formed on said channel region and said body contact region.
3. A method of manufacturing the semiconductor device according to claim 2, wherein said gate electrode is electrically conductive to said body contact region.
4. A method of manufacturing the semiconductor device according to claim 2, wherein said gate electrode is formed on said body contact region through a body contact insulator.
5. A method of manufacturing a semiconductor device comprising:
preparing a semiconductor substrate;
forming an oxide film on said semiconductor substrate;
forming an active layer on said oxide film; and
forming an isolation region in a desired region of said active layer to separate said active layer into a channel region and a body contact region, an isolation width between said channel region and said body contact region being narrower than the other isolation widths.
6. The method according to claim 5, wherein said isolation is formed by LOCOS method.
7. The method according to claim 5, wherein the isolation width is calculated by a simulation.
8. The method according to claim 5, wherein said forming an isolation region includes forming a region which connects said channel region and said body contact region.
9. The method according to claim 5, further comprising forming a gate electrode on said channel region.
US10/107,657 1997-02-28 2002-03-25 Method of manufacturing SOI element having body contact Abandoned US20020098643A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9-046688 1997-02-28
JP04668897A JP3441330B2 (en) 1997-02-28 1997-02-28 Semiconductor device and manufacturing method thereof
US3221498A true 1998-02-27 1998-02-27
US09/956,575 US6403405B1 (en) 1997-02-28 2001-09-18 Method of manufacturing SOI element having body contact
US10/107,657 US20020098643A1 (en) 1997-02-28 2002-03-25 Method of manufacturing SOI element having body contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/107,657 US20020098643A1 (en) 1997-02-28 2002-03-25 Method of manufacturing SOI element having body contact

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/956,575 Division US6403405B1 (en) 1997-02-28 2001-09-18 Method of manufacturing SOI element having body contact

Publications (1)

Publication Number Publication Date
US20020098643A1 true US20020098643A1 (en) 2002-07-25

Family

ID=12754329

Family Applications (4)

Application Number Title Priority Date Filing Date
US09/956,575 Expired - Lifetime US6403405B1 (en) 1997-02-28 2001-09-18 Method of manufacturing SOI element having body contact
US10/107,657 Abandoned US20020098643A1 (en) 1997-02-28 2002-03-25 Method of manufacturing SOI element having body contact
US10/128,004 Abandoned US20020127784A1 (en) 1997-02-28 2002-04-22 Method of manufacturing SOI element having body contact
US10/439,370 Expired - Fee Related US6841828B2 (en) 1997-02-28 2003-05-16 Method of manufacturing SOI element having body contact

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/956,575 Expired - Lifetime US6403405B1 (en) 1997-02-28 2001-09-18 Method of manufacturing SOI element having body contact

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/128,004 Abandoned US20020127784A1 (en) 1997-02-28 2002-04-22 Method of manufacturing SOI element having body contact
US10/439,370 Expired - Fee Related US6841828B2 (en) 1997-02-28 2003-05-16 Method of manufacturing SOI element having body contact

Country Status (2)

Country Link
US (4) US6403405B1 (en)
JP (1) JP3441330B2 (en)

Cited By (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040021137A1 (en) * 2001-06-18 2004-02-05 Pierre Fazan Semiconductor device
US20040228168A1 (en) * 2003-05-13 2004-11-18 Richard Ferrant Semiconductor memory device and method of operating same
US20040227166A1 (en) * 2003-05-13 2004-11-18 Lionel Portmann Reference current generator, and method of programming, adjusting and/or operating same
US20040238890A1 (en) * 2002-04-18 2004-12-02 Pierre Fazan Semiconductor device
US20040240306A1 (en) * 2002-04-18 2004-12-02 Pierre Fazan Data storage device and refreshing method for use with such device
US20050013163A1 (en) * 2003-05-13 2005-01-20 Richard Ferrant Semiconductor memory cell, array, architecture and device, and method of operating same
US20050017240A1 (en) * 2003-07-22 2005-01-27 Pierre Fazan Integrated circuit device, and method of fabricating same
US20050063224A1 (en) * 2003-09-24 2005-03-24 Pierre Fazan Low power programming technique for a floating body memory transistor, memory cell, and memory array
US20060091462A1 (en) * 2004-11-04 2006-05-04 Serguei Okhonin Memory cell having an electrically floating body transistor and programming technique therefor
US20060098481A1 (en) * 2004-11-10 2006-05-11 Serguei Okhonin Circuitry for and method of improving statistical distribution of integrated circuits
US20060126374A1 (en) * 2004-12-13 2006-06-15 Waller William K Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US20060131650A1 (en) * 2004-12-22 2006-06-22 Serguei Okhonin Bipolar reading technique for a memory cell having an electrically floating body transistor
US20070023833A1 (en) * 2005-07-28 2007-02-01 Serguei Okhonin Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
US20070058427A1 (en) * 2005-09-07 2007-03-15 Serguei Okhonin Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US20070064489A1 (en) * 2005-09-19 2007-03-22 Philippe Bauser Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
US20070085140A1 (en) * 2005-10-19 2007-04-19 Cedric Bassin One transistor memory cell having strained electrically floating body region, and method of operating same
US20070138530A1 (en) * 2005-12-19 2007-06-21 Serguei Okhonin Electrically floating body memory cell and array, and method of operating or controlling same
US20070187775A1 (en) * 2006-02-16 2007-08-16 Serguei Okhonin Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
US20070285982A1 (en) * 2006-04-07 2007-12-13 Eric Carman Memory array having a programmable word length, and method of operating same
US20080315313A1 (en) * 1998-12-24 2008-12-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, method of manufacturing same and method of designing same
US7924630B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US7933142B2 (en) 2006-05-02 2011-04-26 Micron Technology, Inc. Semiconductor memory cell and array using punch-through to program and read same
US7933140B2 (en) 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US20110122687A1 (en) * 2009-11-24 2011-05-26 Innovative Silicon Isi Sa Techniques for reducing disturbance in a semiconductor device
US7957206B2 (en) 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7969779B2 (en) 2006-07-11 2011-06-28 Micron Technology, Inc. Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US8014195B2 (en) 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US8085594B2 (en) 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8189376B2 (en) 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US8194487B2 (en) 2007-09-17 2012-06-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8199595B2 (en) 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8213226B2 (en) 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8223574B2 (en) 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
US8264041B2 (en) 2007-01-26 2012-09-11 Micron Technology, Inc. Semiconductor device with electrically floating body
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US8315099B2 (en) 2009-07-27 2012-11-20 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8319294B2 (en) 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
US8349662B2 (en) 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
US8369177B2 (en) 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
US8411513B2 (en) 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US8416636B2 (en) 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8498157B2 (en) 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8508994B2 (en) 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8518774B2 (en) 2007-03-29 2013-08-27 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8547738B2 (en) 2010-03-15 2013-10-01 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8710566B2 (en) 2009-03-04 2014-04-29 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US8748959B2 (en) 2009-03-31 2014-06-10 Micron Technology, Inc. Semiconductor memory device
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0989613B1 (en) * 1998-08-29 2005-05-04 International Business Machines Corporation SOI transistor with body contact and method of forming same
JP4540641B2 (en) * 1998-12-24 2010-09-08 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4540684B2 (en) * 1998-12-24 2010-09-08 ルネサスエレクトロニクス株式会社 Semiconductor device
GB2360874B (en) * 1999-10-25 2002-07-03 Samsung Electronics Co Ltd An SOI semiconductor integrated circuit for eliminating floating body effects in SOI mosfets and method of fabricating the same
JP3716406B2 (en) * 2000-02-08 2005-11-16 富士通株式会社 An insulated gate semiconductor device and a manufacturing method thereof
US6368903B1 (en) * 2000-03-17 2002-04-09 International Business Machines Corporation SOI low capacitance body contact
JP3788217B2 (en) 2000-09-08 2006-06-21 株式会社村田製作所 Directional coupler, an antenna device and a radar device
WO2002025701A2 (en) * 2000-09-19 2002-03-28 Motorola, Inc. Body-tied silicon on insulator semiconductor device structure and method therefor
US6804502B2 (en) 2001-10-10 2004-10-12 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
JP2004119884A (en) 2002-09-27 2004-04-15 Toshiba Corp Semiconductor device
KR100501706B1 (en) * 2003-10-16 2005-07-18 삼성에스디아이 주식회사 Gate-body contact TFT
WO2006002347A1 (en) 2004-06-23 2006-01-05 Peregrine Semiconductor Corporation Integrated rf front end
US7072220B1 (en) * 2004-12-28 2006-07-04 Macronix International Co., Ltd. Method and apparatus for operating a non-volatile memory array
US7130215B2 (en) * 2004-12-28 2006-10-31 Macronix International Co., Ltd. Method and apparatus for operating a non-volatile memory device
US7072219B1 (en) * 2004-12-28 2006-07-04 Macronix International Co., Ltd. Method and apparatus for operating a non-volatile memory array
US7910993B2 (en) * 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
EP2255443B1 (en) 2008-02-28 2012-11-28 Peregrine Semiconductor Corporation Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device
US8829967B2 (en) 2012-06-27 2014-09-09 Triquint Semiconductor, Inc. Body-contacted partially depleted silicon on insulator transistor
US8729952B2 (en) 2012-08-16 2014-05-20 Triquint Semiconductor, Inc. Switching device with non-negative biasing
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US8847672B2 (en) 2013-01-15 2014-09-30 Triquint Semiconductor, Inc. Switching device with resistive divider
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US8923782B1 (en) 2013-02-20 2014-12-30 Triquint Semiconductor, Inc. Switching device with diode-biased field-effect transistor (FET)
US8977217B1 (en) 2013-02-20 2015-03-10 Triquint Semiconductor, Inc. Switching device with negative bias circuit
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US20150236798A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Methods for Increasing RF Throughput Via Usage of Tunable Filters
JP2014229737A (en) 2013-05-22 2014-12-08 株式会社東芝 Semiconductor device
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124243A (en) 1982-01-21 1983-07-23 Toshiba Corp Manufacture of semiconductor device
JPH06105784B2 (en) 1984-07-26 1994-12-21 株式会社日立製作所 Semiconductor device
JPS6139958A (en) 1984-07-31 1986-02-26 Sanyo Electric Co Ltd Recording speed discriminating circuit of tape
JPS63241967A (en) 1987-03-30 1988-10-07 Toshiba Corp Insulating substrate type mis transistor
JP2512216B2 (en) 1989-08-01 1996-07-03 松下電器産業株式会社 A method of manufacturing a semiconductor device
JPH04348068A (en) 1991-03-18 1992-12-03 Toshiba Corp Semiconductor memory device
JP2903892B2 (en) 1992-09-07 1999-06-14 日本電気株式会社 A method of manufacturing a field effect transistor
JP3778581B2 (en) * 1993-07-05 2006-05-24 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5405795A (en) 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact
US5559368A (en) 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
JPH08125187A (en) 1994-10-24 1996-05-17 Nippon Telegr & Teleph Corp <Ntt> Method and system for fabricating mos type semiconductor device having soi structure
JP2950232B2 (en) * 1996-03-29 1999-09-20 日本電気株式会社 The method of manufacturing a semiconductor memory device
US5821575A (en) 1996-05-20 1998-10-13 Digital Equipment Corporation Compact self-aligned body contact silicon-on-insulator transistor
US5767549A (en) 1996-07-03 1998-06-16 International Business Machines Corporation SOI CMOS structure
JPH11195704A (en) * 1998-01-05 1999-07-21 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US6093585A (en) * 1998-05-08 2000-07-25 Lsi Logic Corporation High voltage tolerant thin film transistor

Cited By (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080315313A1 (en) * 1998-12-24 2008-12-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, method of manufacturing same and method of designing same
US7741679B2 (en) 1998-12-24 2010-06-22 Renesas Technology Corp. Semiconductor device, method of manufacturing same and method of designing same
US20080073719A1 (en) * 2001-06-18 2008-03-27 Pierre Fazan Semiconductor device
US20040159876A1 (en) * 2001-06-18 2004-08-19 Pierre Fazan Semiconductor device
US20080165577A1 (en) * 2001-06-18 2008-07-10 Pierre Fazan Semiconductor device
US20040135202A1 (en) * 2001-06-18 2004-07-15 Pierre Fazan Semiconductor device
US20040124488A1 (en) * 2001-06-18 2004-07-01 Pierre Fazan Semiconductor device
US7732816B2 (en) 2001-06-18 2010-06-08 Innovative Silicon Isi Sa Semiconductor device
US20040021137A1 (en) * 2001-06-18 2004-02-05 Pierre Fazan Semiconductor device
US20050280028A1 (en) * 2001-06-18 2005-12-22 Pierre Fazan Semiconductor device
US6969662B2 (en) 2001-06-18 2005-11-29 Pierre Fazan Semiconductor device
US6873539B1 (en) 2001-06-18 2005-03-29 Pierre Fazan Semiconductor device
US20050213379A1 (en) * 2001-06-18 2005-09-29 Pierre Fazan Semiconductor device
US20080055974A1 (en) * 2001-06-18 2008-03-06 Pierre Fazan Semiconductor device
US20080068882A1 (en) * 2001-06-18 2008-03-20 Pierre Fazan Semiconductor device
US20040240306A1 (en) * 2002-04-18 2004-12-02 Pierre Fazan Data storage device and refreshing method for use with such device
US20070109896A1 (en) * 2002-04-18 2007-05-17 Pierre Fazan Data storage device and refreshing method for use with such device
US20050128851A1 (en) * 2002-04-18 2005-06-16 Pierre Fazan Data storage device and refreshing method for use with such device
US20040238890A1 (en) * 2002-04-18 2004-12-02 Pierre Fazan Semiconductor device
US7733693B2 (en) 2003-05-13 2010-06-08 Innovative Silicon Isi Sa Semiconductor memory device and method of operating same
US20050013163A1 (en) * 2003-05-13 2005-01-20 Richard Ferrant Semiconductor memory cell, array, architecture and device, and method of operating same
US20050157580A1 (en) * 2003-05-13 2005-07-21 Richard Ferrant Semiconductor memory device and method of operating same
US20040227166A1 (en) * 2003-05-13 2004-11-18 Lionel Portmann Reference current generator, and method of programming, adjusting and/or operating same
US20050174873A1 (en) * 2003-05-13 2005-08-11 Richard Ferrant Semiconductor memory device and method of operating same
US20080205114A1 (en) * 2003-05-13 2008-08-28 Richard Ferrant Semiconductor memory device and method of operating same
US20040228168A1 (en) * 2003-05-13 2004-11-18 Richard Ferrant Semiconductor memory device and method of operating same
US20070159911A1 (en) * 2003-05-13 2007-07-12 Richard Ferrant Semiconductor memory device and method of operating same
US20050017240A1 (en) * 2003-07-22 2005-01-27 Pierre Fazan Integrated circuit device, and method of fabricating same
US7736959B2 (en) 2003-07-22 2010-06-15 Innovative Silicon Isi Sa Integrated circuit device, and method of fabricating same
US20080153213A1 (en) * 2003-07-22 2008-06-26 Pierre Fazan Integrated circuit device, and method of fabricating same
US20050063224A1 (en) * 2003-09-24 2005-03-24 Pierre Fazan Low power programming technique for a floating body memory transistor, memory cell, and memory array
US20060114717A1 (en) * 2003-09-24 2006-06-01 Pierre Fazan Low power programming technique for a floating body memory transistor, memory cell, and memory array
US20060091462A1 (en) * 2004-11-04 2006-05-04 Serguei Okhonin Memory cell having an electrically floating body transistor and programming technique therefor
US20060098481A1 (en) * 2004-11-10 2006-05-11 Serguei Okhonin Circuitry for and method of improving statistical distribution of integrated circuits
US20060126374A1 (en) * 2004-12-13 2006-06-15 Waller William K Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US20080025083A1 (en) * 2004-12-22 2008-01-31 Serguei Okhonin Bipolar reading technique for a memory cell having an electrically floating body transistor
US20060131650A1 (en) * 2004-12-22 2006-06-22 Serguei Okhonin Bipolar reading technique for a memory cell having an electrically floating body transistor
US20070023833A1 (en) * 2005-07-28 2007-02-01 Serguei Okhonin Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
US8873283B2 (en) 2005-09-07 2014-10-28 Micron Technology, Inc. Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US20100020597A1 (en) * 2005-09-07 2010-01-28 Serguei Okhonin Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same
US20070058427A1 (en) * 2005-09-07 2007-03-15 Serguei Okhonin Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US20070064489A1 (en) * 2005-09-19 2007-03-22 Philippe Bauser Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
US20070085140A1 (en) * 2005-10-19 2007-04-19 Cedric Bassin One transistor memory cell having strained electrically floating body region, and method of operating same
US20070138530A1 (en) * 2005-12-19 2007-06-21 Serguei Okhonin Electrically floating body memory cell and array, and method of operating or controlling same
US7683430B2 (en) 2005-12-19 2010-03-23 Innovative Silicon Isi Sa Electrically floating body memory cell and array, and method of operating or controlling same
US20070187775A1 (en) * 2006-02-16 2007-08-16 Serguei Okhonin Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
US8134867B2 (en) 2006-04-07 2012-03-13 Micron Technology, Inc. Memory array having a programmable word length, and method of operating same
US7940559B2 (en) 2006-04-07 2011-05-10 Micron Technology, Inc. Memory array having a programmable word length, and method of operating same
US20070285982A1 (en) * 2006-04-07 2007-12-13 Eric Carman Memory array having a programmable word length, and method of operating same
US8295078B2 (en) 2006-05-02 2012-10-23 Micron Technology, Inc. Semiconductor memory cell and array using punch-through to program and read same
US7933142B2 (en) 2006-05-02 2011-04-26 Micron Technology, Inc. Semiconductor memory cell and array using punch-through to program and read same
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US8402326B2 (en) 2006-06-26 2013-03-19 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating same
US8395937B2 (en) 2006-07-11 2013-03-12 Micron Technology, Inc. Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US7969779B2 (en) 2006-07-11 2011-06-28 Micron Technology, Inc. Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US8492209B2 (en) 2007-01-26 2013-07-23 Micron Technology, Inc. Semiconductor device with electrically floating body
US8796770B2 (en) 2007-01-26 2014-08-05 Micron Technology, Inc. Semiconductor device with electrically floating body
US8264041B2 (en) 2007-01-26 2012-09-11 Micron Technology, Inc. Semiconductor device with electrically floating body
US8518774B2 (en) 2007-03-29 2013-08-27 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US9276000B2 (en) 2007-03-29 2016-03-01 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US9257155B2 (en) 2007-05-30 2016-02-09 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8659956B2 (en) 2007-05-30 2014-02-25 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8085594B2 (en) 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US8659948B2 (en) 2007-06-01 2014-02-25 Micron Technology, Inc. Techniques for reading a memory cell with electrically floating body transistor
US8194487B2 (en) 2007-09-17 2012-06-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8446794B2 (en) 2007-09-17 2013-05-21 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8797819B2 (en) 2007-09-17 2014-08-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8349662B2 (en) 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
US9019788B2 (en) 2008-01-24 2015-04-28 Micron Technology, Inc. Techniques for accessing memory cells
US8014195B2 (en) 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8325515B2 (en) 2008-02-06 2012-12-04 Micron Technology, Inc. Integrated circuit device
US8189376B2 (en) 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US8274849B2 (en) 2008-04-04 2012-09-25 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7957206B2 (en) 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US8790968B2 (en) 2008-09-25 2014-07-29 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9553186B2 (en) 2008-09-25 2017-01-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US8315083B2 (en) 2008-10-02 2012-11-20 Micron Technology Inc. Techniques for reducing a voltage swing
US7933140B2 (en) 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7924630B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US8223574B2 (en) 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
US8213226B2 (en) 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8319294B2 (en) 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
US8710566B2 (en) 2009-03-04 2014-04-29 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9064730B2 (en) 2009-03-04 2015-06-23 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US8748959B2 (en) 2009-03-31 2014-06-10 Micron Technology, Inc. Semiconductor memory device
US9093311B2 (en) 2009-03-31 2015-07-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8861247B2 (en) 2009-04-27 2014-10-14 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9425190B2 (en) 2009-04-27 2016-08-23 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8400811B2 (en) 2009-04-27 2013-03-19 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines
US8351266B2 (en) 2009-04-27 2013-01-08 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8508970B2 (en) 2009-04-27 2013-08-13 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9240496B2 (en) 2009-04-30 2016-01-19 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8792276B2 (en) 2009-04-30 2014-07-29 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8508994B2 (en) 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8498157B2 (en) 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8982633B2 (en) 2009-05-22 2015-03-17 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8817534B2 (en) 2009-07-10 2014-08-26 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9331083B2 (en) 2009-07-10 2016-05-03 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9679612B2 (en) 2009-07-27 2017-06-13 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8964461B2 (en) 2009-07-27 2015-02-24 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8315099B2 (en) 2009-07-27 2012-11-20 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8947965B2 (en) 2009-07-27 2015-02-03 Micron Technology Inc. Techniques for providing a direct injection semiconductor memory device
US8587996B2 (en) 2009-07-27 2013-11-19 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9076543B2 (en) 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8199595B2 (en) 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US20110122687A1 (en) * 2009-11-24 2011-05-26 Innovative Silicon Isi Sa Techniques for reducing disturbance in a semiconductor device
US8699289B2 (en) 2009-11-24 2014-04-15 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor memory device
US8760906B2 (en) 2009-11-24 2014-06-24 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor memory device
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device
US8174881B2 (en) 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US8416636B2 (en) 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8964479B2 (en) 2010-03-04 2015-02-24 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8411513B2 (en) 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8369177B2 (en) 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
US9524971B2 (en) 2010-03-15 2016-12-20 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8547738B2 (en) 2010-03-15 2013-10-01 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9019759B2 (en) 2010-03-15 2015-04-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8630126B2 (en) 2010-05-06 2014-01-14 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9142264B2 (en) 2010-05-06 2015-09-22 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9263133B2 (en) 2011-05-17 2016-02-16 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells

Also Published As

Publication number Publication date
US20030205760A1 (en) 2003-11-06
JPH10242470A (en) 1998-09-11
JP3441330B2 (en) 2003-09-02
US20020037608A1 (en) 2002-03-28
US6403405B1 (en) 2002-06-11
US6841828B2 (en) 2005-01-11
US20020127784A1 (en) 2002-09-12

Similar Documents

Publication Publication Date Title
US5767549A (en) SOI CMOS structure
KR100606299B1 (en) Semiconductor device
US7001822B2 (en) Semiconductor device formed on insulating layer and method of manufacturing the same
US6392271B1 (en) Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6376317B1 (en) Methods for dual-gated transistors
US6881621B2 (en) Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same
US5308778A (en) Method of formation of transistor and logic gates
US6566176B1 (en) SOI device with wrap-around contact to underside of body, and method of making
US5729039A (en) SOI transistor having a self-aligned body contact
US8268709B2 (en) Independently accessed double-gate and tri-gate transistors in same process flow
US7335543B2 (en) MOS device for high voltage operation and method of manufacture
US5886376A (en) EEPROM having coplanar on-insulator FET and control gate
US7061055B2 (en) Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6955972B2 (en) Methods of fabricating integrated circuit devices having trench isolation structures
KR100650419B1 (en) Method and structure for buried circuits and devices
US6933569B2 (en) Soi mosfet
KR0176202B1 (en) Soi transistor and its fabrication method
US6489650B2 (en) Semiconductor device and a method of manufacturing the same
US6087698A (en) Semiconductor device and method of manufacturing the same
US4951102A (en) Trench gate VCMOS
EP1191479A1 (en) Programmable neuron mosfet
KR100589710B1 (en) Semiconductor device
US20030067044A1 (en) Semiconductor-on-insulator resistor-capacitor circuit
US7786535B2 (en) Design structures for high-voltage integrated circuits
US5712173A (en) Method of making semiconductor device with self-aligned insulator