US20020097035A1 - Apparatus for measuring the duty cycle of a high speed clocking signal - Google Patents
Apparatus for measuring the duty cycle of a high speed clocking signal Download PDFInfo
- Publication number
- US20020097035A1 US20020097035A1 US09/766,200 US76620001A US2002097035A1 US 20020097035 A1 US20020097035 A1 US 20020097035A1 US 76620001 A US76620001 A US 76620001A US 2002097035 A1 US2002097035 A1 US 2002097035A1
- Authority
- US
- United States
- Prior art keywords
- duty cycle
- voltage
- iteration
- value
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
Definitions
- the present invention relates generally to digital circuits and, particularly, to a system and method for measuring the duty cycle of a high speed clocking signal.
- a system and method for accurately measuring the duty cycle of an input periodic pulsed signal comprises a device for converting the input signal to be measured into a first dc voltage; a device for encoding a plurality of duty cycle values for selection thereof in an iterative manner, one value of which represents a duty cycle of the input signal; a device for iteratively generating a second dc voltage according to a difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value; and a selection mechanism responsive to the first and second dc voltages for selecting an encoded duty cycle value for each iteration.
- the system selects an encoded duty cycle value in each successive iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof.
- the system may measure the input signal's duty cycle accurately regardless of its frequency as any error associated with its frequency is eliminated. Furthermore, the system may be incorporated in a phase lock loop (PLL) or a delay lock loop (DLL) within an IC itself, adding only a minor increase in silicon real estate.
- PLL phase lock loop
- DLL delay lock loop
- FIG. 1 illustrates a schematic diagram of the duty cycle measuring circuit 10 according to the invention.
- FIG. 2 illustrates an example encoding table 100 representing the SAR bit assignments corresponding to the signals of various duty cycles and corresponding DAC output voltages.
- FIGS. 3 ( a )- 3 ( c ) represent various timing features of the duty cycle measuring circuit 10 according to an example implementation.
- FIG. 1 illustrates the duty cycle measuring circuit 10 of the invention which includes a precise and programmable duty cycle adjuster 25 , a Low Pass Filter (LPF 1 ) device 30 which converts the incoming signal's duty cycle into a DC analog voltage; a tri-statable analog comparator device (COMP) 35 which is used to compare the analog voltage output from with LPF 1 and the analog voltage output of a second low pass filter LPF 2 40 when the comparator device 35 is enabled or not tri-stated; and, an n-bit Successive Approximation Register SAR 50 which stores the encoded value of the signal's output duty cycle.
- LPF 1 Low Pass Filter
- COMP tri-statable analog comparator device
- the output of the Successive Approximation Register or SAR 50 provides the digital representation 55 of the duty cycle of the signal under test, which is additionally input to a Digital to Analog Converter (DAC) device 60 which converts the digital contents of the SAR into an analog voltage.
- DAC Digital to Analog Converter
- the number of bits out of the SAR matches the number of bits representing the accuracy of the DAC. Hence, for improved accuracy, the number of bits of the SAR and DAC may be increased as the technology warrants.
- a Lock Detector circuit 75 is also provided which acquires a lock generated in duty cycle adjuster 25 and generates an enable signal 38 for activating (or tri-stating) the comparator 35 .
- the programmable duty cycle adjuster circuit 25 utilizes a novel Voltage Controlled Duty Cycle Generator (VCDCG) 29 the operation of which is described in commonly-owned, copending U.S. patent application Ser. No. ______ (RAL8-02000-0008) entitled “A Precise and Programmable Duty Cycle Adjuster”.
- VCDCG Voltage Controlled Duty Cycle Generator
- the Precise and Programmable Duty Cycle Adjuster 25 includes an Operational Transconductance Amplifier (OTA) 23 used to compare the analog voltage 26 output from LPF 2 representing the desired duty cycle with an analog feedback voltage 66 output from the DAC 60 .
- the OTA 23 particularly generates a current that is proportional to the difference of its input voltages.
- the two voltages are equal, then no current will charge or discharge the capacitor C 1 leading to a DC voltage at VCONT that forces the waveform output of the VCDCG 29 to be equal to the duty cycle of the signal output 80 as programmed by the SAR.
- the duty cycle of the signal 26 at the output of the LPF 2 40 is less than the desired duty cycle, then the output of the LPF 2 40 will be smaller than the output of the DAC 60 .
- the OTA will generate a current proportional to the difference between the output of the DAC and the output of the Low Pass Filter 40 . The current will charge the capacitor causing VCONT to rise and the duty cycle at the output of the VCDCG 29 to increase.
- the mechanism is the same but in the other direction if the duty cycle of the VCDCG 29 is greater than the output 80 of the SAR.
- the Voltage Controlled Duty Cycle Generator (VCDCG) is inverting the input signal whose duty cycle is to be measured. If a non-inverting signal is desired, the output of the DAC 60 and the output of the LPF 2 40 may be swapped going into the OTA 23 .
- the Voltage Controlled Duty Cycle Generator 29 receives an input clock signal 12 under test and the output of the OTA.
- the output of the VCDCG 29 is the duty cycle corrected clock generated by a signal of a desired duty cycle in accordance with the output of the OTA (Vcont voltage).
- FIG. 2 illustrates an example encoding table 100 representing the SAR bit assignments 110 corresponding to the signals of various duty cycles 120 and corresponding DAC output voltages.
- 4-bits of accuracy is assumed as is a voltage supply of 1.8 Volts DC assumed.
- the operation of the duty cycle measuring circuit of the invention is commenced by setting the output of the SAR register 50 to a digital code 102 representing an initial 50/50 duty cycle 104 .
- This SAR setting and corresponding DAC output voltage 66 will initially reset the Lock Detector circuit 75 to “zero” for disabling the COMP 35 .
- This setting constitutes the start of the first cycle of the Successive Approximation Technique of the invention.
- this technique requires at least the same number of cycles as the accuracy of its DAC.
- a four-bit DAC 60 will enable the technique to reach a solution in four (4) cycles.
- the starting digital code would be “1000” which causes the DAC 60 to output a voltage equal to half of the power supply.
- the voltage representing the 50/50 duty cycle is (1.8)/2 or 0.9V.
- the output 66 of the DAC 60 is connected to one of the inputs of the Operational Transconductance Amplifier or OTA 23 provided in the programmable duty cycle adjuster circuit 25 .
- the OTA 23 additionally receives as input the output 26 of a Low Pass Filter 2 or LPF 2 40 whose voltage is a representation of the duty cycle out of the Voltage Controlled Duty Cycle Generator or VCDCG 29 .
- the OTA 23 outputs a current proportional to the difference in voltage of its two inputs.
- the IOTA 23 will charge the capacitor C 1 , thus raising the voltage at the output of the OTA 23 and at the V cont input pin of the VCDCG 29 . This, in turn, will force the duty cycle at the output of the VCDCG 29 and the output of the LPF 2 40 to move closer to the duty cycle depicted by the DAC 60 .
- the output 26 of the LPF 2 40 will match the output of the DAC 60 and cause the Lock Detector to go to a “one” which enables the COMP 35 .
- the two inputs of the COMP are the output 26 of LPF 2 40 and the output 36 of LPF 1 30 which represents the duty cycle of the input signal 12 whose duty cycle is being measured.
- FIGS. 3 ( a )- 3 ( c ) represent various timing features of the duty cycle measuring circuit 10 according to an example implementation having an example signal under test with a duty cycle of 45/55.
- the output 66 of the DAC in a first cycle of operation, is 0.9 volts corresponding to an initial SAR register setting of “1000” as mentioned above.
- the example signal under test having with a duty cycle of 45/55 will generate an output voltage 36 at the LPF 1 30 of 0.45 ⁇ 1.8V or 0.81 V.
- FIG. 3( b ) illustrates the setting of the lock signal 38 to a zero which marks the beginning of Cycle 2 of the Successive Approximation technique.
- the output of LPF 2 will match the output 66 of the DAC thus, forcing the Lock Detector to go to a “one” enabling the COMP 35 and evaluating its input. Since the output voltage 36 of LPF 1 is still lower than the output 26 of LPF 2 , the COMP will go to “zero” changing and latching the second most significant bit to “zero”. At the same time, the third most significant bit will go to “1” resulting in an SAR digital code word of “00010”. The DAC 60 , for the third time will change its output value to 1 ⁇ 4 of the value between 0.9V and the minimum value of the DAC, or 0.792V.
- the Lock Detector output 38 will go to “zero” in the third cycle thus disabling the COMP 35 .
- the output of LPF 2 40 will reach the same voltage as the output of the DAC forcing the Lock Detector to go to “one” and thus enabling the COMP.
- the output of LPF 2 is lower than LPF 1 , the COMP will output a “one” thus keeping and latching the “one” as the third most significant bit.
- the least significant bit (LSB) shifts to “one” resulting in an SAR code of “0011” which corresponds to a DAC output of 0.81V.
- the result will have an accuracy of +/ ⁇ 1 ⁇ 2 lsb, and therefore, the accuracy of the DAC and the range of measured duty cycle determine the accuracy of the result.
- each digital code represents 1% of duty cycle.
- the maximum duty cycles that can be measured will be limited to 57/43 and 42/58, respectively.
- the design of the VCDCG 29 has certain operational frequency limits to provide the desired noise immunity and hence, it is important to know the relative frequency range.
- the slope of the curve of duty cycle versus VCONT is affected by the number of stages of the VCDCG 29 which is, in turn, a function of the expected frequency range.
- a commonly-owned disclosure entitled “Enhanced Operational Frequency for a precise and programmable Duty Cycle Generator” [IBM Reference No. RAL8-2000-0029], describes a means to address these frequency limitations.
Abstract
A system and method for accurately measuring the duty cycle of an input periodic pulsed signal. The system comprises a device for converting the input signal to be measured into a first dc voltage; a device for encoding a plurality of duty cycle values for selection thereof in an iterative manner, one value of which represents a duty cycle of the input signal; a device for iteratively generating a second dc voltage according to a difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value; and a selection mechanism responsive to the first and second dc voltages for selecting an encoded duty cycle value for each iteration. The system selects an encoded duty cycle value in each successive iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof. By representing the input signal's duty cycle as a dc voltage, the system may measure the input signal's duty cycle accurately regardless of its frequency.
Description
- The present invention relates generally to digital circuits and, particularly, to a system and method for measuring the duty cycle of a high speed clocking signal.
- In the specification of system clock signals provided for integrated circuits (ICs), the signal “jitter” is the most important specification. The second most important specification of a system clock in ICs is its duty cycle. The high frequency of the clock signals implemented in high-speed circuits prohibits measurement at the pins of the integrated circuit (IC). To overcome this, techniques for measuring frequency and jitter have implemented a divided clock. Un fortunately, the duty cycle information gets lost once the clock signal is divided down.
- Particular prior art systems for measuring the duty cycle of a periodic signal have been described in U.S. Pat. Nos. 4,475,086, issued Mar. 31, 1982, and U.S. Pat. No. 5,367,200, issued Nov. 29, 1993. These systems rely on counter devices for measuring and, in the case of U.S. Pat. No. 4,475,086, implementing a higher frequency clock. An alternative technique is to measure the duty cycle at the wafer level which is very expensive and can only be done at the development cycle and not at the production level.
- It would be highly desirable to provide a circuit that enables the measure of the duty cycle of a clock independent of its frequency.
- It would be further highly desirable an integrated circuit provided with a clock measurement circuit that is designed for measuring and ensuring that that the duty signal of a clock signal meets its specification.
- It is an object of the invention to provide a clock measurement circuit that provides a reliable and accurate means of measuring and ensuring that the clock duty cycle meets its specification.
- It is a further object of the invention to provide a clock measurement circuit that provides a reliable and accurate means of measuring and ensuring that the clock duty cycle meets its specification independent of its frequency.
- It is another object of the invention to provide a clock measurement circuit that measures the clock duty cycle independent of its frequency, and which may be implemented in an IC to enable testing at the production level.
- According to the principles of the invention, there is provided a system and method for accurately measuring the duty cycle of an input periodic pulsed signal. The system comprises a device for converting the input signal to be measured into a first dc voltage; a device for encoding a plurality of duty cycle values for selection thereof in an iterative manner, one value of which represents a duty cycle of the input signal; a device for iteratively generating a second dc voltage according to a difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value; and a selection mechanism responsive to the first and second dc voltages for selecting an encoded duty cycle value for each iteration. The system selects an encoded duty cycle value in each successive iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof.
- Advantageously, by representing the input signal's duty cycle as a dc voltage, the system may measure the input signal's duty cycle accurately regardless of its frequency as any error associated with its frequency is eliminated. Furthermore, the system may be incorporated in a phase lock loop (PLL) or a delay lock loop (DLL) within an IC itself, adding only a minor increase in silicon real estate.
- Further features, aspects and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and the accompanying drawings in which:
- FIG. 1 illustrates a schematic diagram of the duty
cycle measuring circuit 10 according to the invention. - FIG. 2 illustrates an example encoding table100 representing the SAR bit assignments corresponding to the signals of various duty cycles and corresponding DAC output voltages.
- FIGS.3(a)-3(c) represent various timing features of the duty
cycle measuring circuit 10 according to an example implementation. - This present invention utilizes the successive approximation technique for determining the duty cycle of a high speed clock signal, which is in the form of an encoded digital representation FIG. 1 illustrates the duty
cycle measuring circuit 10 of the invention which includes a precise and programmableduty cycle adjuster 25, a Low Pass Filter (LPF1)device 30 which converts the incoming signal's duty cycle into a DC analog voltage; a tri-statable analog comparator device (COMP) 35 which is used to compare the analog voltage output from with LPF1 and the analog voltage output of a second lowpass filter LPF2 40 when thecomparator device 35 is enabled or not tri-stated; and, an n-bit Successive Approximation Register SAR 50 which stores the encoded value of the signal's output duty cycle. The output of the Successive Approximation Register or SAR 50 provides thedigital representation 55 of the duty cycle of the signal under test, which is additionally input to a Digital to Analog Converter (DAC)device 60 which converts the digital contents of the SAR into an analog voltage. The number of bits out of the SAR matches the number of bits representing the accuracy of the DAC. Hence, for improved accuracy, the number of bits of the SAR and DAC may be increased as the technology warrants. ALock Detector circuit 75 is also provided which acquires a lock generated induty cycle adjuster 25 and generates an enablesignal 38 for activating (or tri-stating) thecomparator 35. - The programmable duty
cycle adjuster circuit 25 utilizes a novel Voltage Controlled Duty Cycle Generator (VCDCG) 29 the operation of which is described in commonly-owned, copending U.S. patent application Ser. No. ______ (RAL8-02000-0008) entitled “A Precise and Programmable Duty Cycle Adjuster”. As described therein, the Precise and ProgrammableDuty Cycle Adjuster 25 includes an Operational Transconductance Amplifier (OTA) 23 used to compare theanalog voltage 26 output from LPF2 representing the desired duty cycle with ananalog feedback voltage 66 output from theDAC 60. TheOTA 23 particularly generates a current that is proportional to the difference of its input voltages. If the two voltages are equal, then no current will charge or discharge the capacitor C1 leading to a DC voltage at VCONT that forces the waveform output of theVCDCG 29 to be equal to the duty cycle of thesignal output 80 as programmed by the SAR. On the other hand, if the duty cycle of thesignal 26 at the output of theLPF2 40 is less than the desired duty cycle, then the output of theLPF2 40 will be smaller than the output of theDAC 60. The OTA will generate a current proportional to the difference between the output of the DAC and the output of theLow Pass Filter 40. The current will charge the capacitor causing VCONT to rise and the duty cycle at the output of theVCDCG 29 to increase. The mechanism is the same but in the other direction if the duty cycle of theVCDCG 29 is greater than theoutput 80 of the SAR. It should be understood that the Voltage Controlled Duty Cycle Generator (VCDCG) is inverting the input signal whose duty cycle is to be measured. If a non-inverting signal is desired, the output of theDAC 60 and the output of theLPF2 40 may be swapped going into theOTA 23. With more particularity, the Voltage Controlled Duty CycleGenerator 29 receives aninput clock signal 12 under test and the output of the OTA. The output of theVCDCG 29 is the duty cycle corrected clock generated by a signal of a desired duty cycle in accordance with the output of the OTA (Vcont voltage). - FIG. 2 illustrates an example encoding table100 representing the
SAR bit assignments 110 corresponding to the signals ofvarious duty cycles 120 and corresponding DAC output voltages. In the example system described herein, 4-bits of accuracy is assumed as is a voltage supply of 1.8 Volts DC assumed. The operation of the duty cycle measuring circuit of the invention is commenced by setting the output of theSAR register 50 to a digital code 102 representing an initial 50/50 duty cycle 104. This SAR setting and correspondingDAC output voltage 66 will initially reset theLock Detector circuit 75 to “zero” for disabling theCOMP 35. This setting constitutes the start of the first cycle of the Successive Approximation Technique of the invention. Typically, this technique requires at least the same number of cycles as the accuracy of its DAC. For example, a four-bit DAC 60 will enable the technique to reach a solution in four (4) cycles. Following the example in Table 1, the starting digital code would be “1000” which causes theDAC 60 to output a voltage equal to half of the power supply. Thus, from the table of FIG. 2, for the initial SAR setting 102 of 50/50 duty cycle and given a power supply voltage of 1.8V, the voltage representing the 50/50 duty cycle is (1.8)/2 or 0.9V. - As mentioned in view of FIG. 1, the
output 66 of theDAC 60 is connected to one of the inputs of the Operational Transconductance Amplifier orOTA 23 provided in the programmable dutycycle adjuster circuit 25. TheOTA 23 additionally receives as input theoutput 26 of aLow Pass Filter 2 orLPF2 40 whose voltage is a representation of the duty cycle out of the Voltage Controlled Duty Cycle Generator or VCDCG 29. TheOTA 23 outputs a current proportional to the difference in voltage of its two inputs. If the voltage at theoutput 66 of theDAC 60 is higher than thevoltage 26 output of theLPF2 40, theIOTA 23 will charge the capacitor C1, thus raising the voltage at the output of theOTA 23 and at the Vcont input pin of theVCDCG 29. This, in turn, will force the duty cycle at the output of theVCDCG 29 and the output of theLPF2 40 to move closer to the duty cycle depicted by theDAC 60. Eventually, after the lock time ofLoop 1, theoutput 26 of theLPF2 40 will match the output of theDAC 60 and cause the Lock Detector to go to a “one” which enables theCOMP 35. The two inputs of the COMP are theoutput 26 ofLPF2 40 and theoutput 36 of LPF1 30 which represents the duty cycle of theinput signal 12 whose duty cycle is being measured. - FIGS.3(a)-3(c) represent various timing features of the duty
cycle measuring circuit 10 according to an example implementation having an example signal under test with a duty cycle of 45/55. In the example implementation of FIG. 3(a), in a first cycle of operation, theoutput 66 of the DAC is 0.9 volts corresponding to an initial SAR register setting of “1000” as mentioned above. According to the example and, in further view of the table 100 of FIG. 2. the example signal under test having with a duty cycle of 45/55 will generate anoutput voltage 36 at theLPF1 30 of 0.45×1.8V or 0.81 V. Since the output of LPF1 is lower than the output of LPF2, then 50/50 is larger than the duty cycle of the signal under test. In response, theCOMP 35 will output a “zero” 39 forcing the most significant bit of theSAR 50 to change and latch a “zero”. At the same time, the second most significant bit gets set to a “one” or “0100”. In view of table 100 of FIG. 2, the output of theDAC 60 will now be at a value of 0.828V half way between 0.9V and the minimum voltage value of the DAC. The change in input to theDAC 60 causes a change at the input of the OTA and theinput 66 to the Lock Detector, causing the Lock Detector to output a “zero” disabling the COMP. FIG. 3(b) illustrates the setting of thelock signal 38 to a zero which marks the beginning ofCycle 2 of the Successive Approximation technique. - As described earlier, after the lock time of
Loop 1, the output of LPF2 will match theoutput 66 of the DAC thus, forcing the Lock Detector to go to a “one” enabling theCOMP 35 and evaluating its input. Since theoutput voltage 36 of LPF1 is still lower than theoutput 26 of LPF2, the COMP will go to “zero” changing and latching the second most significant bit to “zero”. At the same time, the third most significant bit will go to “1” resulting in an SAR digital code word of “00010”. TheDAC 60, for the third time will change its output value to ¼ of the value between 0.9V and the minimum value of the DAC, or 0.792V. TheLock Detector output 38 will go to “zero” in the third cycle thus disabling theCOMP 35. Again, after the lock time ofLoop 1, the output of LPF2 40 will reach the same voltage as the output of the DAC forcing the Lock Detector to go to “one” and thus enabling the COMP. Now the output of LPF2 is lower than LPF1, the COMP will output a “one” thus keeping and latching the “one” as the third most significant bit. At the same time, the least significant bit (LSB) shifts to “one” resulting in an SAR code of “0011” which corresponds to a DAC output of 0.81V. This new value results in theoutput 26 of LPF2 40 to be equal to theoutput 36 LPF1 in the fourth cycle, and the LSB will stay at a “one” indicating that the duty cycle of the signal under test is 45/55. The resulting digital output code of “0011” may then be read out by any digital testing device, either in parallel or, shifted out serially at a single IC output pin/wire. - The result will have an accuracy of +/−½ lsb, and therefore, the accuracy of the DAC and the range of measured duty cycle determine the accuracy of the result. In the example described, each digital code represents 1% of duty cycle. With only 4-bits, the maximum duty cycles that can be measured will be limited to 57/43 and 42/58, respectively. The design of the
VCDCG 29 has certain operational frequency limits to provide the desired noise immunity and hence, it is important to know the relative frequency range. The slope of the curve of duty cycle versus VCONT is affected by the number of stages of theVCDCG 29 which is, in turn, a function of the expected frequency range. A commonly-owned disclosure entitled “Enhanced Operational Frequency for a precise and programmable Duty Cycle Generator” [IBM Reference No. RAL8-2000-0029], describes a means to address these frequency limitations. - While the invention has been particularly shown and described with respect to illustrative and preformed embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention which should be limited only by the scope of the appended claims.
Claims (17)
1. A system for accurately measuring the duty cycle of an input periodic pulsed signal comprising:
device for converting said input signal to be measured into a first dc voltage;
device for encoding a plurality of duty cycle values for selection thereof in an iterative manner, one value of which represents a duty cycle of said input signal;
device for iteratively generating a second dc voltage according to a difference between the duty cycle of said input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value;
selection mechanism responsive to said first and second dc voltages for selecting an encoded duty cycle value for each iteration, said system selecting an encoded duty cycle value in each successive iteration until said first and second dc voltages are matching, wherein said selected encoded duty cycle value at that iteration represents the duty cycle of said input voltage for output thereof.
2. The system according to claim 1 , further comprising a device for generating a reference dc voltage having a value according to a selected duty cycle value in each iteration, said device for iteratively generating a second dc voltage comprising:
voltage controlled duty cycle generator system for receiving said input signal to be measured and converting said input signal into a periodic signal having a duty cycle in accordance with said reference dc voltage value for each iteration; and,
device for converting said generated periodic signal into said second dc voltage for each iteration.
3. The system according to claim 2 , wherein said selection mechanism comprises a device for comparing said first dc voltage and second dc voltage at each iteration and generating an output voltage in accordance with said difference, said output voltage for selecting a further encoded duty cycle value for a next successive iteration.
4. The system according to claim 3 , wherein said voltage controlled duty cycle generator system is a closed loop system, operating for a lock time period defined as a time interval for said generated second dc voltage to match said current reference dc voltage in each iteration.
5. The system according to claim 3 , wherein said further comprising a locking device for preventing said comparing of said first dc and second dc voltages during said lock time period, and enabling said comparing at each iteration when said generated second dc voltage matches said current reference dc voltage.
6. The system according to claim 4 , wherein said encoding device comprises an n-bit successive approximation register for digitally encoding said duty cycle values.
7. The system according to claim 6 , wherein said output comprises a digitally encoded word capable of being read out one in parallel or shifted out serially to a common output pin.
8. The system according to claim 6 , wherein said device for generating a reference de voltage includes an n-bit digital to analog converter (DAC) device, said system capable of generating an output signal in a number of iterations as determined by an accuracy of said DAC.
9. The system according to claim 4 , wherein said device for converting said input signal to be measured into a first dc voltage comprises a low pass filter device.
10. A method for accurately measuring the duty cycle of an input periodic pulsed signal comprising the steps of:
a) converting said input signal to be measured into a first dc voltage:
b) selecting one duty cycle value of a plurality of encoded duty cycle values, one encoded value of said plurality representing a duty cycle of said input signal;
c) generating a second dc voltage according to a difference between the duty cycle of said input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value;
d) enabling a comparison of said generated first dc and second dc voltages; and
e) repeating steps b) through d) until said first and second dc voltages are matching, wherein said selected encoded duty cycle value at that iteration represents the duty cycle of said input voltage for output thereof.
11. The method according to claim 10 , wherein after said selecting step b), the step of: generating a reference dc voltage having a value according to a selected duty cycle value in each iteration.
12. The method according to claim 11 , wherein said generating step c) comprises the steps of: converting said input signal to be measured into a periodic signal having a duty cycle in accordance with said reference dc voltage value for each iteration; and, converting said generated periodic signal into said second dc voltage for each iteration.
13. The method according to claim 12 , wherein said selecting step b) comprises the step of: generating an output voltage in accordance with a difference between said first dc voltage and second dc voltage at each iteration, and, utilizing said output voltage for selecting a further encoded duty cycle value for a next successive iteration.
14. The method according to claim 12 , wherein said step of converting said generated periodic signal into a second dc voltage occurs for a lock time period defined as a time interval for said generated second dc voltage to match said current reference dc voltage in each iteration.
15. The method according to claim 14 , further comprising the step of: preventing said comparison of said first dc and second dc voltages during said lock time period, and enabling said comparison at each iteration when said generated second dc voltage matches said current reference dc voltage.
16. The method according to claim 13 , wherein said step b) of selecting one duty cycle value of a plurality of encoded duty cycle values further includes inputting said output voltage into an encoding device comprising an n-bit successive approximation register for digitally encoding said duty cycle values, said output voltage enabling selection of a different duty cycle value in each iteration.
17. The method according to claim 16 , wherein said output comprises a digitally encoded word capable of being read out one in parallel or shifted out serially to a common output pin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/766,200 US6441600B1 (en) | 2001-01-19 | 2001-01-19 | Apparatus for measuring the duty cycle of a high speed clocking signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/766,200 US6441600B1 (en) | 2001-01-19 | 2001-01-19 | Apparatus for measuring the duty cycle of a high speed clocking signal |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020097035A1 true US20020097035A1 (en) | 2002-07-25 |
US6441600B1 US6441600B1 (en) | 2002-08-27 |
Family
ID=25075704
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/766,200 Expired - Fee Related US6441600B1 (en) | 2001-01-19 | 2001-01-19 | Apparatus for measuring the duty cycle of a high speed clocking signal |
Country Status (1)
Country | Link |
---|---|
US (1) | US6441600B1 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007067378A2 (en) * | 2005-12-08 | 2007-06-14 | Teradyne, Inc. | Calibration circuitry |
US20070255517A1 (en) * | 2006-05-01 | 2007-11-01 | Ibm Corporation | Method and apparatus for on-chip duty cycle measurement |
US20070252629A1 (en) * | 2006-05-01 | 2007-11-01 | Ibm Corporation | Method and apparatus for correcting the duty cycle of a digital signal |
US20070266285A1 (en) * | 2006-05-01 | 2007-11-15 | Ibm Corporation | Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode |
US20070271051A1 (en) * | 2006-05-01 | 2007-11-22 | Ibm Corporation | Method and apparatus for measuring the duty cycle of a digital signal |
US20070271068A1 (en) * | 2006-05-01 | 2007-11-22 | Ibm Corporation | Method and Apparatus for Measuring the Relative Duty Cycle of a Clock Signal |
CN100414511C (en) * | 2005-10-27 | 2008-08-27 | 国际商业机器公司 | Duty cycle measurement apparatus and method |
US20090125857A1 (en) * | 2007-11-12 | 2009-05-14 | International Business Machines Corporation | Design Structure for an Absolute Duty Cycle Measurement Circuit |
US20090128133A1 (en) * | 2007-11-20 | 2009-05-21 | Boerstler David W | Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device |
US20090138834A1 (en) * | 2007-11-20 | 2009-05-28 | International Business Machines Corporation | Structure for a Duty Cycle Measurement Circuit |
US7646177B2 (en) | 2006-05-01 | 2010-01-12 | International Business Machines Corporation | Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode |
US7904264B2 (en) | 2007-11-12 | 2011-03-08 | International Business Machines Corporation | Absolute duty cycle measurement |
US20120086474A1 (en) * | 2008-10-30 | 2012-04-12 | Siemens Aktiengesellschaft | Field Device for Process Automation |
CN112054741A (en) * | 2020-08-06 | 2020-12-08 | 深圳市杉川机器人有限公司 | Motor control method and device, terminal equipment and storage medium |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7164310B1 (en) * | 2001-04-12 | 2007-01-16 | Integration Associates Inc. | Systems and apparatus for digital control of bias for transistors |
US6593789B2 (en) * | 2001-12-14 | 2003-07-15 | International Business Machines Corporation | Precise and programmable duty cycle generator |
US6509771B1 (en) * | 2001-12-14 | 2003-01-21 | International Business Machines Corporation | Enhanced operational frequency for a precise and programmable duty cycle generator |
US6529055B1 (en) * | 2001-12-21 | 2003-03-04 | Xerox Corporation | Method for adjusting the center frequency of a phase locked loop |
US6943556B2 (en) * | 2003-06-30 | 2005-09-13 | Intel Corporation | High-speed duty cycle test through DC measurement using a combination of relays |
US7151367B2 (en) * | 2004-03-31 | 2006-12-19 | Teradyne, Inc. | Method of measuring duty cycle |
US7084790B2 (en) * | 2004-12-07 | 2006-08-01 | Stmicroelectronics S.R.L. | Device to effectuate a digital estimate of a periodic electric signal, related method and control system for an electric motor which comprises said device |
US20080136468A1 (en) * | 2006-12-06 | 2008-06-12 | Dandan Li | Method and system for doubling phase-frequency detector comparison frequency for a fractional-n pll |
US8773186B1 (en) * | 2013-08-01 | 2014-07-08 | Elite Semiconductor Memory Technology Inc. | Duty cycle correction circuit |
CN104579332B (en) * | 2013-10-29 | 2018-06-19 | 晶豪科技股份有限公司 | Responsibility cycle correcting circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4041386A (en) | 1976-05-21 | 1977-08-09 | Data Test Corporation | Multifunctional circuit analyzer |
US4164733A (en) | 1977-04-29 | 1979-08-14 | Siliconix Inc. | Quantized feedback analog to digital converter with offset voltage compensation |
US4475086A (en) | 1982-03-31 | 1984-10-02 | Eastman Kodak Company | Duty cycle detector |
US5130565A (en) * | 1991-09-06 | 1992-07-14 | Xerox Corporation | Self calibrating PWM utilizing feedback loop for adjusting duty cycles of output signal |
US5367200A (en) | 1993-11-29 | 1994-11-22 | Northern Telecom Limited | Method and apparatus for measuring the duty cycle of a digital signal |
US6040726A (en) | 1998-09-14 | 2000-03-21 | Lucent Technologies Inc. | Digital duty cycle correction loop apparatus and method |
US6316926B1 (en) * | 2000-05-19 | 2001-11-13 | Stmicroelectronics S.R.L. | Switching control circuit |
-
2001
- 2001-01-19 US US09/766,200 patent/US6441600B1/en not_active Expired - Fee Related
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100414511C (en) * | 2005-10-27 | 2008-08-27 | 国际商业机器公司 | Duty cycle measurement apparatus and method |
WO2007067378A2 (en) * | 2005-12-08 | 2007-06-14 | Teradyne, Inc. | Calibration circuitry |
JP4728403B2 (en) * | 2005-12-08 | 2011-07-20 | テラダイン、 インコーポレイテッド | Calibration circuit |
WO2007067378A3 (en) * | 2005-12-08 | 2007-11-01 | Teradyne Inc | Calibration circuitry |
KR101257251B1 (en) | 2005-12-08 | 2013-04-23 | 테라다인 인코퍼레이티드 | Calibration circuitry |
JP2009518952A (en) * | 2005-12-08 | 2009-05-07 | テラダイン、 インコーポレイテッド | Calibration circuit |
US20070266285A1 (en) * | 2006-05-01 | 2007-11-15 | Ibm Corporation | Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode |
US20070271068A1 (en) * | 2006-05-01 | 2007-11-22 | Ibm Corporation | Method and Apparatus for Measuring the Relative Duty Cycle of a Clock Signal |
US7330061B2 (en) | 2006-05-01 | 2008-02-12 | International Business Machines Corporation | Method and apparatus for correcting the duty cycle of a digital signal |
US7333905B2 (en) | 2006-05-01 | 2008-02-19 | International Business Machines Corporation | Method and apparatus for measuring the duty cycle of a digital signal |
US7363178B2 (en) | 2006-05-01 | 2008-04-22 | International Business Machines Corporation | Method and apparatus for measuring the relative duty cycle of a clock signal |
US20080174345A1 (en) * | 2006-05-01 | 2008-07-24 | Ibm Corporation | Method and apparatus for measuring the duty cycle of a digital signal |
US20070271051A1 (en) * | 2006-05-01 | 2007-11-22 | Ibm Corporation | Method and apparatus for measuring the duty cycle of a digital signal |
US7420400B2 (en) | 2006-05-01 | 2008-09-02 | International Business Machines Corporation | Method and apparatus for on-chip duty cycle measurement |
US7617059B2 (en) | 2006-05-01 | 2009-11-10 | International Business Machines Corporation | Method and apparatus for measuring the duty cycle of a digital signal |
US20070252629A1 (en) * | 2006-05-01 | 2007-11-01 | Ibm Corporation | Method and apparatus for correcting the duty cycle of a digital signal |
US20070255517A1 (en) * | 2006-05-01 | 2007-11-01 | Ibm Corporation | Method and apparatus for on-chip duty cycle measurement |
US7646177B2 (en) | 2006-05-01 | 2010-01-12 | International Business Machines Corporation | Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode |
US7595675B2 (en) | 2006-05-01 | 2009-09-29 | International Business Machines Corporation | Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode |
WO2007132015A1 (en) * | 2006-05-16 | 2007-11-22 | International Business Machines Corporation | Method and apparatus for measuring the duty cycle or relative duty cycle of a digital signal |
US7904264B2 (en) | 2007-11-12 | 2011-03-08 | International Business Machines Corporation | Absolute duty cycle measurement |
US8032850B2 (en) | 2007-11-12 | 2011-10-04 | International Business Machines Corporation | Structure for an absolute duty cycle measurement circuit |
US20090125857A1 (en) * | 2007-11-12 | 2009-05-14 | International Business Machines Corporation | Design Structure for an Absolute Duty Cycle Measurement Circuit |
US20090138834A1 (en) * | 2007-11-20 | 2009-05-28 | International Business Machines Corporation | Structure for a Duty Cycle Measurement Circuit |
US7895005B2 (en) | 2007-11-20 | 2011-02-22 | International Business Machines Corporation | Duty cycle measurement for various signals throughout an integrated circuit device |
US7917318B2 (en) | 2007-11-20 | 2011-03-29 | International Business Machines Corporation | Structure for a duty cycle measurement circuit |
US20090128133A1 (en) * | 2007-11-20 | 2009-05-21 | Boerstler David W | Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device |
US20120086474A1 (en) * | 2008-10-30 | 2012-04-12 | Siemens Aktiengesellschaft | Field Device for Process Automation |
US8970203B2 (en) * | 2008-10-30 | 2015-03-03 | Siemens Aktiengesellschaft | Field device for process automation |
CN112054741A (en) * | 2020-08-06 | 2020-12-08 | 深圳市杉川机器人有限公司 | Motor control method and device, terminal equipment and storage medium |
Also Published As
Publication number | Publication date |
---|---|
US6441600B1 (en) | 2002-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6441600B1 (en) | Apparatus for measuring the duty cycle of a high speed clocking signal | |
US6396889B1 (en) | Method and circuit for built in self test of phase locked loops | |
JP2619988B2 (en) | Integrated circuit including analog-to-digital converter and self-test means | |
US5589788A (en) | Timing adjustment circuit | |
US6211803B1 (en) | Test circuit and method for measuring switching point voltages and integral non-linearity (INL) of analog to digital converters | |
US8378865B2 (en) | Method of testing digital-to-analog and analog-to-digital converters | |
Nadeau-Dostie | Design for at-speed test, diagnosis and measurement | |
US7603602B2 (en) | Built-in self test circuit for analog-to-digital converter and phase lock loop and the testing methods thereof | |
KR100269704B1 (en) | Apparatus for testing delay circuit and integrated circuit including means for testing the same | |
US7719453B2 (en) | Analogue-digital converter using Josephson DAC and method thereof | |
US5712855A (en) | Apparatus for testing and measuring electronic device and method of calibrating its timing and voltage level | |
US4745310A (en) | Programmable delay circuit | |
US6316929B1 (en) | Frequency measurement test circuit and semiconductor integrated circuit having the same | |
US7274185B2 (en) | Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices | |
Liu et al. | A high-accuracy programmable pulse generator with a 10-ps timing resolution | |
JP2011223404A (en) | Operation testing method for analog-digital converter, analog-digital converter, and operation testing device for analog-digital converter | |
EP0191478B1 (en) | Measurement circuit for evaluating a digital-to-analog converter | |
JP2002006003A (en) | All digital built-in self-inspection circuit for phase lock loop and inspecting method | |
US6011500A (en) | Integrated circuit with a built-in D/A converter | |
Chang et al. | BIST scheme for DAC testing | |
US8860592B2 (en) | Signal generating circuit | |
US9213669B2 (en) | Test apparatus and test method | |
US20030220758A1 (en) | Method for testing an AD-converter | |
US7324027B2 (en) | Circuit and method for testing analog-digital converter | |
JP3265286B2 (en) | A / D converter test equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ATALLAH, FRANCOIS IBRAHIM;CORREALE, ANTHONY, JR.;REEL/FRAME:011486/0615 Effective date: 20010119 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140827 |