US20020090789A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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US20020090789A1
US20020090789A1 US10/092,526 US9252602A US2002090789A1 US 20020090789 A1 US20020090789 A1 US 20020090789A1 US 9252602 A US9252602 A US 9252602A US 2002090789 A1 US2002090789 A1 US 2002090789A1
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layer
base
semiconductor device
contact layer
base contact
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Hisao Shigematsu
Kenji Imanishi
Hitoshi Tanaka
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to US11/508,152 priority patent/US20060284213A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L31/03046—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP

Definitions

  • the present invention relates to a semiconductor device of a hetero-junction bipolar transistor structure, and a method for fabricating the same.
  • HBTs Hetero-junction bipolar transistors
  • a collector contact layer 102 formed of an n + -InGaAs layer is formed on a semi-insulating InP substrate 100 .
  • a collector layer 104 of an i-InGaAs layer is formed on the collector contact layer 102 .
  • a base layer 106 of a p + -InGaAs layer is formed on the collector layer 104 .
  • An emitter layer 108 of an n-InP layer is formed on the base layer 106 .
  • An emitter contact layer 110 of an n + -InGaAs layer is formed on the emitter layer 108 .
  • An emitter electrode 112 of WSi film is formed on the emitter contact layer 110 .
  • the emitter contact layer 110 and the emitter layer 108 are processed in a mesa-shape, and a base electrode 116 is formed on an exposed part of the base layer 106 .
  • the base layer 106 and the collector layer 104 are processed in a mesa-shape, and a collector electrode 118 is formed on an exposed part of the collector contact layer 102 .
  • an InP/InGaAs-based HBT is formed.
  • a maximum oscillation frequency f max is expressed by
  • f max ⁇ square root ⁇ square root over ( ) ⁇ ( f T /(8 ⁇ R B ⁇ C BC ))
  • a maximum cut-off frequency is represented by f T
  • a base resistance is represented by R B
  • a base-collector capacitance is represented by C BC .
  • a maximum oscillation frequency f max is proportional to a reciprocal of a square root of a base resistance R B ( ⁇ square root ⁇ square root over ( ) ⁇ (1/(R B ))), and for a higher maximum oscillation frequency f max , it is necessary to obtain a lower base resistance R B .
  • InP/InGaAs-based HBTs actually doping techniques using carbon as a dopant for the base have not been sufficiently established.
  • the base layer cannot be heavily doped with carbon, and this will be because carbon is not dissociated from hydrogen in forming InGaAs layer to be the base layer to be taken in the films in the form of CH, and the carbon does not function as an acceptor (hydrogen passivation).
  • This phenomenon is conspicuous especially in MOCVD method using hydrogen as a carrier gas and a hydrogen content gas as a source gas.
  • InP/InGaAs-based HBTs have very high maximum cut-off frequencies f T but cannot have sufficiently maximum oscillation frequencies f max .
  • An object of the present invention is to provide a structure of a semiconductor device which enables an InP/InGaAs-based HBT to have a lower base resistance, and a method for fabricating the same.
  • the above-described object can be achieved by a semiconductor device comprising: a collector layer; a base layer of a carbon-doped Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer having one surface connected to the collector layer; an emitter layer connected the other surface of the base layer; a base contact layer of a carbon-doped GaAsSb layer electrically connected to the base layer; and a base electrode formed on the base contact layer.
  • the semiconductor device of such structure can have a much reduced base resistance R B , whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency f max . Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
  • the base contact layer is formed on said one surface or said the other surface of the base layer.
  • the base contact layer is formed on a surface of the collector layer connected to the base layer and has a side surface connected to a side surface of the base layer.
  • the base contact layer is formed on a surface of the emitter layer connected to the base layer and has a side surface connected to a side surface of the base layer.
  • the device further comprises a surface passivation layer for protecting the base contact layer formed on the surface of the base contact layer with the base electrode formed on. Because of the surface passivation layer covering the surface of the base contact layer, surface recombination on the base contact layer can be restrained, whereby dependence of current gains on sizes can be restrained, and the semiconductor device can have higher reliability.
  • the base contact layer is formed of a carbon-doped GaInAsSb layer in place of said carbon-doped GaAsSb layer.
  • an In composition x of the Ga x In 1 ⁇ x As y Sb 1 ⁇ y is 0, so that the base layer is formed of a GaAsSb layer.
  • a dopant concentration of the base contact layer is not less than 1 ⁇ 10 20 cm 31 3 .
  • the above-described object can be also achieved by a method for fabricating a semiconductor device comprising the steps of: forming a first semiconductor layer on a semiconductor substrate; forming a base layer of a carbon-doped Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer on the first semiconductor layer; forming a second semiconductor layer on the base layer; patterning the second semiconductor layer in a mesa-shape; forming a base contact layer on the base layer exposed by patterning the second semiconductor layer; and forming a base electrode on the base contact layer.
  • the semiconductor device can have a much reduced base resistance R B , whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency f max . Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
  • the method further comprises, after the step of patterning the second semiconductor layer, a step of removing the base contact layer in a exposed region which is exposed by patterning the second semiconductor layer, wherein in the step of forming the base contact layer, the base contact layer having a side surface connected to the base layer is formed on the first semiconductor layer exposed by removing the base layer.
  • the base layer of an InGaAs layer which corresponds to the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer whose As composition y is 1, or a GaAsSb layer which corresponds to the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer whose In composition X is 0 is formed.
  • the base contact layer is formed of a material which lattice-matches with a material forming the base layer.
  • the base contact layer is formed of a material which lattice-matches with a material forming the base layer, whereby characteristic deterioration of the semiconductor device due to lattice deformation can be prevented.
  • the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer.
  • the base contact layer is formed of such carbon-doped materials, whereby the base contact layer can effectively have a low resistance, and the semiconductor device can have higher reliability.
  • the method further comprises, before the step of forming the base contact layer, a step of thermal-treating for eliminating hydrogen in the base layer. Hydrogen in the base layer is eliminated, whereby carbon bonded with the hydrogen is electrically activated, whereby the base layer can have a further lower resistance.
  • the method further comprises, after the step of patterning the second semiconductor layer, a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer.
  • the method further comprises, after the step of forming the base contact layer, a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer. Because of the surface passivation layer covering the surface of the base contact layer, surface recombination on the base contact layer can be restrained, whereby dependence of current gains on sizes can be restrained, and the semiconductor device can have higher reliability.
  • the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer.
  • the structure of the semiconductor device according to the present invention is applicable to not only a semiconductor device including a collector layer, a base layer and an emitter layer sequentially deposited on a semiconductor substrate, but also a semiconductor device of the so-called collector-up structure including an emitter layer, a base layer and a collector layer sequentially deposited on a semiconductor substrate.
  • FIG. 1 is a diagrammatic sectional view of the semiconductor device according to a first embodiment of the present invention.
  • FIGS. 2 A- 2 C and 3 A- 3 C are sectional views of the semiconductor device according to the first embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 4 is a diagrammatic sectional view of the semiconductor device according to a second embodiment of the present invention.
  • FIGS. 5 A- 5 B and 6 A- 6 B are sectional views of the semiconductor device according to the second embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 7 is a diagrammatic sectional view of the semiconductor device according to a third embodiment of the present invention.
  • FIGS. 8 A- 8 B and 9 A- 9 B are sectional views of the semiconductor device according to the third embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 10 is a diagrammatic sectional view of the semiconductor device according to one modification of the first embodiment of the present invention.
  • FIG. 11 is a diagrammatic sectional view of the conventional semiconductor device, which shows a structure thereof.
  • FIGS. 1 , 2 A- 2 C and 3 A- 3 C A semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIGS. 1 , 2 A- 2 C and 3 A- 3 C.
  • FIG. 1 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof, and FIGS. 2 A- 2 C and 3 A- 3 C are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device according to the present embodiment.
  • a collector contact layer 12 of an n + -InGaAs layer is formed on a semi-insulating InP substrate 10 .
  • a collector layer 14 of an i-InGaAs layer is formed on the collector contact layer 12 .
  • a base layer 16 of a p + -InGaAs layer is formed on the collector layer 14 .
  • An emitter layer 18 of an n-InP layer is formed on the base layer 16 .
  • An emitter contact layer 20 of an n + -InP layer and an emitter contact layer 22 of an n + -InGaAs layer are formed on the emitter layer 18 .
  • An emitter electrode 26 of WSi (tungsten silicide) film is formed on the emitter contact layer 22 .
  • the emitter contact layers 20 , 22 and the emitter layer 18 are processed in a mesa-shape, and a sidewall insulation film 28 of SiN film is formed on the side wall of the emitter mesa.
  • a base contact layer 30 of a p ++ -GaAsSb layer is formed on the base layer 16 , which is exposed.
  • a base electrode 32 is formed on the base contact layer 30 .
  • the base contact layer 30 , the base layer 16 and the collector layer 14 are processed in a mesa-shape.
  • a collector electrode 36 is formed on the contact layer 12 , which is exposed. Thus, an InP/InGaAs-based HBT is formed.
  • the semiconductor device according to the present embodiment is characterized in that the base contact layer 30 of a p ++ -GaAsSb layer is formed on the base layer 16 .
  • a base resistance R B which influences a maximum oscillation frequency f max , is determined by a sheet resistance of the base layer and a contact resistance between the base layer and the base electrode.
  • the base layer 106 is formed of the carbon-doped InGaAs, but in this case unless the base layer 106 has a resistance sufficiently reduced, resultantly a base resistance R B is much increased, which leads to a lower maximum oscillation frequency f max .
  • the base contact layer 30 of a p ++ -GaAsSb layer formed on the base layer 16 can much reduce a resistance between an intrinsic base region (the region of the base layer 16 immediately below the emitter layer 18 ) and the base electrode 32 . Accordingly, a much reduced base resistance R B can be obtained, and a higher maximum oscillation frequency f max can be obtained.
  • the collector contact layer 12 of an n + -InGaAs layer (film thickness: 350 nm; electron concentration: 1 ⁇ 10 19 cm ⁇ 3 ), the collector layer 14 of an i-InGaAs layer (film thickness: 300 nm), the base layer 16 of a p + -InGaAs layer (film thickness: 30 nm; hole concentration: 1 ⁇ 10 19 cm ⁇ 3 ), the emitter layer 18 of an n-InP layer (film thickness: 50 nm; electron concentration 3 ⁇ 10 17 cm ⁇ 3 ), the emitter contact layer 20 of an n + -InP layer (film thickness: 25 nm; electron concentration 5 ⁇ 10 18 cm ⁇ 3 ) and the emitter contact layer 22 of an n + -InGaAs layer (film thickness: 50 nm; electron concentration; 1 ⁇ 10 19 cm ⁇ 3 ) are sequentially deposited on a semi-insulating InP substrate 10 by, e.g., MOCVD method. Then, the collector contact layer 12
  • the WSi film 24 is patterned by, e.g., dry etching to form the emitter electrode 26 of the WSi film 24 .
  • the emitter contact layer 22 of the n + -InGaAs layer is selectively etched with the emitter electrode 26 as a mask and by the use of an etchant of, H 3 PO 4 :H 2 O 2 :H 2 O solution.
  • the emitter contact layer 20 and the emitter layer 18 are selectively etched by the use of an etchant of, e.g., HCl:H 3 PO 4 solution.
  • an emitter mesa of the emitter layer 18 , the emitter contact layer 20 , the emitter contact layer 22 and the emitter electrode 26 is formed (FIG. 2B).
  • SiN film is deposited on the entire surface by, e.g., CVD method and anisotropically etched to leave the SiN film on only the side wall of the emitter mesa.
  • the sidewall insulation film 28 of the SiN film is formed on the side wall of the emitter mesa (FIG. 2C).
  • the substrate with the emitter mesa thus formed is annealed.
  • This annealing is for eliminating hydrogen introduced into the base layer 16 during the film depositing step, and can prevent hydrogen passivation.
  • the annealing at above about 300° C. can eliminate hydrogen in the film.
  • the InGaAs layer of the base layer 16 is annealed in its exposed state, whereby hydrogen can be removed more effectively than in a case that the emitter layer 18 , etc. are formed on the base layer 16 .
  • the base contact layer 30 of an 125 nm-thick p ++ -GaAsSb layer heavily doped with carbon is selectively grown by, e.g., MOCVD method on the base layer 16 exposed around the emitter mesa.
  • GaAsSb can be doped heavily with an about 5 ⁇ 10 20 cm ⁇ 3 concentration carbon, and the base contact layer 30 to be connected to the base layer 16 is formed of the heavily doped p ++ -GaAsSb layer, whereby the base region can have a much lower sheet resistance R B and contact resistance.
  • the base contact layer 30 is formed of one selected from materials which contain no In and lattice-match with the material of the base layer 16 . It is empirically known that In-content groups are apt to have hydrogen passivation. Lattice mismatch introduces lattice deformation which leads to characteristic deterioration.
  • a composition of GaAs 1 ⁇ x Sb x has an antimony composition ratio x of 0.1 ⁇ 0.9, whereby the base contact layer 30 can be lattice-matched with the base layer 16 of an InGaAs layer without lattice deformation.
  • the lattice constant of GaAsSb is substantially the same as the lattice constant of InGaAs.
  • the base contact layer 30 is doped with, e.g., a high concentration of about 1 ⁇ 10 20 cm ⁇ 3 .
  • a dopant concentration in the base contact layer 30 is suitably adjusted in accordance with a film thickness or others of the base contact layer 30 .
  • the base electrode 32 of, e.g., a Pt/Ti/Pt/Au structure is formed on the base contact layer 30 by, e.g., lift-off method (FIG. 3A).
  • a resist mask 34 formed covering the emitter mesa and extended over the base electrode 32 is formed, and then the base contact layer 30 , the base layer 16 and the collector layer 14 are sequentially etched with the resist mask 34 and the base electrode 32 as a mask.
  • the base mesa of the collector layer 14 , the base layer 16 and the base contact layer 30 is formed (FIG. 3B).
  • the collector electrode 35 of, e.g., a Ti/Pt/Au structure is formed on the exposed collector contact layer 12 by, e.g., lift-off method (FIG. 3C).
  • an HBT including the base layer 16 of a carbon-doped p + -InGaAs layer and the base contact layer 30 of a p ++ -GaAsSb layer having a low resistance can be formed.
  • the base contact layer 30 of a heavily carbon-doped p ++ -GaAsSb layer having a low resistance is formed on the base layer 16 , whereby a much reduced base resistance R B can be obtained.
  • an InP/InGaAs-base HBT can have an increased maximum oscillation frequency f max .
  • FIGS. 4 , 5 A- 5 B and 6 A- 6 C The same members of the second embodiment as those of the semiconductor device and the method for fabricating the same according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.
  • FIG. 4 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof.
  • FIGS. 5 A- 5 B and 6 A- 6 B are sectional views of the semiconductor device in the steps of the method for fabricating the semiconductor device, which show the method.
  • the base contact layer 30 of the p ++ -GaAsSb layer is formed on the base layer 16 but may be connected to the base layer 16 at the sides thereof.
  • the emitter mesa is formed of the emitter contact layers 22 , 20 , the emitter layer 18 and the base layer 16 , and the base contact layer 30 formed on the collector layer 14 is connected to the base layer 16 at the side surface thereof.
  • the semiconductor device having such structure can have a lower base resistance R B .
  • the emitter mesa of the emitter contact layers 22 , 20 and the emitter layer 18 , and the sidewall insulation film 28 on the side wall of the emitter mesa is formed (FIG. 5A).
  • the substrate with the emitter mesa thus formed is annealed. This annealing is for eliminating hydrogen introduced into the base layer 16 during the film depositing step, and can prevent hydrogen passivation.
  • the base contact layer 30 of an about 155 nm-thick p ++ -GaAsSb layer heavily doped with carbon is selectively grown by, e.g., MOCVD method on the collector layer 14 exposed around the emitter mesa (FIG. 6A).
  • an HBT including the base layer 16 of a carbon-doped p + -InGaAs layer, and the base contact layer 30 of p ++ -GaAsSb layer having a low resistance (FIG. 6B).
  • the base contact layer 30 of a p ++ -GaAsSb layer is formed connected to the base layer 16 at the side thereof, whereby a very low base resistance R B can be obtained.
  • FIGS. 7 , 8 A- 8 B and 9 A- 9 B A semiconductor device and a method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS. 7 , 8 A- 8 B and 9 A- 9 B.
  • FIG. 7 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof.
  • FIGS. 8 A- 8 B and 9 A- 9 B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the same, which show the method.
  • the basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. 1 but is characterized in that a surface passivation layer 38 of InP layer is formed on the base contact layer 30 .
  • the surface passivation layer 38 of InP layer is formed on the base contact layer 30 of the p ++ -GaAsSb layer, whereby surface recombination of the p ++ -GaAsSb layer forming the base contact layer 30 can be restrained, whereby size dependence of current gain can be restrained, and higher reliability can be obtained.
  • the base electrode 32 is based on an alloy, e.g., Pd/Zn/Pt/Au or others.
  • the emitter mesa of the emitter contact layers 22 , 20 and the emitter layer 18 is formed, and the sidewall insulation film 28 is formed on the side wall of the emitter mesa (FIG. 8A).
  • the substrate with the emitter mesa thus formed on is annealed. This annealing is for eliminating hydrogen which may be introduced into the base layer 16 during the film forming steps and can prevent hydrogen passivation.
  • the base contact layer 30 of an about 125 nm-thick p ++ -GaAsSb layer heavily doped with carbon is grown selectively on the base layer 16 exposed around the emitter mesa by, e.g., MOCVD method.
  • the surface passivation layer 38 of an about 30 nm-thick InP layer is formed on the base contact layer 30 by, e.g., MOCVD method (FIG. 8B).
  • an electrode material of, e.g., Pd/Zn/Pt/Au structure is deposited on the surface passivation layer 38 by, e.g., lift-off method and alloyed to form the base electrode 32 (FIG. 9A)).
  • an HBT including the base layer 16 of a carbon-doped p + -InGaAs layer, and the base contact layer 30 of a p ++ -GaAsSb layer of a low resistance is fabricated (FIG. 9B).
  • the surface passivation layer 38 is applied to the semiconductor device according to the first embodiment, but the surface passivation layer 38 can be also applied to the semiconductor device according to the second embodiment.
  • the present invention is applied to, e.g., the semiconductor devices of the structures including the collector layer 14 , the base layer 16 , emitter layer 18 formed on the InP substrate 10 in the stated order but is applicable similarly to the semiconductor device of the so-called collector-up structure including the emitter layer, the base layer and the collector layer deposited on the InP substrate in the stated order.
  • An emitter contact layer 42 of an n + -InGaAs layer (film thickness: 350 nm, electron concentration: 1 ⁇ 10 19 cm ⁇ 3 ) is formed on a semi-insulating InP substrate 40 .
  • An emitter contact layer 44 of an n + -InP layer (film thickness: 25 nm, electron concentration: 5 ⁇ 10 18 cm ⁇ 3 ) is formed on the emitter contact layer 42 .
  • An emitter layer 46 of an n-InP layer (film thickness: 50 nm, electron concentration: 3 ⁇ 10 17 cm ⁇ 3 ) is formed on the emitter contact layer 44 .
  • a base layer 48 of a p + -InGaAs layer (film thickness: 30 nm, hole concentration: 1 ⁇ 10 19 cm ⁇ 3 ) is formed on the emitter layer 46 .
  • a collector layer 50 of an i-InGaAs layer (film thickness: 300 nm) is formed on the base layer 48 .
  • a collector contact layer 52 of an n + -InGaAs layer (film thickness: 50 nm, electron concentration: 1 ⁇ 10 19 cm ⁇ 3 ) is formed on the collector layer 50 .
  • a collector electrode 54 of WSi film is formed on the collector contact layer 52 .
  • the collector contact layer 52 and the collector layer 50 are processed in a mesa-shape, and a sidewall insulation film 56 of SiN film is formed on the side wall of the collector mesa.
  • a base contact layer 50 of a p ++ -GaAsSb layer is formed on the exposed base layer 48 .
  • a base electrode 60 is formed on the base contact layer 58 .
  • the base contact layer 58 , the base layer 48 , the emitter layer 46 and the emitter contact layer 44 are processed in a mesa-shape, and an emitter electrode 62 is formed on the exposed emitter contact layer 42 .
  • An InP/InGaAs-based HBT of the collector-up structure is thus formed, whereby the semiconductor device of the collector-up structure can have a low base resistance R B .
  • the semiconductor device shown in FIG. 10 is one example of applications of the structure of the semiconductor device according to the first embodiment to a semiconductor device of the collector-up structure. Similarly the structures of the semiconductor device according to the second and the third embodiments are applicable to semiconductor devices of the collector-up structure.
  • the semiconductor device having the base layer 16 , 48 of a p + -InGaAs layer has been mainly explained, but the present invention can be widely applicable to the semiconductor device having the base layer of a Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer.
  • the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer it is preferable that the Ga composition (x) is a range of 0 ⁇ 1 and the As composition (y) is a range of 0 ⁇ y ⁇ 1.
  • the As composition (y) equals to 1
  • the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer corresponds to the InGaAs layer.
  • the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer corresponds to the GaAsSb layer.
  • the HBTs having a base layer of the Ga x In 1 ⁇ x As y Sb 1 ⁇ y layer can be formed by simply replacing the base layers 16 , 48 of the p + -InGaAs layers in the above-described embodiments with the p + -Ga x In 1 ⁇ x As y Sb 1 ⁇ y layers.
  • the problem of the hydrogen passivation in a case that the base layers 16 , 48 are formed of a p + -InGaAs layer has been mainly explained, but the base resistance R B reduction effect obtained by the presence of the base contact layers 30 , 58 is very high also in semiconductor devices including the base layers 16 , 48 formed of layers other than p + -InGaAs layer and p + -GaInAsSb layer which are sensitive to the hydrogen passivation effect. Accordingly, even in the case that the base layer is formed of GaAsSb layers, a further low base resistance R B can be obtained by providing the base contact layers 30 , 58 .
  • This structure is applicable not only to InP/GaInAsSb-based HBTs but also to GaAs-based HBTs.
  • the base contact layers 30 , 58 are not essentially formed of p ++ -GaAsSb layer. That is, the base contact layer may be formed of any semiconductor layer, e.g., a GaInAsSb layer as long as the material can be epitaxially grown on the base layer, the collector layer or the emitter layer and can provide a low base resistance R B .
  • the present invention is similarly applicable to a semiconductor device including the base layers 14 , 48 formed of In x Ga 1 ⁇ x As and having a gradient composition having a composition ratio x gradually changed.

Abstract

The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device of a hetero-junction bipolar transistor structure, and a method for fabricating the same. [0001]
  • Recently optical communications systems and mobile communication systems which have high efficiency are required. To make these systems highly efficient semiconductor devices are essential. Hetero-junction bipolar transistors (hereinafter called “HBTs”), which are known as high-speed devices, are one of such devices whose efficiency improvement is prospective. [0002]
  • A structure of a conventional HBT will be explained with reference to FIG. 11. [0003]
  • A [0004] collector contact layer 102 formed of an n+-InGaAs layer is formed on a semi-insulating InP substrate 100. A collector layer 104 of an i-InGaAs layer is formed on the collector contact layer 102. A base layer 106 of a p+-InGaAs layer is formed on the collector layer 104. An emitter layer 108 of an n-InP layer is formed on the base layer 106. An emitter contact layer 110 of an n+-InGaAs layer is formed on the emitter layer 108. An emitter electrode 112 of WSi film is formed on the emitter contact layer 110. The emitter contact layer 110 and the emitter layer 108 are processed in a mesa-shape, and a base electrode 116 is formed on an exposed part of the base layer 106. The base layer 106 and the collector layer 104 are processed in a mesa-shape, and a collector electrode 118 is formed on an exposed part of the collector contact layer 102. Thus, an InP/InGaAs-based HBT is formed.
  • To make the HBT-ICs more speedy, a higher maximum oscillation frequency f[0005] max is necessary. A maximum oscillation frequency fmax is expressed by
  • f max={square root}{square root over ( )}(f T/(8π×R B ×C BC))
  • wherein a maximum cut-off frequency is represented by f[0006] T, a base resistance is represented by RB, and a base-collector capacitance is represented by CBC. A maximum oscillation frequency fmax is proportional to a reciprocal of a square root of a base resistance RB ({square root}{square root over ( )}(1/(RB))), and for a higher maximum oscillation frequency fmax, it is necessary to obtain a lower base resistance RB.
  • In GaAs-based HBTs, recently carbon (C) is dominantly used as a dopant for the bases from the viewpoint of ensured reliability, etc., and doping techniques for higher concentrations of above 1×10[0007] 20 cm−3 have been developed.
  • On the other hands, in InP/InGaAs-based HBTs, actually doping techniques using carbon as a dopant for the base have not been sufficiently established. The base layer cannot be heavily doped with carbon, and this will be because carbon is not dissociated from hydrogen in forming InGaAs layer to be the base layer to be taken in the films in the form of CH, and the carbon does not function as an acceptor (hydrogen passivation). This phenomenon is conspicuous especially in MOCVD method using hydrogen as a carrier gas and a hydrogen content gas as a source gas. [0008]
  • As a result, InP/InGaAs-based HBTs have very high maximum cut-off frequencies f[0009] T but cannot have sufficiently maximum oscillation frequencies fmax.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a structure of a semiconductor device which enables an InP/InGaAs-based HBT to have a lower base resistance, and a method for fabricating the same. [0010]
  • The above-described object can be achieved by a semiconductor device comprising: a collector layer; a base layer of a carbon-doped Ga[0011] xIn1−xAsySb1−y layer having one surface connected to the collector layer; an emitter layer connected the other surface of the base layer; a base contact layer of a carbon-doped GaAsSb layer electrically connected to the base layer; and a base electrode formed on the base contact layer. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
  • In the above-described semiconductor device, it is preferable that the base contact layer is formed on said one surface or said the other surface of the base layer. [0012]
  • In the above-described semiconductor device, it is possible that the base contact layer is formed on a surface of the collector layer connected to the base layer and has a side surface connected to a side surface of the base layer. [0013]
  • In the above-described semiconductor device, it is possible that the base contact layer is formed on a surface of the emitter layer connected to the base layer and has a side surface connected to a side surface of the base layer. [0014]
  • In the above-described semiconductor device, it is possible that the device further comprises a surface passivation layer for protecting the base contact layer formed on the surface of the base contact layer with the base electrode formed on. Because of the surface passivation layer covering the surface of the base contact layer, surface recombination on the base contact layer can be restrained, whereby dependence of current gains on sizes can be restrained, and the semiconductor device can have higher reliability. [0015]
  • In the above-described semiconductor device, it is possible that the base contact layer is formed of a carbon-doped GaInAsSb layer in place of said carbon-doped GaAsSb layer. [0016]
  • In the above-described semiconductor device, it is possible that an As composition y of the Ga[0017] xIn1−xAsySb1−y is 1, so that the base layer is formed of a InGaAs layer.
  • In the above-described semiconductor device, it is preferable that an In composition x of the Ga[0018] xIn1−xAsySb1−y is 0, so that the base layer is formed of a GaAsSb layer.
  • In the above-described semiconductor device, it is preferable that a dopant concentration of the base contact layer is not less than 1×10[0019] 20 cm31 3.
  • The above-described object can be also achieved by a method for fabricating a semiconductor device comprising the steps of: forming a first semiconductor layer on a semiconductor substrate; forming a base layer of a carbon-doped Ga[0020] xIn1−xAsySb1−y layer on the first semiconductor layer; forming a second semiconductor layer on the base layer; patterning the second semiconductor layer in a mesa-shape; forming a base contact layer on the base layer exposed by patterning the second semiconductor layer; and forming a base electrode on the base contact layer. By fabricating the above-described semiconductor device fabricating method, the semiconductor device can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
  • In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, after the step of patterning the second semiconductor layer, a step of removing the base contact layer in a exposed region which is exposed by patterning the second semiconductor layer, wherein in the step of forming the base contact layer, the base contact layer having a side surface connected to the base layer is formed on the first semiconductor layer exposed by removing the base layer. [0021]
  • In the above-described method for fabricating a semiconductor device, it is preferable that in the step of forming the base layer, the base layer of an InGaAs layer which corresponds to the Ga[0022] xIn1−xAsySb1−y layer whose As composition y is 1, or a GaAsSb layer which corresponds to the GaxIn1−xAsySb1−y layer whose In composition X is 0 is formed.
  • In the above-described method for fabricating a semiconductor device, it is preferable that in the step of forming the base contact layer, the base contact layer is formed of a material which lattice-matches with a material forming the base layer. The base contact layer is formed of a material which lattice-matches with a material forming the base layer, whereby characteristic deterioration of the semiconductor device due to lattice deformation can be prevented. [0023]
  • In the above-described method for fabricating a semiconductor device, it is preferable that in the step of forming the base contact layer, the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer. The base contact layer is formed of such carbon-doped materials, whereby the base contact layer can effectively have a low resistance, and the semiconductor device can have higher reliability. [0024]
  • In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, before the step of forming the base contact layer, a step of thermal-treating for eliminating hydrogen in the base layer. Hydrogen in the base layer is eliminated, whereby carbon bonded with the hydrogen is electrically activated, whereby the base layer can have a further lower resistance. [0025]
  • In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, after the step of patterning the second semiconductor layer, a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer. [0026]
  • In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, after the step of forming the base contact layer, a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer. Because of the surface passivation layer covering the surface of the base contact layer, surface recombination on the base contact layer can be restrained, whereby dependence of current gains on sizes can be restrained, and the semiconductor device can have higher reliability. [0027]
  • In the above-described method for fabricating a semiconductor device, it is preferable that the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer. [0028]
  • The structure of the semiconductor device according to the present invention is applicable to not only a semiconductor device including a collector layer, a base layer and an emitter layer sequentially deposited on a semiconductor substrate, but also a semiconductor device of the so-called collector-up structure including an emitter layer, a base layer and a collector layer sequentially deposited on a semiconductor substrate.[0029]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagrammatic sectional view of the semiconductor device according to a first embodiment of the present invention. [0030]
  • FIGS. [0031] 2A-2C and 3A-3C are sectional views of the semiconductor device according to the first embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 4 is a diagrammatic sectional view of the semiconductor device according to a second embodiment of the present invention. [0032]
  • FIGS. [0033] 5A-5B and 6A-6B are sectional views of the semiconductor device according to the second embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 7 is a diagrammatic sectional view of the semiconductor device according to a third embodiment of the present invention. [0034]
  • FIGS. [0035] 8A-8B and 9A-9B are sectional views of the semiconductor device according to the third embodiment in the steps of the method for fabricating the same, which explain the method.
  • FIG. 10 is a diagrammatic sectional view of the semiconductor device according to one modification of the first embodiment of the present invention. [0036]
  • FIG. 11 is a diagrammatic sectional view of the conventional semiconductor device, which shows a structure thereof.[0037]
    • DETAILED DESCRIPTION OF THE INVENTION
  • [A First Embodiment][0038]
  • A semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIGS. [0039] 1, 2A-2C and 3A-3C.
  • FIG. 1 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof, and FIGS. [0040] 2A-2C and 3A-3C are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device according to the present embodiment.
  • First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 1. [0041]
  • A [0042] collector contact layer 12 of an n+-InGaAs layer is formed on a semi-insulating InP substrate 10. A collector layer 14 of an i-InGaAs layer is formed on the collector contact layer 12. A base layer 16 of a p+-InGaAs layer is formed on the collector layer 14. An emitter layer 18 of an n-InP layer is formed on the base layer 16. An emitter contact layer 20 of an n+-InP layer and an emitter contact layer 22 of an n+-InGaAs layer are formed on the emitter layer 18. An emitter electrode 26 of WSi (tungsten silicide) film is formed on the emitter contact layer 22. The emitter contact layers 20, 22 and the emitter layer 18 are processed in a mesa-shape, and a sidewall insulation film 28 of SiN film is formed on the side wall of the emitter mesa. A base contact layer 30 of a p++-GaAsSb layer is formed on the base layer 16, which is exposed. A base electrode 32 is formed on the base contact layer 30. The base contact layer 30, the base layer 16 and the collector layer 14 are processed in a mesa-shape. A collector electrode 36 is formed on the contact layer 12, which is exposed. Thus, an InP/InGaAs-based HBT is formed.
  • The semiconductor device according to the present embodiment is characterized in that the [0043] base contact layer 30 of a p++-GaAsSb layer is formed on the base layer 16.
  • A base resistance R[0044] B, which influences a maximum oscillation frequency fmax, is determined by a sheet resistance of the base layer and a contact resistance between the base layer and the base electrode.
  • In the conventional semiconductor device shown in FIG. 11, the [0045] base layer 106 is formed of the carbon-doped InGaAs, but in this case unless the base layer 106 has a resistance sufficiently reduced, resultantly a base resistance RB is much increased, which leads to a lower maximum oscillation frequency fmax.
  • However, in the semiconductor device according to the present embodiment shown in FIG. 1, because of the [0046] base contact layer 30 of a p++-GaAsSb layer formed on the base layer 16, even if the base layer 16 does not have a sufficiently low resistance, the base contact layer 30 can much reduce a resistance between an intrinsic base region (the region of the base layer 16 immediately below the emitter layer 18) and the base electrode 32. Accordingly, a much reduced base resistance RB can be obtained, and a higher maximum oscillation frequency fmax can be obtained.
  • Because of the [0047] base electrode 32 formed on the base contact layer 30 of a p++-GaAsSb layer of a low resistance, a contact resistance between the base electrode 32 and the base layer 16 can be lowered.
  • Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. [0048] 2A-2C and 3A-3C.
  • The [0049] collector contact layer 12 of an n+-InGaAs layer (film thickness: 350 nm; electron concentration: 1×1019 cm−3), the collector layer 14 of an i-InGaAs layer (film thickness: 300 nm), the base layer 16 of a p+-InGaAs layer (film thickness: 30 nm; hole concentration: 1×1019 cm−3), the emitter layer 18 of an n-InP layer (film thickness: 50 nm; electron concentration 3×1017 cm−3), the emitter contact layer 20 of an n+-InP layer (film thickness: 25 nm; electron concentration 5×1018 cm−3) and the emitter contact layer 22 of an n+-InGaAs layer (film thickness: 50 nm; electron concentration; 1×1019 cm−3) are sequentially deposited on a semi-insulating InP substrate 10 by, e.g., MOCVD method. Then, the WSi layer 24 is deposited on the emitter contact layer 22 by, e.g., sputtering method (FIG. 2A).
  • Then, the [0050] WSi film 24 is patterned by, e.g., dry etching to form the emitter electrode 26 of the WSi film 24.
  • Subsequently, the [0051] emitter contact layer 22 of the n+-InGaAs layer is selectively etched with the emitter electrode 26 as a mask and by the use of an etchant of, H3PO4:H2O2:H2O solution.
  • Then, also with the [0052] emitter electrode 26 as a mask, the emitter contact layer 20 and the emitter layer 18 are selectively etched by the use of an etchant of, e.g., HCl:H3PO4 solution.
  • Thus, an emitter mesa of the [0053] emitter layer 18, the emitter contact layer 20, the emitter contact layer 22 and the emitter electrode 26 is formed (FIG. 2B).
  • Next, SiN film is deposited on the entire surface by, e.g., CVD method and anisotropically etched to leave the SiN film on only the side wall of the emitter mesa. Thus, the [0054] sidewall insulation film 28 of the SiN film is formed on the side wall of the emitter mesa (FIG. 2C).
  • Subsequently, the substrate with the emitter mesa thus formed is annealed. This annealing is for eliminating hydrogen introduced into the [0055] base layer 16 during the film depositing step, and can prevent hydrogen passivation. The annealing at above about 300° C. can eliminate hydrogen in the film.
  • In the method for fabricating the semiconductor device according to the present embodiment, the InGaAs layer of the [0056] base layer 16 is annealed in its exposed state, whereby hydrogen can be removed more effectively than in a case that the emitter layer 18, etc. are formed on the base layer 16.
  • Next, the [0057] base contact layer 30 of an 125 nm-thick p++-GaAsSb layer heavily doped with carbon is selectively grown by, e.g., MOCVD method on the base layer 16 exposed around the emitter mesa.
  • GaAsSb can be doped heavily with an about 5×10[0058] 20 cm−3 concentration carbon, and the base contact layer 30 to be connected to the base layer 16 is formed of the heavily doped p++-GaAsSb layer, whereby the base region can have a much lower sheet resistance RB and contact resistance.
  • Preferably the [0059] base contact layer 30 is formed of one selected from materials which contain no In and lattice-match with the material of the base layer 16. It is empirically known that In-content groups are apt to have hydrogen passivation. Lattice mismatch introduces lattice deformation which leads to characteristic deterioration.
  • In a case that a material of the [0060] base contact layer 30 is GaAsSb, a composition of GaAs1−xSbx has an antimony composition ratio x of 0.1≦×≦0.9, whereby the base contact layer 30 can be lattice-matched with the base layer 16 of an InGaAs layer without lattice deformation. When the composition of GaAs1−xSbx has an antimony composition ratio x of about 0.5, the lattice constant of GaAsSb is substantially the same as the lattice constant of InGaAs.
  • To make the base resistance R[0061] B reduction sufficiently effective, it is preferable that the base contact layer 30 is doped with, e.g., a high concentration of about 1×1020 cm−3. Preferably a dopant concentration in the base contact layer 30 is suitably adjusted in accordance with a film thickness or others of the base contact layer 30.
  • Next, the [0062] base electrode 32 of, e.g., a Pt/Ti/Pt/Au structure is formed on the base contact layer 30 by, e.g., lift-off method (FIG. 3A).
  • Subsequently, a resist mask [0063] 34 formed covering the emitter mesa and extended over the base electrode 32 is formed, and then the base contact layer 30, the base layer 16 and the collector layer 14 are sequentially etched with the resist mask 34 and the base electrode 32 as a mask.
  • Thus, the base mesa of the [0064] collector layer 14, the base layer 16 and the base contact layer 30 is formed (FIG. 3B).
  • Then, the collector electrode [0065] 35 of, e.g., a Ti/Pt/Au structure is formed on the exposed collector contact layer 12 by, e.g., lift-off method (FIG. 3C).
  • Thus, an HBT including the [0066] base layer 16 of a carbon-doped p+-InGaAs layer and the base contact layer 30 of a p++-GaAsSb layer having a low resistance can be formed.
  • As described above, according to the present embodiment, the [0067] base contact layer 30 of a heavily carbon-doped p++-GaAsSb layer having a low resistance is formed on the base layer 16, whereby a much reduced base resistance RB can be obtained. Thus, an InP/InGaAs-base HBT can have an increased maximum oscillation frequency fmax.
  • [A Second Embodiment][0068]
  • The semiconductor device and a method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. [0069] 4, 5A-5B and 6A-6C. The same members of the second embodiment as those of the semiconductor device and the method for fabricating the same according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.
  • FIG. 4 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof. FIGS. [0070] 5A-5B and 6A-6B are sectional views of the semiconductor device in the steps of the method for fabricating the semiconductor device, which show the method.
  • In the present embodiment another semiconductor device having a decreased base resistance R[0071] B and the method for fabricating the same will be explained.
  • First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 4. [0072]
  • In the semiconductor device and the method for fabricating the same according to the first embodiment, the [0073] base contact layer 30 of the p++-GaAsSb layer is formed on the base layer 16 but may be connected to the base layer 16 at the sides thereof.
  • That is, as shown in FIG. 4, it is possible that the emitter mesa is formed of the emitter contact layers [0074] 22, 20, the emitter layer 18 and the base layer 16, and the base contact layer 30 formed on the collector layer 14 is connected to the base layer 16 at the side surface thereof. The semiconductor device having such structure can have a lower base resistance RB.
  • Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. [0075] 5A-5B and 6A-6B.
  • In the same way as in the method for fabricating the semiconductor device according to the first embodiment shown in FIGS. 2A to [0076] 2C, the emitter mesa of the emitter contact layers 22, 20 and the emitter layer 18, and the sidewall insulation film 28 on the side wall of the emitter mesa is formed (FIG. 5A).
  • Then, by the use of an etchant of, e.g., H[0077] 3PO4:H2O2:H2O solution, the base layer 16 of a p+-InGaAs layer is selectively etched (FIG. 5B).
  • Subsequently, the substrate with the emitter mesa thus formed is annealed. This annealing is for eliminating hydrogen introduced into the [0078] base layer 16 during the film depositing step, and can prevent hydrogen passivation.
  • Then, the [0079] base contact layer 30 of an about 155 nm-thick p++-GaAsSb layer heavily doped with carbon is selectively grown by, e.g., MOCVD method on the collector layer 14 exposed around the emitter mesa (FIG. 6A).
  • Next, in the same was as in the method for fabricating the semiconductor device according to the first embodiment shown in FIGS. 3A to [0080] 3C, an HBT including the base layer 16 of a carbon-doped p+-InGaAs layer, and the base contact layer 30 of p++-GaAsSb layer having a low resistance (FIG. 6B).
  • As described above, according to the present embodiment, the [0081] base contact layer 30 of a p++-GaAsSb layer is formed connected to the base layer 16 at the side thereof, whereby a very low base resistance RB can be obtained.
  • [A Third Embodiment][0082]
  • A semiconductor device and a method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS. [0083] 7, 8A-8B and 9A-9B.
  • FIG. 7 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof. FIGS. [0084] 8A-8B and 9A-9B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the same, which show the method.
  • First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 7. [0085]
  • The basic structure of the semiconductor device according to the present embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. 1 but is characterized in that a [0086] surface passivation layer 38 of InP layer is formed on the base contact layer 30.
  • The [0087] surface passivation layer 38 of InP layer is formed on the base contact layer 30 of the p++-GaAsSb layer, whereby surface recombination of the p++-GaAsSb layer forming the base contact layer 30 can be restrained, whereby size dependence of current gain can be restrained, and higher reliability can be obtained.
  • In a case that the [0088] surface passivation layer 38 is provided, the base electrode 32 is based on an alloy, e.g., Pd/Zn/Pt/Au or others.
  • Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. [0089] 8A-8B and 9A-9B.
  • In the same way as in the method for fabricating the semiconductor device according to, e.g., the first embodiment shown in FIGS. 2A to [0090] 2C, the emitter mesa of the emitter contact layers 22, 20 and the emitter layer 18 is formed, and the sidewall insulation film 28 is formed on the side wall of the emitter mesa (FIG. 8A).
  • Next, the substrate with the emitter mesa thus formed on is annealed. This annealing is for eliminating hydrogen which may be introduced into the [0091] base layer 16 during the film forming steps and can prevent hydrogen passivation.
  • Subsequently, the [0092] base contact layer 30 of an about 125 nm-thick p++-GaAsSb layer heavily doped with carbon is grown selectively on the base layer 16 exposed around the emitter mesa by, e.g., MOCVD method.
  • Then, the [0093] surface passivation layer 38 of an about 30 nm-thick InP layer is formed on the base contact layer 30 by, e.g., MOCVD method (FIG. 8B).
  • Next, an electrode material of, e.g., Pd/Zn/Pt/Au structure is deposited on the [0094] surface passivation layer 38 by, e.g., lift-off method and alloyed to form the base electrode 32 (FIG. 9A)).
  • Then, in the same way as in the method for fabricating the semiconductor device according to, e.g., the first embodiment shown in FIGS. 3B and 3C, an HBT including the [0095] base layer 16 of a carbon-doped p+-InGaAs layer, and the base contact layer 30 of a p++-GaAsSb layer of a low resistance is fabricated (FIG. 9B).
  • As described above, according to the present embodiment, because of the [0096] surface passivation layer 38 covering the surface of the base contact layer 30 of the p++-GaAsSb layer, surface recombination on the p++-GaAsSb layer forming the base contact layer 30 can be restrained. Thus, size dependence of current gains can be restrained, and higher reliability can be obtained.
  • In the present embodiment the [0097] surface passivation layer 38 is applied to the semiconductor device according to the first embodiment, but the surface passivation layer 38 can be also applied to the semiconductor device according to the second embodiment.
  • [Modifications][0098]
  • The present invention is not limited to the above-described embodiment and covers various modifications. [0099]
  • In the above-described embodiments, the present invention is applied to, e.g., the semiconductor devices of the structures including the [0100] collector layer 14, the base layer 16, emitter layer 18 formed on the InP substrate 10 in the stated order but is applicable similarly to the semiconductor device of the so-called collector-up structure including the emitter layer, the base layer and the collector layer deposited on the InP substrate in the stated order.
  • One example in which the structure of the semiconductor device according to the first embodiment is applied to the semiconductor device of collector-up structure will be explained with reference to FIG. 10. [0101]
  • An [0102] emitter contact layer 42 of an n+-InGaAs layer (film thickness: 350 nm, electron concentration: 1×1019 cm−3) is formed on a semi-insulating InP substrate 40. An emitter contact layer 44 of an n+-InP layer (film thickness: 25 nm, electron concentration: 5×1018 cm−3) is formed on the emitter contact layer 42. An emitter layer 46 of an n-InP layer (film thickness: 50 nm, electron concentration: 3×1017 cm−3) is formed on the emitter contact layer 44. A base layer 48 of a p+-InGaAs layer (film thickness: 30 nm, hole concentration: 1×1019 cm−3) is formed on the emitter layer 46. A collector layer 50 of an i-InGaAs layer (film thickness: 300 nm) is formed on the base layer 48. A collector contact layer 52 of an n+-InGaAs layer (film thickness: 50 nm, electron concentration: 1×1019 cm−3) is formed on the collector layer 50. A collector electrode 54 of WSi film is formed on the collector contact layer 52. The collector contact layer 52 and the collector layer 50 are processed in a mesa-shape, and a sidewall insulation film 56 of SiN film is formed on the side wall of the collector mesa. A base contact layer 50 of a p++-GaAsSb layer is formed on the exposed base layer 48. A base electrode 60 is formed on the base contact layer 58. The base contact layer 58, the base layer 48, the emitter layer 46 and the emitter contact layer 44 are processed in a mesa-shape, and an emitter electrode 62 is formed on the exposed emitter contact layer 42.
  • An InP/InGaAs-based HBT of the collector-up structure is thus formed, whereby the semiconductor device of the collector-up structure can have a low base resistance R[0103] B.
  • The semiconductor device shown in FIG. 10 is one example of applications of the structure of the semiconductor device according to the first embodiment to a semiconductor device of the collector-up structure. Similarly the structures of the semiconductor device according to the second and the third embodiments are applicable to semiconductor devices of the collector-up structure. [0104]
  • In the above-described embodiments, the semiconductor device having the [0105] base layer 16, 48 of a p+-InGaAs layer has been mainly explained, but the present invention can be widely applicable to the semiconductor device having the base layer of a GaxIn1−xAsySb1−y layer. In the GaxIn1−xAsySb1−y layer, it is preferable that the Ga composition (x) is a range of 0<×≦1 and the As composition (y) is a range of 0<y≦1. When the As composition (y) equals to 1, the GaxIn1−xAsySb1−y layer corresponds to the InGaAs layer. When the Ga composition (x) equals to 1, the GaxIn1−xAsySb1−y layer corresponds to the GaAsSb layer. The HBTs having a base layer of the GaxIn1−xAsySb1−y layer can be formed by simply replacing the base layers 16, 48 of the p+-InGaAs layers in the above-described embodiments with the p+-GaxIn1−xAsySb1−y layers.
  • In the above-described embodiments, the problem of the hydrogen passivation in a case that the base layers [0106] 16, 48 are formed of a p+-InGaAs layer has been mainly explained, but the base resistance RB reduction effect obtained by the presence of the base contact layers 30, 58 is very high also in semiconductor devices including the base layers 16, 48 formed of layers other than p+-InGaAs layer and p+-GaInAsSb layer which are sensitive to the hydrogen passivation effect. Accordingly, even in the case that the base layer is formed of GaAsSb layers, a further low base resistance RB can be obtained by providing the base contact layers 30, 58. This structure is applicable not only to InP/GaInAsSb-based HBTs but also to GaAs-based HBTs.
  • The base contact layers [0107] 30, 58 are not essentially formed of p++-GaAsSb layer. That is, the base contact layer may be formed of any semiconductor layer, e.g., a GaInAsSb layer as long as the material can be epitaxially grown on the base layer, the collector layer or the emitter layer and can provide a low base resistance RB.
  • In the present modification an example of the application of the structure of the semiconductor device according to the first embodiment to a bipolar transistor of the single hetero structure including the base layer and the collector layer formed of InGaAs layer, but the structure is similarly applicable to a bipolar transistor of the double hetero structure including the collector layer formed of InP layer or InGaAsP layer. [0108]
  • The present invention is similarly applicable to a semiconductor device including the base layers [0109] 14, 48 formed of InxGa1−xAs and having a gradient composition having a composition ratio x gradually changed.

Claims (26)

What is claimed is
1. A semiconductor device comprising:
a collector layer;
a base layer of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer;
an emitter layer connected the other surface of the base layer;
a base contact layer of a carbon-doped GaAsSb layer electrically connected to the base layer; and
a base electrode formed on the base contact layer.
2. A semiconductor device according to claim 1, wherein
the base contact layer is formed on said one surface or said the other surface of the base layer.
3. A semiconductor device according to claim 1, wherein
the base contact layer is formed on a surface of the collector layer connected to the base layer and has a side surface connected to a side surface of the base layer.
4. A semiconductor device according to claim 1, wherein
the base contact layer is formed on a surface of the emitter layer connected to the base layer and has a side surface connected to a side surface of the base layer.
5. A semiconductor device according to claim 1, further comprising
a surface passivation layer for protecting the base contact layer formed on the surface of the base contact layer with the base electrode formed on.
6. A semiconductor device according to claim 1, wherein
the base contact layer is formed of a carbon-doped GaInAsSb layer in place of said carbon-doped GaAsSb layer.
7. A semiconductor device according to claim 1, wherein
an As composition y of the GaxIn1−xAsySb1−y is 1, so that the base layer is formed of a InGaAs layer.
8. A semiconductor device according to claim 6, wherein
an As composition y of the GaxIn1−xAsySb1−y is 1, so that the base layer is formed of a InGaAs layer.
9. A semiconductor device according to claim 1, wherein
an In composition x of the GaxIn1−xAsySb1−y is 0, so that the base layer is formed of a GaAsSb layer.
10. A semiconductor device according to claim 6, wherein
an In composition x of the GaxIn1−xAsySb1−y is 0, so that the base layer is formed of a GaAsSb layer.
11. A semiconductor device according to claim 1, wherein
a dopant concentration of the base contact layer is not less than 1×1020 cm−3.
12. A semiconductor device according to claim 6, wherein
a dopant concentration of the base contact layer is not less than 1×1020 cm−3.
13. A method for fabricating a semiconductor device comprising the steps of:
forming a first semiconductor layer on a semiconductor substrate;
forming a base layer of a carbon-doped GaxIn1−xAsySb1−y layer on the first semiconductor layer;
forming a second semiconductor layer on the base layer;
patterning the second semiconductor layer in a mesa-shape;
forming a base contact layer on the base layer exposed by patterning the second semiconductor layer; and
forming a base electrode on the base contact layer.
14. A method for fabricating a semiconductor device according to claim 13, further comprising, after the step of patterning the second semiconductor layer, a step of removing the base contact layer in a exposed region which is exposed by patterning the second semiconductor layer, wherein
in the step of forming the base contact layer, the base contact layer having a side surface connected to the base layer is formed on the first semiconductor layer exposed by removing the base layer.
15. A method for fabricating a semiconductor device according to claim 13, wherein
in the step of forming the base layer, the base layer of an InGaAs layer which corresponds to the GaxIn1−xAsySb1−y layer whose As composition y is 1, or a GaAsSb layer which corresponds to the GaxIn1−xAsySb1−y layer whose In composition X is 0 is formed.
16. A method for fabricating a semiconductor device according to claim 14, wherein
in the step of forming the base layer, the base layer of an InGaAs layer which corresponds to the GaxIn1−xAsySb1−y layer whose As composition y is 1, or a GaAsSb layer which corresponds to the GaxIn1−xAsySb1−y layer whose In composition X is 0 is formed.
17. A method for fabricating a semiconductor device according to claim 13, wherein
in the step of forming the base contact layer, the base contact layer is formed of a material which lattice-matches with a material forming the base layer.
18. A method for fabricating a semiconductor device according to claim 13, wherein
in the step of forming the base contact layer, the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer.
19. A method for fabricating a semiconductor device according to claim 14, wherein
in the step of forming the base contact layer, the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer.
20. A method for fabricating a semiconductor device according to claim 13, further comprising, before the step of forming the base contact layer, a step of thermal-treating for eliminating hydrogen in the base layer.
21. A method for fabricating a semiconductor device according to claim 13, further comprising, after the step of patterning the second semiconductor layer,
a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer.
22. A method for fabricating a semiconductor device according to claim 14, further comprising, after the step of patterning the second semiconductor layer,
a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer.
23. A method for fabricating a semiconductor device according to claim 13, further comprising, after the step of forming the base contact layer,
a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer.
24. A method for fabricating a semiconductor device according to claim 14, further comprising, after the step of forming the base contact layer,
a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer.
25. A method for fabricating a semiconductor device according to claim 13, wherein
the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer.
26. A method for fabricating a semiconductor device according to claim 14, wherein
the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer.
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