US20020067648A1 - Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same - Google Patents
Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same Download PDFInfo
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- US20020067648A1 US20020067648A1 US09/822,487 US82248701A US2002067648A1 US 20020067648 A1 US20020067648 A1 US 20020067648A1 US 82248701 A US82248701 A US 82248701A US 2002067648 A1 US2002067648 A1 US 2002067648A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Definitions
- the invention relates to a semiconductor memory device, and more particularly, to an asynchronous static random access memory (SRAM) using a dynamic random access memory (DRAM) cell, and a method for driving the same.
- SRAM static random access memory
- DRAM dynamic random access memory
- a random access memory (RAM) of a semiconductor memory device is classified as either an SRAM or a DRAM.
- a unit memory cell for storing one-bit of information used in a conventional SRAM is implemented by four (4) transistors cross-coupled as a latch and two (2) transistors serving as a transfer gate.
- an SRAM unit memory cell is implemented by six (6) transistors, it occupies a larger die area than a DRAM unit memory cell implemented by one transistor and one capacitor. Therefore, the die area of an SRAM required for implementing a memory device with the same memory capacity is approximately 6 to 10 times that of a DRAM. So, the manufacturing cost is increased.
- a conventional DRAM may be used instead of an SRAM.
- a DRAM controller is additionally required for periodic refresh operations.
- the overall performance of the system itself may be deteriorated due to the periodic refresh operation and low-speed operation of the DRAM.
- Another object of the invention is to provide a method for driving the asynchronous SRAM compatible memory device.
- an SRAM compatible memory device in which a leading address is primarily input and then a lagging address is secondarily input after a predetermined SRAM access time, the SRAM access time being elapsed for accessing valid data from the outside.
- the SRAM compatible memory device includes a DRAM memory array and a DRAM operation controller.
- the DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period.
- the DRAM operation controller controls the DRAM memory array to perform an access operation after a predetermined DRAM access time (period) has elapsed from a time at which the leading address is primarily input.
- the SRAM access time (period) is equal to or longer than twice the DRAM access time.
- a SRAM compatible memory device including an array of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. A leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time (period) has elapsed for accessing valid data from the outside.
- the SRAM access time is equal to or longer than the sum of a refresh time for refreshing the DRAM memory cells and a DRAM access time for effectively accessing the DRAM memory cells.
- an SRAM compatible memory device In the SRAM compatible memory device, a leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time has elapsed for accessing valid data from the outside.
- the SRAM compatible memory device comprises a DRAM memory array and a DRAM operation controller.
- the DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period.
- the DRAM operation controller controls the DRAM memory array to start an actual access operation during a predetermined DRAM access time (period), in response to the input of a leading address.
- the DRAM operation controller controls the DRAM memory array to input the lagging address after another DRAM access time from a time at which the actual operation is completed.
- the SRAM access time is equal to or longer than twice the DRAM access time.
- the SRAM compatible memory device has a DRAM memory array including a plurality of DRAM memory cells arranged in a row and column type matrix. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period.
- the method includes the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) allowing a predetermined DRAM access time to elapse after generation of the address transition detection signal, (d) after the step (c), performing an access operation to access the DRAM memory array for the duration of the DRAM access time, and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from time of inputting the leading address.
- the SRAM access time is equal to or longer than twice the DRAM access time.
- the SRAM compatible memory device includes an array of DRAM memory cells arranged in rows and columns, each DRAM memory cell requiring a refresh operation for retention of data stored within a predetermined refresh period.
- the method comprises the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) performing an access operation to access the DRAM memory array for the duration of a predetermined DRAM access time in response to the address transition detection signal, (d) allowing another DRAM access time to elapse after the step (c), and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from the leading address input time.
- the SRAM access time is equal to or longer than twice the DRAM access time.
- the DRAM memory cell is operated twice within each access time, to be fully compatible with an asynchronous SRAM. Also, the SRAM compatible memory according to the invention can be easily implemented. Further, since the SRAM compatible memory according to the invention uses DRAM cells, it can function as a low power asynchronous SRAM.
- FIG. 1 is a block diagram of an SRAM compatible memory device according to an embodiment of the invention.
- FIG. 2 is a timing diagram illustrating an example of when a read operation is performed from an idle (IDLE) state
- FIGS. 3 through 5 are timing diagrams illustrating examples of when write operations are performed from an idle (IDLE) state
- FIGS. 6 and 7 are timing diagrams illustrating examples of when read and write operations are performed from a reserved (RESERVED) state
- FIG. 8 is a timing diagram for a case in which a read command is further generated from a read (READ) state;
- FIG. 9 is a timing diagram for a case in which a read command is generated from a refresh (REFRESH) state;
- FIG. 10 is a timing diagram illustrating an example of generating a refresh command from an idle (IDLE) state
- FIG. 11 is a timing diagram illustrating an example of when a refresh command is generated from a reserved (RESERVED) state or a read (READ) state;
- FIG. 12 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to an embodiment of the invention.
- FIG. 13 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to another embodiment of the invention.
- FIG. 14A and FIG. 14B are timing diagrams for explaining a reserved period.
- FIG. 1 is a block diagram of an SRAM compatible memory device according to an embodiment of the invention.
- the SRAM compatible memory device according to the invention is implemented using a DRAM memory cell.
- a plurality of DRAM memory cells is arranged in a DRAM memory array shown in FIG. 1.
- the DRAM memory cell is implemented by including one transistor and one capacitor as a unit cell. Thus, in order to retain data stored therein, a refresh operation is performed within a predetermined refresh period.
- An externally input address ADDR is decoded by a row decoder 103 and a column decoder 105 . Also, a specific memory cell arranged at a row and column of the DRAM memory cell array 101 , is designated with the decoded address. Externally input data is stored in the designated memory cell in a write (WRITE) mode. Also, in a read (READ) mode, the data stored in the designated memory cell is output to the outside through an output buffer 109 .
- WRITE write
- READ read
- the DRAM memory array 101 , the row decoder 103 , the column decoder 105 , a write buffer 107 and the output buffer 109 are referred to as an internal DRAM 100 .
- an address latch 111 In order to effectively perform the read/write operations of the internal DRAM 100 , an address latch 111 , an address transition detection (ATD) circuit 113 , a data latch 115 and a data transition detection (DTD) circuit 117 are incorporated in the SRAM compatible memory device.
- the address latch 111 latches the ADDR and supplies the same to the row decoder 103 and the column decoder 105 .
- the ATD circuit 113 detects the change in the logic level of the ADDR to generate an address transition detection (ATD) signal.
- the ATD signal becomes activated with a predetermined pulse width when the ADDR makes a transition in a state in which a chip selection signal CS is logic “high”.
- the data latch 115 latches input data DATA and supplies the same to the write buffer 107 .
- the DTD circuit 117 generates a data transition detection (DTD) signal.
- the DTD signal becomes activated with a predetermined pulse width when the DATA is input and a write enable (WEB) signal goes “low”.
- a refresh timer 119 for refreshing DRAM memory cells arranged in the memory array 101 is incorporated in the SRAM compatible memory device according to an embodiment of the invention.
- a refresh request (REFREQ) signal supplied from the refresh timer 119 is activated for a constant refresh period.
- the SRAM compatible memory device according to the invention internally employs DRAM memory cells, an externally controlled refresh operation is not required, which makes the SRAM compatible memory device similar to the conventional SRAM. Also, signals for controlling the refresh operation are not input. In other words, the SRAM compatible memory device of the invention operates externally in the same manner that the conventional SRAM does.
- a DRAM operation controller 121 is incorporated in the SRAM compatible memory device according to an embodiment of the invention.
- the DRAM operation controller 121 includes a DRAM state switching portion 121 a , a DRAM operation controlling portion 121 b , a DRAM state identifying portion 121 c and a reserved state controlling portion 121 d .
- the DRAM state identifying portion 121 c identifies the current operating state of the internal DRAM 100 by the information contained in the ATD signal and the WEB signal.
- the reserved state controlling portion 121 d determines the width of a reserved (RESERVED) state period of the internal DRAM 100 , in accordance with the operating state of the internal DRAM 100 and the length of the time elapsed from the ATD signal being activated.
- the DRAM operation controlling portion 121 b controls the internal DRAM 100 to perform an access operation such as a read operation, a write operation or a refresh operation, after the RESERVED state period of the internal DRAM 100 determined by the reserved state controlling portion 121 d has lapsed.
- the DRAM state switching portion 121 a switches the operating state of the internal DRAM 100 , in response to the DTD, ATD or WEB signal.
- the fifth operating states of the internal DRAM 100 in the SRAM compatible memory device are designated as a READ state, a WRITE state, a REFRESH state, a RESERVED state and an IDLE state.
- the DRAM is in the READ state, the operation of reading out data is performed.
- the WRITE state the operation of writing externally input data in the DRAM memory array 101 is performed.
- the REFRESH state the operation of amplifying the data stored in the DRAM memory array 101 and rewriting the same is performed.
- the RESERVED state the refresh operation can be allocated to the internal DRAM 100 .
- the fifth state of the DRAM 100 , the IDLE state is a state other than the READ state, the WRITE state, the REFRESH state and the RESERVED state, that is, a state in which no operation is performed.
- FIG. 2 is a timing diagram illustrating an example of initiating a read operation from an idle (IDLE) state. If an address ADDR primarily is input at a time t 1 , an ATD signal is generated as a pulse.
- the internal DRAM 100 is switched from an IDLE state (A 1 ) to a RESERVED state (A 2 ). Successively, if a predetermined DRAM access time (period) D_tRC has elapsed, the internal DRAM 100 is switched from the RESERVED state (A 2 ) to a READ state (A 3 ), and reads out data for the duration of the access time D_tRC, to be output.
- a predetermined DRAM access time (period) D_tRC has elapsed
- an SRAM access time S_tRC of a period from the leading ADDR input time t 1 to the lagging ADDR input time t 2 , is longer than twice the DRAM access time D_tRC, the SRAM compatible memory device according to the invention performs a read operation in the same manner as the conventional SRAM does.
- activation of a CS signal to a logic “high” indicates that the internal DRAM 100 has entered a state in which it is capable of performing read/write access and refresh operations.
- the “high” state of the WEB signal indicates a READ state, and the “low” state thereof indicates a WRITE state.
- an explanation of the CS and WEB signals is omitted.
- FIG. 3 is a timing diagram illustrating an example of initiating a write operation from an idle (IDLE) state.
- the internal DRAM 100 is switched from an IDLE state (B 1 ) to a RESERVED state (B 2 ).
- the internal DRAM 100 is further switched to a WRITE state (B 3 ) to perform a data write operation.
- a DTD signal is activated with a predetermined pulse width responsive to activation of a WEB signal and input of data.
- the internal DRAM 100 identifies a WRITE state by the first pulse of the DTD signal responsive to activation of the WEB signal.
- the internal DRAM 100 writes valid data by the second pulse of the DTD signal responsive to input of data.
- the SRAM compatible memory device according to the invention performs a write operation in the same manner as does the conventional SRAM.
- FIG. 4 is a timing diagram illustrating another example of initiating a write operation from an idle (IDLE) state.
- a WEB signal is activated within a DRAM access time D_tRC following a leading ADDR input time t 1 .
- data is input after a period twice the DRAM access time D_tRC.
- the internal DRAM 100 is switched to a RESERVED state (C 2 ) in response to an ATD signal.
- the internal DRAM 100 is further switched to a first WRITE state (C 3 ) to perform a data write operation.
- a first WRITE state (C 3 ) data is not input.
- an invalid WRITE operation is performed, that is, invalid data is input.
- the internal DRAM 100 is switched to a WRITE state (C 4 ) in which valid data is written.
- a SRAM access time S_tRC that is, a time period from the leading ADDR input time t 1 to a lagging ADDR input time t 2 , is longer than twice the DRAM access time D_tRC, that is, longer than the minimum SRAM access time S_tRCmin. If such conditions of ADDR input, WEB signal input and data input as shown in FIG. 4 are allowed in the conventional SRAM, the SRAM compatible memory device according to the invention will satisfactorily perform an access operation such as a write operation, in the same manner as does the conventional SRAM.
- FIG. 5 is a timing diagram illustrating still another example of initiating a write operation from an idle (IDLE) state.
- a WEB signal is activated during a DRAM access time D_tRC following a leading address ADDR input time t 1 .
- data is input during a period twice the length of the DRAM access time D_tRC following the leading address ADDR input time.
- the internal DRAM 100 is switched to a RESERVED state (D 2 ) in response to an ATD signal. After the lapse of the DRAM access time D_tRC, the internal DRAM 100 is switched to a READ state (D 3 ).
- the reason for the switch to the READ state (D 3 ) is that the WEB signal is not yet activated to a logic “low”. However, the READ state (D 3 ) is subsequently changed to an invalid READ state in which invalid data is read out.
- the internal DRAM 100 is switched to a first WRITE state (D 4 ) to perform a write operation. However, since no data is input in the first WRITE state (D 4 ), an invalid WRITE operation is performed. Thereafter, at a time t 3 , responsive to the input of data, the internal DRAM 100 is switched to a second WRITE state (D 5 ) in which valid data is written.
- an SRAM access time S_tRC is longer than the minimum SRAM access time S_tRCmin.
- the SRAM compatible memory device according to the invention will satisfactorily perform an access operation such as a write operation, as does the conventional SRAM.
- FIG. 6 is a timing diagram illustrating an example of performing a read operation from a reserved (RESERVED) state, in which a lagging address ADDR is input at a time t 2 prior to a DRAM access time D_tRC following a time t 1 at which a leading ADDR is input.
- RESERVED reserved address
- the internal DRAM 100 is switched from an IDLE state (E 1 ) to a RESERVED state (E 2 ) in response to generation of an ATD signal.
- the lagging ADDR is secondarily input at the time t 2 .
- a time interval (T 1 ) from the time t 1 and the time t 2 is shorter than the DRAM access time D_tRC.
- the ATD signal is again generated and the internal DRAM 100 is further switched to a RESERVED state (E 3 ).
- the internal DRAM 100 operates such that if a predetermined access time D_tRC has elapsed, the internal DRAM 100 is switched from the RESERVED state (E 3 ) to a READ state (E 4 ). And the data is read out for the duration of the access time D_tRC, to then be output.
- FIG. 7 is a timing diagram illustrating an example of performing a write operation from a reserved (RESERVED) state.
- a lagging address ADDR is input at a time t 2 prior to a DRAM access time D_tRC following a time t 1 at which a leading ADDR is input.
- the internal DRAM 100 is switched to a WRITE state (F 4 ) after two RESERVED states (F 2 and F 3 ).
- FIG. 8 is a timing diagram illustrating the case in which a read command is further generated from a read (READ) state, in which a lagging address ADDR is input at a time t 2 that comes after a DRAM access time D_tRC from a leading ADDR input time t 1 , and comes prior to a time which is twice the time D_tRC.
- READ read
- an ATD signal is generated as a pulse. Then, the internal DRAM 100 is switched from an IDLE state (G 1 ) to a RESERVED state (G 2 ) in response to generation of the ATD signal. Continuously, if a predetermined DRAM access time D_tRC has elapsed, the internal DRAM 100 is switched from the RESERVED state (G 2 ) to a READ state (G 3 ) to remain in the READ state (G 3 ) for the duration of the access time D_tRC. However, as shown in FIG.
- the lagging ADDR is input at the time t 2 while the DRAM is in the READ state (G 3 ). Then, the ATD signal is generated as a pulse. If the READ state (G 3 ) is terminated, the internal DRAM 100 is further switched to a RESERVED state (G 4 ). Then, if the access time D_tRC has elapsed after the ATD signal is generated, the internal DRAM 100 is switched to a READ state (G 5 ) to perform a read operation.
- FIG. 9 is a timing diagram illustrating the case in which a read command is generated from a refresh (REFRESH) state of the DRAM.
- REFRESH refresh
- the REFRESH state (H 1 ) is initiated at a time t 1 and an address ADDR is input at a time t 2 prior to completion of a REFRESH state (H 2 ).
- a DRAM access time D_tRC elapses, the internal DRAM 100 is switched to the RESERVED state (H 2 ).
- the internal DRAM 100 is switched from the RESERVED state (H 2 ) to a READ state (H 3 ). Continuously, the READ state (H 3 ) is held for the duration of the access time D_tRC.
- FIG. 10 is a timing diagram illustrating an example of generating a refresh command from an idle (IDLE) state, in which the refresh request (REFREQ) signal generated from the refresh timer ( 119 of FIG. 1) is activated during an IDLE state ( 11 ). Then, the internal DRAM 100 is switched to a REFRESH state ( 12 ) in response to the REFREQ signal. The activation of the REFREQ signal may occur irrespective of the logical state of a CS signal. After the REFRESH state ( 12 ) is held for the duration of the access time D_tRC, the internal DRAM 100 is switched again to an IDLE state ( 13 ).
- IDLE idle
- REFREQ refresh request
- FIG. 11 is a timing diagram illustrating an example of generating a refresh command from a reserved (RESERVED) or read (READ) state.
- RESERVED reserved
- READ read
- a REFRESH state (J 3 ) is then started. Also, even if the REFREQ signal is activated to a logic “high” in the READ state (J 2 ), the REFRESH state (J 3 ) is started after the READ state (J 2 ), held for the duration of access time D_tRC, is terminated.
- FIG. 12 shows conceptually a state transition scheme of the internal DRAM, which is shown in detail in FIG. 2 to FIG. 11. Referring to FIG. 1 and FIG. 12, the state transition scheme of the internal DRAM will be summarized.
- the internal DRAM 100 is switched to a reserved state S 1203 , at transition T 1201 . If the WEB signal is in non-activation when the reserved state S 1203 is terminated, the internal DRAM 100 is switched to a read state S 1205 , at transition T 1202 . If the WEB signal is in activation when the reserved state S 1203 is terminated, the internal DRAM 100 is switched to a write state S 1207 , at transition T 1203 .
- the reserved period is a predetermined time interval of the reserved state from the activation of the ATD signal, which is illustrated in FIG. 14A and FIG. 14B.
- the internal DRAM 100 When the activation of the WEB signal is generated from the read state S 1205 , the internal DRAM 100 is switched to the write state S 1207 , at transition T 1206 . If the activation of the REFREQ signal is generated from the idle state S 1201 , the internal DRAM 100 is switched to a first refresh state S 1209 , at transition T 1207 . However, if the activation of the REFREQ signal is generated from the read state S 1205 or the write state S 1207 , the internal DRAM 100 is switched to a second refresh state S 1211 after the completion of the read state S 1205 or the write state S 1207 , at transition T 1208 or T 1209 .
- the refresh state is shown as the first and the second refresh state S 1209 and S 1211 , because the transition conditions from the first and the second refresh state S 1209 and S 1211 to the other state are different.
- the internal DRAM 100 is switched to the idle state S 1201 , at transition T 2110 .
- the internal DRAM 100 is switched to the reserved state S 1203 , at transition T 1213 or T 1214 .
- the internal DRAM 100 is switched to the write state S 1207 , at transition T 1215 .
- the internal DRAM 100 is maintained with the reserved state S 1203 , at transition T 1218 . If the activation of the DTD signal is generated from the write state S 1207 , the internal DRAM 100 is maintained in the write state S 1207 , at transition T 1218 .
- FIG. 13 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to another embodiment of the invention. Referring to FIG. 13, a read state or a write state is generated in advance of a refresh state. The state transition scheme of the internal DRAM in an SRAM compatible memory device according to this other embodiment of the invention will be described below.
- the internal DRAM 100 is switched to a read state S 1305 , at transition T 1301 . If the WEB signal is in activation when the activation of the ATD signal or the DTD signal is generated from an idle state S 1301 , the internal DRAM 100 is switched to a write state S 1307 , at transition T 1302 . When the activation of the REFREQ signal is generated from an idle state S 1301 , the internal DRAM 100 is switched to a refresh state S 1303 , at transition T 1303 .
- the internal DRAM 100 is switched to a read state S 1305 or a write state S 1307 depending on the activation of the WEB signal, at transition T 1304 or T 1305 .
- the successive flag SF is set as 1 when the activation of the signal ATD is generated during a READ, WRITE or REFRESH operation.
- the successive flag SF is set as 0 when a read operation, a write operation or a refresh operation starts.
- the internal DRAM 100 is switched to the idle state S 1301 , at transition T 1306 . If the REFREQ signal is in activation when the read state S 1305 or the write state S 1307 is terminated, the internal DRAM 100 is switched to the refresh state S 1301 , at transition T 1307 or T 1308 . If the successive flag SF is 1 and the WEB signal is in activation when the read state S 1305 is terminated, the internal DRAM 100 is switched to the write state S 1307 , at transition T 1309 . If the successive flag SF is 1 and the WEB signal is in non-activation when the read state S 1305 is terminated, the internal DRAM 100 is maintained in the write state S 1307 , at transition T 1310 .
- the internal DRAM 100 is switched to the read state S 1305 , at transition T 1311 . If the successive flag SF is I and the WEB signal is in activation when the write state S 1307 is terminated, the internal DRAM 100 is maintained in the read state S 1305 , at transition T 1312 . If the successive flag SF is 0 when the read state S 1305 or the write state S 1307 is terminated, the internal DRAM 100 is switched to the idle state S 1301 , at transition T 1313 or T 1314 .
- a reserved state capable of a refresh operation is generated in advance of a read state or a write state.
- a read state or a write state is generated in advance of a refresh.
- a DRAM memory cell is operated twice within an access time of an SRAM.
- the internal DRAM 100 is configured to have an access time of 35 ns or less and the internal DRAM 100 is operated twice, for a period of 70 ns.
- no operation is performed, or a refresh operation is performed.
- read/write operations are performed.
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Abstract
Description
- 1. Field of the Invention
- The invention relates to a semiconductor memory device, and more particularly, to an asynchronous static random access memory (SRAM) using a dynamic random access memory (DRAM) cell, and a method for driving the same.
- 2. Description of the Related Art
- In general, a random access memory (RAM) of a semiconductor memory device is classified as either an SRAM or a DRAM. A unit memory cell for storing one-bit of information used in a conventional SRAM is implemented by four (4) transistors cross-coupled as a latch and two (2) transistors serving as a transfer gate.
- In a general SRAM, since stored data is latched, a refresh operation for data retention is not required. Also, SRAMs typically are able to operate faster and consume less power than DRAMs.
- However, since an SRAM unit memory cell is implemented by six (6) transistors, it occupies a larger die area than a DRAM unit memory cell implemented by one transistor and one capacitor. Therefore, the die area of an SRAM required for implementing a memory device with the same memory capacity is approximately 6 to 10 times that of a DRAM. So, the manufacturing cost is increased.
- In order to reduce the cost, a conventional DRAM may be used instead of an SRAM. In this case, however, a DRAM controller is additionally required for periodic refresh operations. Also, the overall performance of the system itself may be deteriorated due to the periodic refresh operation and low-speed operation of the DRAM.
- To overcome the disadvantages of the DRAM and SRAM, various implementations of the SRAM using DRAM cells continuously are being devised. One such implementation is disclosed in U.S. Pat. No. 5,999,474 to Wingyu Leung et al., in which a memory device consists of a multi-bank DRAM and an SRAM cache, so that the refresh of the memory can be hidden from the outside to be compatible with an SRAM.
- However, according to the technology of the above-noted U.S. patent, an SRAM having the same storage capacity and configuration as a single DRAM bank, needs to be provided inside a memory device, and the circuit implementation is relatively complicated. Also, the memory device according to the above-noted U.S. patent is compatible with a synchronous SRAM in which external clocks are necessary. Thus, the technology based on the above-noted U.S. patent cannot be applied to a low power asynchronous SRAM for mobile equipment or the like.
- To solve the above problems, it is an object of the invention to provide an asynchronous SRAM compatible memory device using a DRAM cell, which is easily implemented and can be used as a low power asynchronous SRAM.
- Another object of the invention is to provide a method for driving the asynchronous SRAM compatible memory device.
- Accordingly, to achieve the above object, there is provided an SRAM compatible memory device in which a leading address is primarily input and then a lagging address is secondarily input after a predetermined SRAM access time, the SRAM access time being elapsed for accessing valid data from the outside. The SRAM compatible memory device includes a DRAM memory array and a DRAM operation controller. The DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The DRAM operation controller controls the DRAM memory array to perform an access operation after a predetermined DRAM access time (period) has elapsed from a time at which the leading address is primarily input. The SRAM access time (period) is equal to or longer than twice the DRAM access time.
- According to another aspect of the invention, there is provided a SRAM compatible memory device including an array of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. A leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time (period) has elapsed for accessing valid data from the outside. The SRAM access time is equal to or longer than the sum of a refresh time for refreshing the DRAM memory cells and a DRAM access time for effectively accessing the DRAM memory cells.
- According to still another aspect of the invention, there is provided an SRAM compatible memory device. In the SRAM compatible memory device, a leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time has elapsed for accessing valid data from the outside. The SRAM compatible memory device comprises a DRAM memory array and a DRAM operation controller. The DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The DRAM operation controller controls the DRAM memory array to start an actual access operation during a predetermined DRAM access time (period), in response to the input of a leading address. The DRAM operation controller controls the DRAM memory array to input the lagging address after another DRAM access time from a time at which the actual operation is completed. The SRAM access time is equal to or longer than twice the DRAM access time.
- To achieve another object of the invention, there is provided a method for driving an SRAM compatible memory device. The SRAM compatible memory device has a DRAM memory array including a plurality of DRAM memory cells arranged in a row and column type matrix. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The method includes the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) allowing a predetermined DRAM access time to elapse after generation of the address transition detection signal, (d) after the step (c), performing an access operation to access the DRAM memory array for the duration of the DRAM access time, and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from time of inputting the leading address. The SRAM access time is equal to or longer than twice the DRAM access time.
- According to another aspect of the invention, there is provided a method for driving an SRAM compatible memory device. The SRAM compatible memory device includes an array of DRAM memory cells arranged in rows and columns, each DRAM memory cell requiring a refresh operation for retention of data stored within a predetermined refresh period. The method comprises the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) performing an access operation to access the DRAM memory array for the duration of a predetermined DRAM access time in response to the address transition detection signal, (d) allowing another DRAM access time to elapse after the step (c), and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from the leading address input time. The SRAM access time is equal to or longer than twice the DRAM access time.
- In the SRAM compatible memory device and method of driving the same according to the invention, the DRAM memory cell is operated twice within each access time, to be fully compatible with an asynchronous SRAM. Also, the SRAM compatible memory according to the invention can be easily implemented. Further, since the SRAM compatible memory according to the invention uses DRAM cells, it can function as a low power asynchronous SRAM.
- The foregoing and further objects, features and advantages of the invention will become more apparent from a consideration of the following description, the appended claims and the accompanying drawings in which the same numerals indicate the same or corresponding parts.
- FIG. 1 is a block diagram of an SRAM compatible memory device according to an embodiment of the invention;
- FIG. 2 is a timing diagram illustrating an example of when a read operation is performed from an idle (IDLE) state;
- FIGS. 3 through 5 are timing diagrams illustrating examples of when write operations are performed from an idle (IDLE) state;
- FIGS. 6 and 7 are timing diagrams illustrating examples of when read and write operations are performed from a reserved (RESERVED) state;
- FIG. 8 is a timing diagram for a case in which a read command is further generated from a read (READ) state;
- FIG. 9 is a timing diagram for a case in which a read command is generated from a refresh (REFRESH) state;
- FIG. 10 is a timing diagram illustrating an example of generating a refresh command from an idle (IDLE) state;
- FIG. 11 is a timing diagram illustrating an example of when a refresh command is generated from a reserved (RESERVED) state or a read (READ) state;
- FIG. 12 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to an embodiment of the invention;
- FIG. 13 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to another embodiment of the invention; and
- FIG. 14A and FIG. 14B are timing diagrams for explaining a reserved period.
- FIG. 1 is a block diagram of an SRAM compatible memory device according to an embodiment of the invention. The SRAM compatible memory device according to the invention is implemented using a DRAM memory cell. A plurality of DRAM memory cells is arranged in a DRAM memory array shown in FIG. 1. The DRAM memory cell is implemented by including one transistor and one capacitor as a unit cell. Thus, in order to retain data stored therein, a refresh operation is performed within a predetermined refresh period.
- An externally input address ADDR is decoded by a
row decoder 103 and acolumn decoder 105. Also, a specific memory cell arranged at a row and column of the DRAMmemory cell array 101, is designated with the decoded address. Externally input data is stored in the designated memory cell in a write (WRITE) mode. Also, in a read (READ) mode, the data stored in the designated memory cell is output to the outside through anoutput buffer 109. In this specification, for the convenience of explanation, theDRAM memory array 101, therow decoder 103, thecolumn decoder 105, awrite buffer 107 and theoutput buffer 109, are referred to as aninternal DRAM 100. - In order to effectively perform the read/write operations of the
internal DRAM 100, anaddress latch 111, an address transition detection (ATD)circuit 113, adata latch 115 and a data transition detection (DTD)circuit 117 are incorporated in the SRAM compatible memory device. Theaddress latch 111 latches the ADDR and supplies the same to therow decoder 103 and thecolumn decoder 105. TheATD circuit 113 detects the change in the logic level of the ADDR to generate an address transition detection (ATD) signal. The ATD signal becomes activated with a predetermined pulse width when the ADDR makes a transition in a state in which a chip selection signal CS is logic “high”. - The data latch115 latches input data DATA and supplies the same to the
write buffer 107. TheDTD circuit 117 generates a data transition detection (DTD) signal. The DTD signal becomes activated with a predetermined pulse width when the DATA is input and a write enable (WEB) signal goes “low”. - Also, a
refresh timer 119 for refreshing DRAM memory cells arranged in thememory array 101, is incorporated in the SRAM compatible memory device according to an embodiment of the invention. A refresh request (REFREQ) signal supplied from therefresh timer 119 is activated for a constant refresh period. - Although the SRAM compatible memory device according to the invention internally employs DRAM memory cells, an externally controlled refresh operation is not required, which makes the SRAM compatible memory device similar to the conventional SRAM. Also, signals for controlling the refresh operation are not input. In other words, the SRAM compatible memory device of the invention operates externally in the same manner that the conventional SRAM does.
- For implementation of the operation shown in FIGS. 2 through 11, a
DRAM operation controller 121 is incorporated in the SRAM compatible memory device according to an embodiment of the invention. In detail, theDRAM operation controller 121 includes a DRAMstate switching portion 121 a, a DRAMoperation controlling portion 121 b, a DRAMstate identifying portion 121 c and a reservedstate controlling portion 121 d. The DRAMstate identifying portion 121 c identifies the current operating state of theinternal DRAM 100 by the information contained in the ATD signal and the WEB signal. - The reserved
state controlling portion 121 d determines the width of a reserved (RESERVED) state period of theinternal DRAM 100, in accordance with the operating state of theinternal DRAM 100 and the length of the time elapsed from the ATD signal being activated. The DRAMoperation controlling portion 121 b controls theinternal DRAM 100 to perform an access operation such as a read operation, a write operation or a refresh operation, after the RESERVED state period of theinternal DRAM 100 determined by the reservedstate controlling portion 121 d has lapsed. The DRAMstate switching portion 121 a switches the operating state of theinternal DRAM 100, in response to the DTD, ATD or WEB signal. - Five operating states of the
internal DRAM 100 in the SRAM compatible memory device are designated as a READ state, a WRITE state, a REFRESH state, a RESERVED state and an IDLE state. When the DRAM is in the READ state, the operation of reading out data is performed. In the WRITE state, the operation of writing externally input data in theDRAM memory array 101 is performed. In the REFRESH state, the operation of amplifying the data stored in theDRAM memory array 101 and rewriting the same is performed. In the RESERVED state, the refresh operation can be allocated to theinternal DRAM 100. The fifth state of theDRAM 100, the IDLE state, is a state other than the READ state, the WRITE state, the REFRESH state and the RESERVED state, that is, a state in which no operation is performed. - Various operations of the SRAM compatible memory device according to the invention will now be described with reference to FIGS. 2 through 11.
- FIG. 2 is a timing diagram illustrating an example of initiating a read operation from an idle (IDLE) state. If an address ADDR primarily is input at a time t1, an ATD signal is generated as a pulse. The
internal DRAM 100 is switched from an IDLE state (A1) to a RESERVED state (A2). Successively, if a predetermined DRAM access time (period) D_tRC has elapsed, theinternal DRAM 100 is switched from the RESERVED state (A2) to a READ state (A3), and reads out data for the duration of the access time D_tRC, to be output. - If an SRAM access time S_tRC, of a period from the leading ADDR input time t1 to the lagging ADDR input time t2, is longer than twice the DRAM access time D_tRC, the SRAM compatible memory device according to the invention performs a read operation in the same manner as the conventional SRAM does.
- In FIG. 2, activation of a CS signal to a logic “high” indicates that the
internal DRAM 100 has entered a state in which it is capable of performing read/write access and refresh operations. The “high” state of the WEB signal indicates a READ state, and the “low” state thereof indicates a WRITE state. For convenience of explanation, an explanation of the CS and WEB signals is omitted. - FIG. 3 is a timing diagram illustrating an example of initiating a write operation from an idle (IDLE) state. Like in the READ operation shown in FIG. 2, the
internal DRAM 100 is switched from an IDLE state (B1) to a RESERVED state (B2). After the lapse of the DRAM access time D_tRC, theinternal DRAM 100 is further switched to a WRITE state (B3) to perform a data write operation. Here, a DTD signal is activated with a predetermined pulse width responsive to activation of a WEB signal and input of data. In other words, theinternal DRAM 100 identifies a WRITE state by the first pulse of the DTD signal responsive to activation of the WEB signal. Also, theinternal DRAM 100 writes valid data by the second pulse of the DTD signal responsive to input of data. In this case as shown in FIG. 3, like in FIG. 2, when an SRAM access time S_tRC is longer than twice the DRAM access time D_tRC, the SRAM compatible memory device according to the invention performs a write operation in the same manner as does the conventional SRAM. - FIG. 4 is a timing diagram illustrating another example of initiating a write operation from an idle (IDLE) state. A WEB signal is activated within a DRAM access time D_tRC following a leading ADDR input time t1. However, data is input after a period twice the DRAM access time D_tRC.
- In FIG. 4, the
internal DRAM 100 is switched to a RESERVED state (C2) in response to an ATD signal. After the lapse of the DRAM access time D_tRC, theinternal DRAM 100 is further switched to a first WRITE state (C3) to perform a data write operation. However, in the first WRITE state (C3), data is not input. Thus, in the first WRITE state (C3), an invalid WRITE operation is performed, that is, invalid data is input. Thereafter, at a time t3, responsive to the input of data, theinternal DRAM 100 is switched to a WRITE state (C4) in which valid data is written. Here, a SRAM access time S_tRC, that is, a time period from the leading ADDR input time t1 to a lagging ADDR input time t2, is longer than twice the DRAM access time D_tRC, that is, longer than the minimum SRAM access time S_tRCmin. If such conditions of ADDR input, WEB signal input and data input as shown in FIG. 4 are allowed in the conventional SRAM, the SRAM compatible memory device according to the invention will satisfactorily perform an access operation such as a write operation, in the same manner as does the conventional SRAM. - FIG. 5 is a timing diagram illustrating still another example of initiating a write operation from an idle (IDLE) state. A WEB signal is activated during a DRAM access time D_tRC following a leading address ADDR input time t1. Also, data is input during a period twice the length of the DRAM access time D_tRC following the leading address ADDR input time.
- The
internal DRAM 100 is switched to a RESERVED state (D2) in response to an ATD signal. After the lapse of the DRAM access time D_tRC, theinternal DRAM 100 is switched to a READ state (D3). The reason for the switch to the READ state (D3) is that the WEB signal is not yet activated to a logic “low”. However, the READ state (D3) is subsequently changed to an invalid READ state in which invalid data is read out. - If the WEB signal is activated to a logic “low”, the
internal DRAM 100 is switched to a first WRITE state (D4) to perform a write operation. However, since no data is input in the first WRITE state (D4), an invalid WRITE operation is performed. Thereafter, at a time t3, responsive to the input of data, theinternal DRAM 100 is switched to a second WRITE state (D5) in which valid data is written. - In FIG. 5, an SRAM access time S_tRC is longer than the minimum SRAM access time S_tRCmin. However, if such rules of WEB signal input and data input as shown in FIG. 5 were allowed in the conventional SRAM, the SRAM compatible memory device according to the invention will satisfactorily perform an access operation such as a write operation, as does the conventional SRAM.
- FIG. 6 is a timing diagram illustrating an example of performing a read operation from a reserved (RESERVED) state, in which a lagging address ADDR is input at a time t2 prior to a DRAM access time D_tRC following a time t1 at which a leading ADDR is input.
- First, if the leading ADDR primarily is input at the time t1, the
internal DRAM 100 is switched from an IDLE state (E1) to a RESERVED state (E2) in response to generation of an ATD signal. However, during the period of the RESERVED state (E2), the lagging ADDR is secondarily input at the time t2. In other words, a time interval (T1) from the time t1 and the time t2 is shorter than the DRAM access time D_tRC. Then, the ATD signal is again generated and theinternal DRAM 100 is further switched to a RESERVED state (E3). Thereafter, theinternal DRAM 100 operates such that if a predetermined access time D_tRC has elapsed, theinternal DRAM 100 is switched from the RESERVED state (E3) to a READ state (E4). And the data is read out for the duration of the access time D_tRC, to then be output. - FIG. 7 is a timing diagram illustrating an example of performing a write operation from a reserved (RESERVED) state. Like in FIG. 6, a lagging address ADDR is input at a time t2 prior to a DRAM access time D_tRC following a time t1 at which a leading ADDR is input. Thus, similarly to the case shown in FIG. 6, the
internal DRAM 100 is switched to a WRITE state (F4) after two RESERVED states (F2 and F3). - FIG. 8 is a timing diagram illustrating the case in which a read command is further generated from a read (READ) state, in which a lagging address ADDR is input at a time t2 that comes after a DRAM access time D_tRC from a leading ADDR input time t1, and comes prior to a time which is twice the time D_tRC.
- First, if the leading address ADDR is primarily input at the time t1, an ATD signal is generated as a pulse. Then, the
internal DRAM 100 is switched from an IDLE state (G1) to a RESERVED state (G2) in response to generation of the ATD signal. Continuously, if a predetermined DRAM access time D_tRC has elapsed, theinternal DRAM 100 is switched from the RESERVED state (G2) to a READ state (G3) to remain in the READ state (G3) for the duration of the access time D_tRC. However, as shown in FIG. 8, the lagging ADDR is input at the time t2 while the DRAM is in the READ state (G3). Then, the ATD signal is generated as a pulse. If the READ state (G3) is terminated, theinternal DRAM 100 is further switched to a RESERVED state (G4). Then, if the access time D_tRC has elapsed after the ATD signal is generated, theinternal DRAM 100 is switched to a READ state (G5) to perform a read operation. - FIG. 9 is a timing diagram illustrating the case in which a read command is generated from a refresh (REFRESH) state of the DRAM. In FIG. 9, the REFRESH state (H1) is initiated at a time t1 and an address ADDR is input at a time t2 prior to completion of a REFRESH state (H2). Then, if during the REFRESH state (H1) a DRAM access time D_tRC elapses, the
internal DRAM 100 is switched to the RESERVED state (H2). Also, if another DRAM access time D_tRC elapses after generation of an ATD signal, theinternal DRAM 100 is switched from the RESERVED state (H2) to a READ state (H3). Continuously, the READ state (H3) is held for the duration of the access time D_tRC. - FIG. 10 is a timing diagram illustrating an example of generating a refresh command from an idle (IDLE) state, in which the refresh request (REFREQ) signal generated from the refresh timer (119 of FIG. 1) is activated during an IDLE state (11). Then, the
internal DRAM 100 is switched to a REFRESH state (12) in response to the REFREQ signal. The activation of the REFREQ signal may occur irrespective of the logical state of a CS signal. After the REFRESH state (12) is held for the duration of the access time D_tRC, theinternal DRAM 100 is switched again to an IDLE state (13). - FIG. 11 is a timing diagram illustrating an example of generating a refresh command from a reserved (RESERVED) or read (READ) state. First, if an address ADDR is input and an ATD signal is then activated, the SRAM compatible memory device according to the invention enters a RESERVED state (J1). Even if a REFREQ signal is activated to a logic “high” in the RESERVED state (J1), the RESERVED state (J1) and a READ state (J2) are held for the duration of the access time D_tRC and another (following) access time D_tRC, respectively. After the READ state (J2) is terminated, a REFRESH state (J3) is then started. Also, even if the REFREQ signal is activated to a logic “high” in the READ state (J2), the REFRESH state (J3) is started after the READ state (J2), held for the duration of access time D_tRC, is terminated.
- FIG. 12 shows conceptually a state transition scheme of the internal DRAM, which is shown in detail in FIG. 2 to FIG. 11. Referring to FIG. 1 and FIG. 12, the state transition scheme of the internal DRAM will be summarized.
- When the activation of the ATD signal is generated from an idle state S1201, the
internal DRAM 100 is switched to a reserved state S1203, at transition T1201. If the WEB signal is in non-activation when the reserved state S1203 is terminated, theinternal DRAM 100 is switched to a read state S1205, at transition T1202. If the WEB signal is in activation when the reserved state S1203 is terminated, theinternal DRAM 100 is switched to a write state S1207, at transition T1203. If the read state S1205 or the write state S1207 is terminated within a reserved period RSVD=I, theinternal DRAM 100 is switched to the reserved state S1203, at transition T1204 or T1205. The reserved period is a predetermined time interval of the reserved state from the activation of the ATD signal, which is illustrated in FIG. 14A and FIG. 14B. In this specification, RSVD=I means the inside of the reserved period, while RSVD=O means the outside of the reserved period. - When the activation of the WEB signal is generated from the read state S1205, the
internal DRAM 100 is switched to the write state S1207, at transition T1206. If the activation of the REFREQ signal is generated from the idle state S1201, theinternal DRAM 100 is switched to a first refresh state S1209, at transition T1207. However, if the activation of the REFREQ signal is generated from the read state S1205 or the write state S1207, theinternal DRAM 100 is switched to a second refresh state S1211 after the completion of the read state S1205 or the write state S1207, at transition T1208 or T1209. In this specification the refresh state is shown as the first and the second refresh state S1209 and S1211, because the transition conditions from the first and the second refresh state S1209 and S1211 to the other state are different. If the first refresh state S1209 is terminated in the outside of the reserved period RSVD=O, theinternal DRAM 100 is switched to the idle state S1201, at transition T2110. However, in the case of the second refresh state, theinternal DRAM 100 is switched to the read state S1205 or the write state S1207 according to the whether the WEB signal is activated or not, at transition T1211 or T1212, in spite of the second refresh state being terminated in the outside of the reserved period RSVD=O. When the first refresh state S1209 or the second refresh state S1211 is terminated in the inside of the reserved period RSVD=I, theinternal DRAM 100 is switched to the reserved state S1203, at transition T1213 or T1214. - If the WEB signal is in activation when the activation of the DTD signal is generated from the idle state S1201, the
internal DRAM 100 is switched to the write state S1207, at transition T1215. When the read state S1205 or the write state S1207 is terminated in the outside of the reserved period RSVD=O, theinternal DRAM 100 is switched to the idle state S1201, at transition T1216 or T1217. - If the activation of the ATD signal is generated from the reserved state S1203, the
internal DRAM 100 is maintained with the reserved state S1203, at transition T1218. If the activation of the DTD signal is generated from the write state S1207, theinternal DRAM 100 is maintained in the write state S1207, at transition T1218. - FIG. 13 is a state transition diagram of the internal DRAM in an SRAM compatible memory device according to another embodiment of the invention. Referring to FIG. 13, a read state or a write state is generated in advance of a refresh state. The state transition scheme of the internal DRAM in an SRAM compatible memory device according to this other embodiment of the invention will be described below.
- If the WEB signal is in non-activation when the activation of the ATD signal is generated from an idle state S1301, the
internal DRAM 100 is switched to a read state S1305, at transition T1301. If the WEB signal is in activation when the activation of the ATD signal or the DTD signal is generated from an idle state S1301, theinternal DRAM 100 is switched to a write state S1307, at transition T1302. When the activation of the REFREQ signal is generated from an idle state S1301, theinternal DRAM 100 is switched to a refresh state S1303, at transition T1303. If the successive flag SF is 1 when the refresh state S1303 is terminated, theinternal DRAM 100 is switched to a read state S1305 or a write state S1307 depending on the activation of the WEB signal, at transition T1304 or T1305. The successive flag SF is set as 1 when the activation of the signal ATD is generated during a READ, WRITE or REFRESH operation. The successive flag SF is set as 0 when a read operation, a write operation or a refresh operation starts. - If the successive flag SF is 0 when the refresh state S1303 is terminated, the
internal DRAM 100 is switched to the idle state S1301, at transition T1306. If the REFREQ signal is in activation when the read state S1305 or the write state S1307 is terminated, theinternal DRAM 100 is switched to the refresh state S1301, at transition T1307 or T1308. If the successive flag SF is 1 and the WEB signal is in activation when the read state S1305 is terminated, theinternal DRAM 100 is switched to the write state S1307, at transition T1309. If the successive flag SF is 1 and the WEB signal is in non-activation when the read state S1305 is terminated, theinternal DRAM 100 is maintained in the write state S1307, at transition T1310. - If the successive flag SF is 1 and the WEB signal is in non-activation when the write state S1307 is terminated, the
internal DRAM 100 is switched to the read state S1305, at transition T1311. If the successive flag SF is I and the WEB signal is in activation when the write state S1307 is terminated, theinternal DRAM 100 is maintained in the read state S1305, at transition T1312. If the successive flag SF is 0 when the read state S1305 or the write state S1307 is terminated, theinternal DRAM 100 is switched to the idle state S1301, at transition T1313 or T1314. - In the embodiment shown in FIG. 12, a reserved state capable of a refresh operation is generated in advance of a read state or a write state. However, in the other embodiment, shown in FIG. 13, a read state or a write state is generated in advance of a refresh.
- In the invention, in order to implement a memory that is fully compatible with an asynchronous SRAM, a DRAM memory cell is operated twice within an access time of an SRAM. For example, in order to implement an asynchronous SRAM having an access time of 70 ns, the
internal DRAM 100 is configured to have an access time of 35 ns or less and theinternal DRAM 100 is operated twice, for a period of 70 ns. During the first period of access time of theinternal DRAM 100, no operation is performed, or a refresh operation is performed. However, during the second period of access time of theinternal DRAM 100, read/write operations are performed. - While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. It will be understood by those skilled in the art that various modifications may occur to those skilled in the art without departing from the spirit and scope of the invention. It is, therefore, intended that the true spirit and scope of the invention be defined by the appended claims and their equivalents.
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004057620A2 (en) * | 2002-12-19 | 2004-07-08 | Cypress Semiconductor Corporation | Method and system for performing memory operations of a memory device |
US20050052941A1 (en) * | 2002-06-25 | 2005-03-10 | Fujitsu Limited | Semiconductor memory |
US20050265506A1 (en) * | 1994-10-06 | 2005-12-01 | Mosaid Technologies, Inc. | Delay locked loop implementation in a synchronous dynamic random access memory |
US20060044293A1 (en) * | 2004-08-20 | 2006-03-02 | Dialog Semiconductor Gmbh | Display controller with DRAM graphic memory |
EP1647028A2 (en) * | 2003-07-14 | 2006-04-19 | Zmos Technology, Inc. | 1t1c sram |
US20070025137A1 (en) * | 1990-04-06 | 2007-02-01 | Lines Valerie L | Dynamic memory word line driver scheme |
US20070200611A1 (en) * | 1990-04-06 | 2007-08-30 | Foss Richard C | DRAM boosted voltage supply |
TWI407436B (en) * | 2004-07-14 | 2013-09-01 | Zmos Technology Inc | 1t1c sram |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7743114B1 (en) * | 2000-06-30 | 2010-06-22 | Automated Business Companies | Automated data delivery systems |
JP4000242B2 (en) * | 2000-08-31 | 2007-10-31 | 富士通株式会社 | Semiconductor memory device |
JP3531602B2 (en) * | 2000-11-08 | 2004-05-31 | セイコーエプソン株式会社 | Activation of word lines in semiconductor memory devices |
KR100381615B1 (en) * | 2001-01-04 | 2003-04-26 | (주)실리콘세븐 | SRAM Compatible Memory For Complete Hiding of The Refresh Operation Using a DRAM Cache Memory |
KR100394587B1 (en) * | 2001-05-19 | 2003-08-14 | (주)실리콘세븐 | Refresh circuit in sram using dram cell |
JP2003059264A (en) * | 2001-08-08 | 2003-02-28 | Hitachi Ltd | Semiconductor memory device |
TW533413B (en) * | 2001-10-11 | 2003-05-21 | Cascade Semiconductor Corp | Asynchronous hidden refresh of semiconductor memory |
US6735139B2 (en) * | 2001-12-14 | 2004-05-11 | Silicon Storage Technology, Inc. | System and method for providing asynchronous SRAM functionality with a DRAM array |
KR100481818B1 (en) * | 2002-07-24 | 2005-04-11 | (주)실리콘세븐 | SRAM compatible and Burst Accessible Synchronous Memory Device using DRAM cell and Operating Method thereof |
JP4188640B2 (en) * | 2002-08-08 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor memory device, semiconductor memory device control method, and semiconductor memory device test method |
DE10245546B3 (en) * | 2002-09-30 | 2004-05-13 | Infineon Technologies Ag | Pseudostatic memory circuit |
KR100525459B1 (en) * | 2003-05-16 | 2005-10-31 | (주)실리콘세븐 | SRAM compatable memory performing REFRESH operation in which the inducing and the rewriting operation are performed seperately and Operating Method thereof |
KR102373544B1 (en) | 2015-11-06 | 2022-03-11 | 삼성전자주식회사 | Memory Device and Memory System Performing Request-based Refresh and Operating Method of Memory Device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5841479B2 (en) * | 1972-10-18 | 1983-09-12 | 株式会社日立製作所 | Genshiroyosoku Monitor |
JP3304413B2 (en) * | 1992-09-17 | 2002-07-22 | 三菱電機株式会社 | Semiconductor storage device |
JP2660488B2 (en) * | 1994-09-13 | 1997-10-08 | 三菱電機株式会社 | Semiconductor storage device |
KR980006305A (en) * | 1996-06-07 | 1998-03-30 | 김광호 | DRAM semiconductor device and access method thereof |
JPH10302471A (en) * | 1997-02-28 | 1998-11-13 | Mitsubishi Electric Corp | Semiconductor memory |
US5999474A (en) * | 1998-10-01 | 1999-12-07 | Monolithic System Tech Inc | Method and apparatus for complete hiding of the refresh of a semiconductor memory |
-
2000
- 2000-12-04 KR KR10-2000-0072815A patent/KR100367690B1/en not_active IP Right Cessation
-
2001
- 2001-01-20 TW TW090101416A patent/TW591657B/en not_active IP Right Cessation
- 2001-04-02 US US09/822,487 patent/US6392958B1/en not_active Expired - Lifetime
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070200611A1 (en) * | 1990-04-06 | 2007-08-30 | Foss Richard C | DRAM boosted voltage supply |
US20070025137A1 (en) * | 1990-04-06 | 2007-02-01 | Lines Valerie L | Dynamic memory word line driver scheme |
US20050265506A1 (en) * | 1994-10-06 | 2005-12-01 | Mosaid Technologies, Inc. | Delay locked loop implementation in a synchronous dynamic random access memory |
US8638638B2 (en) | 1994-10-06 | 2014-01-28 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US8369182B2 (en) | 1994-10-06 | 2013-02-05 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US7064998B2 (en) | 2002-06-25 | 2006-06-20 | Fujitsu Limited | Semiconductor memory |
CN101261877B (en) * | 2002-06-25 | 2010-07-28 | 富士通微电子株式会社 | Semiconductor memory |
US20050052941A1 (en) * | 2002-06-25 | 2005-03-10 | Fujitsu Limited | Semiconductor memory |
EP1669999A1 (en) * | 2002-06-25 | 2006-06-14 | Fujitsu Limited | Semiconductor memory |
US7072243B2 (en) | 2002-06-25 | 2006-07-04 | Fujitsu Limited | Semiconductor memory |
US20060023547A1 (en) * | 2002-06-25 | 2006-02-02 | Fujitsu Limited | Semiconductor memory |
EP1517332A4 (en) * | 2002-06-25 | 2005-09-14 | Fujitsu Ltd | Semiconductor memory |
EP1517332A1 (en) * | 2002-06-25 | 2005-03-23 | Fujitsu Limited | Semiconductor memory |
WO2004057620A3 (en) * | 2002-12-19 | 2004-08-26 | Cypress Semiconductor Corp | Method and system for performing memory operations of a memory device |
WO2004057620A2 (en) * | 2002-12-19 | 2004-07-08 | Cypress Semiconductor Corporation | Method and system for performing memory operations of a memory device |
EP1647028A4 (en) * | 2003-07-14 | 2006-09-06 | Zmos Technology Inc | 1t1c sram |
EP1647028A2 (en) * | 2003-07-14 | 2006-04-19 | Zmos Technology, Inc. | 1t1c sram |
TWI407436B (en) * | 2004-07-14 | 2013-09-01 | Zmos Technology Inc | 1t1c sram |
US7446776B2 (en) * | 2004-08-20 | 2008-11-04 | Dialog Semiconductor Gmbh | Display controller with DRAM graphic memory |
US20060044293A1 (en) * | 2004-08-20 | 2006-03-02 | Dialog Semiconductor Gmbh | Display controller with DRAM graphic memory |
Also Published As
Publication number | Publication date |
---|---|
KR100367690B1 (en) | 2003-01-14 |
TW591657B (en) | 2004-06-11 |
US6392958B1 (en) | 2002-05-21 |
KR20020043347A (en) | 2002-06-10 |
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