US20020052169A1 - Systems and methods to significantly reduce the grinding marks in surface grinding of semiconductor wafers - Google Patents

Systems and methods to significantly reduce the grinding marks in surface grinding of semiconductor wafers Download PDF

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US20020052169A1
US20020052169A1 US09809634 US80963401A US2002052169A1 US 20020052169 A1 US20020052169 A1 US 20020052169A1 US 09809634 US09809634 US 09809634 US 80963401 A US80963401 A US 80963401A US 2002052169 A1 US2002052169 A1 US 2002052169A1
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velocity
wafer
grinding
method
face
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US09809634
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Krishna Vepa
Duncan Dobson
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Wafer Solutions Inc
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Wafer Solutions Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02013Grinding, lapping
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber

Abstract

The present invention provides systems and methods for varying the speed of a wafer chuck relative to a grinding wheel during the grinding process. The systems and methods involve relative rotation between a wafer and a grinding wheel at a first velocity and subsequently at a second velocity. The variance between the first and second velocities reduces striations on the face of the wafer being ground. In addition, the change in velocity increases the ploughing capability of the grinding element.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • This application claims the benefit of the following U.S. Applications, the complete disclosures of which are incorporated herein by reference for all purposes: [0001]
  • Non-Provisional Application No. ______ (Attorney Docket No. 20468-000510), entitled “Grind And Single Wafer Etch Process To Remove Metallic Contamination In Silicon Wafers” and filed on a date even herewith; [0002]
  • Provisional Application No. 60/190,278 (Attorney Docket No. 20468-000100), filed on Mar. 17, 2000; [0003]
  • Provisional Application No. 60/190,478 (Attorney Docket No. 20468-000200), filed on Mar. 17, 2000; and [0004]
  • Provisional Application No. 60/190,276 (Attorney Docket No. 20468-000500), filed on Mar. 17, 2000.[0005]
  • BACKGROUND OF THE INVENTION
  • The present invention is directed to the processing of wafers, substrates or disks, such as silicon wafers, and more specifically to systems and methods of varying the rotational speed during the grinding process of a semiconductor wafer manufacturing process. [0006]
  • Wafers or substrates with exemplary characteristics must first be formed prior to the formation of circuit devices. In determining the quality of the semiconductor wafer, the flatness of the wafer is a critical parameter to customers since wafer flatness has a direct impact on the subsequent use and quality of semiconductor chips diced from the wafer. Hence, it is desirable to produce wafers having as near a planar surface as possible. [0007]
  • In a current practice, cylindrical boules of single-crystal silicon are formed, such as by Czochralski (CZ) growth process. The boules typically range from 100 to 300 millimeters in diameter. These boules are cut with an internal diameter (ID) saw or a wire saw into disc-shaped wafers approximately one millimeter (mm) thick. The wire saw reduces the kerf loss and permits many wafers to be cut simultaneously. However, the use of these saws results in undesirable waviness of the surfaces of the wafer. For example, the topography of the front surface of a wafer may vary by as much as 1-2 microns (μ) as a result of the natural distortions or warpage of the wafer as well as the variations in the thickness of the wafer across its surface. It is not unusual for the amplitude of the waves in each surface of a wafer to exceed fifteen (15) micrometers. The surfaces need to be made more planar (planarized) before they can be polished, coated or subjected to other processes. [0008]
  • FIG. 1 depicts a typical prior art method [0009] 10 for processing a silicon wafer prior to device formation. Method 10 includes a slice step 12 as previously described to remove a disc-shaped portion of wafer from the silicon boule. Once the wafer has been sliced, the wafer is cleaned and inspected (Step 14). Thereafter, an edge profile process (Step 16) is performed. Once the edge profile has been performed, the wafer is again cleaned and inspected (Step 18), and is laser marked (Step 20).
  • Next, a lapping process (Step [0010] 22) is performed to control thickness and remove bow and warp of the silicon wafer. The wafer is simultaneously lapped on both sides with an abrasive slurry in a lapping machine. The lapping process may involve one or more lapping steps with increasingly finer polishing grit. However, even where multiple lapping steps are performed with increasingly fine polishing grit, the lapping process leaves significant scratches in the wafer surface. Such scratches can be very deep requiring significant polishing in a subsequent polishing process (step 40). Such polishing must remove a portion of the processed wafer roughly equivalent to the depth of the scratches. Thus, the scratches left in the wafer during the lapping process are wasteful both because of the time involved in removing deep scratches through a polishing process and because of the amount of wafer material which must be removed and wasted. Furthermore, the depth of scratches caused by the lapping step can be increased by alkaline anisotropic etching during subsequent polishing steps. This alkaline anisotropic etching is the result of chemicals and processes associated with conventional polishing methods.
  • Some methods replace the lapping process with a grinding process. However, the problems are similar. For example, the grinding process results in a grinding pattern of substantially deep scratches. These scratches must ultimately be removed by a subsequent polishing step as previously described. [0011]
  • Upon finishing the lapping process (step [0012] 22), the wafer is cleaned (Step 24) and etched (Step 26) to remove damage caused by the lapping process. The etching process may involve placing the wafer in an acid bath to remove the outer surface layer of the wafer. Typically, the etchant is a material requiring special handling and disposal. Thereafter, an additional cleaning of the wafer (Step 28) is performed.
  • The prior art method continues with a donor anneal (Step [0013] 30) followed by wafer inspection (Step 32). Thereafter, the wafer edge is polished (Step 24) and the wafer is again cleaned (Step 36). Typical wafer processing involves the parallel processing of a multitude of wafers. Hence at this juncture wafers may be sorted, such as by thickness (Step 38), after which a double side polish process is performed (Step 40).
  • The wafers then are cleaned (Step [0014] 42) and a final polish (Step 44) is performed. The wafers are again cleaned (Step 46), inspected (Step 48) and potentially cleaned and inspected again (Steps 50 and 52). For epitaxial substrates, a poly or oxide layer is overlaid to seal in the dopants after inspection Step 52. At this point, the wafer is packed (Step 54), shipped (Step 56) and delivered to the end user (Step 58). Hence, as seen in FIG. 1 and as described above, typical wafer processing involves a lengthy, time consuming process with a large number of processing steps.
  • In light of the preceding discussion, a variety of deficiencies in the prior art are noted. For example, the prior art processes result in significant wafer damage which must be cured by subsequent steps. Accordingly, systems and methods are desired for producing high quality wafers in a shorter period of time, such as by requiring fewer processing steps and/or steps of shorter duration. Further, systems and methods for producing wafers that reduce the amount of wasted wafer material are also desired. Additional deficiencies in the prior art, and improvements in the present invention, are described below and will be recognized by those of ordinary skill in the art. [0015]
  • SUMMARY OF THE INVENTION
  • The present invention provides systems and methods for reducing grinding patterns resulting from grinding processes used during wafer manufacturing. In some embodiments the depth of the grinding pattern is reduced to six (6) microns or less. By reducing the grinding pattern depth, the amount of material which must be removed in subsequent polishing steps is reduced. This advantageously results in more wafers per boule, increased wafer throughput, a reduction in flatness degradation and other benefits. Also, the incidence of rapid anisotropic etching during polish is reduced. [0016]
  • One method for fabricating wafers according to the present invention includes providing a wafer with a wafer face and back and affixing the wafer back to a susceptor. A grinding element, which in some embodiments is a grinding wheel comprised of a diamond abrasive material imbedded therein, is provided such that the face of the grinding element and the wafer can be rotated relative to each other. In some embodiments, the grinding wheel moves about a fixed axis, while in other embodiments it revolves in an orbital manner. The wafer face and the face of the grinding element are rotated relative to each other at a first velocity. The face of the grinding element is applied to the wafer face such that a portion of the wafer is removed by the grinding action. The wafer and the grinding element are then rotated relative to each other at a second rotational speed. In some embodiments, the first rotational velocity is greater than the second rotational velocity, while in other embodiments, the second rotational velocity is greater than the first. The variance between the two rotational velocities reduces striations on the face of the wafer and also regenerates the grinding element to expose abrasive material imbedded in the element. In some embodiments, the striations are reduced to less than ten microns [0017]
  • In some embodiments, the method includes rotating the wafer and the grinding element relative to each other at a third rotational velocity. The variance between the three rotational velocities further reduces striations on the face of the wafer. In some embodiments, the relative rotations are produced by rotating only the grinding element, while in other embodiments, the relative rotations are produced by rotating the wafer or a combination of the wafer and the grinding element. [0018]
  • Another method according to the present invention includes providing an unpolished substrate. The substrate is placed on a rotatable mount. The grinding element and the substrate are rotated relative to each other at a first velocity with the grinding element being applied to the substrate. The velocity is increased to a second velocity. In some embodiments, the increase in velocity is accomplished by gradually increasing the velocity from the first velocity to the second velocity. Such a change in velocity increases the ploughing capability of the grinding element and reduces the presence of striations on the face of the unpolished substrate. [0019]
  • One system for fabricating semiconductor substrates according to the present invention includes a grinding wheel, which in some embodiments comprises diamond abrasive material imbedded therein, and a wafer mounted on a chuck relative to the grinding wheel. A microprocessor based controller is included to control the velocity of rotation of the wafer relative to the grinding wheel. In addition, the system includes a database associated with the microprocessor based controller which comprises code executable by the microprocessor to cause relative rotation between the wafer and the grinding wheel at a first velocity and subsequently to provide relative rotation at a second velocity. The variance of the rotational velocities reduces the striations on the face of the wafer. Additionally, in some embodiments, the increase in velocity from the first velocity to the second velocity regenerates the face of the grinding wheel. [0020]
  • In other embodiments, the database comprises code executable by the microprocessor which causes the grinding wheel to move at three velocities in which each subsequent velocity is greater than the previous velocity. The variance between the three rotational velocities further reduces striations on the face of the wafer. [0021]
  • Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.[0022]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 depicts a prior art method for processing a silicon wafer; [0023]
  • FIG. 2 is a simplified flow diagram of a wafer processing method according to the present invention; [0024]
  • FIGS. [0025] 3A-C depict grind damage cluster tools according to the present invention;
  • FIG. 4 depicts an edge profile/polish cluster tool according to the present invention; [0026]
  • FIGS. 5A and 5B depict double side polish cluster tools according to the present invention; [0027]
  • FIG. 6 depicts a finish polish cluster tool according to the present invention; [0028]
  • FIG. 7 depicts a wafer grinding machine which may be used in accordance with the present invention; and [0029]
  • FIG. 8 depicts a simplified flow diagram of a wafer grinding method according to the present invention[0030]
  • DESCRIPTION OF THE SPECIFIC EMBODIMENTS
  • FIG. 2 depicts an exemplary method [0031] 200 of the present invention. Additional details of exemplary methods may be found in U.S. patent application Ser. No. ______ (Attorney Docket No. 20468-000110), entitled “CLUSTER TOOL SYSTEMS AND METHODS FOR PROCESSING WAFERS”, the complete disclosure of which is incorporated herein by reference for all purposes. Method 200 includes a slice process 210, using a wire saw, inner diameter saw or the like, to create a generally disc-shaped wafer or substrate. In one embodiment, the wafer is a silicon wafer. Alternatively, the wafer may comprise polysilicon, germanium, glass, quartz, or other materials. Further, the wafer may have an initial diameter of about 200 mm, about 300 mm, or other sizes, including diameters larger than 300 mm.
  • The wafer is cleaned and inspected (Step [0032] 212) and then may, or may not, be laser-marked (Step 214). Laser marking involves creating an alphanumeric identification mark on the wafer. The ID mark may identify the wafer manufacturer, flatness, conductivity type, wafer number and the like. The laser marking preferably is performed to a sufficient depth so that the ID mark remains even after portions of the wafer have been removed by subsequent process steps such as grinding, etching, polishing, and the like.
  • Thereafter, the wafer is processed through a first module (Step [0033] 216), with details of embodiments of the first module described below in conjunction with FIGS. 3A-3C. First module processing (Step 216) includes a grinding process, an etching process, a cleaning process and metrology testing of the wafer. In this module, the use of a grinding process in lieu of lapping helps to remove wafer bow and warpage. The grinding process of the present invention also is beneficial in removing wafer surface waves caused by the wafer slicing in Step 210. Benefits of grinding in lieu of lapping include reduced kerf loss, better thickness tolerance, improved wafer shape for polishing and better laser mark dot depth tolerance, and reduced damage, among others.
  • The grinding process within the first module is a more benign process than the prior art grind or lap step described in conjunction with FIG. 1. For example, conventional grinding may involve deep scratches forming a grind pattern in the wafer. Such scratches cannot be lowered below ten (10) microns even with the use of a very fine abrasive, such as a 2000# diamond wheel in a vitrified matrix. To remove these scratches, considerable polish time and loss of significant wafer material is required. In contrast, the grind process of the present invention preferably leaves scratches of six (6) microns or less. Thus, the subsequent polish process can be performed in roughly 50% of the time required for a similar polish associated with a conventional grind. Furthermore, the grind process of the present invention reduces the amount of wafer material which must be removed during polish by approximately 50%. [0034]
  • Similarly, the etching process within the first module is a more benign process than the prior art etch step described in conjunction with FIG. 1. For example, typical prior art etching (Step [0035] 26 in FIG. 1) may involve the bulk removal of forty (40) or more microns of wafer thickness. In contrast, the etch process of the present invention preferably removes ten (10) microns or less from the wafer thickness. In one embodiment, the first module etch process removes between about two (2) microns to about five (5) microns of wafer material per side, or a total of about four (4) to about ten (10) microns. In another embodiment, the first module etch process removes between about three (3) microns and about four (4) microns of wafer material per side for a total of about six (6) to about (8) microns.
  • After first module processing, the wafer is subjected to a donor anneal (Step [0036] 218) and thereafter inspected (Step 220). The donor anneal removes unstable oxygen impurities within the wafer. As a result, the original wafer resistivity may be fixed. In an alternative embodiment, donor anneal is not performed.
  • The wafer then is processed through a second module (Step [0037] 222) in which an edge process is performed. The edge process includes both an edge profile and an edge polish procedure. Edge profiling may include removing chips from the wafer edge, controlling the diameter of the wafer and/or the creation of a beveled edge. Edge profiling also may involve notching the wafer to create primary and secondary flat edges. The flats facilitate wafer alignment in subsequent processing steps and/or provide desired wafer information (e.g., conductivity type). In one embodiment, one or both flats are formed near the ID mark previously created in the wafer surface. One advantage of the present invention involves performing the edge profiling after wafer grinding. In this manner, chips or other defects to the wafer edge, which may arise during grinding or lapping, are more likely to be removed. Prior art edge profiling occurs before lapping, and edge polishing subsequent to the lapping step may not sufficiently remove edge defects.
  • The wafer is then processed through a third module (Step [0038] 224). A third module process includes a double side polish, a cleaning process and wafer metrology. Wafer polishing is designed to remove stress within the wafer and smooth any remaining roughness. The polishing also helps eliminate haze and light point defects (LPD) within the wafer, and produces a flatter, smoother finish wafer. As shown by the arrow in FIG. 2, wafer metrology may be used to adjust the double side polishing process within the third module. In other words, wafer metrology may be feed back to the double side polisher and used to adjust the DSP device in the event the processed wafer needs to have different or improved characteristics, such as flatness, or to further polish out scratches.
  • Thereafter, the wafer is subjected to a finish polish, a cleaning process and metrology testing, all within a fourth process module ([0039] 226). The wafer is cleaned (Step 228), inspected (Step 230) and delivered (Step 232).
  • With reference to FIGS. [0040] 3-6, additional details on process modules according to the present invention will be provided. It will be appreciated by those skilled in the art that the process modules described in FIGS. 3-6 are embodiments of the present invention, from which a large number of variations for each module exist within the scope of the present invention. Further, additional process steps may be removed or added, and process steps may be rearranged within the scope of the present invention.
  • FIG. 3A depicts a grind damage cluster module described as first module [0041] 216 in conjunction with FIG. 2. First module 300 defines a clean room environment 310 in which a series of process steps are carried out. Wafers that have been processed through Step 214 (FIG. 2) are received in first module 300 via a portal, such as a front opening unified pod (FOUP) 312. First module 300 is shown with two FOUPs 312, although a larger or smaller number of FOUPs/portals may be used. FOUPs 312 are adapted to hold a number of wafers so that the frequency of ingress into the clean room environment 310 may be minimized. A transfer device 314, schematically depicted as a robot, operates to remove a wafer from FOUPs 312 and place the wafer on a grinder 318. If needed, transfer device 314 travels down a track 316 to properly align itself, and hence the wafer, in front of grinder 318. Grinder 318 operates to grind a first side of the wafer.
  • The wafer may be held down on grinder [0042] 318 by way of a vacuum or other type of chuck, and other methods. Once grinder 318 has ground the first side of the wafer, the wafer is cleaned in cleaner 322 and the transfer device 314 transfers the wafer back to grinder 318 for grinding the converse side of the wafer. In one embodiment, wafer grinding of both wafer sides removes about forty (40) microns to about seventy (70) microns of wafer thickness. After the second wafer side is ground, the wafer is again cleaned in cleaner 322. In one embodiment, cleaning steps occur on grinder 318 subsequent to grinding thereon. In one embodiment, cleaning and drying are accomplished by spraying a cleaning solution on the wafer held by or near the edges and spun.
  • In another embodiment, at least one side of the wafer is subjected to two sequential grinding steps on grinder [0043] 318. The two grinding processes preferably include a coarse grind followed by a fine grind. Grinder 318 may include, for example, two different grinding platens or pads with different grit patterns or surface roughness. In one embodiment, the wafer is cleaned on grinder 318 between the two grinding steps to the same wafer side. Alternatively, cleaning may occur after both grinding steps to the same wafer side.
  • A schematic side view of grinder [0044] 318 is illustrated in FIG. 7. Referring to FIG. 7, a wafer 720 is attached to a chuck 730 with a wafer back 722 affixed to chuck 730. Chuck 730 is attached to a grinder base 740. A wafer face 724 is located relative to a grinding element 710, which is attached to grinder 318. In some embodiments, grinding element 710 is a grinding wheel with diamond abrasive imbedded therein. In one embodiment, contact between grinding element 710 and wafer 720 is caused by adjusting the height of a grinder arm 750 using a height adjustment 760.
  • In addition, a microprocessor based controller [0045] 770 provides commands to grinder 318, including to chuck 730 across interfaces 790 and 795. Such commands are derived from computer executable code resident on database 780. The commands can include control of rotational velocity of grinding element 710 and/or chuck 730, as well as control of height adjustment 760.
  • Grinder [0046] 318 removes material from wafer 720 by contacting grinding element 710 with wafer 720 as wafer 720 and grinding element 710 are rotated relative to each other. The rotation of grinding element 710 relative to wafer 720 occurs at a rotational velocity. In some embodiments, providing this relative rotation is done by rotating grinding element 710, while maintaining chuck 730, and thereby wafer 720 in a generally fixed position. Thus, in this embodiment, the rotational velocity is the velocity of grinding element 710. In other embodiments, providing the relative rotation is done by rotating chuck 730, and thereby wafer 720, while maintaining grinding element 710 in a fixed position. Therefore, the rotational velocity is the speed at which chuck 730 is rotating wafer 720. In yet other embodiments, the relative rotation is provided by rotating both grinding element 710 and chuck 730. In such embodiments, the rotational velocity is the difference between the speed at which grinding element 710 and chuck 730 are rotating.
  • In still another embodiment, wafer [0047] 720 is rotated relative to both chuck 730 and grinding element 710. For example, a rotational device (not shown) may be coupled to a template (not shown) in which wafer 720 resides, with the rotational device rotating the template, and hence wafer 720.
  • According to the present invention, the rotational velocity is varied during the wafer grind steps. Varying the rotational velocity allows for greater self dressing of grinder element [0048] 710 and ploughing at the early part of the grinding cycle. In particular, self dressing includes constantly exposing abrasive poritons of the grinding element and ploughing includes cutting into a work piece as opposed to a dull surface merely scratching the surface and generating frictional heat. Thus, the change in velocity regenerates the face of grinder element 710 to expose abrasive material imbedded therein. In some embodiments, the velocity of relative rotation is gradually increased over the duration of the grinding process. Thus, for example, rotational velocity may be increased from about forty (40) revolutions per minute (rpm) up to over about 700 rpm. By varying the rotational velocity, the resulting grind pattern depth incident on wafer 720 is both reduced and/or minimized in comparison to conventional grinding processes. Such a reduction of grind pattern depth is observable using post polish optical characterization methods, such as, ADE's Magic mirror or other interferometric methods.
  • As an example, the present invention is capable of reducing the depth of the grind pattern to less than ten (10) microns. In some embodiments of the present invention, the grind pattern may be reduced to about six (6) microns or less. Because of the reduced depth of grind patterns, material removal during subsequent polishing steps is reduced along with the time required to finish the polishing step. This results in more wafers per boule, increased wafer throughput, a reduction in flatness degradation and also a reduction in the incidence of rapid anisotropic etching during subsequent polish steps. [0049]
  • Other embodiments, which similarly reduce grind pattern depth involve gradually reducing the rotational velocity from about 700 rpm down to about 40 rpm. Yet other embodiments involve incrementally increasing or decreasing rotational velocity during the grinding process. For example, in one embodiment, the grinding process begins at a rotational velocity between approximately 40 and 250 rpm for a first period. The rotational velocity is then incrementally increased to a speed between approximately 250 and 450 rpm for a second period and the grind is finished by incrementing the rotational velocity to between approximately 450 and 700 rpm for a third period. In some embodiments, ten (10) microns of material is removed at two (2) microns per second during the first period, 5 (five) microns of material is removed at 0.5 microns per second during the second period, and 5 (five) microns of material is removed at 0.3 microns per second during the third period. [0050]
  • Additionally, varying the rotational velocity during the grinding process results in a distribution of stress across the crystal lattice of the wafer. Thus, the incidence of high stress points on the wafer are minimized. By minimizing high stress points on the wafer, the incidence of rapid anisotropic etching is further lowered and a more uniform polishing of the wafer under alkaline conditions (ph>7) is achieved. [0051]
  • FIG. 8 illustrates a flow diagram [0052] 800 according to an embodiment of the present invention where the rotational velocity is varied during a grind of wafer 720. Referring to FIG. 8, wafer 720 is provided and wafer back 722 is coupled to chuck 730 (step 810). Grinding element 710 is rotated relative to wafer 720 (step 820). Grinding element 710 is brought into contact with wafer 720 by adjusting the height of grinder arm 750 using height adjustment 760 (step 830).
  • With grinder element [0053] 710 in contact with wafer 720, a grind is performed at a rotational velocity of between approximately 40 and 250 rpm. The rotational velocity is then incrementally increased to a speed between approximately 250 and 450 rpm (step 840). After a period, the rotational velocity is increased to between approximately 450 and 700 rpm (step 850). Once the grind is completed, grinding element 710 is moved away from wafer 720 by adjusting the height of grinder arm 750 again using height adjustment 760 (step 860).
  • Other embodiments, which similarly reduce grind pattern depth involve gradually reducing the relative rotational velocity between grinder element [0054] 710 and wafer 720 from about 700 rpm to about 40 rpm. Yet other embodiments involve gradually increasing or decreasing the relative rotational velocity between grinder element 710 and wafer 720 during the grinding process. For example, in one embodiment, the grinding process begins at a rotational velocity of about 40 rpm and is ramped over a smooth velocity curve to a velocity of over 700 rpm.
  • Of course, it should be recognized by those skilled in the art that varying the relative rotational velocities between grinder element [0055] 710 and wafer 720 may be performed during one grind step and not performed during another. For example, varying the relative rotational velocity between grinder element 710 and wafer 720 may be done during a fine grind step, and not during the coarse grind. Additionally, it should be recognized that causing contact between wafer 720 and grinding element 710 can be accomplished by moving chuck 730 toward grinding element 710, rather than by moving grinding element 710.
  • Returning to FIG. 3A, in some embodiments, transfer device [0056] 314 transfers the wafer from cleaner 322 to a backside polisher 326. For example, this process flow may occur for 200 mm wafers. In this embodiment, the back side is polished and not ground, or both ground and polished.
  • As shown in FIG. 3A, a second grinder [0057] 320 and a second cleaner 324 are provided within module 300. In this manner, two wafers may be simultaneously processed therethrough. Since both grinders 318, 320 have a corresponding cleaner 322, 324, wafer processing times are consistent even if two wafers are being ground simultaneously on grinders 318, 320. In one embodiment, grinders 318 and 320 are used to grind opposite sides of the same wafer. In this case, one side of the wafer is ground on grinder 318 and the other side of the same wafer is ground on grinder 320. As with grinder 318, wafers may be ground on grinder 320 and then cleaned on grinder 320 before removal, or cleaned in cleaner 324.
  • Once the wafers have been ground, a second transfer device [0058] 336, again a robot in one embodiment, operates to transfer the wafer to an etcher 330. Etcher 330 operates to remove material from the wafer, preferably a portion on both primary sides of the wafer. The etching process is designed to remove stresses within the silicon crystal caused by the grinding process. Such an operation, in one embodiment, removes ten (10) microns or less of total wafer thickness. In this manner, etcher 330 operates to remove less wafer material than in prior art etch processes. Further, the present invention requires less etchant solution, and hence poses fewer environmental problems related to disposal of the acids or other etchants.
  • Wafer metrology is then tested at a metrology station [0059] 328. In one embodiment wafer metrology is tested subsequent to grinding on grinder 318, and prior to the etching within etcher 330. Alternatively, wafer metrology is tested subsequent to etching in etcher 330. In still another embodiment, wafer metrology is tested both prior to and subsequent to the etching process. Evaluation of wafer metrology involves the testing of wafer flatness and other wafer characteristics to ensure the wafer conforms to the desired specifications. If the wafer does not meet specifications, the wafer is placed in a recycle area 342, which in one embodiment comprises a FOUP 342 (not shown in FIG. 3A). Wafers with acceptable specifications are placed in an out portal or FOUP 340 for removal from first module 300.
  • As shown and described in conjunction with FIG. 3A, first module [0060] 300 provides an enclosed clean room environment in which a series of process steps are performed. Wafers are processed in series through first module 300. Hence, each wafer has generally uniform or uniform process time through the module as well as generally uniform or uniform delay times between process steps. Further, by immediately cleaning and etching the wafer after grinding, the formation of haze and light point defects (LPD) within the wafer are reduced. Such a module configuration is an improvement over the prior art in which wafers are typically processed during the lapping step in batch mode. As a result, some wafers will wait longer before the cleaning or etching steps than others within the same batch. As a result, haze and other wafer defects vary from wafer to wafer, even between wafers within the same batch. Such a shortcoming of the prior art can make it difficult if not impossible to isolate problems within the wafer process flow in the event defective wafers are discovered.
  • An additional benefit of first module [0061] 300 is its compact size. In one embodiment, module 300 has a width 342 that is about 9 feet 3 inches and a length 344 that is about 12 feet 6 inches. In another embodiment, first module 300 has a footprint ranging between about ninety (90) square feet (sqft) and about one hundred and fifty (150) square feet. It will be appreciated by those skilled in the art that the width and length, and hence the footprint of first module 300, may vary within the scope of the present invention. For example, additional grinders 318, 320 may be added within first module 300 to increase the footprint of module 300. In one embodiment, first module 300 is adapted to process about thirty (30) wafers per hour. In another embodiment, first module 300 is adapted to process between about twenty-nine (29) and about thirty-three (33) 300 mm wafers per hour.
  • FIG. 3B depicts an alternative embodiment of a grind damage cluster module according to the present invention. Again, the grind damage cluster module [0062] 350 may correspond to first module 216 described in conjunction with FIG. 2. Module 350 includes many of the same components as the embodiment depicted in FIG. 3A, and like reference numerals are used to identify like components. Module 350 receives wafers or substrates to be processed at portal 312, identified as a send FOUP 312 in FIG. 3B. Wafers are transferred by transfer device 314, shown as wet robot 314, to a preprocessing station 354. In one embodiment, transfer device 314 travels on a track, groove, raised member or other mechanism which allows transfer device 314 to reach several process stations within module 350.
  • At preprocessing station [0063] 354, a coating is applied to one side of the wafer. In one embodiment, a polymer coating is spun on the wafer to provide exemplary coverage. This coating then is cured using ultraviolet (UV) light to provide a low shrink, rapid cured coating on one side of the wafer. In addition to UV curing, curing of the coating may be accomplished by heating and the like. In a particular embodiment, the coating is applied to a thickness between about five (5) microns and about thirty (30) microns.
  • Once cured, the coating provides a completely or substantially tack free, stress free surface on one side of the wafer. In one embodiment of the present invention, transfer device [0064] 314 transfers the wafer to grinder 318, placing the polymer-coated side down on the grinder 318 platen. In one embodiment, the platen is a porous ceramic chuck which uses a vacuum to hold the wafer in place during grinding. The waves created during wafer slicing are absorbed by the coating and not reflected to the front side of the wafer when held down during the grinding process. After the first wafer side is ground on grinder 318, the wafer is flipped over and the second side is ground. As described in conjunction with FIG. 3A, an in situ clean of the wafer may occur before turning the wafer, or the wafer may be cleaned subsequent to grinding of both sides. Again, the second side grinding may occur on grinder 318 or grinder 320. Grinding of the second side removes the cured polymer, and a portion of the second wafer surface resulting in a generally smooth wafer on both sides, with little to no residual surface waves. Additional details on exemplary grinding methods are discussed in U.S. patent application Ser. No. ______ (Attorney Docket No. 20468-001010), entitled “CLUSTER TOOL SYSTEMS AND METHODS TO ELIMINATE WAFER WAVINESS DURING GRINDING”, the complete disclosure of which is incorporated herein by reference.
  • After grinding on grinder [0065] 318 and/or 320, the wafer is transferred to a combined etch/clean station 352 for wafer etch. Again, wafer etching in station 352 removes a smaller amount of wafer material, and hence requires a smaller amount of etchant solutions, than is typically required by prior art processes.
  • Processing continues through module [0066] 350 ostensibly as described in FIG. 3A. The wafer metrology is tested at metrology station 328. Wafers having desired characteristics are transferred by transfer device 336, shown as a dry robot, to out portals 340, identified as receive FOUPS 340 in FIG. 3B. Wafers having some shortcoming or undesirable parameter are placed in a recycle area 342, shown as a buffer FOUP 342, for appropriate disposal.
  • In one embodiment, module [0067] 350 has a width 342 at its widest point of about one hundred and fourteen (114) inches, and a length at its longest point of about one hundred and forty-five inches (145), with a total footprint of about one hundred and fourteen square feet (114 sqft). As will be appreciated by those skilled in the art, the dimensions and footprint of module 350 may vary within the scope of the present invention.
  • Still another embodiment of a grind damage cluster module according to the present invention is shown in FIG. 3C. FIG. 3C depicts a first module [0068] 360 having similar stations and components as module 350 described in FIG. 3B. However, module 350 is a flow through module, with wafers being received at one end or side of module 350 and exiting an opposite end or side of module 350. Module 360 has FOUPS 312, 342 and 340 grouped together. Such a configuration provides a single entry point into module 360, and hence into clean room environment 310. Transfer devices 314 and 336 again facilitate the movement of wafers from station to station within module 360. As shown in FIGS. 3B and 3C, transfer device 314 travels on mechanism 316, as discussed in conjunction with FIG. 3B . Transfer device 336 operates from a generally fixed position with arms or platens extending therefrom to translate the wafer to the desired processing station. Module 360 further includes station 354 for application of a wafer coating, such as the UV cured polymer coating described above.
  • Turning now to FIG. 4, an exemplary second module comprising an edge profile and edge polishing module will be described. Second module [0069] 400 again includes a clean room environment 410 to facilitate clean operations. Second module 400 has a portal 412 for receiving wafers to be processed. Again, in one embodiment, portal 412 is one or more FOUPs. A robot or other transfer device 414 operates to take a wafer from portal 412 and transfer the wafer to an edge profiler/polisher 418. Edge profiler/polisher 418 may comprise one device, or two separate devices with the first device for profiling and the second device for polishing. Transfer device 414 may travel down a track 416 to permit proper placement of the wafer in the edge profiler/polisher 418.
  • The edge of the wafer is profiled and polished as described in conjunction with FIG. 2. In one embodiment, edge profiling removes about ten (10) microns to about fifty (50) microns of material from the diameter of the wafer, with a resultant diameter tolerance of about +/−0.5μ. After edge profiling and polishing, a transfer device [0070] 420 operates to transfer the wafer to a cleaner 430. Again, transfer device 420 may travel on a track 422 to place the wafer in cleaner 430. Cleaner 430 may comprise a mixture of dilute ammonia, peroxide, and water, or an ammonia peroxide solution and soap, followed by an aqueous clean, and the like.
  • Subsequent to cleaning in cleaner [0071] 430, the wafer is transferred to a metrology station 432 at which wafer metrology is examined. An out-portal 434 is positioned to receive wafers having successfully completed processing through second module 400. In one embodiment, portal 434 is a FOUP which collects wafers meeting desired specifications. Again, rejected wafers are set aside in a separate area or FOUP.
  • Second module [0072] 400 has a compact configuration similar to first module. In one embodiment, second module 400 has a width 450 of about 7 feet 6 inches and a length 460 of about 22 feet 11 inches. In another embodiment, second module 400 has a footprint ranging between about ninety (90) square feet (sqft) and about one hundred and fifty (150) square feet. The module 400 shown in FIG. 4 may be used to carry out process step 222 depicted in FIG. 2. In one embodiment, second module 400 processes about thirty (30) wafers per hour. In another embodiment, second module 400 is adapted to process between about twenty-nine (29) and about thirty-three (33) 300 mm wafers per hour. In still another embodiment, second module 400 processing occurs prior to first module 300 processing. In this manner, edge profile and/or edge polish procedures occur before wafer grinding.
  • FIG. 5A depicts a third module [0073] 500 comprising a double side polisher for use in process step 224 shown in FIG. 2. Module 500 again includes an in-portal 512 which may be one or more FOUPs in one embodiment. Wafers are received in portal 512 and transferred within a clean room environment 510 by a transfer device 514. Transfer device 514, which in one embodiment is a robot, may travel along a track 516 to deliver the wafer to one or more double side polishers (DSP) 518.
  • As shown in FIG. 5A, double side polisher [0074] 518 accommodates three wafers 520 within each polisher. It will be appreciated by those skilled in the art that a greater or fewer number of wafers may be simultaneously polished within DSP 518. Prior art double side polishing (DSP) typically polishes a batch of ten or more wafers at a time in a double side polisher. The polisher initially only contacts the two or three thickest wafers due to their increased height within the DSP machine. Only after the upper layers of the thickest wafers are removed by polishing, are additional wafers polished within the batch. As a result, the batch mode polishing takes longer, and uses more polishing fluids and deionized water than in the present invention.
  • Hence in one preferred embodiment of the present invention, three wafers are polished simultaneously. Subsequent to polishing on polisher [0075] 518, the wafers are transferred via a transfer device 536, traveling on track 538 to a buffer station 522. Thereafter, the wafers are buffed, cleaned and dried. Either prior to or after processing through station 522, or both, wafers are tested at a metrology station 540. For wafers meeting desired specifications, transfer device 536 transfers those wafers to an out-portal 544, again, one or more FOUPs in one embodiment. Wafers which do not meet specifications are placed in a reject FOUP 542.
  • As with prior modules, the third module [0076] 500 has a compact footprint. In one embodiment, module 500 has a width 546 that is about 13 feet 11 inches and a length 548 that is about 15 feet 11 inches. In another embodiment, third module 500 has a footprint ranging between about one hundred (100) square feet (sqft) and about one hundred and eighty (180) square feet. Third module 500 may have a different footprint within the scope of the present invention.
  • In one embodiment, DSP [0077] 518 removes about twelve (12) microns of wafer thickness from both sides combined, at a rate of about 1.25 to 2.0 microns per minute. DSP 518 operates on a twelve (12) minute cycle time per load. Hence, in one embodiment, two DSPs 518 process about thirty (30) wafers per hour. In another embodiment, third module 500 is adapted to process between about twenty-nine (29) and about thirty-three (33) 300 mm wafers per hour. It will be appreciated by those skilled in the art that DSP 518 process times, third module 500 throughput, and other parameters may vary within the scope of the present invention. For example, additional DSPs 518 may be added to increase module 500 throughput. In one embodiment, wafer metrology tested at metrology station 540 is fed back to DSPs 518 to adjust DSP 518 operation as needed to produce desired wafer metrology.
  • FIG. 5B depicts an alternative embodiment of a third module according to the present invention. As shown in FIG. 5B, third module [0078] 550 comprises a double side polisher for use in process step 224 shown in FIG. 2, as well as several other components shown in FIG. 5A. As a result, like components are identified with like reference numerals. Module 550 includes a clean/dry station 552 for wafer cleaning and drying subsequent to wafer polishing in polisher 518. Transfer devices 514 and 536, shown as a wet robot and a dry robot, respectively, operate to transfer wafers within module 550. In one embodiment, transfer device 514 travels on a track, groove, raised feature or the like to reach several processing stations and portals 512, while transfer device 536 operates from a fixed base.
  • While module [0079] 500 in FIG. 5A is a flow through module, with wafers received by module 500 at one side and exiting from an opposite side, module 550 in FIG. 5B groups portals 512 and 544. Again, such a grouping of in and out portals facilitates access to module 550 from a single point or side. In one embodiment, a buffer or reject FOUPS (not shown) also is grouped with portals 512 and 544. Alternatively, one or more of portals 512 and 544 may operate as a reject FOUPS.
  • Third module [0080] 550, in one embodiment, has a compact footprint with a width 546 at the widest point of about one hundred and forty two (142) inches and a length at the longest point of about one hundred and fifty-five inches (155).
  • Turning now to FIG. 6, a fourth module [0081] 600, comprising a finish polish cluster, will be described. Fourth module 600 in one embodiment will be used for process step 226 shown in FIG. 2. As with the prior modules, fourth module 600 defines a clean room environment 610 which has ingress and egress through one or more portals or FOUPs. For example, an in-portal or FOUP 612 receives a plurality of wafers for finish polishing. Wafers are removed from FOUP 612 and transferred by a transfer device 614 along a track 616 to a finish polisher 618. While two finish polishers 618 are depicted in FIG. 6, a larger or smaller number of polishers 618 may be used within the scope of the present invention.
  • Wafers are finish polished for about five (5) to six (6) minutes within finish polisher [0082] 618 in an embodiment. Wafers that have undergone finish polishing are transferred to a single wafer cleaner 630 by a transfer device 636. Again, transfer device 636 in one embodiment comprises a robot that travels along a track 638. After wafer cleaning at cleaner station 630, wafer metrology is again tested at a metrology station 640. In one embodiment, metrology processing within fourth module 600 uses a feedback loop to provide data to finish polishers 618 as a result of wafer metrology testing. In one embodiment, the feedback loop is of sufficiently short duration to permit adjustments to the finish polisher process prior to the polishing of the next wafer after the wafer being tested. Wafers which do not meet specification are placed in a reject FOUP or portal 642 for proper disposal. Wafers meeting specifications will be placed in an out-portal or FOUP 644 for subsequent processing, packaging and shipping.
  • Fourth module [0083] 600, in one embodiment, has a width 650 of about 14 feet 0 inches and a length 660 of about 16 feet 0 inches. In another embodiment, fourth module 600 has a footprint ranging between about one hundred (100) square feet (sqft) and about one hundred and eighty (180) square feet. Again, as with all prior modules, the exact size may vary within the scope of the present invention. In one embodiment, fourth module 600 processes about thirty (30) wafers per hour. In another embodiment, fourth module 600 is adapted to process between about twenty-nine (29) and about thirty-three (33) 300 mm wafers per hour.
  • In one embodiment, the four modules [0084] 300, 400, 500 and 600, or their alternative embodiments, and ancillary equipment take up about 4,000 square feet or less of a production facility. This total footprint is much smaller than required for prior art equipment performing similar processes. As a result, apparatus, systems and methods of the present invention may be incorporated more readily in smaller facilities, or as part of a device fabrication facility in which circuit devices are formed. In this manner, the time and cost of packing and shipping, as well as unpacking and inspecting, are avoided. The costs of packing and shipping can, for example, save on the order of about two (2) percent or more of the total wafer processing costs. Additional details on exemplary in-fab wafer processing methods are discussed in U.S. patent application Ser. No. ______ (Attorney Docket No. 20468-000310), entitled “Cluster Tool Systems and Methods for In Fab Wafer Processing”, the complete disclosure of which is incorporated herein by reference.
  • The invention has now been described in detail for purposes of clarity and understanding. However, it will be appreciated that certain changes and modifications may be practiced within the scope of the appended claims. For example, the modules may have different layouts, dimensions and footprints than as described above. Additionally, transfer devices that have been described as traveling or fixed, may also be fixed or traveling, respectively. [0085]

Claims (23)

    What is claimed is:
  1. 1. A method for fabricating wafers for semiconductor manufacture, the method comprising:
    providing a wafer, the wafer comprising a wafer face and a wafer back;
    coupling the wafer back to a susceptor;
    providing a grinding element, the grinding element comprising a grinding face;
    providing a relative rotation between the wafer and the grinding face, said relative rotation being about a rotational axis at a first rotational velocity;
    applying the grinding face to the wafer face, wherein a portion of the wafer face is removed by grinding action; and
    providing said relative rotation about the rotational axis at a second rotational velocity, wherein the first velocity is different than the second velocity, and wherein the variance between the first and second velocities reduces striations on the face of the wafer.
  2. 2. The method of claim 1, the method further comprising:
    providing said relative rotation about the rotational axis at a third rotational velocity, wherein each of the first velocity, the second velocity and the third velocity are different, and wherein the variance between the first, second, and third velocities further reduces striations on the face of the wafer.
  3. 3. The method of claim 1, wherein the first velocity is between about 40 and about 250 revolutions per minute, and the second velocity is between about 250 and about 450 revolutions per minute.
  4. 4. The method of claim 2, wherein the third velocity is between about 450 and about 700 revolutions per minute.
  5. 5. The method of claim 1, wherein the grinding element is a grinding wheel comprising a diamond abrasive material imbedded in the wheel.
  6. 6. The method of claim 5, wherein the grinding wheel moves about a fixed axis.
  7. 7. The method of claim 5 wherein the grinding wheel revolves in an orbital manner.
  8. 8. The method of claim 2, wherein the variance regenerates the grinding face to expose abrasive material embedded in the grinding wheel.
  9. 9. The method of claim 1, wherein the grinding is performed first at the first velocity and second at the second velocity, wherein the second velocity is greater than the first velocity.
  10. 10. The method of claim 1, wherein the grinding is performed first at the first velocity and second at the second velocity, wherein the second velocity is less than the first velocity.
  11. 11. The method as in claim 1, wherein said relative rotation is provided by rotating said grinding element.
  12. 12. The method as in claim 1, wherein said relative rotation is provided by rotating said grinding element in a first direction and rotating said wafer in a second direction opposite said first direction.
  13. 13. The method as in claim 1, wherein said applying said grinding face to said wafer occurs simultaneously with providing said relative rotation at both said first and second velocities, and a transition from said first velocity to said second velocity.
  14. 14. The method of claim 1, wherein the striations are ten microns or less.
  15. 15. The method of claim 1, the method further comprising:
    polishing the face of the wafer, wherein the polished face of the wafer is substantially free of striations.
  16. 16. A system for fabricating semiconductor substrates, the system comprising:
    a grinding wheel;
    a wafer mounted on a chuck relative to the grinding wheel;
    a microprocessor based controller for controlling a velocity of rotation of the grinding wheel relative to the chuck; and
    a database associated with the microprocessor based controller, wherein the database comprises code executable by the microprocessor to cause the grinding wheel to rotate relative to the chuck at a first velocity and subsequently to rotate relative to the chuck at a second velocity, wherein the first velocity is different than the second velocity, and wherein the variance between the first and second velocities reduces striations on the face of the wafer.
  17. 17. The system of claim 16, wherein the database further comprises code executable by the microprocessor to cause the wafer to move relative to the grinding wheel, wherein the grinding wheel contacts the wafer.
  18. 18. The system of claim 16, wherein the database further comprises code executable by the microprocessor to cause the grinding wheel to rotate relative to the chuck at a third velocity, the second velocity being greater than the first velocity and the third velocity being greater than the second velocity, and wherein the variance between the first, second, and third velocities further reduces striations on the face of the wafer.
  19. 19. The system of claim 18, wherein the first velocity is between about 40 and about 250 revolutions per minute, the second velocity is between about 25 and about 450 revolutions per minute, and the third velocity is between about 450 and about 700 revolutions per minute.
  20. 20. The system of claim 16, wherein the grinding wheel comprises a diamond abrasive material imbedded in the wheel.
  21. 21. The system of claim 16, wherein rotating the grinding wheel relative to the chuck is done at the first velocity and subsequently at the second velocity, the second velocity being greater than the first velocity, wherein the increase in velocity between the first velocity and the second velocity regenerates the face of the grinding wheel.
  22. 22. A method for manufacturing substrates, the method comprising:
    providing an unpolished substrate, the unpolished substrate comprising a back, a face, and an edge;
    placing the unpolished substrate on a rotatable mount, wherein the back is fixed on the rotatable mount;
    moving a grinding element relative to the unpolished substrate, wherein the movement is at a first velocity;
    applying the grinding element to the face of the unpolished substrate as the grinding element moves relative to the unpolished substrate;
    moving the grinding element relative to the unpolished substrate at a second velocity, wherein the second velocity is greater than the first velocity, and wherein the increase in velocity increases the ploughing capability of the grinding element and reduces a presence of striations on the face of the unpolished substrate.
  23. 23. The method of claim 22, wherein moving the unpolished substrate relative to the grinding element at a second velocity comprises a gradual change in velocity from the first velocity to the second velocity.
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US20050181316A1 (en) * 2003-12-31 2005-08-18 Microfabrica Inc. Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
US20060094210A1 (en) * 2003-09-08 2006-05-04 Keiichi Kajiyama Semiconductor wafer processing method and processing apparatus
WO2008083071A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Method of grinding a sapphire substrate
US20080164458A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US20080164578A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US20090020433A1 (en) * 2003-12-31 2009-01-22 Microfabrica Inc. Electrochemical Fabrication Methods for Producing Multilayer Structures Including the use of Diamond Machining in the Planarization of Deposits of Material
US20110045740A1 (en) * 2006-01-30 2011-02-24 Memc Electronic Materials, Inc. Methods and Systems For Adjusting Operation Of A Wafer Grinder Using Feedback from Warp Data
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US20120115398A1 (en) * 2010-11-09 2012-05-10 James Bopp Chemical-mechanical polishing wafer and method of use
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US20060094210A1 (en) * 2003-09-08 2006-05-04 Keiichi Kajiyama Semiconductor wafer processing method and processing apparatus
US20090020433A1 (en) * 2003-12-31 2009-01-22 Microfabrica Inc. Electrochemical Fabrication Methods for Producing Multilayer Structures Including the use of Diamond Machining in the Planarization of Deposits of Material
US8702956B2 (en) 2003-12-31 2014-04-22 Microfabrica Inc. Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
US20050181316A1 (en) * 2003-12-31 2005-08-18 Microfabrica Inc. Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
US20100038253A1 (en) * 2003-12-31 2010-02-18 Microfabrica Inc. Method and Apparatus for Maintaining Parallelism of Layers and/or Achieving Desired Thicknesses of Layers During the Electrochemical Fabrication of Structures
US7588674B2 (en) * 2003-12-31 2009-09-15 Microfabrica Inc. Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
US9714473B2 (en) 2003-12-31 2017-07-25 Microfabrica Inc. Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures
US20110045740A1 (en) * 2006-01-30 2011-02-24 Memc Electronic Materials, Inc. Methods and Systems For Adjusting Operation Of A Wafer Grinder Using Feedback from Warp Data
US8145342B2 (en) * 2006-01-30 2012-03-27 Memc Electronic Materials, Inc. Methods and systems for adjusting operation of a wafer grinder using feedback from warp data
KR101369828B1 (en) 2006-12-28 2014-03-05 생-고뱅 세라믹스 앤드 플라스틱스, 인코포레이티드 A sapphire substrate lot
US20080164458A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
JP2010514580A (en) * 2006-12-28 2010-05-06 サン−ゴバン セラミックス アンド プラスティクス,インコーポレイティド Grinding method of the sapphire substrate
US7956356B2 (en) 2006-12-28 2011-06-07 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US20080166951A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US9464365B2 (en) 2006-12-28 2016-10-11 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrate
US8740670B2 (en) 2006-12-28 2014-06-03 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US8197303B2 (en) 2006-12-28 2012-06-12 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US8455879B2 (en) 2006-12-28 2013-06-04 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
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JP2012178617A (en) * 2006-12-28 2012-09-13 Saint-Gobain Ceramics & Plastics Inc Method of grinding sapphire substrate
US20080164578A1 (en) * 2006-12-28 2008-07-10 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US20120115398A1 (en) * 2010-11-09 2012-05-10 James Bopp Chemical-mechanical polishing wafer and method of use
CN102407483A (en) * 2011-11-14 2012-04-11 大连理工大学 High-efficiency nano-precision reducing method for semiconductor wafer
US20130210321A1 (en) * 2012-02-10 2013-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Modular grinding apparatuses and methods for wafer thinning
US9570311B2 (en) * 2012-02-10 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Modular grinding apparatuses and methods for wafer thinning

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