US20020024384A1 - Common mode feedback bias for low voltage opamps - Google Patents
Common mode feedback bias for low voltage opamps Download PDFInfo
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- US20020024384A1 US20020024384A1 US09/932,376 US93237601A US2002024384A1 US 20020024384 A1 US20020024384 A1 US 20020024384A1 US 93237601 A US93237601 A US 93237601A US 2002024384 A1 US2002024384 A1 US 2002024384A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45695—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedforward means
- H03F3/45699—Measuring at the input circuit of the differential amplifier
- H03F3/45717—Controlling the loading circuit of the differential amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
- H03F3/45641—Measuring at the loading circuit of the differential amplifier
- H03F3/45659—Controlling the loading circuit of the differential amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45408—Indexing scheme relating to differential amplifiers the CMCL comprising a short circuited differential output of a dif amp as an addition circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45418—Indexing scheme relating to differential amplifiers the CMCL comprising a resistor addition circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45431—Indexing scheme relating to differential amplifiers the CMCL output control signal being a current signal
Definitions
- This invention generally relates to electronic systems, and more particularly relates to common mode feedback bias for low voltage opamps.
- FIG. 1 shows a prior art two stage fully differential opamp for low voltage systems.
- Differential pair transistors M 1 and M 2 with active loads transistors M 3 and M 4 form the first stage
- common source amplifier transistors M 5 and M 6 with active load transistors M 11 and M 12 serve as a class-A output stage driving the output terminals OUTP and OUTM. Miller pole-splitting compensation is shown.
- Common mode feedback is applied with differential pair transistors M 7 and M 8 , loaded with current mirror transistor M 9 working into the first stage active load devices M 3 and M 4 .
- the desired level of output common mode voltage is applied at terminal CMDES, and the actual output common mode level is sensed with a pair of matched averaging resistors R 1 and R 2 .
- the common mode feedback drives the observed level to the desired level with the loop gain. Small capacitors C 1 and C 2 bypassing R 1 and R 2 improve the common mode loop phase margin.
- this troublesome behavior is caused by the conflict between two common mode feedback loops, one being the intended one through the differential pair of transistors M 7 and M 8 to accurately control the output level, and the other the path through the overall feedback resistors through the input pair of transistors M 1 and M 2 .
- the high drain resistance of tail source transistor M 13 degenerates the second feedback path, leaving only the intended one to act in the circuit.
- the input voltage is high enough to send transistor M 13 into the ohmic region, its drain resistance falls markedly, increasing the common mode gain through the opamp signal path. Since for a two stage amplifier the common mode gain is positive, this path may take over and latch the opamp state.
- An opamp with common mode feedback bias includes: a first differential pair having first and second inputs; active load devices coupled to the first differential pair; a common mode feedback circuit coupled to the active load devices for controlling the active load devices; a second differential pair having a first input coupled to the first input of the first differential pair and a second input coupled to the second input of the first differential pair; and current drivers having control nodes coupled to the second differential pair and outputs coupled to the active load devices.
- FIG. 1 is a schematic circuit diagram of a prior art two stage fully differential opamp with common mode feedback
- FIG. 2 is a schematic circuit diagram of a prior art two stage fully differential opamp with common mode feedback with guaranteed bias current
- FIG. 3 is a schematic circuit diagram of a preferred embodiment opamp with common mode feedback bias
- FIG. 4 is a graph comparing the common mode feedback loop performance of the circuits of FIGS. 1 and 3.
- FIG. 3 A preferred embodiment opamp with common mode feedback bias is shown in FIG. 3.
- a small scale replica of the input stage is fashioned with transistors M 18 and M 19 , and tail source transistor M 20 . If these devices are scaled versions of the actual input differential pair devices, then transistor M 20 will go into the ohmic region at the same input common mode level that sends transistor M 13 into its ohmic region.
- Transistor M 21 is arranged to have a small bias current flowing through it. It is a long, thin device, and its gate must be biased a little above threshold.
- Load device M 10 of the common mode feedback circuit 20 which should be included to fully balance the loads to common mode feedback amplifier transistors M 7 and M 8 , provides a convenient source of such a voltage. Under normal operation, with enough gate bias being applied to transistors M 18 and M 19 from the input terminals INP and INM, the small bias current from transistor M 21 will not be sufficient to keep transistors M 18 , M 19 and M 20 in their saturation regions, and devices M 22 and M 23 will be below threshold. Thus, they will not contribute noise or otherwise degrade the opamp function.
- FIG. 4 illustrates the effectiveness of the referred embodiment circuit of FIG. 3.
- the common mode output level of the opamps of FIGS. 1 and 3 are plotted against the common mode input terminal level.
- the supply voltage for the opamps is 1.1 volt, and the desired common mode output level is set at 0.6 volt.
Abstract
The opamp with common mode feedback bias includes: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.
Description
- This invention generally relates to electronic systems, and more particularly relates to common mode feedback bias for low voltage opamps.
- FIG. 1 shows a prior art two stage fully differential opamp for low voltage systems. Differential pair transistors M 1 and M2 with active loads transistors M3 and M4 form the first stage, and common source amplifier transistors M5 and M6 with active load transistors M11 and M12 serve as a class-A output stage driving the output terminals OUTP and OUTM. Miller pole-splitting compensation is shown. Common mode feedback is applied with differential pair transistors M7 and M8, loaded with current mirror transistor M9 working into the first stage active load devices M3 and M4. The desired level of output common mode voltage is applied at terminal CMDES, and the actual output common mode level is sensed with a pair of matched averaging resistors R1 and R2. The common mode feedback drives the observed level to the desired level with the loop gain. Small capacitors C1 and C2 bypassing R1 and R2 improve the common mode loop phase margin.
- This topology works fairly well, but it is possible that if the opamp is used in a circuit with overall resistive feedback, the common mode loop can settle in a stable operating point which drives both the output terminals to the positive rail. Suppose that in either an initial startup condition or a transient condition both the input terminals INP and INM are close to the positive rail. This will leave the input stage tail current source transistor M 13 with virtually no drain voltage, reducing its output current to very small levels. This will cause transistors M3 and M4 to lose control of the common mode output level at the output of the first stage, and second stage devices MS and M6 will be below threshold. This lifts the output voltage close to the positive rail. If the feedback around the opamp is resistive, with no other bias source ensuring proper input terminal common mode biasing, then the input terminals will have their high levels latched, and the opamp will be in a stable but virtually useless state.
- In general, this troublesome behavior is caused by the conflict between two common mode feedback loops, one being the intended one through the differential pair of transistors M 7 and M8 to accurately control the output level, and the other the path through the overall feedback resistors through the input pair of transistors M1 and M2. Usually the high drain resistance of tail source transistor M13 degenerates the second feedback path, leaving only the intended one to act in the circuit. But if the input voltage is high enough to send transistor M13 into the ohmic region, its drain resistance falls markedly, increasing the common mode gain through the opamp signal path. Since for a two stage amplifier the common mode gain is positive, this path may take over and latch the opamp state.
- Prior art designs have addressed this problem by including two additional devices M 15 and M16 as shown in FIG. 2. An appropriate bias voltage is applied to terminal BIAS such that in normal operation, with the input terminals at their desired common mode level, transistors M15 and M16 will be held subthreshold by the tail voltage at the sources of transistors M1 and M2. The common mode feedback loop operated normally, and transistors M15 and M16 do not contribute any noise into the opamp. However, if the input levels ever rise toward the positive rail, transistors M15 and M16 will conduct, maintaining bias current to transistors M3 and M4, and ensuring that the common mode loop will not lose control and latch.
- This simple arrangement unfortunately becomes unusable at very low supply voltages. Generally, the lower supply limit for an opamp of this topology will be determined by the supply voltage where tail current transistor M 13 goes into the ohmic region at the prescribed input common mode level. Therefore, operating the opamp at the minimum supply voltage means that there is no value of the BIAS voltage in FIG. 2 which will leave transistors M15 and M16 off, and not degrading performance, yet enabling transistors M15 and M16 to catch the condition that transistor M13 is entering the ohmic region
- An opamp with common mode feedback bias includes: a first differential pair having first and second inputs; active load devices coupled to the first differential pair; a common mode feedback circuit coupled to the active load devices for controlling the active load devices; a second differential pair having a first input coupled to the first input of the first differential pair and a second input coupled to the second input of the first differential pair; and current drivers having control nodes coupled to the second differential pair and outputs coupled to the active load devices.
- In the drawings:
- FIG. 1 is a schematic circuit diagram of a prior art two stage fully differential opamp with common mode feedback;
- FIG. 2 is a schematic circuit diagram of a prior art two stage fully differential opamp with common mode feedback with guaranteed bias current;
- FIG. 3 is a schematic circuit diagram of a preferred embodiment opamp with common mode feedback bias;
- FIG. 4 is a graph comparing the common mode feedback loop performance of the circuits of FIGS. 1 and 3.
- A preferred embodiment opamp with common mode feedback bias is shown in FIG. 3. In this opamp a small scale replica of the input stage is fashioned with transistors M 18 and M19, and tail source transistor M20. If these devices are scaled versions of the actual input differential pair devices, then transistor M20 will go into the ohmic region at the same input common mode level that sends transistor M13 into its ohmic region. Transistor M21 is arranged to have a small bias current flowing through it. It is a long, thin device, and its gate must be biased a little above threshold. Load device M10 of the common
mode feedback circuit 20, which should be included to fully balance the loads to common mode feedback amplifier transistors M7 and M8, provides a convenient source of such a voltage. Under normal operation, with enough gate bias being applied to transistors M18 and M19 from the input terminals INP and INM, the small bias current from transistor M21 will not be sufficient to keep transistors M18, M19 and M20 in their saturation regions, and devices M22 and M23 will be below threshold. Thus, they will not contribute noise or otherwise degrade the opamp function. However, if the opamp input level rises to the point where the tail current available from transistor M20 is markedly reduced, then the voltage at the gates of transistors M22 and M23 will lower, driving current into the load devices M3 and M4, properly biasing them to maintain operation of the common mode feedback loop. - FIG. 4 illustrates the effectiveness of the referred embodiment circuit of FIG. 3. In FIG. 4, the common mode output level of the opamps of FIGS. 1 and 3 are plotted against the common mode input terminal level. The supply voltage for the opamps is 1.1 volt, and the desired common mode output level is set at 0.6 volt.
- As can be clearly seen following the dashed plot line in FIG. 4, without the circuitry of FIG. 3 the common mode feedback loop is disabled with input common mode levels approaching the positive rail. This would result in a self-consistent latched condition as the output common mode drifts up to the supply. The solid line represents the improved behavior of the circuit of FIG. 3, where the common mode loop is in operation irrespective of the input level, precluding a latched condition.
- The extra circuitry of transistors M 18-M23 in FIG. 3 is somewhat more complex than the simple addition of two devices in FIG. 2, but the simple solution of FIG. 2 will not work in low voltage opamps, and the current and area required for the extra six devices is quite small relative to what is generally needed for transistors M1 and M2 in a low noise amplifier.
- While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims (19)
1. A circuit comprising:
a first differential pair having first and second inputs;
active load devices coupled to the first differential pair;
a common mode feedback circuit coupled to the active load devices for controlling the active load devices;
a second differential pair having a first input coupled to the first input of the first differential pair and a second input coupled to the second input of the first differential pair; and
current drivers having control nodes coupled to the second differential pair and outputs coupled to the active load devices.
2. The circuit of claim 1 further comprising:
a first tail current source coupled to the first differential pair; and
a second tail current source coupled to the second differential pair.
3. The circuit of claim 1 further comprising:
a first common source amplifier coupled to a first branch of the first differential pair; and
a second common source amplifier coupled to a second branch of the first differential pair.
4. The circuit of claim 3 further comprising:
a first input of the common mode feedback circuit coupled to the first common source amplifier; and
a second input of the common mode feedback circuit coupled to the second common source amplifier.
5. The circuit of claim 2 further comprising a bias current source coupled to the second differential pair.
6. The circuit of claim 1 wherein the active load devices comprise:
a first transistor coupled to a first branch of the first differential pair; and
a second transistor coupled to a second branch of the first differential pair.
7. The circuit of claim 6 further comprising:
a third transistor having a control node coupled to the first branch of the first differential pair; and
a fourth transistor having a control node coupled to the second branch of the first differential pair.
8. The circuit of claim 7 wherein the common mode feedback circuit comprises:
a third differential pair having first and second input nodes;
a first resistor coupled between the third transistor and the first input node;
a second resistor coupled between the fourth transistor and the first input node; and
a common mode reference voltage node coupled to the second input node.
9. The circuit of claim 8 further comprising:
a first capacitor coupled in parallel with the first resistor; and
a second capacitor coupled in parallel with the second resistor.
10. The circuit of claim 7 further comprising:
a first active load transistor coupled to the third transistor; and
a second active load transistor coupled to the fourth transistor.
11. The circuit of claim 8 further comprising a fifth transistor coupled to a first branch of the third differential pair, a control node of the first transistor is coupled to the first branch of the third differential pair and to a control node of the fifth transistor, a control node of the second transistor is coupled to the control node of the first transistor.
12. A circuit comprising:
a first differential pair having first and second inputs;
active load devices coupled to the first differential pair;
a common mode feedback circuit coupled to the active load devices for controlling the active load devices;
a second differential pair having a first input coupled to the first input of the first differential pair and a second input coupled to the second input of the first differential pair;
current drivers having control nodes coupled to the second differential pair and outputs coupled to the active load devices; and
a class A output stage coupled to the first differential pair and coupled to an input of the common mode feedback circuit.
13. The circuit of claim 12 further comprising:
a first tail current source coupled to the first differential pair; and
a second tail current source coupled to the second differential pair.
14. The circuit of claim 12 further comprising a bias current source coupled to the second differential pair.
15. The circuit of claim 12 wherein the active load devices comprise:
a first transistor coupled to a first branch of the first differential pair; and
a second transistor coupled to a second branch of the first differential pair.
16. The circuit of claim 12 wherein the class A output stage comprises:
a first common source amplifier coupled to a first branch of the first differential pair; and
a second common source amplifier coupled to a second branch of the first differential pair.
17. The circuit of claim 16 wherein the common mode feedback circuit comprises:
a third differential pair having first and second input nodes;
a first resistor coupled between the first common source amplifier and the first input node;
a second resistor coupled between the second common source amplifier and the first input node; and
a common mode reference voltage node coupled to the second input node.
18. The circuit of claim 17 further comprising:
a first capacitor coupled in parallel with the first resistor; and
a second capacitor coupled in parallel with the second resistor.
19. The circuit of claim 17 further comprising:
a first transistor coupled to a first branch of the third differential pair and coupled to a control node of the active load devices;
a second transistor coupled to a second branch of the third differential pair; and
a third transistor coupled to the second differential pair and having a control node coupled to the second branch of the third differential pair.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/932,376 US6388522B1 (en) | 2000-08-23 | 2001-08-17 | Common mode feedback bias for low voltage opamps |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22722700P | 2000-08-23 | 2000-08-23 | |
| US09/932,376 US6388522B1 (en) | 2000-08-23 | 2001-08-17 | Common mode feedback bias for low voltage opamps |
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| Publication Number | Publication Date |
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| US20020024384A1 true US20020024384A1 (en) | 2002-02-28 |
| US6388522B1 US6388522B1 (en) | 2002-05-14 |
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| US09/932,376 Expired - Lifetime US6388522B1 (en) | 2000-08-23 | 2001-08-17 | Common mode feedback bias for low voltage opamps |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060267685A1 (en) * | 2005-05-24 | 2006-11-30 | Texas Instruments Incorporated | Fast settling, low noise, low offset operational amplifier and method |
| US7560987B1 (en) * | 2005-06-07 | 2009-07-14 | Cypress Semiconductor Corporation | Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up |
| ITMI20112100A1 (en) * | 2011-11-18 | 2013-05-19 | St Microelectronics Grenoble 2 | COMPLETELY DIFFERENTIAL OPERATIONAL AMPLIFIER WITH COMMON MODE FEEDBACK CIRCUIT |
| IT202100003350A1 (en) * | 2021-02-15 | 2022-08-15 | St Microelectronics Srl | MULTISTAGE AMPLIFIER CIRCUITS AND PROCEDURES |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538513B2 (en) * | 2000-12-22 | 2003-03-25 | Intersil Americas Inc. | Common mode output current control circuit and method |
| US6977543B2 (en) * | 2003-08-26 | 2005-12-20 | Intel Corporation | Biasing technique using thin and thick oxide transistors |
| US6965268B2 (en) * | 2003-08-26 | 2005-11-15 | Intel Corporation | Common mode feedback circuit for fully differential two-stage operational amplifiers |
| KR100574968B1 (en) * | 2004-02-10 | 2006-04-28 | 삼성전자주식회사 | The OP-Amplifier with offset cancellation circuit |
| US7453319B2 (en) * | 2006-02-13 | 2008-11-18 | Texas Instruments Incorporated | Multi-path common mode feedback for high speed multi-stage amplifiers |
| TWI343702B (en) * | 2007-05-17 | 2011-06-11 | Realtek Semiconductor Corp | Fully differential amplifier |
| US7777531B2 (en) * | 2007-10-30 | 2010-08-17 | Texas Instruments Incorporated | Low power low voltage differential signaling (LVDS) output drivers |
| CN101510762B (en) * | 2009-03-12 | 2011-07-20 | 上海交通大学 | Low power supply voltage whole-differential rail-to-rail amplifying circuit |
| US8427237B2 (en) * | 2010-12-16 | 2013-04-23 | Fujitsu Semiconductor Limited | Common-mode feedback circuit |
| IT1403945B1 (en) * | 2011-02-17 | 2013-11-08 | St Microelectronics Srl | COMPARATOR OF A DIFFERENCE OF ENTRY VOLTAGES WITH AT LEAST ONE THRESHOLD |
| US8319554B1 (en) * | 2011-05-18 | 2012-11-27 | Texas Instruments Incorporated | Amplifier with start-up common mode feedback |
| CN113726298B (en) * | 2021-11-02 | 2022-03-15 | 杭州洪芯微电子科技有限公司 | Fully-differential two-stage operational amplifier circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797631A (en) * | 1987-11-24 | 1989-01-10 | Texas Instruments Incorporated | Folded cascode amplifier with rail-to-rail common-mode range |
| KR100284024B1 (en) * | 1997-07-29 | 2001-03-02 | 윤종용 | Low Voltage Seamos Op Amp Circuit and Sample and Hold Circuit With It |
| US6140877A (en) * | 1998-12-11 | 2000-10-31 | Micron Technology, Inc. | Low power supply CMOS differential amplifier topology |
| US6265941B1 (en) * | 1999-11-12 | 2001-07-24 | Agere Systems Guardian Corp. | Balanced differential amplifier having common mode feedback with kick-start |
-
2001
- 2001-08-17 US US09/932,376 patent/US6388522B1/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060267685A1 (en) * | 2005-05-24 | 2006-11-30 | Texas Instruments Incorporated | Fast settling, low noise, low offset operational amplifier and method |
| US7298210B2 (en) * | 2005-05-24 | 2007-11-20 | Texas Instruments Incorporated | Fast settling, low noise, low offset operational amplifier and method |
| US7560987B1 (en) * | 2005-06-07 | 2009-07-14 | Cypress Semiconductor Corporation | Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up |
| ITMI20112100A1 (en) * | 2011-11-18 | 2013-05-19 | St Microelectronics Grenoble 2 | COMPLETELY DIFFERENTIAL OPERATIONAL AMPLIFIER WITH COMMON MODE FEEDBACK CIRCUIT |
| US8854136B2 (en) | 2011-11-18 | 2014-10-07 | Stmicroelectronics (Grenoble 2) Sas | Fully differential operational amplifier with common-mode feedback circuit |
| IT202100003350A1 (en) * | 2021-02-15 | 2022-08-15 | St Microelectronics Srl | MULTISTAGE AMPLIFIER CIRCUITS AND PROCEDURES |
| EP4044431A1 (en) * | 2021-02-15 | 2022-08-17 | STMicroelectronics S.r.l. | Multi-stage amplifier circuits and methods |
| US11716061B2 (en) | 2021-02-15 | 2023-08-01 | Stmicroelectronics S.R.L. | Multi-stage amplifier circuits and methods |
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|---|---|
| US6388522B1 (en) | 2002-05-14 |
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