New! View global litigation for patent families

US20020024083A1 - Dram technology compatible non volatile memory cells - Google Patents

Dram technology compatible non volatile memory cells Download PDF

Info

Publication number
US20020024083A1
US20020024083A1 US09259493 US25949399A US20020024083A1 US 20020024083 A1 US20020024083 A1 US 20020024083A1 US 09259493 US09259493 US 09259493 US 25949399 A US25949399 A US 25949399A US 20020024083 A1 US20020024083 A1 US 20020024083A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
capacitor
memory
plate
non
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09259493
Other versions
US6380581B1 (en )
Inventor
Wendell P. Noble
Eugene H. Cloud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28273Making conductor-insulator-conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10894Multistep manufacturing methods with simultaneous manufacture of periphery and memory cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Abstract

Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor.
The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.

Description

    RELATED APPLICATIONS
  • [0001]
    (This section will be completed as the additional titles are finalized) This application is related to the co-filed and commonly assigned applications, attorney docket number 303.582us1, entitled “Applications for Dram Technology Compatible EEPROM Cells,” by Eugene H. Cloud and Wendell P. Noble, attorney docket number 303.583us1, entitled “Dram Technology Compatible Processor/Memory Chips,” by Leonard Forbes, Eugene H. Cloud, and Wendell P. Noble, and attorney docket number 303.584us1, entitled “ConstructuDram Technology Compatible Non Volatile Memory Cells,” by Wendell P. Noble and Eugene H. Cloud which are hereby incorporated by reference and filed on even day herewith.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates generally to semiconductor integrated circuits and, more particularly, to dynamic random access memory (DRAM) technology compatible non volatile memory cells.
  • BACKGROUND OF THE INVENTION
  • [0003]
    With the increasing array density of successive generations of DRAM chips, the attractiveness of merging other functions onto the DRAM process chip also increases. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to provide added functions such as high speed logic, SRAM or EEPROM becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Thus, there is a need for a means of providing additional functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
  • [0004]
    Among the desired additional functions, incorporating non volatile memory capability into a DRAM process flow is one area for which the differences between the separately optimized technologies is the greatest. Electronically erasable and reprogrammable read only memory (EEPROM) cells represent one form of nonvolatile memory. EEPROM cells can be electrically programmed, erased, and reprogrammed. The typical EEPROM cell consists of a MOSFET with two stacked gates, a floating gate directly over the device channel and a control gate atop and capacitively coupled to it. Since the floating gate is electrically isolated, any charge stored on the floating gate is trapped. Storing sufficient negative charge on the floating gate will suppress the creation of an inversion channel between source and drain of the MOSFET. Thus, the presence or absence of charge on the floating gate represents two distinct data states. Or the level of change represents a plurality of data states.
  • [0005]
    Typically, EEPROM cells are selectively programmed by hot electron injection which places a negative charge on a floating gate during a write. The EEPROM cells are selectively erased by Fowler-Nordheim tunneling which removes the a charge from the floating gate. During a write, a high programming voltage is placed on the control gate. This forces an inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage (6 volts) while the source is grounded (0 volts), increasing the voltage drop between the drain and source. In the presence of the inversion region, the current between the drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the outside barrier and collect on the floating gate.
  • [0006]
    After the write is completed, the negative charge on the floating gate raises the cell's threshold voltage (Vt) above the wordline logic 1 voltage. When a written cell's wordline is brought to a logic 1 during a read, the MOSFET in the EEPROM cell will not turn on. Sense amps detect and amplify the cell current, and output a 0 for a written cell.
  • [0007]
    The floating gate can be erased by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source terminal of the transistor by tunneling through the insulating gate oxide. After the erase is completed, the lack of charge on the floating gate lowers the cell's Vt below the wordline logic 1 voltage. Thus when an erased cell's wordline is brought to a logic 1 during a read, the transistor will turn on and conduct more current than a written cell. Some EEPROM cells use FowlerNordheim tunneling for writes as well as erase.
  • [0008]
    The EEPROM cells can be selectively reprogrammed in the same manner as described above, since the Fowler-Nordheim tunneling process is nondestructive. The programming and erasure voltages which effect Fowler-Nordheim tunneling are higher than the voltages normally used in reading the memory. Thus the FowlerNordheim tunneling effect is negligible at the lower voltages used in reading the memory, allowing a EEPROM cell to maintain its programmed state for years if subjected only to normal read cycles.
  • [0009]
    The programming voltages required for EEPROM operation pose an additional problem to merging EEPROM and DRAM chip technologies. The EEPROM cell includes a capacitor plate which must be fabricated with a large enough area to retain a charge sufficient to withstand the effects of parasitic capacitances and noise due to circuit operation. The increased cell array density found on DRAM chips places significant constraints on the size of the EEPROM capacitor plate. Typically, smaller cell designs necessitate increasing programming voltages in order to retain required capacitance levels. Increasing the programming voltage, however, increases the power dissipation and future generations of EEPROM cells will require lower power dissipation.
  • [0010]
    Modern DRAM technologies are driven by market forces and technology limitations to converge upon a high degree of commonality in basic cell structure. For the DRAM technology generations from 4 Mbit through 1 Gbit, the cell technology has converged into two basic structural alternatives; trench capacitor and stacked capacitor. A method for utilizing a trench DRAM capacitor technology to provide a compatible EEPROM cell has been described in U.S. Pat. No. 5,598,367. A different approach is needed for stacked capacitors however.
  • [0011]
    Thus, there is a need for novel DRAM technology compatible non volatile memory cells. It is desirable that such DRAM technology compatible non volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
  • SUMMARY OF THE INVENTION
  • [0012]
    The above mentioned problems for merging other functions onto the DRAM chip as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention includes a compact non volatile memory cell structure formed using a stacked DRAM capacitor technology.
  • [0013]
    In one embodiment a non volatile memory cell structure is provided. The non volatile memory cell includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor.
  • [0014]
    In another embodiment, an array of non volatile memory cells is provided. The array of non volatile memory cells includes a number of non volatile memory cells. Each non volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. Each non volatile memory cell includes a stacked capacitor which has a bottom plate, a capacitor dielectric, and a top plate. The stacked capacitor is formed in a subsequent layer above the MOSFET and is separated from the MOSFET by an insulator layer. An electrical contact couples the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer. A wordline is coupled to the top plate of the stacked capacitor in the number of non volatile memory cells. A bit line is coupled to a drain region of the MOSFET in the number of non volatile memory cells. And, a sourceline is coupled to a source region of the MOSFET in the number of non volatile memory cells.
  • [0015]
    In another embodiment, a method for forming a non volatile memory cell on a DRAM chip is provided. The method includes forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip. The method includes forming a stacked capacitor above a gate of the MOSFET using a DRAM process. The stacked capacitor is separated from the MOSFET by an insulator layer. An electrical contact is formed using a DRAM process such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer.
  • [0016]
    In another embodiment, a method for operating a memory cell is provided. The method includes controlling a charge placed on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placed on a bottom plate of a stacked capacitor which is coupled to the gate by an electrical contact through an insulator layer. Controlling the charge placed on the gate and on the bottom plate regulates a threshold voltage (Vt) for the memory cell.
  • [0017]
    These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0018]
    [0018]FIG. 1A is a perspective view, illustrating one embodiment of a non volatile memory cell according to the teachings of the present invention.
  • [0019]
    [0019]FIG. 1B, illustrates an alternative embodiment of the DRAM capacitor shown in FIG. 1A.
  • [0020]
    [0020]FIG. 1C, illustrates another alternative embodiment of the DRAM capacitor shown in FIG. 1A.
  • [0021]
    [0021]FIG. 2 is a perspective view illustrating a non volatile memory array according to the teachings of the present invention.
  • [0022]
    [0022]FIG. 3 is a block diagram illustrating an electronic system according to the teachings of the present invention.
  • [0023]
    [0023]FIG. 4 illustrates, in flow diagram form, a method for forming a non volatile memory cell on a DRAM chip according to the teachings of the present invention.
  • [0024]
    [0024]FIG. 5 illustrates, in flow diagram form, a method for forming a non volatile memory array on a DRAM chip.
  • [0025]
    [0025]FIG. 6 illustrates, flow diagram form, a method for operating a memory device according to the teachings of the present invention.
  • [0026]
    [0026]FIG. 7 illustrates, in flow diagram form, a method for programming a memory device according to the teachings of the present invention.
  • [0027]
    [0027]FIG. 8 illustrates, in flow diagram form, another method for programming a memory device according to the teachings of the present invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0028]
    In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer, chip, and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer, chip, and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • [0029]
    In particular, an illustrative embodiment of the present invention includes a non volatile memory cell. The non volatile memory cell includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor.
  • [0030]
    In another embodiment of the present invention a non volatile random access memory (NVRAM) is provided. The NVRAM includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate. The NVRAM includes a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET. The stacked capacitor is separated from the MOSFET by an insulator layer. An electrical contact couples a bottom plate of the stacked capacitor to a gate of the MOSFET. In one embodiment, the electrical contact includes a polysilicon plug and the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the stacked capacitor. The dielectric layer is conformal to the bottom plate and the top plate is conformal to the dielectric layer. A portion of the top plate is located within the interior walls of the bottom plate.
  • [0031]
    In another embodiment of the present invention, an EEPROM cell is provided. The EEPROM cell includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. The MOSFET has a gate separated by a gate oxide from a channel region. The channel region couples a first diffused region to a second diffused region. The EEPROM cell includes a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer. An electrical via couples a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET. In one embodiment, the stacked capacitor includes a double sided stacked type capacitor structure having at least one roughened surface. In an alternative embodiment, the stacked capacitor includes a fin type capacitor structure. The gate oxide has a thickness of less than 100 Angstroms (Å). The stacked capacitor includes a top plate separated from the bottom plate of the capacitor by a capacitor dielectric. The bottom plate of the stacked capacitor comprises a floating gate for the EEPROM cell and the top plate comprises a control gate for the EEPROM cell. In one embodiment, a capacitive coupling ratio (C1/C2) of a capacitance between the-control gate and the floating gate (C1) to a capacitance between the floating gate and the channel region (C2) is greater than 1.0. The capacitor dielectric has a thickness of less than 100 Å.
  • [0032]
    In another embodiment, a non volatile memory array is provided. The non volatile memory array includes a number of non volatile memory cells. Each non volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. Each non volatile memory cell includes a stacked capacitor which has a bottom plate, a capacitor dielectric, and a top plate. The stacked capacitor is formed in a subsequent layer above the MOSFET and is separated from the MOSFET by an insulator layer. An electrical contact couples the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer. A wordline is coupled to the top plate of the stacked capacitor in the number of non volatile memory cells. A bit line is coupled to a drain region of the MOSFET in the number of non volatile memory cells. And, a sourceline is coupled to a source region of the MOSFET in the number of non volatile memory cells. The non volatile memory array is formed on a DRAM chip. In one embodiment, the non volatile memory array includes an array of electrically erasable and programmable read only memories (EEPROMs). In an alternative embodiment, the non volatile memory array includes an array of flash memory cells.
  • [0033]
    In another embodiment of the present invention, an electronic system is provided. The electronic system includes a processor and a dynamic random access memory (DRAM) chip. A system bus couples the processor to the DRAM chip. The DRAM chip includes a non volatile memory array. The non volatile memory array includes a number of non volatile memory cells. Each non volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. Each non volatile memory cell includes a stacked capacitor. The stacked capacitor has a bottom plate, a capacitor dielectric, and a top plate. The stacked capacitor is formed in a subsequent layer above the MOSFET and is separated from the MOSFET by an insulator layer. Each non volatile memory cell includes an electrical contact coupling the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer. A wordline is coupled to the top plate of the stacked capacitor in the number of non volatile memory cells. A bit line is coupled to a drain region of the MOSFET in the number of non volatile memory cells. And, a sourceline is coupled to a source region of the MOSFET in the number of non volatile memory cells.
  • [0034]
    In another embodiment of the present invention, a method for forming a non volatile memory cell on a DRAM chip is provided. The method includes forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip. The method includes forming a stacked capacitor above a gate of the MOSFET using a DRAM process. The stacked capacitor is separated from the MOSFET by an insulator layer. An electrical contact is formed using a DRAM process such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer.
  • [0035]
    In another embodiment, a method for forming a non volatile memory array on a DRAM chip is provided. The method includes forming a plurality of metal oxide semiconductor field effect transistors (MOSFETs) in a semiconductor substrate on the DRAM chip. The method includes forming a plurality of stacked capacitors in an insulator layer above a gate for each of the plurality of MOSFETs using a DRAM process technology. A bottom plate for each of the plurality of stacked capacitors is electrically coupled to the gates of each of the plurality of the MOSFETs using a contact plug formed according to a DRAM process technology. The method includes coupling a wordline to the top plate for each of the stacked capacitors in the plurality of stacked capacitors. A bit line is coupled to a drain region for each of the MOSFETs in the plurality of MOSFETs. The method further includes coupling a sourceline a source region for each of the MOSFETs in the plurality of MOSFETs.
  • [0036]
    In another embodiment, a method for operating a memory cell is provided. The method includes controlling a charge placed on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placed on a bottom plate of a stacked capacitor which is coupled to the gate by an electrical contact through an insulator layer. Controlling the charge placed on the gate and on the bottom plate regulates a threshold voltage (Vt) for the memory cell.
  • [0037]
    In another embodiment of the present invention, a method for operating a memory device is provided. The method includes placing a charge on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placing a charge on a bottom plate of a stacked capacitor. The stacked capacitor is separated from the MOSFET by an insulator layer and an electrical contact couples the bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer. The method includes applying a potential to a top plate of the stacked capacitor. The method further includes detecting a current flow between a first diffused region and a second diffused region in the MOSFET.
  • [0038]
    In another embodiment of the present invention, a method for programming a memory device is provided. The method includes grounding a source region for a metal oxide semiconductor field effect transistor (MOSFET). A control gate voltage is applied to a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET. The stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate. The bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET. The method further includes applying a drain voltage of approximately half the control gate voltage to a drain region of the MOSFET such that an electrical charge is placed on the gate of the MOSFET and the bottom plate of the stacked capacitor.
  • [0039]
    In another embodiment of the present invention, another method for programming a memory device is provided. The method includes applying a voltage potential to a source region for a metal oxide semiconductor field effect transistor (MOSFET). The method includes grounding a top plate of a stacked capacitor formed in an insulator layer which separates the stacked capacitor from the MOSFET. The stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate. The bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET. The method further includes disconnecting a drain region of the MOSFET from a voltage supply such that the method removes an electrical charge from the gate of the MOSFET and removes an electrical charge from the bottom plate of the stacked capacitor.
  • [0040]
    [0040]FIG. 1A is a perspective view, illustrating one embodiment of a non volatile memory cell 100, a non volatile random access memory (NVRAM) 100, an electrically erasable and programmable read only memory cell (EEPKOM) 100, or FLASH memory cell, according to the teachings of the present invention. The non volatile memory cell structure 100 includes a MOSFET 110 and a capacitor 120 fabricated using conventional DRAM process steps. In one embodiment, the MOSFET 110 includes an n-channel metal oxide semiconductor (NMOS) transistor 110 formed in a semiconducting substrate 111. The MOSFET 110 includes a gate 112 separated by a gate oxide 113 from a channel region 114 of the MOSFET 110. In one embodiment, the gate oxide 113 has a thickness of less than 100 Angstroms (Å) and acts as a tunneling oxide. Gate 112 includes a polysilicon gate 112, a polycide gate 112, salicded gate structure, or other conductive gate material as known to one of ordinary skill in the art of DRAM transistor fabrication. The channel region 114 couples a first diffused region 115 to a second diffused region 116. The DRAM transistor is formed according to a conventional, DRAM optimized process flow, as is known to those of ordinary skill in the art of DRAM chip fabrication.
  • [0041]
    As shown in FIG. 1A, the capacitor 120 is formed in a subsequent layer above the MOSFET 110. The capacitor 120 is separated from the transistor by an insulator layer 132. Capacitor 120 includes a bottom plate 121 and a top plate 123 which is separated from the bottom plate 121 by a dielectric layer or a control gate insulator, or capacitor dielectric 122. The bottom plate 121 serves as a storage node 121 and the top plate serves as a plate capacitor 123 for the capacitor 120. The bottom plate 121 comprises a floating gate 121 for the non volatile memory cell 100 which is connected through 130 to gate 112. Entire stack 121, 130 and 112 is a floating gate. The top plate 123 comprises a control gate 123 for the non volatile memory cell 100. In one embodiment, shown in FIG. 1A, capacitor 120 includes a stacked capacitor which is cup shaped 120. The bottom plate 121 has interior walls 121A and exterior walls 121B. The capacitor dielectric 122 is conformal to the interior walls 121A and the exterior walls 121B of the bottom plate 121. The top plate 123 is conformal to the capacitor dielectric 122. A portion of the top plate 123 is located within and opposes the interior walls 121A of the bottom plate 121, separated therefrom by the capacitor dielectric 122. A portion of the top plate 123 is locate outside of and opposes the exterior walls 121B of the bottom plate 121, separated therefrom by the capacitor dielectric 122. In one embodiment, the capacitor dielectric has a thickness of less than 100 Angstroms (Å).
  • [0042]
    In an alternative embodiment, shown in FIG. 1 B, the capacitor includes a fin type stacked capacitor structure 120′. capacitor 120′includes a bottom plate 121′ and a top plate 123′ which is separated from the bottom plate 121′ by a dielectric layer, or capacitor dielectric 122′. The bottom plate 121′ serves as a storage node 121′ and the top plate serves as a plate capacitor 123′ for the capacitor 120′. The bottom plate 121′ has interior walls 121A′ and exterior walls 121B′. The capacitor dielectric 122′ is conformal to the interior walls 121A′ and the exterior walls 121B′ of the bottom plate 121′. The top plate 123′ is conformal to the capacitor dielectric 122′. A portion of the top plate 123′ is located within and opposes the interior walls 121A′ of the bottom plate 121′, separated therefrom by the capacitor dielectric 122′. A portion of the top plate 123′ is locate outside of and opposes the exterior walls 121B′ of the bottom plate 121′, separated therefrom by the capacitor dielectric 122′. In one embodiment, the capacitor dielectric has a thickness of less than 100 Angstroms (Å).
  • [0043]
    In another alternative embodiment, shown in FIG. 1C, the capacitor includes a double sided stacked type capacitor structure having at least one roughened surface 121″. Capacitor 120″ includes a bottom plate 121″ and a top plate 123″ which is separated from the bottom plate 121″ by a dielectric layer, or capacitor dielectric 122″. The bottom plate 121″ serves as a storage node 121″ and the top plate serves as a plate capacitor 123″ for the capacitor 120″. The bottom plate 121″ has interior walls 121A″ and exterior walls 121B″. The capacitor dielectric 122″ is conformal to the interior walls 121A″ and the exterior walls 121B″ of the bottom plate 121″. The top plate 123″ is conformal to the capacitor dielectric 122″. A portion of the top plate 123″ is located within and opposes the interior walls 121A″ of the bottom plate 121″, separated therefrom by the capacitor dielectric 122″. A portion of the top plate 123″ is locate outside of and opposes the exterior walls 121B″ of the bottom plate 121″, separated therefrom by the capacitor dielectric 122″. In one embodiment, the capacitor dielectric has a thickness of less than the equivalent of 100 Angstroms (Å) of SiO2.
  • [0044]
    Other known structures for stacked capacitors are included within the scope of the present invention for comprising capacitor 120. The capacitor 120 is formed according to a conventional, DRAM optimized process flow, as is known to those of ordinary skill in the art of DRAM chip fabrication. In one embodiment, a TEOS layer, or O3-TEOS layer is used to form the insulator layer 132, or interlayer dielectric 132, separating the capacitor 120 from the MOSFET 110. Other insulator layers such as silicon-dioxide (SiO2) or silicon-nitride (Si3N4) may similarly be substituted as the insulator layer 132.
  • [0045]
    As shown in FIG. 1A, an electrical via 130, or electrical contact 130, or plug couples the bottom plate 121, or first plate 121, of the capacitor 120 through the insulator layer 132 to the gate 112 of the MOSFET 110. In one embodiment, the electrical contact 130 includes a polysilicon plug 130. Other electrical contacts 130 of suitable conductivity may similarly be employed to form the electrical contact 130 between the bottom plate 121 and the gate 112 through the insulator layer 132. To form the electrical contact 130 through the insulator layer 132, a photoresist layer, or other suitable mask, is deposited on the insulator layer patterned and exposed to form an opening in the mask above the gate 112 of the MOSFET 110. A DRAM etch process is used to create a contact opening through the insulator layer 132 to the gate 112 of the MOSFET 110. In-one embodiment, the DRAM etch process includes a reactive ion etch (RIE). Other suitable etches may similarly be employed. A first level interconnection to the gate 112 of the MOSFET 110 is made to form the electrical contact 130 through the insulator layer. In one embodiment, the electrical via 130, or electrical contact 130, is formed using an Aluminum (Al) reflow process and Titanium/Titanium-Nitride (Ti/TiN) as a barrier metal to enhance electromigration and stressmigration resistance in contrast to conventional Al deposition. Alternatively, electrical contact is formed using DRAM chemical vapor deposition (CVD) to create a conductive connection between the bottom plate 121 of the capacitor 120 and the gate 112 of the MOSFET 110 through an opening in the insulator layer 132. In this manner, non volatile memory cell 100, shown in FIG. 1A, is formed entirely according to an optimized process flow. Thus, the lengthy process steps associated with conventional non volatile memory cell fabrication is avoided. Also, the non volatile memory cell 100 structure of the present invention is achievable in the high density DRAM fabrication format of 256 Mbit DRAMs and beyond.
  • [0046]
    The non volatile memory cell 100 of the present invention may provide a greater capacitive coupling ratio (C1/C2) than conventional non volatile memory cells. The capacitive coupling ratio (C1/C2) is measured as the ratio between the capacitance of the control gate to the floating gate (C1) and the capacitance of the floating gate to the channel region (C2). The capacitive coupling ratio may also be expressed as the ratio of the capacitance between the control gate to the floating gate (C1) and the capacitance of the floating gate to either the first diffused region or the second diffused region (C2). Conventional non volatile memory cells have a capacitive coupling ratio (C1/C2) in the range from 0.6 to 1.0. However, the inherently high capacitor surface area of the capacitor 120, included as part of the non volatile cell 100 of the present invention, may provide a capacitive coupling ratio (C1/C2) many times this.
  • [0047]
    [0047]FIG. 2 is a perspective view illustrating a non volatile memory array 200 according to the teachings of the present invention. The non volatile memory array 200 includes a number of non volatile memory cells, shown generally as 218A and 218B. Each non volatile memory cell, 200A, 200B etc., includes a metal oxide semiconductor field effect transistor (MOSFET), shown in FIG. 2 as 210A and 210B, formed in a semiconductor substrate 211. Each MOSFET is structured and formed as described above in connection with FIG. 1A. Each non volatile memory cell, 218A, 218B etc., includes a capacitor, shown in FIG. 2 as 220A and 220B which is fabricated using conventional DRAM process steps. Each capacitor is structured and formed as described in detail above in connection with FIGS. 1A, 1B, or IC. As shown in FIG. 2, the capacitors, 220A, 220B, etc., are formed in a subsequent layer above the MOSFETs, 210A, 210B, etc. respectively. The capacitors, 220A, 220B, etc., are separated from the MOSFETs, 210A, 210B, etc., by an insulator layer 232. An electrical contact couples a bottom plate, 221A, 221B, etc., of each capacitor, 220A, 220B, etc., to a gate, 212A, 212B, etc., for each MOSFET, 210A, 210B, etc., located beneath the capacitors, 220A, 220B, etc. In FIG. 2 the electrical contacts are shown as 230A and 230B respectively. The electrical contacts, 230A, 230B, etc., are structured and formed as described above in detail in connection with FIG. 1A. The electrical contacts, 230A, 230B, etc., couple a bottom plate, 221A, 221B, etc., in each capacitor, 220A, 220B, etc., to the gate, 212A, 212B, etc., for each MOSFET, 210A, 210B, etc., through the insulator layer 232. The insulator layer 232 includes an insulator layer 232 as described in detail above in connection with FIG. 1A.
  • [0048]
    A top plate 223, shown as a continuous top plate in FIG. 2, serves as a wordline, and control gate 223, for each of the number of non volatile memory cells, 218A, 218B, etc., in the non volatile memory array 200. A bit line, shown in FIG. 2 as 219A or 219B, couples to a drain region, 216A or 216B, of the MOSFET in the number of non volatile memory, 218A, 218B, etc., in the non volatile memory array 200. In one embodiment, the bit line, 219A or 219B, couples the drain region, 216A or 216B, of the MOSFET in a direction orthogonal to the control gate 223 and couples the drain region, 216A or 216B, to other drain regions for MOSFETs, not shown, in a direction perpendicular to the vertical plane. A sourceline, shown in FIG. 2 as 217A or 217B, couples to a source region, 215A or 21 SB, of the MOSFET in the number of non volatile memory cells, 218A, 218B, etc., in the non volatile memory array 200. In one embodiment, the sourceline, 217A or 217B, couples the source region, 215A or 215B, of the MOSFET in a direction orthogonal to the control gate 223 and couples the source region, 215A or 215B, to other source regions for MOSFETs, not shown, in a direction perpendicular to the vertical. The non volatile memory array 200 may be formed on a DRAM chip 211, or other devices.
  • [0049]
    In one embodiment, the non volatile memory array 200 includes an array of electrically erasable and programmable read only memories (EEPROMs). In an alternative embodiment, the non volatile memory array 200 includes an array of flash memory cells. The inherently high capacitor surface area of the capacitors, 220A, 220B, etc., included as part of the non volatile memory array 200 of the present invention, provides a capacitive coupling ratio superior to that found in convention non volatile memory arrays.
  • [0050]
    [0050]FIG. 3 is a block diagram illustrating an electronic system 300 according to the teachings of the present invention. The electronic system 300 includes a processor 310 and a dynamic random access memory (DRAM) chip 320. A system bus 330 couples the processor 310 to the DRAM chip 320. The system bus 330 includes any system bus 330 suitable for transferring data between the processor 310 and the DRAM chip 320. The DRAM chip 320 includes a non volatile memory array as described in detail in connection with FIG. 2.
  • [0051]
    [0051]FIG. 4 illustrates, in flow diagram form, a method for forming a non volatile memory cell on a DRAM chip according to the teachings of the present invention. The method includes forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip 410. The method includes forming a stacked capacitor above a gate of the MOSFET using a DRAM process such that the stacked capacitor is separated by an insulator layer from the MOSFET 420. The method further includes forming an electrical contact using a DRAM process such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer 430. In one embodiment, forming the electrical contact includes forming a polysilicon plug. In one embodiment, forming a MOSFET in a substrate on the DRAM chip includes forming an n-channel metal oxide semiconductor (NMOS) transistor. In one embodiment, forming a stacked capacitor includes forming a stacked capacitor having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor such that a portion of the top plate is located within the interior walls of the bottom plate. The method of FIG. 4 thus provides a non volatile memory cell with an inherently high capacitor surface area for retaining charge. The novel non volatile memory cell operates at lower programming voltages yet still affords a greater capacitive coupling ratio than conventional non volatile memory cells.
  • [0052]
    [0052]FIG. 5 illustrates, in flow diagram form, a method for forming a non volatile memory array on a DRAM chip. The method includes forming a plurality of metal oxide semiconductor field effect transistors (MOSFETs) in a semiconductor substrate on the DRAM chip 510. The method includes forming a plurality of stacked capacitors in an insulator layer above a gate for each of the plurality of MOSFETs using a DRAM process technology 520. The method includes electrically coupling a bottom plate for each of the plurality of stacked capacitors to the gates of each of the plurality of the MOSFETs using a contact plug formed according to a DRAM process technology 530. A wordline is coupled to and formed by the top plate for each of the stacked capacitors in the plurality of stacked capacitors 540. A bit line is coupled to a drain region for each of the MOSFETs in the plurality of MOSFETs 550. The method further includes coupling a sourceline a source region for each of the MOSFETs in the plurality of MOSFETs 560. In one embodiment, forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors each having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor, and wherein a portion of the top plate is located within the interior walls of the bottom plate.
  • Method of Operation
  • [0053]
    The operation of the novel non volatile memory cells of the present invention is explained in reference to FIG. 2. Programming the novel non volatile memory cells, 218A, 218B, etc., can be achieved through the use of hot electron injection. By this method, the wordline 223 is brought to a high programming voltage, e.g. 2×Vcc. This forces an inversion region to form in the channel regions, shown in FIG. 2 as 214A and 214B, of unprogrammed cells. A voltage of approximately half the wordline 223 voltage is placed on the bit line, 219A and/or 219B which are coupled to drain regions, 216A and/or 216B, of the MOSFETs in the number of non volatile memory cells, 218A, 218B, etc., of the non volatile memory array 200. The sourcelines, shown in FIG. 2 as 217A and 217B, which are coupled to the source regions, 215A and 215B, of the MOSFETs in the non volatile memory array 200 are held at ground. This increases the voltage drop between the source regions, 215A and 215B, and the drain regions, 216A and 216B, for the number of non volatile memory cells, 218A, 218B, etc., in the non volatile memory array 200. In the presence of the inversion region, the current between the source regions, 215A and 215B, and the drain regions, 216A and 216B, respectively increases. The resulting high electron flow from the source regions, 215A and 215B, and the drain regions, 216A and 216B, increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the gate oxides, 213A and 213B respectively, collect on the gates, 212A and 212B. The gates, 212A and 212B, are coupled by the electrical contacts, 230A and 230B respectively, to the bottom plates, 221A and 221B, for the capacitors, 220A and 220B, in each of the number of non volatile memory cells, 218A, 218B, etc., of the non volatile memory array 200. The electrons are thus trapped on the bottom plates, 221A and 221B, for the capacitors, 220A and 220B.
  • [0054]
    After the programming is completed, the negative charge on the gates, 212A and 212B, the electrical contacts, 230A and 230B, and the bottom plates, 221A and 221B, for the capacitors, 220A and 220B, in each of the number of non volatile memory cells, 218A, 218B, etc., of the non volatile memory array 200 raises a threshold voltage (Vt) for each of the number of non volatile memory cells, 218A, 218B, etc., of the non volatile memory array 200 above the wordline 223 logic “1” voltage. When a programmed cell's wordline 223 is brought to a logic “1” during a read, the non volatile memory cells, 218A, 218B, etc., will not turn on. Sense amps, not shown detect and amplify the cell current, and output a 0 for a written, or “programmed” cell.
  • [0055]
    The negative charge on the gates, 212A and 212B, the electrical contacts, 230A and 230B, and the bottom plates, 221A and 221B, for the capacitors, 220A and 220B, can be erased by grounding the wordline/control gate 223 and raising the sourcelines, 217A and 217B, which are coupled to the source regions, 215A and 21 SB, of the MOSFETs in the non volatile memory array 200 to a sufficiently high positive voltage to transfer electrons out of the gates, 212A and 212B, the electrical contacts, 230A and 230B, and the bottom plates, 221A and 221B, for the capacitors, 220A and 220B to the source regions, 215A and 215B, of the MOSFETs by tunneling through the gate oxides, 213A and 213B respectively. After the erase is completed, the lack of charge on the gates, 212A and 212B, the electrical contacts, 230A and 230B, and the bottom plates, 221A and 221B, for the capacitors, 220A and 220B, lowers the threshold voltage (Vt) for each of the number of non volatile memory cells, 218A, 218B, etc., of the non volatile memory array 200 below the wordline 223 logic “1” voltage. Thus when the wordline 223 of an erased non volatile memory cell, 218A, 218B, etc., wordline is brought to a logic “1” during a read, the non volatile memory cell, 218A, 218B, etc., will turn on and conduct more current than a programmed non volatile memory cell, 218A, 218B, etc. Sense amps, not shown, detect and amplify the current conducted through the non volatile memory cell, 218A, 218B, etc, and output a logic “1” for an unprogrammed, or unwritten, cell. In one embodiment, the method of operation for Fowler Nordheim erase functions is reversed and utilized to program the non volatile memory cells, 218A, 218B, etc. As is appreciated by those skilled in the art, the non volatile memory array 200 will be complemented with other logic architectures to attain high random access memory (RAM) read performance.
  • [0056]
    [0056]FIG. 6 illustrates, in flow diagram form, a method for operating a memory device according to the teachings of the present invention. The method includes placing a charge on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placing a charge on a bottom plate of a stacked capacitor where the stacked capacitor is separated from the MOSFET by an insulator layer, and where an electrical contact couples the bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer 610. The method includes applying a potential to a top plate of the stacked capacitor 620. The method further includes detecting a current flow between a first diffused region and a second diffused region in the MOSFET 630.
  • [0057]
    [0057]FIG. 7 illustrates, in flow diagram form a method for programming a memory device according to the teachings of the present invention. The method includes grounding a source region for a metal oxide semiconductor field effect transistor (MOSFET) 710. The method includes applying a control gate voltage to a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET where the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, and where the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET 720. The method further includes applying a drain voltage of approximately half the control gate voltage to a drain region of the MOSFET such that an electrical charge is placed on the gate of the MOSFET and the bottom plate of the stacked capacitor 730.
  • [0058]
    [0058]FIG. 8 illustrates, in flow diagram form, a method for programming a memory device according to the teachings of the present invention. The method includes applying a voltage potential to a source region for a metal oxide semiconductor field effect transistor (MOSFET) 810. The method includes grounding a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET where the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, and where the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET 820. The method further includes disconnecting a drain region of the MOSFET from a voltage supply such that an electrical charge is removed from the gate of the MOSFET and removed from the bottom plate of the stacked capacitor 830.
  • Conclusion
  • [0059]
    Thus, structures and methods for novel DRAM technology compatible non volatile memory cells has been provided. The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable devices which utilize non volatile memory cells.
  • [0060]
    It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (46)

    What is claimed is:
  1. 1. A non volatile memory cell structure, comprising:
    a transistor;
    a capacitor; and
    a vertical electrical via which couples a first plate of the capacitor through an insulator layer to a gate of the transistor.
  2. 2. The non volatile memory cell structure of claim 1, wherein the transistor includes an n-channel metal oxide semiconductor (NMOS) transistor.
  3. 3. The non volatile memory cell structure of claim 1, wherein the transistor includes a transistor formed in a semiconductor substrate including a channel and a first and a second diffused region in the semiconductor substrate, and wherein a gate for the transistor is separated from the channel by a gate oxide.
  4. 4. The non volatile memory cell structure of claim 3, wherein the capacitor includes a stacked capacitor formed in a subsequent layer above the transistor and separated from the transistor by the insulator layer.
  5. 5. The non volatile memory cell structure of claim 4, wherein the first plate of the stacked capacitor is cup shaped and is separated by a dielectric layer from a second plate of the capacitor.
  6. 6. A stacked non volatile random access memory (NVRAM), comprising:
    a metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;
    a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and
    an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET.
  7. 7. The NVRAM of claim 6, wherein the electrical contact includes a polysilicon plug.
  8. 8. The NVRAM of claim 6, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor.
  9. 9. The NVRAM of claim 8, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate.
  10. 10. The NVRAM of claim 8, wherein the bottom plate serves as a storage node, and wherein the top plate serves as a plate conductor for the stacked capacitor.
  11. 11. The NVRAM of claim 6, wherein the NVRAM includes an electrically erasable and programmable read only memory (EEPROM).
  12. 12. The NVRAM of claim 6, wherein the NVRAM includes a flash memory cell.
  13. 13. An EEPROM cell, comprising:
    a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, wherein the MOSFET includes a gate separated by a gate oxide from a channel region, and wherein the channel region couples a first diffused region to a second diffused region;
    a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and
    an electrical via coupling a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET.
  14. 14. The EEPROM cell of claim 13, wherein the stacked capacitor includes a double sided stacked type capacitor structure having at least one roughened surface.
  15. 15. The EEPROM cell of claim 13, wherein the stacked capacitor includes a fin type capacitor structure.
  16. 16. The EEPROM cell of claim 13, wherein the gate oxide has a thickness of less than the equivalent of 100 Å of SiO2.
  17. 17. The EEPROM cell of claim 13, wherein the stacked capacitor includes a top plate separated from the bottom plate of the capacitor by a capacitor dielectric, and wherein the bottom plate of the stacked capacitor comprises a floating gate for the EEPROM cell, and wherein the top plate comprises a control gate for the EEPROM cell.
  18. 18. The EEPROM cell of claim 17, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) to a capacitance between the floating gate and the channel region (C2) is greater than 1.0.
  19. 19. The EEPROM cell of claim 17, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) to a capacitance between the floating gate and either the first diffused region or the second diffused region (C2) is greater than 1.0.
  20. 20. The EEPROM cell of claim 17, wherein the capacitor dielectric has a thickness of less than the equivalent of 100 Å of SiO2.
  21. 21. A non volatile memory array, comprising:
    a number of non volatile memory cells wherein each non volatile memory cell includes:
    a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
    a stacked capacitor having a bottom plate, a capacitor dielectric, and a top plate, wherein the stacked capacitor is formed in a subsequent layer above the MOSFET, and wherein the stacked capacitor is separated from the MOSFET by an insulator layer; and
    an electrical contact coupling the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer;
    a wordline coupled to the top plate of the stacked capacitor in the number of non volatile memory cells;
    a bit line coupled to a drain region of the MOSFET in the number of non volatile memory cells; and
    a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells.
  22. 22. The non volatile memory array of claim 21, wherein the non volatile memory array is formed on a DRAM chip.
  23. 23. The non volatile memory array of claim 21, wherein the electrical contact includes a polysilicon plug.
  24. 24. The non volatile memory array of claim 21, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls.
  25. 25. The non volatile memory array of claim 24, wherein the capacitor dielectric is conformal to the bottom plate, and wherein the top plate is conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.
  26. 26. The non volatile memory array of claim 21, wherein the gate of the MOSFET serves as a floating gate, and wherein the top plate of the stacked capacitor serves as a control gate in the number of non volatile memory cells.
  27. 27. The non volatile memory array of claim 21, wherein the array of non volatile memory cells includes an array of electrically erasable and programmable read only memories (EEPROMs).
  28. 28. The non volatile memory array of claim 21, wherein the array of non volatile memory cells includes an array of flash memory cells.
  29. 29. An electronic system, comprising:
    a processor;
    a dynamic random access memory (DRAM) chip; and
    a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a non volatile memory array, and wherein the non volatile memory array includes:
    a number of non volatile memory cells wherein each non volatile memory cell includes:
    a MOSFET formed in a semiconductor substrate;
    a stacked capacitor, wherein the stacked capacitor is separated from the MOSFET by an insulator layer; and
    an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer;
    a wordline coupled to a top plate of the stacked capacitor in the number of non volatile memory cells;
    a bit line coupled to a drain region of the MOSFET in the number of non volatile memory cells; and
    a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells.
  30. 30. The electronic system of claim 29, wherein the electrical contact includes a polysilicon plug.
  31. 31. The electronic system of claim 29, wherein the stacked capacitor includes a double sided stacked type capacitor structure having at least one roughened surface.
  32. 32. The electronic system of claim 29, wherein the stacked capacitor includes a fin type capacitor structure.
  33. 33. The electronic system of claim 29, wherein the MOSFET includes a gate oxide which has a thickness of less than the equivalent of 100 Å of SiO2.
  34. 34. The electronic system of claim 29, wherein the top plate of the stacked capacitor serves as a control gate, and wherein a gate for the MOSFET serves as a floating gate for the number of non volatile memory cells.
  35. 35. The electronic system of claim 34, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) to a capacitance between the floating gate and a channel region (C2) of the MOSFET is greater than 1.0 in the number of non volatile memory cells.
  36. 36. A method for forming a non volatile memory cell on a DRAM chip, comprising:
    forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip;
    forming a stacked capacitor above a gate of the MOSFET using a DRAM process, wherein the stacked capacitor is separated by an insulator layer from the MOSFET; and
    forming an electrical contact using a DRAM process such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer.
  37. 37. The method of claim 36, wherein forming an electrical contact includes forming a polysilicon plug.
  38. 38. The method of claim 36, wherein forming a MOSFET includes forming an n-channel metal oxide semiconductor (NMOS) transistor.
  39. 39. The method of claim 36, wherein forming a stacked capacitor includes forming a stacked capacitor having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor, and wherein a portion of the top plate is located-within the interior walls of the bottom plate.
  40. 40. A method for forming a non volatile memory array on a DRAM chip, comprising:
    forming a plurality of metal oxide semiconductor field effect transistors (MOSFETs) in a semiconductor substrate on the DRAM chip;
    forming a plurality of stacked capacitors in an insulator layer above a gate for each of the plurality of MOSFETs using a DRAM process technology;
    electrically coupling a bottom plate for each of the plurality of stacked capacitors to the gates of each of the plurality of the MOSFETs using a contact plug formed according to a DRAM process technology;
    coupling a wordline to the top plate for each of the stacked capacitors in the plurality of stacked capacitors;
    coupling a bit line to a drain region for each of the MOSFETs in the plurality of MOSFETs; and
    coupling a sourceline a source region for each of the MOSFETs in the plurality of MOSFETs.
  41. 41. The method of claim 40, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors each having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor, and wherein a portion of the top plate is located within the interior walls of the bottom plate.
  42. 42. A method for operating a memory cell, comprising:
    controlling a charge placed on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placed on a bottom plate of a stacked capacitor which is coupled to the gate by an electrical contact through an insulator; and
    wherein controlling the charge placed on the gate and dn the bottom plate regulates a threshold voltage (Vt) for the memory cell.
  43. 43. The method of claim 42, wherein the method further includes:
    applying a potential to a top plate of the stacked capacitor; and
    detecting a current flow between a first diffused region and a second diffused region in the MOSFET.
  44. 44. A method for operating a memory device, comprising:
    placing a charge on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placing a charge on a bottom plate of a stacked capacitor, wherein the stacked capacitor is separated from the MOSFET by an insulator layer, and wherein an electrical contact couples the bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer;
    applying a potential to a top plate of the stacked capacitor; and
    detecting a current flow between a first diffused region and a second diffused region in the MOSFET.
  45. 45. A method for programming a memory device, comprising:
    grounding a source region for a metal oxide semiconductor field effect transistor (MOSFET);
    applying a control gate voltage to a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET, wherein the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, and wherein the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET;
    applying a drain voltage of approximately half the control gate voltage to a drain region of the MOSFET; and
    wherein an electrical charge is placed on the gate of the MOSFET and the bottom plate of the stacked capacitor.
  46. 46. A method for programming a memory device, comprising:
    applying a voltage potential to a source region for a metal oxide semiconductor field effect transistor (MOSFET);
    grounding a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET, wherein the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, and wherein the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET;
    disconnecting a drain region of the MOSFET from a voltage supply; and
    wherein an electrical charge is removed from the gate of the MOSFET and removed from the bottom plate of the stacked capacitor.
US09259493 1999-02-26 1999-02-26 DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors Active US6380581B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09259493 US6380581B1 (en) 1999-02-26 1999-02-26 DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09259493 US6380581B1 (en) 1999-02-26 1999-02-26 DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors

Publications (2)

Publication Number Publication Date
US20020024083A1 true true US20020024083A1 (en) 2002-02-28
US6380581B1 US6380581B1 (en) 2002-04-30

Family

ID=22985189

Family Applications (1)

Application Number Title Priority Date Filing Date
US09259493 Active US6380581B1 (en) 1999-02-26 1999-02-26 DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors

Country Status (1)

Country Link
US (1) US6380581B1 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436762B1 (en) * 2001-05-14 2002-08-20 Taiwan Semiconductor Manufactoring Company Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins
US20040129999A1 (en) * 2002-12-30 2004-07-08 Jung Kyung Yun Semiconductor device and method of manufacturing the same
US20040160830A1 (en) * 2001-08-30 2004-08-19 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US20050026349A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US20050024945A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
US20050023603A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20050169054A1 (en) * 2001-08-30 2005-08-04 Micron Technology, Inc. SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US7084452B2 (en) 2002-12-06 2006-08-01 Samsung Electronics Co., Ltd. Semiconductor device having one-time programmable ROM and method of fabricating the same
US20060231886A1 (en) * 2001-08-30 2006-10-19 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US20060278917A1 (en) * 2001-08-30 2006-12-14 Micron Technology, Inc. Floating gate structures
US20070048953A1 (en) * 2005-08-30 2007-03-01 Micron Technology, Inc. Graded dielectric layers
US20070105313A1 (en) * 2001-08-30 2007-05-10 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
US20090166697A1 (en) * 2007-12-27 2009-07-02 Sung Kun Park Semiconductor Device and Method of Fabricating the Same
KR100989231B1 (en) 2006-10-17 2010-10-20 가부시끼가이샤 도시바 Nonvolatile semiconductor storage apparatus and method for manufacturing the same

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6902975B2 (en) * 2003-10-15 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory technology compatible with 1T-RAM process
US7046549B2 (en) * 2003-12-31 2006-05-16 Solid State System Co., Ltd. Nonvolatile memory structure
US7195970B2 (en) * 2004-03-26 2007-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal capacitors
US9170744B1 (en) 2011-04-06 2015-10-27 P4tents1, LLC Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system
US9176671B1 (en) 2011-04-06 2015-11-03 P4tents1, LLC Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system
US9158546B1 (en) 2011-04-06 2015-10-13 P4tents1, LLC Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory
US9164679B2 (en) 2011-04-06 2015-10-20 Patents1, Llc System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
US7716411B2 (en) 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
US7514740B2 (en) * 2006-07-10 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Logic compatible storage device
US8293602B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Method of fabricating a finFET having cross-hair cells
US8930647B1 (en) 2011-04-06 2015-01-06 P4tents1, LLC Multiple class memory systems
US9417754B2 (en) 2011-08-05 2016-08-16 P4tents1, LLC User interface system, method, and computer program product
US8812744B1 (en) 2013-03-14 2014-08-19 Microsoft Corporation Assigning priorities to data for hybrid drives
US9626126B2 (en) 2013-04-24 2017-04-18 Microsoft Technology Licensing, Llc Power saving mode hybrid drive access management

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051354A (en) 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4766569A (en) 1985-03-04 1988-08-23 Lattice Semiconductor Corporation Programmable logic array
US4761768A (en) 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US5247346A (en) 1988-02-05 1993-09-21 Emanuel Hazani E2 PROM cell array including single charge emitting means per row
US5057448A (en) 1988-02-26 1991-10-15 Hitachi, Ltd. Method of making a semiconductor device having DRAM cells and floating gate memory cells
US5327380B1 (en) 1988-10-31 1999-09-07 Texas Instruments Inc Method and apparatus for inhibiting a predecoder when selecting a redundant row line
JPH0447595A (en) 1990-06-15 1992-02-17 Mitsubishi Electric Corp Nonvolatile semiconductor memory device
JP2623979B2 (en) 1991-01-25 1997-06-25 日本電気株式会社 Dynamic logic circuit
JP2723386B2 (en) 1991-07-02 1998-03-09 シャープ株式会社 Non-volatile random access memory
US5110754A (en) 1991-10-04 1992-05-05 Micron Technology, Inc. Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM
US5331188A (en) 1992-02-25 1994-07-19 International Business Machines Corporation Non-volatile DRAM cell
US5196722A (en) 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
DE4493150T1 (en) 1993-05-11 1995-07-20 Nippon Kokan Kk A nonvolatile memory device, nonvolatile memory cell and method for setting the threshold value of the non-volatile memory cell and each of the plurality transistors
WO1996001499A1 (en) 1994-07-05 1996-01-18 Zycad Corporation A general purpose, non-volatile reprogrammable switch
US5550072A (en) 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
US5498560A (en) * 1994-09-16 1996-03-12 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US5598367A (en) 1995-06-07 1997-01-28 International Business Machines Corporation Trench EPROM
US6015986A (en) * 1995-12-22 2000-01-18 Micron Technology, Inc. Rugged metal electrodes for metal-insulator-metal capacitors
US5595929A (en) 1996-01-16 1997-01-21 Vanguard International Semiconductor Corporation Method for fabricating a dram cell with a cup shaped storage node
KR100192551B1 (en) * 1996-05-16 1999-06-15 구본준 Semiconductor memory device and fabrication method of the same
US5908311A (en) 1996-07-25 1999-06-01 National Semiconductor Corporation Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells
KR100209724B1 (en) * 1996-08-21 1999-07-15 구본준 Flash memory and method of manufacturing the same
US5912840A (en) 1997-08-21 1999-06-15 Micron Technology Memory cell architecture utilizing a transistor having a dual access gate
US5981335A (en) * 1997-11-20 1999-11-09 Vanguard International Semiconductor Corporation Method of making stacked gate memory cell structure

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436762B1 (en) * 2001-05-14 2002-08-20 Taiwan Semiconductor Manufactoring Company Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins
US20070138534A1 (en) * 2001-08-30 2007-06-21 Micron Technology, Inc. Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20040160830A1 (en) * 2001-08-30 2004-08-19 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US20050026349A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US20050024945A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
US20050023603A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20050169054A1 (en) * 2001-08-30 2005-08-04 Micron Technology, Inc. SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US20070178635A1 (en) * 2001-08-30 2007-08-02 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20060231886A1 (en) * 2001-08-30 2006-10-19 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US20070145462A1 (en) * 2001-08-30 2007-06-28 Micron Technology, Inc. Low tunnel barrier insulators
US20060234450A1 (en) * 2001-08-30 2006-10-19 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US20060237768A1 (en) * 2001-08-30 2006-10-26 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US20060278917A1 (en) * 2001-08-30 2006-12-14 Micron Technology, Inc. Floating gate structures
US7166886B2 (en) * 2001-08-30 2007-01-23 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US20070048923A1 (en) * 2001-08-30 2007-03-01 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US20090008697A1 (en) * 2001-08-30 2009-01-08 Micron Technology, Inc. Sram cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US20070105313A1 (en) * 2001-08-30 2007-05-10 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
US7759724B2 (en) 2001-08-30 2010-07-20 Micron Technology, Inc. Memory cells having gate structure with multiple gates and multiple materials between the gates
US20060234435A1 (en) * 2002-12-06 2006-10-19 Samsung Electronics Co., Ltd Semiconductor device having one-time programmable ROM and method of fabricating the same
US7084452B2 (en) 2002-12-06 2006-08-01 Samsung Electronics Co., Ltd. Semiconductor device having one-time programmable ROM and method of fabricating the same
US7422939B2 (en) 2002-12-06 2008-09-09 Samsung Electronics Co., Ltd. Semiconductor device having one-time programmable ROM and method of fabricating the same
US20040129999A1 (en) * 2002-12-30 2004-07-08 Jung Kyung Yun Semiconductor device and method of manufacturing the same
US7649241B2 (en) * 2002-12-30 2010-01-19 Dongbu Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20070048953A1 (en) * 2005-08-30 2007-03-01 Micron Technology, Inc. Graded dielectric layers
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US8951903B2 (en) 2005-08-30 2015-02-10 Micron Technology, Inc. Graded dielectric structures
US9627501B2 (en) 2005-08-30 2017-04-18 Micron Technology, Inc. Graded dielectric structures
KR100989231B1 (en) 2006-10-17 2010-10-20 가부시끼가이샤 도시바 Nonvolatile semiconductor storage apparatus and method for manufacturing the same
US7750387B2 (en) * 2007-12-27 2010-07-06 Dongbu Hitek Co., Ltd. Semiconductor device and method of fabricating the same
US20090166697A1 (en) * 2007-12-27 2009-07-02 Sung Kun Park Semiconductor Device and Method of Fabricating the Same

Also Published As

Publication number Publication date Type
US6380581B1 (en) 2002-04-30 grant

Similar Documents

Publication Publication Date Title
US5989958A (en) Flash memory with microcrystalline silicon carbide film floating gate
US6407424B2 (en) Flash memory with nanocrystalline silicon film floating gate
US5677556A (en) Semiconductor device having inversion inducing gate
US6243293B1 (en) Contacted cell array configuration for erasable and programmable semiconductor memories
US6888750B2 (en) Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US6950340B2 (en) Asymmetric band-gap engineered nonvolatile memory device
US6212103B1 (en) Method for operating flash memory
US5511020A (en) Pseudo-nonvolatile memory incorporating data refresh operation
US6248626B1 (en) Floating back gate electrically erasable programmable read-only memory (EEPROM)
US6388293B1 (en) Nonvolatile memory cell, operating method of the same and nonvolatile memory array
US6556477B2 (en) Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same
US6323085B1 (en) High coupling split-gate transistor and method for its formation
US5943262A (en) Non-volatile memory device and method for operating and fabricating the same
US6214666B1 (en) Method of forming a non-volatile memory device
US6329240B1 (en) Non-volatile memory cell and methods of fabricating and operating same
US6136652A (en) Preventing dielectric thickening over a channel area of a split-gate transistor
US20110286283A1 (en) 3d two-bit-per-cell nand flash memory
US5751037A (en) Non-volatile memory cell having dual gate electrodes
US6282123B1 (en) Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell
US5892709A (en) Single level gate nonvolatile memory device and method for accessing the same
US6310374B1 (en) Nonvolatile semiconductor memory device having extracting electrode
US7120063B1 (en) Flash memory cell and methods for programming and erasing
US6031771A (en) Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements
US8203187B2 (en) 3D memory array arranged for FN tunneling program and erase
US4590504A (en) Nonvolatile MOS memory cell with tunneling element

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NOBLE, WENDELL P.;CLOUD, EUGENE H.;REEL/FRAME:010308/0298;SIGNING DATES FROM 19990420 TO 19991004

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426