US20020022362A1 - Buried ground plane for high performance system modules - Google Patents

Buried ground plane for high performance system modules Download PDF

Info

Publication number
US20020022362A1
US20020022362A1 US09/199,442 US19944298A US2002022362A1 US 20020022362 A1 US20020022362 A1 US 20020022362A1 US 19944298 A US19944298 A US 19944298A US 2002022362 A1 US2002022362 A1 US 2002022362A1
Authority
US
United States
Prior art keywords
substrate
conductor
conductive metal
pores
system module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/199,442
Other versions
US6432724B1 (en
Inventor
Kie Y. Ahn
Leonard Forbes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/199,442 priority Critical patent/US6432724B1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FORBES, LEONARD, AHN, KIE Y.
Priority to US09/515,083 priority patent/US6670703B1/en
Publication of US20020022362A1 publication Critical patent/US20020022362A1/en
Application granted granted Critical
Publication of US6432724B1 publication Critical patent/US6432724B1/en
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor

Definitions

  • the present invention relates generally to semiconductor circuits, and more particularly to substrates having buried ground planes and their method of processing.
  • a system module may consist of two chips, i.e., a logic chip and a memory chip, with one stacked on the other in a structure called Chip-on-Chip (COC) using a micro bump bonding (MBB) technology.
  • COC Chip-on-Chip
  • MBB micro bump bonding
  • the multiple chips mounted on the single substrate in a system module typically include different circuits, i.e., some analog circuits and some digital circuits. This requires a low impedance ground in the system module to suppress digital noise that may appear in the analog circuits of these mixed mode circuits.
  • Digital noise is the side effect of the switching of the logic circuits.
  • High-speed synchronous digital integrated circuits require large switching currents which can induce noise on the power distribution networks and ground busses due to the finite resistance and inductance in these circuits.
  • the noise may consist of voltage spikes appearing at the power supply terminals of the chip with the switching activity. Power supply noise can have a significant effect due to simultaneous switching noise in CMOS integrated circuits. These problems are more severe in mixed-mode circuits and require careful design of the power distribution systems.
  • a silicon substrate with a low impedance built-in ground plane is necessary for the system modules to suppress noise. It is also desirable for a built-in ground plane to be planar with the surface of the substrate to maintain a flat surface on the substrate upon which various chips, active circuits, and passive components (such as decoupling capacitors and termination resistors) can be subsequently mounted.
  • a conventional method for forming buried conductors in a substrate is the use of heavy ion implantation of conducting atoms into the substrate to form the conductor. This approach, however, is not economically viable due to the required high-current, high-energy implanters, and may also cause damage to the overlying substrate.
  • Another conventional method for fabricating a multilevel interconnect is to implant silicon into silicon oxide followed by a selective deposition of tungsten to build a multi-layer structure with low electrical resistivity.
  • This method is suitable only for fabricating a buried conductor in a silicon oxide, and not in a silicon substrate as is required in a system module.
  • the present invention provides a simple and low-cost scheme for producing a buried ground plane in a silicon substrate.
  • the desired conductors are patterned by ordinary lithography on the surface of the silicon substrate in a mesh pattern to leave room for other chips and components to be mounted.
  • a porous structure is produced only in the patterned conductors by depositing silicon nitride windows on the silicon and subjecting the wafer to a chemical anodization process. After the formation of the pores, the pores are then filled with a conductive metal by the use of a selective deposition technique. The filled pores may be subjected to a high-temperature annealing process to convert the deposited conductive metal to a metal silicide.
  • FIG. 1 illustrates a cross-sectional view of a portion of a silicon substrate with buried ground planes
  • FIG. 2 illustrates a top view of a portion of the silicon substrate of FIG. 1 with buried ground planes
  • FIGS. 3A, 3B and 3 C illustrate a cross-sectional view of the wafer of FIG. 2 during intermediate processes in accordance with the method of the present invention
  • FIG. 4 illustrates a cross-sectional view of a processed wafer with buried ground planes according to a first embodiment of the present invention
  • FIG. 5 illustrates a cross-sectional view of a processed wafer according to a second embodiment of the present invention
  • FIGS. 6A and 6B illustrate in flow chart form the steps for forming a buried ground plane in accordance with a first and second method of the present invention.
  • FIG. 7 illustrates in system module in accordance with the present invention.
  • FIGS. 1 - 7 The present invention will be described as set forth in the preferred embodiment illustrated in FIGS. 1 - 7 . Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope of the present invention.
  • wafer and “substrate” are used interchangeably and are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
  • SOI silicon-on-insulator
  • SOS silicon-on-sapphire
  • FIG. 1 A cross-sectional diagram of a portion of a wafer 10 having buried ground planes is illustrated generally in FIG. 1.
  • the term buried as used herein refers both to covered conductors, i.e., under the surface and concealed from view, and to conductors that are formed in the substrate whose top surface is planar with the surface of the substrate.
  • Wafer 10 consists of a first level top conductor 12 and a first level bottom conductor 14 .
  • a silicon interposer 16 is provided between the conductors 12 , 14 .
  • Via holes 20 , 22 are provided through the wafer 10 to provide for interconnection between the top and bottom surfaces of wafer 10 .
  • a layer 26 of insulating material such as silicon dioxide (SiO 2 ) may be provided between top conductor 12 and silicon interposer 16 .
  • a layer of insulating material 28 such as silicon dioxide (SiO 2 ) may be provided between bottom conductor 14 and silicon interposer 16 .
  • Buried ground planes 30 are provided within the silicon interposer 16 . The buried ground planes 30 provide a low-impedance ground connection suitable for suppressing noise produced by digital circuits that may be mounted on silicon interposer 16 .
  • FIG. 2 illustrates a top view of a portion of the silicon substrate 10 of FIG. 1 across the line a-a′. Space 52 is left between conductors 30 for mounting or integrating chips and/or components. Ground planes 30 may be formed in a mesh pattern to allow for areas such as space 52 .
  • the processes for forming buried ground plane conductors in a silicon substrate in accordance with the present invention is as follows.
  • the pattern for the desired conductors, such as conductors 30 of FIG. 2 is printed on the surface of silicon substrate 16 by conventional lithography or any other method for printing a pattern on the surface of substrate 16 as is known in the art.
  • Space 52 may be left between conductors 30 for other chips and components to be mounted.
  • a protective layer 72 such as for example silicon nitride, is deposited to form windows on the surface of the silicon substrate 16 in which only the printed pattern areas for conductors 30 are left exposed.
  • FIG. 3A illustrates a cross-sectional diagram of silicon substrate 16 along line b-b′ in FIG. 2 after the deposition of the silicon nitride windows. The deposition of a layer 72 of silicon nitride covers the surface of substrate 16 , except for the areas where the pattern for conductors 30 has been printed. The preferable thickness for the layer 72 of silicon nitride is approximately 100 nm.
  • the substrate 16 is then subjected to a chemical anodization process, as is well known in the art, to form a porous layer in the areas not covered with the layer 72 of silicon nitirde, i.e., the areas where the pattern for conductors 30 has been printed.
  • Porous silicon may be formed by the anodization of silicon in aqueous solutions of hydroflouric acid. Pores are etched into the silicon during the anodization process. The resulting structure is illustrated in FIG. 3B.
  • the areas of silicon substrate 16 which have been printed with the pattern for conductors 30 contain a porous layer 74 in substrate 16 created by the anodization process. Those portions of the substrate 16 covered with layer 72 of silicon nitride do not have a porous layer. It is well known that under appropriate anodic conditions, silicon can be converted into a highly porous material.
  • the porosity may be controlled in the 30%-85% range, i.e., the pores in the silicon can comprise approximately 30 to 85% of the total volume within the silicon substrate 16 .
  • a porosity of 50% indicates a material in which half of its volume is comprised of pores within the material.
  • a conductor 30 is formed by filling the pores with a conductive metal 76 . Since the conductors 30 usually must be able to withstand subsequent high temperature processing, it is preferable to use refractory metals to form the conductors, such as tungsten (W) or molybdenum (Mo) or their silicides. Refractory metals are difficult to pattern by chemical mechanical polishing or standard photolithographic techniques since they are chemically inert. As such, it is desirable to have a self-aligned process that does not require any patterning of the metal.
  • refractory metals such as tungsten (W) or molybdenum (Mo) or their silicides. Refractory metals are difficult to pattern by chemical mechanical polishing or standard photolithographic techniques since they are chemically inert. As such, it is desirable to have a self-aligned process that does not require any patterning of the metal.
  • tungsten used, the chemical vapor deposition (CVD) may be based on tungsten hexaflouride (WF 6 ).
  • WF 6 tungsten hexaflouride
  • the chemical-vapor-deposited tungsten process using either WF 6 /H 2 or WF 6 /SiH 4 chemistry is well known in the art.
  • the tungsten hexaflouride will react with the areas of the exposed substrate 16 , but not with the areas of substrate 16 covered with layer 72 of silicon nitride.
  • FIG. 3C illustrates the silicon substrate 16 after the conductive metal 76 , such as tungsten or molybdenum, has been deposited as described above.
  • the chemical vapor deposition of the metal fills in the pores in the areas where the conductors 30 have been patterned, but does not react with the layer 72 of silicon nitride.
  • copper may be used as the conductive metal for applications which will not require a subsequent high processing temperature.
  • the copper may be deposited into the pores of the areas where conductors 30 have been patterned by a chemical vapor deposition technique similar to that as described above with respect to the chemical vapor deposition of tungsten or molybdenum.
  • the excess metal and nitride windows may be removed by a chemical mechanical polishing process as is known in the art.
  • an insulation layer 80 formed of silicon dioxide (SiO 2 ), or alternatively, a high-temperature polymer film with a low dielectric constant, such as for example polyimide, may be deposited.
  • the substrate 16 can be further processed to fabricate the conductors 30 with a refractory metal silicide. This may be preferable for applications in which a very high subsequent processing temperature will be required.
  • the substrate 16 may be subjected to a high temperature annealing to convert the metal in the pores to a silicide.
  • Preferable parameters for this annealing process for tungsten are a temperature greater than approximately 900° C. for up to 30 minutes. This annealing step may be combined with other processes at a later stage if desired.
  • the resulting tungsten silicide has a typical resistivity of 18-20 micro-cm-cm, and can be subjected to subsequent high temperature processing. As illustrated in FIG. 5, the nitride window and excess metal in the channel area may be removed by chemical mechanical polishing to provide a flat and smooth surface for subsequent processing.
  • An insulation layer (not shown), formed of silicon dioxide or a hightemperature polymer film such as polyimide, may be deposited over the surface of substrate 16 .
  • FIGS. 6A and 6B A first and second method of processing buried ground planes in accordance with the present invention is illustrated in flow chart form in FIGS. 6A and 6B. Like steps are referred to by like numerals in each method.
  • the pattern for conductors 30 is printed on the surface of the silicon wafer 16 by conventional lithography or any other method as is known in the art.
  • the pattern for conductors 30 may be in a mesh pattern as illustrated in FIG. 2 to allow sufficient space between conductors 30 for other chips and components to be mounted.
  • step 620 a layer of silicon nitride, preferably 100 nm thick, is deposited on the surface of the substrate 16 to form silicon nitride windows.
  • the layer of silicon nitride does not cover the areas where the pattern for conductors 30 has been printed.
  • step 630 the wafer is subjected to a chemical anodization process, as is known in the art, to produce a porous layer in the substrate 16 in the areas where the pattern for conductors 30 has been printed.
  • a conductor is formed by depositing a conductive metal into the pores of the porous layer produced in the substrate.
  • a conductive metal such as tungsten (W) or molybdenum (Mo) are preferable for applications in which the substrate 16 must be able to withstand subsequent high temperature processing.
  • the metal may be deposited using a selective deposition technique as is known in the art.
  • copper may be used as the conducting metal.
  • the copper may be deposited by a chemical vapor deposition as is known in the art.
  • step 650 the excess metal and nitride windows may be removed utilizing a chemical mechanical polishing process as is known in the art or any other method.
  • step 660 an insulation layer 80 , formed of silicon dioxide, or alternatively a high-temperature polymer film with a low dielectric constant, such as polyimide, may be deposited on the surface of the substrate 16 .
  • FIG. 6B A second method for producing a buried ground plane in accordance with the present invention is illustrated in FIG. 6B. Steps 610 , 620 , and 630 are identical to those of FIG. 6A and the description will not be repeated here.
  • the conductor is created by depositing a refractory metal into the pores in step 740 using a selective deposition technique as is known in the art.
  • the substrate 16 is subjected to a high temperature annealing to convert the metal in the pores to a silicide.
  • Preferable parameters for this annealing process for tungsten are a temperature greater than approximately 900° C. for up to 30 minutes.
  • step 760 the nitride window and excess metal in the channel area may be removed by chemical mechanical polishing to provide a flat and smooth surface for subsequent processing.
  • step 770 an insulation layer, formed of silicon dioxide, or alternatively a high-temperature polymer film with a low dielectric constant, such as polyimide, may be deposited on the surface of the substrate 16 .
  • a buried ground plane can be formed in a silicon substrate simply and inexpensively, without damaging the surrounding environment within the substrate.
  • FIG. 7 illustrates a portion of a system module having buried ground planes constructed in accordance with the present invention.
  • a high performance system module may be provided with a silicon interposer, such as substrate 102 , onto which semiconductor chips or active or passive components can be easily mounted.
  • a first chip 104 may be stacked on a second chip 100 using MBB technology as is known in the art to result in a chip-on-chip module.
  • the resulting chip-on-chip module structure may be mounted onto substrate 102 along with additional active or passive components.
  • Substrate 102 may have a plurality of such chip-on-chip module structures and components mounted on its surface.
  • Each of the system modules may consist of at least two chips, some of which may be analog circuits and others digital circuits.
  • Substrate 102 in accordance with the present invention, may be provided with buried low impedance ground conductors 106 to suppress digital noise in the analog circuits of the modules.

Abstract

A method and apparatus for producing buried ground planes in a silicon substrate for use in system modules is disclosed. Conductor patterns are printed on the surface of the silicon substrate. Pores are created in the printed conductor patterns by a chemical anodization process. The pores are then filled with a conductive metal, such as tungsten, molybdenum, or copper by a selective deposition process to produce a low impedance ground buried in the substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates generally to semiconductor circuits, and more particularly to substrates having buried ground planes and their method of processing. [0002]
  • 2. Description of the Related Art [0003]
  • As improved technology is developed, the size of semiconductor components, and correspondingly the size of end-product equipment in which they are used, continues to decrease. This has led to the concept of a “system on a chip.” This concept of a “system on a chip” has been around since the very large scale integration (VLSI) era. As integrated circuit technology enters the ultra large scale integration (ULSI) era, the desire for a “system on a chip” is increasing. [0004]
  • The concept of a system on a chip refers ideally to a computing system in which all the necessary integrated circuits are fabricated on a single wafer or substrate, as compared with today's method of fabricating many chips of different functions, i.e., logic and memory, and connecting them to assemble a system. There are problems, however, with the implementation of a truly high performance system on a chip because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. To overcome some of these problems, a “system module” has been developed. A system module may consist of two chips, i.e., a logic chip and a memory chip, with one stacked on the other in a structure called Chip-on-Chip (COC) using a micro bump bonding (MBB) technology. The resulting dual-chip structure is mounted on a silicon substrate. Additional components and chips may also be mounted on the silicon substrate. [0005]
  • The multiple chips mounted on the single substrate in a system module typically include different circuits, i.e., some analog circuits and some digital circuits. This requires a low impedance ground in the system module to suppress digital noise that may appear in the analog circuits of these mixed mode circuits. Digital noise is the side effect of the switching of the logic circuits. High-speed synchronous digital integrated circuits require large switching currents which can induce noise on the power distribution networks and ground busses due to the finite resistance and inductance in these circuits. The noise may consist of voltage spikes appearing at the power supply terminals of the chip with the switching activity. Power supply noise can have a significant effect due to simultaneous switching noise in CMOS integrated circuits. These problems are more severe in mixed-mode circuits and require careful design of the power distribution systems. [0006]
  • Thus, a silicon substrate with a low impedance built-in ground plane is necessary for the system modules to suppress noise. It is also desirable for a built-in ground plane to be planar with the surface of the substrate to maintain a flat surface on the substrate upon which various chips, active circuits, and passive components (such as decoupling capacitors and termination resistors) can be subsequently mounted. A conventional method for forming buried conductors in a substrate is the use of heavy ion implantation of conducting atoms into the substrate to form the conductor. This approach, however, is not economically viable due to the required high-current, high-energy implanters, and may also cause damage to the overlying substrate. Another conventional method for fabricating a multilevel interconnect is to implant silicon into silicon oxide followed by a selective deposition of tungsten to build a multi-layer structure with low electrical resistivity. This method, however, is suitable only for fabricating a buried conductor in a silicon oxide, and not in a silicon substrate as is required in a system module. [0007]
  • Thus, there exists a need for an apparatus and method for simply and inexpensively fabricating a buried ground plane in a silicon substrate for use in multi-chip system modules. [0008]
    • SUMMARY OF THE INVENTION
  • The present invention provides a simple and low-cost scheme for producing a buried ground plane in a silicon substrate. In accordance with the present invention, the desired conductors are patterned by ordinary lithography on the surface of the silicon substrate in a mesh pattern to leave room for other chips and components to be mounted. A porous structure is produced only in the patterned conductors by depositing silicon nitride windows on the silicon and subjecting the wafer to a chemical anodization process. After the formation of the pores, the pores are then filled with a conductive metal by the use of a selective deposition technique. The filled pores may be subjected to a high-temperature annealing process to convert the deposited conductive metal to a metal silicide.[0009]
  • These and other advantages and features of the invention will become apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a cross-sectional view of a portion of a silicon substrate with buried ground planes; [0011]
  • FIG. 2 illustrates a top view of a portion of the silicon substrate of FIG. 1 with buried ground planes; [0012]
  • FIGS. 3A, 3B and [0013] 3C illustrate a cross-sectional view of the wafer of FIG. 2 during intermediate processes in accordance with the method of the present invention;
  • FIG. 4 illustrates a cross-sectional view of a processed wafer with buried ground planes according to a first embodiment of the present invention; [0014]
  • FIG. 5 illustrates a cross-sectional view of a processed wafer according to a second embodiment of the present invention; [0015]
  • FIGS. 6A and 6B illustrate in flow chart form the steps for forming a buried ground plane in accordance with a first and second method of the present invention; and [0016]
  • FIG. 7 illustrates in system module in accordance with the present invention.[0017]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention will be described as set forth in the preferred embodiment illustrated in FIGS. [0018] 1-7. Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope of the present invention.
  • The terms “wafer” and “substrate” are used interchangeably and are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. [0019]
  • Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. [0020]
  • A cross-sectional diagram of a portion of a [0021] wafer 10 having buried ground planes is illustrated generally in FIG. 1. The term buried as used herein refers both to covered conductors, i.e., under the surface and concealed from view, and to conductors that are formed in the substrate whose top surface is planar with the surface of the substrate. Wafer 10 consists of a first level top conductor 12 and a first level bottom conductor 14. A silicon interposer 16 is provided between the conductors 12, 14. Via holes 20, 22 are provided through the wafer 10 to provide for interconnection between the top and bottom surfaces of wafer 10. A layer 26 of insulating material, such as silicon dioxide (SiO2), may be provided between top conductor 12 and silicon interposer 16. Similarly, a layer of insulating material 28, such as silicon dioxide (SiO2), may be provided between bottom conductor 14 and silicon interposer 16. Buried ground planes 30 are provided within the silicon interposer 16. The buried ground planes 30 provide a low-impedance ground connection suitable for suppressing noise produced by digital circuits that may be mounted on silicon interposer 16.
  • FIG. 2 illustrates a top view of a portion of the [0022] silicon substrate 10 of FIG. 1 across the line a-a′. Space 52 is left between conductors 30 for mounting or integrating chips and/or components. Ground planes 30 may be formed in a mesh pattern to allow for areas such as space 52.
  • The processes for forming buried ground plane conductors in a silicon substrate in accordance with the present invention is as follows. The pattern for the desired conductors, such as [0023] conductors 30 of FIG. 2, is printed on the surface of silicon substrate 16 by conventional lithography or any other method for printing a pattern on the surface of substrate 16 as is known in the art. Space 52 may be left between conductors 30 for other chips and components to be mounted.
  • Once the pattern for [0024] conductors 30 has been printed on the surface of substrate 16, a protective layer 72, such as for example silicon nitride, is deposited to form windows on the surface of the silicon substrate 16 in which only the printed pattern areas for conductors 30 are left exposed. FIG. 3A illustrates a cross-sectional diagram of silicon substrate 16 along line b-b′ in FIG. 2 after the deposition of the silicon nitride windows. The deposition of a layer 72 of silicon nitride covers the surface of substrate 16, except for the areas where the pattern for conductors 30 has been printed. The preferable thickness for the layer 72 of silicon nitride is approximately 100 nm.
  • The [0025] substrate 16 is then subjected to a chemical anodization process, as is well known in the art, to form a porous layer in the areas not covered with the layer 72 of silicon nitirde, i.e., the areas where the pattern for conductors 30 has been printed.
  • Porous silicon may be formed by the anodization of silicon in aqueous solutions of hydroflouric acid. Pores are etched into the silicon during the anodization process. The resulting structure is illustrated in FIG. 3B. The areas of [0026] silicon substrate 16 which have been printed with the pattern for conductors 30 contain a porous layer 74 in substrate 16 created by the anodization process. Those portions of the substrate 16 covered with layer 72 of silicon nitride do not have a porous layer. It is well known that under appropriate anodic conditions, silicon can be converted into a highly porous material. The porosity may be controlled in the 30%-85% range, i.e., the pores in the silicon can comprise approximately 30 to 85% of the total volume within the silicon substrate 16. Thus, a porosity of 50% indicates a material in which half of its volume is comprised of pores within the material.
  • After the formation of the pores in the [0027] substrate 16, a conductor 30 is formed by filling the pores with a conductive metal 76. Since the conductors 30 usually must be able to withstand subsequent high temperature processing, it is preferable to use refractory metals to form the conductors, such as tungsten (W) or molybdenum (Mo) or their silicides. Refractory metals are difficult to pattern by chemical mechanical polishing or standard photolithographic techniques since they are chemically inert. As such, it is desirable to have a self-aligned process that does not require any patterning of the metal. The use of a selective deposition technique, as is known in the art, provides a self aligned process that does not require any patterning of the metal. For example, if tungsten is used, the chemical vapor deposition (CVD) may be based on tungsten hexaflouride (WF6). The chemical-vapor-deposited tungsten process using either WF6/H2or WF6/SiH4 chemistry is well known in the art. The tungsten hexaflouride will react with the areas of the exposed substrate 16, but not with the areas of substrate 16 covered with layer 72 of silicon nitride. This will selectively deposit the tungsten in the porous layers 74 in silicon substrate 16 in the areas where the pattern for conductors 30 are printed but not on the areas covered with the silicon nitride layer 72. Molybdenum can be deposited in a similar fashion as tungsten. The deposition of the conductive metal in the pores creates a low impedance buried conductive plane.
  • FIG. 3C illustrates the [0028] silicon substrate 16 after the conductive metal 76, such as tungsten or molybdenum, has been deposited as described above. The chemical vapor deposition of the metal fills in the pores in the areas where the conductors 30 have been patterned, but does not react with the layer 72 of silicon nitride.
  • As an alternative to the above, copper may be used as the conductive metal for applications which will not require a subsequent high processing temperature. The copper may be deposited into the pores of the areas where [0029] conductors 30 have been patterned by a chemical vapor deposition technique similar to that as described above with respect to the chemical vapor deposition of tungsten or molybdenum.
  • After the deposition of the conducting [0030] metal 76, the excess metal and nitride windows may be removed by a chemical mechanical polishing process as is known in the art. As illustrated in FIG. 4, an insulation layer 80, formed of silicon dioxide (SiO2), or alternatively, a high-temperature polymer film with a low dielectric constant, such as for example polyimide, may be deposited.
  • Alternatively, instead of depositing an insulating [0031] layer 80, the substrate 16 can be further processed to fabricate the conductors 30 with a refractory metal silicide. This may be preferable for applications in which a very high subsequent processing temperature will be required. After the pores have been filled with the refractory metal, the substrate 16 may be subjected to a high temperature annealing to convert the metal in the pores to a silicide. Preferable parameters for this annealing process for tungsten are a temperature greater than approximately 900° C. for up to 30 minutes. This annealing step may be combined with other processes at a later stage if desired. The resulting tungsten silicide has a typical resistivity of 18-20 micro-cm-cm, and can be subjected to subsequent high temperature processing. As illustrated in FIG. 5, the nitride window and excess metal in the channel area may be removed by chemical mechanical polishing to provide a flat and smooth surface for subsequent processing. An insulation layer (not shown), formed of silicon dioxide or a hightemperature polymer film such as polyimide, may be deposited over the surface of substrate 16.
  • A first and second method of processing buried ground planes in accordance with the present invention is illustrated in flow chart form in FIGS. 6A and 6B. Like steps are referred to by like numerals in each method. [0032]
  • In accordance with a first method of the present invention as illustrated in FIG. 6A, in [0033] step 610, the pattern for conductors 30 is printed on the surface of the silicon wafer 16 by conventional lithography or any other method as is known in the art. The pattern for conductors 30 may be in a mesh pattern as illustrated in FIG. 2 to allow sufficient space between conductors 30 for other chips and components to be mounted.
  • In [0034] step 620, a layer of silicon nitride, preferably 100 nm thick, is deposited on the surface of the substrate 16 to form silicon nitride windows. The layer of silicon nitride does not cover the areas where the pattern for conductors 30 has been printed. In step 630, the wafer is subjected to a chemical anodization process, as is known in the art, to produce a porous layer in the substrate 16 in the areas where the pattern for conductors 30 has been printed.
  • In [0035] step 640, a conductor is formed by depositing a conductive metal into the pores of the porous layer produced in the substrate. As noted previously, refractory metals such as tungsten (W) or molybdenum (Mo) are preferable for applications in which the substrate 16 must be able to withstand subsequent high temperature processing. The metal may be deposited using a selective deposition technique as is known in the art. For applications in which the substrate 16 will not be subjected to subsequent high processing temperatures, copper may be used as the conducting metal. The copper may be deposited by a chemical vapor deposition as is known in the art.
  • In [0036] step 650, the excess metal and nitride windows may be removed utilizing a chemical mechanical polishing process as is known in the art or any other method. In step 660, an insulation layer 80, formed of silicon dioxide, or alternatively a high-temperature polymer film with a low dielectric constant, such as polyimide, may be deposited on the surface of the substrate 16.
  • A second method for producing a buried ground plane in accordance with the present invention is illustrated in FIG. 6B. [0037] Steps 610, 620, and 630 are identical to those of FIG. 6A and the description will not be repeated here. After the pores have been created in the substrate 16 in step 630, the conductor is created by depositing a refractory metal into the pores in step 740 using a selective deposition technique as is known in the art. In step 750, the substrate 16 is subjected to a high temperature annealing to convert the metal in the pores to a silicide. Preferable parameters for this annealing process for tungsten are a temperature greater than approximately 900° C. for up to 30 minutes. This annealing step may be combined with other processes at a later stage if desired. In step 760, the nitride window and excess metal in the channel area may be removed by chemical mechanical polishing to provide a flat and smooth surface for subsequent processing. In step 770, an insulation layer, formed of silicon dioxide, or alternatively a high-temperature polymer film with a low dielectric constant, such as polyimide, may be deposited on the surface of the substrate 16.
  • In accordance with the present invention, a buried ground plane can be formed in a silicon substrate simply and inexpensively, without damaging the surrounding environment within the substrate. [0038]
  • FIG. 7 illustrates a portion of a system module having buried ground planes constructed in accordance with the present invention. A high performance system module may be provided with a silicon interposer, such as [0039] substrate 102, onto which semiconductor chips or active or passive components can be easily mounted. For example, a first chip 104 may be stacked on a second chip 100 using MBB technology as is known in the art to result in a chip-on-chip module. The resulting chip-on-chip module structure may be mounted onto substrate 102 along with additional active or passive components. Substrate 102 may have a plurality of such chip-on-chip module structures and components mounted on its surface. Each of the system modules may consist of at least two chips, some of which may be analog circuits and others digital circuits. Substrate 102, in accordance with the present invention, may be provided with buried low impedance ground conductors 106 to suppress digital noise in the analog circuits of the modules.
  • While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims. [0040]

Claims (95)

What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. A method for fabricating at least one conductor in a silicon substrate comprising:
forming a pattern for said at least one conductor on a surface of said substrate;
creating pores in said substrate in areas where said pattern of said at least one conductor is formed; and
depositing a conducting metal into said pores created in said substrate.
2. The method according to claim 1, wherein the act of creating pores further comprises:
depositing a protective layer on said surface of said substrate on areas where said pattern of said at least one conductor is not formed; and
subjecting said substrate to a chemical anodization process to produce said pores,
wherein said protective layer prevents said pores from being formed in said substrate beneath said protective layer.
3. The method according to claim 2, wherein said protective layer is formed of silicon nitride.
4. The method according to claim 3, wherein said layer of silicon nitride is approximately 100 nm thick.
5. The method according to claim 1, wherein said act of depositing further comprises:
selectively depositing said conductive metal using a selective deposition technique to fill said pores in said substrate.
6. The method according to claim 5, wherein said selective deposition technique is a chemical vapor deposition technique.
7. The method according to claim 5, wherein said conductive metal is copper.
8. The method according to claim 5, wherein said conductive metal is a refractory metal.
9. The method according to claim 8, wherein said refractory metal is molybdenum.
10. The method according to claim 8, wherein said refractory metal is tungsten.
11. The method according to claim 8, further comprising:
subjecting said substrate to a high-temperature annealing process.
12. The method according to claim 11, further comprising:
performing a chemical mechanical polishing process on said substrate after subjecting said substrate to a high-temperature annealing process.
13. The method according to claim 11, wherein said annealing process is performed at a temperature greater than approximately 9000 ° C.
14. The method according to claim 13, further comprising:
performing said annealing process for approximately 30 minutes.
15. The method according to claim 5, further comprising:
removing excess metal from said surface of said substrate after selectively depositing said conductive metal to fill said pores in said substrate.
16. The method according to claim 15, further comprising:
depositing an insulation layer over all of said surface of said substrate after said removing step.
17. The method according to claim 16, wherein said insulation layer is formed of a high temperature polymer film.
18. The method according to claim 17, wherein said high temperature polymer film is a polyimide.
19. The method according to claim 16, wherein said insulation layer is formed of silicon dioxide.
20. A method for fabricating at least one conductor in a semiconductor substrate, said method comprising:
forming a pattern of at least one conductor on a first surface of said substrate;
depositing a protective layer on said first surface of said substrate on areas where said pattern of said at least one conductor is not formed;
chemically anodizing said substrate to create pores in said substrate in areas where said pattern of said at least one conductor is formed; and
depositing a conductive metal in said pores created in said substrate in said areas where said pattern of said at least one conductor is formed to form said at least one conductor in said substrate.
21. The method according to claim 20, further comprising:
forming a pattern of at least one conductor on a second surface of said substrate, said second surface being opposite said first surface;
depositing a protective layer on said second surface of said substrate on areas where said pattern of said at least one conductor is not formed;
chemically anodizing said substrate to create pores in said substrate in areas where said pattern of said at least one conductor is formed; and
depositing a conductive metal in said pores created in said substrate in said areas where said pattern of said at least one conductor is formed to form said at least one conductor in said substrate.
22. The method according to claim 21, wherein said protective layer is formed of silicon nitride.
23. The method according to claim 21, wherein said conductive metal is copper.
24. The method according to claim 21, wherein said conductive metal is molybdenum.
25. The method according to claim 21, wherein said conductive metal is tungsten.
26. The method according to claim 21, further comprising:
subjecting said substrate to a high temperature annealing process.
27. The method according to claim 26, further comprising:
performing a chemical mechanical polishing process on said first and second surface of said substrate after said annealing process.
28. The method according to claim 21, further comprising:
depositing an insulation layer on said first and said second surface of said substrate.
29. A method for forming a system module comprising:
mounting a first chip on a second chip to produce a multi-chip structure;
mounting said multi-chip structure on a surface of a substrate having at least one conductor in said substrate, said at least one conductor being formed in said substrate by:
forming a pattern for said at least one conductor on said surface of said substrate;
creating pores in said substrate in areas where said pattern of said at least one conductor is formed; and
depositing a conducting metal into said pores created in said substrate.
30. The method according to claim 29, wherein the act of creating pores further comprises:
depositing a protective layer on said surface of said substrate on areas where said pattern of said at least one conductor is not formed; and
subjecting said substrate to a chemical anodization process to produce said pores,
wherein said protective layer prevents said pores from being formed in said substrate beneath said protective layer.
31. The method according to claim 30, wherein said protective layer is formed of silicon nitride.
32. The method according to claim 31, wherein said layer of silicon nitride is approximately 100 nm thick.
33. The method according to claim 29, wherein said act of depositing further comprises:
selectively depositing said conductive metal using a selective deposition technique to fill said pores in said substrate.
34. The method according to claim 33, wherein said selective deposition technique is a chemical vapor deposition technique.
35. The method according to claim 33, wherein said conductive metal is copper.
36. The method according to claim 33, wherein said conductive metal is a refractory metal.
37. The method according to claim 36, wherein said refractory metal is molybdenum.
38. The method according to claim 37, wherein said refractory metal is tungsten.
39. The method according to claim 36, further comprising:
subjecting said substrate to a high-temperature annealing process before mounting said multi-chip structure on said surface of said substrate.
40. The method according to claim 39, further comprising:
performing a chemical mechanical polishing process on said substrate after subjecting said substrate to a high-temperature annealing process.
41. The method according to claim 33, further comprising:
removing excess metal from said surface of said substrate after selectively depositing said conductive metal to fill said pores in said substrate.
42. The method according to claim 41, further comprising:
depositing an insulation layer over all of said surface of said substrate after said removing step and before mounting said multi-chip structure on said surface of said substrate.
43. The method according to claim 42, wherein said insulation layer is formed of a high temperature polymer film.
44. The method according to claim 43, wherein said high temperature polymer film is a polyimide.
45. The method according to claim 42, wherein said insulation layer is formed of silicon dioxide.
46. A method for forming a system module comprising:
mounting a first chip on a second chip to produce a multi-chip structure;
mounting said multi-chip structure on a first surface of a substrate having at least one conductor in said first surface and a second surface opposite said first surface, said at least one conductor being formed in said substrate by:
forming a pattern of at least one conductor on said first and second surfaces of said substrate;
depositing a protective layer on said first and second surfaces of said substrate on areas where said pattern of said at least one conductor is not formed;
chemically anodizing said substrate to create pores in said substrate in areas where said pattern of said at least one conductor is formed; and
depositing a conductive metal in said pores created in said substrate in said areas where said pattern of said at least one conductor is formed to form said at least one conductor in said substrate.
47. The method according to claim 46, wherein said protective layer is formed of silicon nitride.
48. The method according to claim 46, wherein said conductive metal is copper.
49. The method according to claim 46, wherein said conductive metal is molybdenum.
50. The method according to claim 46, wherein said conductive metal is tungsten.
51. The method according to claim 46, further comprising:
subjecting said substrate to a high temperature annealing process.
52. The method according to claim 51, further comprising:
performing a chemical mechanical polishing process on said first and second surface of said substrate after said annealing process.
53. The method according to claim 46, further comprising:
depositing an insulation layer on said first and said second surface of said substrate.
54. A substrate comprising:
at least one conductor buried in a surface of said substrate, said at least one conductor comprising a plurality of pores in said substrate filled with a conductive metal.
55. The substrate according to claim 54, wherein said conductive metal is copper.
56. The substrate according to claim 54, wherein said conductive metal is a refractory metal.
57. The substrate according to claim 56, wherein said refractory metal is molybdenum.
58. The substrate according to claim 56, wherein said refractory metal is tungsten.
59. The substrate according to claim 54, wherein said conductive metal is a metal silicide.
60. The substrate according to claim 54, further comprising:
an insulation layer over said surface of said substrate.
61. The substrate according to claim 60, wherein said insulation layer is formed of a high temperature polymer film.
62. The substrate according to claim 61, wherein said high temperature polymer film is a polyimide.
63. The substrate according to claim 60, wherein said insulation layer is formed of silicon dioxide.
64. A substrate comprising:
at least one conductor buried in a first surface and a second surface of said substrate, said second surface being opposite said first surface, said at least one conductor comprising a plurality of pores in said substrate filled with a conductive metal.
65. The substrate according to claim 64, wherein said conductive metal is copper.
66. The substrate according to claim 64, wherein said conductive metal is a refractory metal.
67. The substrate according to claim 66, wherein said refractory metal is molybdenum.
68. The substrate according to claim 66, wherein said refractory metal is tungsten.
69. The substrate according to claim 64, wherein said conductive metal is a metal silicide.
70. The substrate according to claim 64, further comprising:
an insulation layer over said first and said second surface of said substrate.
71. The substrate according to claim 70, wherein said insulation layer is formed of a high temperature polymer film.
72. The substrate according to claim 71, wherein said high temperature polymer film is a polyimide.
73. The substrate according to claim 70, wherein said insulation layer is formed of silicon dioxide.
74. A system module comprising:
a substrate having at least one buried conductor in a surface of said substrate; said at least one conductor comprising a plurality of pores in said substrate filled with a conductive metal;
a first chip mounted on said surface of said substrate; and
a second chip mounted on said first chip.
75. The system module according to claim 74, wherein said conductive metal is copper.
76. The system module according to claim 74, wherein said conductive metal is a refractory metal.
77. The system module according to claim 76, wherein said refractory metal is molybdenum.
78. The system module according to claim 76, wherein said refractory metal is tungsten.
79. The system module according to claim 74, wherein said conductive metal is a metal silicide.
80. The system module according to claim 74, further comprising:
an insulation layer over said surface of said substrate.
81. The system module according to claim 80, wherein said insulation layer is formed of a high temperature polymer film.
82. The system module according to claim 81, wherein said high temperature polymer film is a polyimide.
83. The system module according to claim 80, wherein said insulation layer is formed of silicon dioxide.
84. The system module according to claim 74, wherein one of said first and second chip includes analog circuits and the other of said first and second chip includes digital circuits.
85. A system module comprising:
a substrate having at least one buried conductor in a first and second surface of said substrate, said second surface being opposite said first surface, said at least one conductor comprising a plurality of pores in said substrate filled with a conductive metal;
a first chip mounted on said surface of said substrate; and
a second chip mounted on said first chip.
86. The system module according to claim 85, wherein said conductive metal is copper.
87. The system module according to claim 85, wherein said conductive metal is a refractory metal.
88. The system module according to claim 87, wherein said refractory metal is molybdenum.
89. The system module according to claim 87, wherein said refractory metal is tungsten.
90. The system module according to claim 85, wherein said conductive metal is a metal silicide.
91. The system module according to claim 85, further comprising:
an insulation layer over said first and said second surface of said substrate.
92. The system module according to claim 91, wherein said insulation layer is formed of a high temperature polymer film.
93. The system module according to claim 92, wherein said high temperature polymer film is a polyimide.
94. The system module according to claim 91, wherein said insulation layer is formed of silicon dioxide.
95. The system module according to claim 85, wherein one of said first and second chip includes analog circuits and the other of said first and second chip includes digital circuits.
US09/199,442 1998-11-25 1998-11-25 Buried ground plane for high performance system modules Expired - Fee Related US6432724B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/199,442 US6432724B1 (en) 1998-11-25 1998-11-25 Buried ground plane for high performance system modules
US09/515,083 US6670703B1 (en) 1998-11-25 2000-02-28 Buried ground plane for high performance system modules

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/199,442 US6432724B1 (en) 1998-11-25 1998-11-25 Buried ground plane for high performance system modules

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/515,083 Division US6670703B1 (en) 1998-11-25 2000-02-28 Buried ground plane for high performance system modules

Publications (2)

Publication Number Publication Date
US20020022362A1 true US20020022362A1 (en) 2002-02-21
US6432724B1 US6432724B1 (en) 2002-08-13

Family

ID=22737520

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/199,442 Expired - Fee Related US6432724B1 (en) 1998-11-25 1998-11-25 Buried ground plane for high performance system modules
US09/515,083 Expired - Fee Related US6670703B1 (en) 1998-11-25 2000-02-28 Buried ground plane for high performance system modules

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/515,083 Expired - Fee Related US6670703B1 (en) 1998-11-25 2000-02-28 Buried ground plane for high performance system modules

Country Status (1)

Country Link
US (2) US6432724B1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030148598A1 (en) * 2001-11-20 2003-08-07 King-Ning Tu Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US20050029555A1 (en) * 2002-12-23 2005-02-10 Figueroa David Gregory Silicon building blocks in integrated circuit packaging
US20070049019A1 (en) * 2005-09-01 2007-03-01 Wai Chien M Method of selectively depositing materials on a substrate using a supercritical fluid
US20090291545A1 (en) * 2005-07-19 2009-11-26 Micron Technology, Inc. Process for enhancing solubility and reaction rates in supercritical fluids
WO2012000015A1 (en) * 2010-07-02 2012-01-05 Newsouth Innovations Pty Limited Metal contact scheme for solar cells
US20140151892A1 (en) * 2012-11-30 2014-06-05 Nvidia Corporation Three dimensional through-silicon via construction

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867491B2 (en) * 2001-12-19 2005-03-15 Intel Corporation Metal core integrated circuit package with electrically isolated regions and associated methods
JP2004071923A (en) * 2002-08-08 2004-03-04 Fujitsu Ltd High temperature superconductive device
US20040075170A1 (en) * 2002-10-21 2004-04-22 Yinon Degani High frequency integrated circuits
US7157791B1 (en) 2004-06-11 2007-01-02 Bridge Semiconductor Corporation Semiconductor chip assembly with press-fit ground plane
US7245023B1 (en) 2004-06-11 2007-07-17 Bridge Semiconductor Corporation Semiconductor chip assembly with solder-attached ground plane
US8021926B2 (en) * 2009-09-22 2011-09-20 Freescale Semiconductor, Inc. Methods for forming semiconductor devices with low resistance back-side coupling

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
KR900008647B1 (en) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 A method for manufacturing three demensional i.c.
GB9108176D0 (en) * 1991-04-17 1991-06-05 Secr Defence Electroluminescent silicon device
JPH05145094A (en) * 1991-11-22 1993-06-11 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5304293A (en) * 1992-05-11 1994-04-19 Teknekron Sensor Development Corporation Microsensors for gaseous and vaporous species
US6017811A (en) * 1993-09-09 2000-01-25 The United States Of America As Represented By The Secretary Of The Navy Method of making improved electrical contact to porous silicon
EP0895293B1 (en) * 1993-11-02 2006-06-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device comprising an aggregate of semiconductor micro-needles
EP0666595B1 (en) * 1994-02-07 1998-08-19 Siemens Aktiengesellschaft Method of manufacture of a cubic integrated circuit structure
US5805425A (en) * 1996-09-24 1998-09-08 Texas Instruments Incorporated Microelectronic assemblies including Z-axis conductive films
US6052286A (en) * 1997-04-11 2000-04-18 Texas Instruments Incorporated Restrained center core anisotropically conductive adhesive
WO1998048456A1 (en) * 1997-04-24 1998-10-29 Massachusetts Institute Of Technology Nanowire arrays
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030148598A1 (en) * 2001-11-20 2003-08-07 King-Ning Tu Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US7176129B2 (en) * 2001-11-20 2007-02-13 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US7772117B2 (en) 2001-11-20 2010-08-10 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US20070117345A1 (en) * 2001-11-20 2007-05-24 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US20050029555A1 (en) * 2002-12-23 2005-02-10 Figueroa David Gregory Silicon building blocks in integrated circuit packaging
US7205638B2 (en) * 2002-12-23 2007-04-17 Intel Corporation Silicon building blocks in integrated circuit packaging
US20090291545A1 (en) * 2005-07-19 2009-11-26 Micron Technology, Inc. Process for enhancing solubility and reaction rates in supercritical fluids
US8043944B2 (en) 2005-07-19 2011-10-25 Micron Technology, Inc. Process for enhancing solubility and reaction rates in supercritical fluids
US8329595B2 (en) 2005-07-19 2012-12-11 Micron Technology, Inc. Process for enhancing solubility and reaction rates in supercritical fluids
US8524610B2 (en) 2005-07-19 2013-09-03 Micron Technology, Inc. Process for enhancing solubility and reaction rates in supercritical fluids
US20090291556A1 (en) * 2005-09-01 2009-11-26 Micron Technology, Inc. Method of selectively depositing materials on a substrate using a supercritical fluid
US7582561B2 (en) * 2005-09-01 2009-09-01 Micron Technology, Inc. Method of selectively depositing materials on a substrate using a supercritical fluid
US20070049019A1 (en) * 2005-09-01 2007-03-01 Wai Chien M Method of selectively depositing materials on a substrate using a supercritical fluid
US7897517B2 (en) 2005-09-01 2011-03-01 Micron Technology, Inc. Method of selectively depositing materials on a substrate using a supercritical fluid
WO2012000015A1 (en) * 2010-07-02 2012-01-05 Newsouth Innovations Pty Limited Metal contact scheme for solar cells
US20140020746A1 (en) * 2010-07-02 2014-01-23 Newsouth Innovations Pty Limited Metal contact scheme for solar cells
US20140151892A1 (en) * 2012-11-30 2014-06-05 Nvidia Corporation Three dimensional through-silicon via construction
CN103855135A (en) * 2012-11-30 2014-06-11 辉达公司 Three dimensional through-silicon via construction

Also Published As

Publication number Publication date
US6670703B1 (en) 2003-12-30
US6432724B1 (en) 2002-08-13

Similar Documents

Publication Publication Date Title
JP5285829B2 (en) Interposer and manufacturing method thereof
US5424245A (en) Method of forming vias through two-sided substrate
US6962866B2 (en) System-on-a-chip with multi-layered metallized through-hole interconnection
US5583739A (en) Capacitor fabricated on a substrate containing electronic circuitry
JP4776618B2 (en) Back-end process transmission line structure for semiconductor devices (Method of forming a suspended transmission line structure in back-end process)
US6593644B2 (en) System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face
US6355950B1 (en) Substrate interconnect for power distribution on integrated circuits
US6174803B1 (en) Integrated circuit device interconnection techniques
US6057226A (en) Air gap based low dielectric constant interconnect structure and method of making same
WO2004100232A1 (en) Method for forming the top plate of a mim capacitor with a single mask in a copper dual damascene integration scheme
KR20060033866A (en) Electronic device, assembly and methods of manufacturing an electronic device
US6432724B1 (en) Buried ground plane for high performance system modules
US6759746B1 (en) Die attachment and method
US6277765B1 (en) Low-K Dielectric layer and method of making same
US7452804B2 (en) Single damascene with disposable stencil and method therefore
US20230378048A1 (en) Semiconductor structure and method for manufacturing the same
KR20110049893A (en) A semiconductor device comprising a carbon based material for through hole vias
US20240096783A1 (en) Flexible wiring architecture for multi-die integration
US20240071929A1 (en) Dielectric caps for power and signal line routing
CN113035810A (en) Through silicon via structure, packaging structure and manufacturing method thereof
JP2000228445A (en) Semiconductor device and its manufacture

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, KIE Y.;FORBES, LEONARD;REEL/FRAME:009634/0430;SIGNING DATES FROM 19981113 TO 19981116

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140813