US20020008319A1 - Commonly housed diverse semiconductor - Google Patents
Commonly housed diverse semiconductor Download PDFInfo
- Publication number
- US20020008319A1 US20020008319A1 US09966092 US96609201A US2002008319A1 US 20020008319 A1 US20020008319 A1 US 20020008319A1 US 09966092 US09966092 US 09966092 US 96609201 A US96609201 A US 96609201A US 2002008319 A1 US2002008319 A1 US 2002008319A1
- Authority
- US
- Grant status
- Application
- Patent type
- Prior art keywords
- die
- pad
- terminal
- device
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48639—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48739—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48744—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/901—MOSFET substrate bias
Abstract
Description
- [0001]This application is a continuation Application Ser. No. 09/645,060, filed Aug. 24, 2000, which is a continuation of Application Ser. No. 09/161,790, filed Sep. 28, 1998, which is a continuation of Application Ser. No. 08/816,829, filed Mar. 18, 1997, now U.S. Pat. No. 5,814,884, and claims the priority of Provisional Application Serial No. 60/029,483 filed Oct. 4, 1996.
- [0002]This invention relates to semiconductor devices, and more specifically relates to a novel device in which a plurality of die, which may be of diverse size and of diverse junction pattern, are fixed to a common lead frame and within a common package or housing.
- [0003]Numerous electrical circuits, for example, DC to DC converters, synchronous converters, and the like require a number of semiconductor components such as MOSFETs and Schottky diodes. These components are frequently used in portable electronics apparatus and are commonly separately housed and must be individually mounted on a support board. The separately housed parts take up board space. Further, each part generates heat and, if near other components, such as microprocessors, can interfere with the operation of the microprocessor.
- [0004]It would be desirable to reduce the board space required by plural semiconductor devices and to reduce part count and assembly costs in power converters and other power subsystems for high-density applications.
- [0005]In accordance with the invention, two or more diverse semiconductor die are laterally spaced and mounted on a common lead frame with a first one of each of their power terminals electrically connected to the lead frame. The main lead frame body then has a first set of externally available pins which are used to make connection to the first one of the power terminals of each of the diverse die. The die are also provided with second power terminals at the tops of the die, and these are connected to respective external pins of the lead frame which are isolated from one another and from the first set of external pins. One or more of the die may also contain a control terminal, such as the gate electrode of a MOSFET die, and a further and isolated pin of the lead frame is connected to this gate terminal.
- [0006]The lead frame and die are then over-molded with a suitable insulation compound housing, with the various pins extending in-line and beyond the edge surfaces of the housing and available for external connection.
- [0007]The housing may take the form of a surface-mounted housing with a very small “footprint”. By way of example, a MOSFET die and a Schottky diode die may be contained within and may have their drain electrodes and cathode electrodes respectively soldered to a common conduction lead frame pad to be interconnected within the housing. The FET source and gate terminals on top of the die are wire bonded to insulated lead frame pins and the top Schottky diode anode is also connected to an isolated pin so that any desired external connection can be made to the package.
- [0008]While any package style can be used, the novel invention has been carried out with an SO-8 style small outline package.
- [0009]The novel package of the invention can improve efficiency of a DC to DC converter by reducing power drain on batteries, leading to a longer life. For desk top systems, the device reduces power dissipation and heat generation near temperature-sensitive parts such as microprocessors. The device also provides substantial savings in board space while reducing component count and assembly costs.
- [0010]For example, the use of a copackaged FET Type IRF7422D2 (a (−20) volt 90 mohm P channel FET) and a Schottky diode (30 volt, 1 ampere) in a buck converter circuit provided a 60% saving in board space and assembly cost.
- [0011]Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
- [0012][0012]FIG. 1 is a circuit diagram of a known buck converter circuit using a P channel MOSFET.
- [0013][0013]FIG. 2 is a circuit diagram of a buck converter circuit employing an N channel MOSFET and a parallel Schottky diode.
- [0014][0014]FIG. 3 is a perspective diagram of an SO-8 style package which can be used to house both the MOSFET die and Schottky die of FIGS. 1 and 2 in accordance with an embodiment of the invention.
- [0015][0015]FIG. 4 is a schematic top view of the package of FIG. 3 with the die of the circuit of FIG. 1 copackaged on a common lead frame.
- [0016][0016]FIG. 5 shows a top view of the lead frame of the package of FIGS. 3 and 4 with the MOSFET die and Schottky diode die fastened to the lead frame.
- [0017][0017]FIG. 6 is an enlarged view of the portion of FIG. 5 which is within the dashed line in FIG. 5.
- [0018][0018]FIG. 7 is a schematic top view of an alternative embodiment of the package of FIG. 3 with the die of the circuit of FIG. 1 copackaged on a common lead frame.
- [0019][0019]FIG. 8 shows a top view of the lead frame of the package of FIG. 7 with the MOSFET die and the Schottky diode die fastened to the lead frame.
- [0020][0020]FIG. 9 is an enlarged view of the portion of FIG. 8 which is within the dashed line in FIG. 8.
- [0021]Referring first to FIG. 1, there is shown a conventional buck converter circuit, sometimes known as a step down converter, which is commonly used to reduce the voltage to integrated circuits and processors on the circuit board of a portable electronic device or the like. For example, the circuit might be used to reduce an input voltage of 12 volts DC to 5 volts DC (or 3.3 volts DC in some cases) to drive an integrated circuit or other load (not shown).
- [0022]The circuit of FIG. 1 is well known and uses a P channel MOSFET 10 for the switching function under the control of a suitable control circuit 11 connected to the FET gate G. FET 10 may be a 20v, 90 m-ohm die available from the International Rectifier Corporation. A Schottky diode 12 which may be a 30 volt, 1 ampere die has its cathode connected to the drain D of FET 10 and is used to perform output current recirculation into inductor 13 and capacitor 14. As will be later shown, and in accordance with the invention, FET 10 and Schottky diode 12 are provided in die form and are mounted on a common lead frame of a single package shown by dotted line block 15. This novel combination produces a 60% space saving on the support board of the device and reduces assembly cost.
- [0023]It will be apparent that the invention can be employed in many other circuit configurations. For example, FIG. 2 shows a synchronous buck converter circuit using an N channel MOSFET 20 as the switching device, an N channel MOSFET 21, and a Schottky diode 22 in parallel for synchronous rectification.
- [0024]In accordance with the invention, FET 21 and Schottky diode 22 may be die which are copackaged within a common housing, as shown by dotted block 23. This circuit is useful to avoid losses found in the “lossy” forward voltage drop of the Schottky diode 12 of FIG. 1. It also eliminates the effects of the inherent body diode of the vertical conduction FET 21 from the circuit since the Schottky diode 22 handles the reverse current flow seen by the synchronous rectifier during the “wait” state of controller 24.
- [0025]FET 21 of FIG. 2 may be a 30v, 35 m-ohm die available from the International Rectifier Corporation.
- [0026]Housings 15 and 23 may take the form of a known housing Type SO-8, shown in FIGS. 3 and 4. Thus, FIG. 3 shows an SO-8 surface mount housing with eight in-line pins 1 to 8 (FIG. 4) which extend from a plastic insulation housing 30. As seen in FIG. 4, the FET die 10 and Schottky diode 12 are internally mounted on a common lead frame, as will be later described and are interconnected to enable their external connection as in FIG. 1 or 2 (with an appropriate FET die 10 or 21) or in other circuit configurations.
- [0027]In FIG. 4, the drain of FET 10 and cathode of Schottky diode 12 are connected to one another and to pins 5 to 8 of a common lead frame section as will be later described. The source and gate of FET 10 are connected by wire bonds to isolated pins 3 and 4, respectively, and the anode of Schottky diode 12 is connected by wire bonds to isolated pins 1 and 2.
- [0028][0028]FIGS. 5 and 6 show the lead frame and FET 10 and Schottky 12 die in more detail. Thus, a lead frame 40 is provided which contains a main pad body 41 from which pins 5 to 8 integrally extend. The main pad body 41 is larger than the main pad body of a conventional lead frame so that both the FET die 60 and the Schottky diode 12 may be mounted to it. According to a novel aspect of the invention, the walls of plastic insulation housing 30 are thinner than a conventional housing to accommodate the larger main pad body without significantly reducing resistance to moisture.
- [0029]The lead frame also contains pins 1 to 4 and respective bond pad extensions which are within molded housing 30. These are originally integral with the lead frame body 40 (during molding), but are shown in their severed condition which isolates pins 1 to 4 from one another and from main pad 41. Typically, pins 1 to 4 are coplanar with each other and with the main bond pad 41.
- [0030]Lead frame 40 is a conductive frame and may have a conventional lead frame solder finish. The bottom cathode surface of diode 12 and the bottom drain surface of FET 10 are connected to pad 41 as by a conductive epoxy die attach compound and are thus connected to pins 5 to 8. Alternatively, the cathode surface of diode 12 and the drain surface of FET 10 are soldered to pad 41 or are connected to the pad using a conductive glass containing silver particles.
- [0031]The top anode electrode of Schottky diode 12 is wire bonded by gold bonding wires 50 and 51 to pins 1 and 2, respectively (before molding), while the source electrode and gate electrode of die 10 are bonded by gold wires 52 and 53 to the internal bonding extensions of pins 3 and 4, respectively, also before molding the housing 30. Alternatively, aluminum bonding wires are used. The internal bonding extension of the pins are typically silver or gold plated. The bonding wires are generally bonded to the die surface and to the internal bonding extensions using thermosonic ball bonding, as is known in the art, though other processes may be used.
- [0032]Thereafter, the molded housing, which may be a mold compound such as NITTO MP7400. It is formed in a conventional molding operation. However, other types of housings, such as a ceramic housing, a hermetic housing or an injection molded metal housing, may be used.
- [0033]It should be noted that other package styles could be used, but the copackaging in a surface-mount package conserves considerable board space. The resulting device can be soldered down to a printed circuit board using conventional mass production soldering techniques.
- [0034][0034]FIGS. 7 and 8 shows an alternative embodiment of the invention in which the source of FET 10 is connected by wire bonds 151 and 152 to isolated pins 2 and 3, the gate of FET 10 is connected by wire bonds 153 to isolated pin 4, and the anode of Schottky diode 12 is connected by wire bonds 150 to isolated pin 1. The drain of FET 10 and the cathode of Schottky diode 12 are connected to one another and to pins 5 to 8 of a common lead frame section in the manner described above.
- [0035][0035]FIGS. 8 and 9 show the lead frame of this embodiment and the FET 10 and the Schottky diode 12 in greater detail. The lead frame 140 is similar to the lead frame 40 described above and includes a similar main pad body 141. The bottom cathode surface of Schottky diode 12 and the bottom drain surface of FET 10 are connected to pad 141 in a similar manner to that described above, and the top anode electrode of Schottky diode 12 and the source and gate electrodes of FET die 10 are similarly bonded to the internal bonding extensions of the pins as described above. Similarly, the housing 130 is formed in the manner described above.
- [0036]Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not only by the specific disclosure herein, by only by the appended claims.
Claims (42)
- 1. A semiconductor device comprising, in combination, a first semiconductor die having opposing surfaces which contain respective electrodes, a second semiconductor die having opposing surfaces which contain respective electrodes, a thin conductive lead frame having a main pad area having a first plurality of parallel pins extending from one edge thereof, and a second plurality of pins separated from one another and from said main pad area; said second plurality of pins being disposed along an edge of said main pad area opposite to the side thereof containing said first plurality of pins; one of said opposing surfaces of each of said first and second semiconductor die being disposed atop and in electrical contact with said main pad area and being laterally spaced from one another; the opposite ones of said opposing surfaces of said first and second die being wire bonded to respective ones of said second plurality of pins; and a molded housing for encapsulating said lead frame and said first and second die and said bonding wires; said first and second pins extending beyond the boundary of said molded housing and available for external connection.
- 2. The device of
claim 1 wherein said first die is a MOSFET die having a source, drain and gate electrode and wherein the surface of said die in contact with said main pad area is the said drain electrode; said source and gate electrodes being connected to respective ones of said second plurality of pins - 3. The device of
claim 1 wherein said first and second pluralities of pins are downwardly bent along the side edges of said housing to define a surface-mount device. - 4. The device of
claim 1 wherein said first and second plurality of pins are in line. - 5. The device of
claim 1 wherein each of said second plurality of pins has an enlarged bonding pad area which are coplanar with one another and with said main pad area. - 6. The device of
claim 2 wherein said second die is a Schottky diode die; said opposite surface of said second die comprising the cathode electrode of said Schottky diode, whereby said cathode electrode of said Schottky diode is permanently connected to said drain electrode of said MOSFET and to said first plurality of pins; the opposite surface of said Schottky diode die comprising its anode electrode. - 7. The device of
claim 6 wherein said anode electrode of said Schottky diode die is connected to at least two of said second plurality of pins. - 8. The device of
claim 6 wherein said first and second pins are downwardly bent along the side edges of said housing to define a surface-mount device. - 9. The device of
claim 7 wherein said first and second pluralities of pins are downwardly bent along the side edges of said housing to define a surface-mount device. - 10. The device of
claim 6 wherein said first and second plurality of pins are in line. - 11. The device of
claim 7 wherein said first and second plurality of pins are in line. - 12. The device of
claim 8 wherein said first and second plurality of pins are in line. - 13. The device of
claim 6 wherein each of said second plurality of pins has an enlarged bonding pad area which are coplanar with one another and with said main pad area. - 14. The device of
claim 7 wherein each of said second plurality of pins has an enlarged bonding pad area which are coplanar with one another and with said main pad area. - 15. The device of
claim 8 wherein each of said second plurality of pins has an enlarged bonding pad area which are coplanar with one another and with said main pad area. - 16. The device of
claim 10 wherein each of said second plurality of pins has an enlarged bonding pad area which are coplanar with one another and with said main pad area. - 17. A surface-mount package which contains a MOSFET die and a Schottky diode die; said surface-mount package having a lead frame which has a main pad section having a first plurality of pins extending through one edge of said housing and a second plurality of coplanar insulated pins extending through an edge of said die opposite to said one edge; said MOSFET die having a drain electrode on one surface and a source electrode and gate electrode on an opposite surface; said Schottky diode containing a cathode electrode on one surface and an anode electrode on an opposite surface; said drain electrode and said cathode electrode being fixed in surface-to-surface contact with said main pad section of said lead frame at laterally displaced locations; said anode electrode, said source electrode and said gate electrode being wire bonded to respective ones of said second plurality of pins within said housing.
- 18. The device of
claim 17 wherein said first and second pluralities of pins consist of four pins, each of which is in line. - 19. The device of
claim 18 wherein said anode electrode is connected to two adjacent pins of said second plurality of pins. - 20. A semiconductor device comprising:a lead frame having a plurality of leads and a die pad;a first semiconductor chip having a bottom surface that is secured to said die pad and comprising a MOSFET having a source terminal, a drain terminal and a gate terminal;a second semiconductor chip having a bottom surface that is secured to said die pad and comprising a Schottky diode having an anode terminal and a cathode terminal;wherein each of said source terminal, said drain terminal, said gate terminal, said anode terminal and said cathode terminal are electrically coupled to said plurality of leads; anda housing surrounding said first and second semiconductor devices, said die pad and a respective portion of each of said plurality of leads.
- 21. The device of
claim 20 wherein said plurality of leads comprises eight leads. - 22. The device of
claim 20 wherein at least one of said plurality of leads includes a plated bond post. - 23. The device of
claim 20 wherein said drain terminal of said MOSFET is formed on the bottom surface of said first semiconductor chip and is conductively bonded to said die pad. - 24. The device of
claim 23 , wherein said die pad is electrically coupled to at least one of said leads. - 25. The device of
claim 23 wherein said die pad is integral with at least one of said plurality of leads. - 26. The device of
claim 23 wherein said cathode terminal of said Schottky diode is formed on the bottom surface of said second semiconductor device and is conductively bonded to said die pad so that said drain of said MOSFET and said cathode of said Schottky diode are electrically coupled to at least one common lead of said plurality of leads. - 27. The device of
claim 23 wherein said drain terminal is soldered to said die pad. - 28. The device of
claim 23 wherein said drain terminal is conductively bonded to said die pad using a conductive epoxy. - 29. The device of
claim 20 wherein said cathode terminal of said Schottky diode is formed on the bottom surface of said second semiconductor chip and is conductively bonded to said die pad. - 30. The device of
claim 29 wherein said die pad is electrically coupled to at least one of said plurality of leads. - 31. The device of
claim 29 wherein said die pad is integral with at least one of said plurality of leads. - 32. The device of
claim 29 wherein said cathode terminal is soldered to said die pad. - 33. The device of
claim 29 wherein said cathode is conductively bonded to said die pad using a conductive epoxy. - 34. The device of
claim 20 wherein said source terminal of said MOSFET is formed on a top surface of said MOSFET and is wire bonded to at least one of said plurality of leads. - 35. The device of
claim 20 wherein said gate terminal of said MOSFET is formed on a top surface of said MOSFET and is wire bonded to at least one of said plurality of leads. - 36. The device of
claim 20 wherein said source terminal of said MOSFET is electrically coupled to at least two of said plurality of leads. - 37. The device of
claim 20 wherein said anode terminal of said Schottky diode is formed on a top surface of said Schottky diode and is wire bonded to at least one of said plurality of leads. - 38. The device of
claim 20 wherein said anode terminal of said Schottky diode is electrically coupled to at least two of said plurality of leads. - 39. The device of
claim 20 wherein said housing is a plastic transfer mold compound. - 40. The device of
claim 39 wherein said plastic transfer mold compound is molded around said first and second semiconductor chips, said die pad and said respective portion of said plurality of leads. - 41. A converter circuit comprising:a semiconductor device includinga lead frame having a plurality of leads and a die pad, a first semiconductor chip having a bottom surface that is secured to said die pad and including a MOSFET having a source terminal, a drain terminal and a gate terminal, a second semiconductor chip having a bottom surface that is secured to said die pad and including a Schottky diode having an anode terminal and a cathode terminal, wherein each of said source terminal, said drain terminal, said gate terminal, said anode terminal and said cathode terminal are electrically coupled to said plurality of leads, and a housing surrounding said first and second semiconductor devices, said die pad and a respective portion of each of said plurality of leads;a supply voltage terminal electrically coupled to said source terminal of said MOSFET;a ground terminal electrically coupled to said anode of said Schottky diode; anda pair of load terminals, wherein said one of said load terminals is electrically coupled to said drain terminal of said MOSFET and to said cathode of said Schottky diode, and another of said pair of load terminals is electrically coupled to said anode terminal of said Schottky diode.
- 42. A synchronous regulator circuit comprising:a semiconductor device includinga lead frame having a plurality of leads and a die pad, a first semiconductor chip having a bottom surface that is secured to said die pad and including a first MOSFET having a source terminal, a drain terminal and a gate terminal, a second semiconductor chip having a bottom surface that is secured to said die pad and including a Schottky diode having an anode terminal and a cathode terminal, wherein each of said source terminal, said drain terminal, said gate terminal, said anode terminal and said cathode terminal are electrically coupled to said plurality of leads, and a housing surrounding said first and second semiconductor devices, said die pad and a respective portion of each of said plurality of leads;a supply voltage terminal;a second MOSFET having a drain terminal electrically coupled to said supply voltage terminal, a source terminal electrically coupled to said drain terminal of said first MOSFET and said cathode terminal of said Schottky diode;a controller coupled to said gate terminals of said first and second MOSFETs; anda ground terminal electrically coupled to said source terminal of said first MOSFET and to said anode terminal of said Schottky diode.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2948396 true | 1996-10-24 | 1996-10-24 | |
US5814884C1 US5814884C1 (en) | 1996-10-24 | 1997-03-18 | Commonly housed diverse semiconductor die |
US09161790 US6133632A (en) | 1996-10-24 | 1998-09-28 | Commonly housed diverse semiconductor die |
US09645060 US6297552B1 (en) | 1996-10-24 | 2000-08-24 | Commonly housed diverse semiconductor die |
US09966092 US6404050B2 (en) | 1996-10-24 | 2001-10-01 | Commonly housed diverse semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09966092 US6404050B2 (en) | 1996-10-24 | 2001-10-01 | Commonly housed diverse semiconductor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date | |
---|---|---|---|---|
US09645060 Continuation US6297552B1 (en) | 1996-10-24 | 2000-08-24 | Commonly housed diverse semiconductor die |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020008319A1 true true US20020008319A1 (en) | 2002-01-24 |
US6404050B2 US6404050B2 (en) | 2002-06-11 |
Family
ID=26704993
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US5814884C1 Expired - Lifetime US5814884C1 (en) | 1996-10-24 | 1997-03-18 | Commonly housed diverse semiconductor die |
US09161790 Expired - Lifetime US6133632A (en) | 1996-10-24 | 1998-09-28 | Commonly housed diverse semiconductor die |
US09645060 Expired - Lifetime US6297552B1 (en) | 1996-10-24 | 2000-08-24 | Commonly housed diverse semiconductor die |
US09966092 Expired - Lifetime US6404050B2 (en) | 1996-10-24 | 2001-10-01 | Commonly housed diverse semiconductor |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US5814884C1 Expired - Lifetime US5814884C1 (en) | 1996-10-24 | 1997-03-18 | Commonly housed diverse semiconductor die |
US09161790 Expired - Lifetime US6133632A (en) | 1996-10-24 | 1998-09-28 | Commonly housed diverse semiconductor die |
US09645060 Expired - Lifetime US6297552B1 (en) | 1996-10-24 | 2000-08-24 | Commonly housed diverse semiconductor die |
Country Status (2)
Country | Link |
---|---|
US (4) | US5814884C1 (en) |
JP (1) | JP2896126B2 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7166496B1 (en) | 2005-08-17 | 2007-01-23 | Ciclon Semiconductor Device Corp. | Method of making a packaged semiconductor device |
US20070085204A1 (en) * | 2005-10-19 | 2007-04-19 | Cicion Semiconductor Device Corp. | Chip scale power LDMOS device |
US20070215939A1 (en) * | 2006-03-14 | 2007-09-20 | Shuming Xu | Quasi-vertical LDMOS device having closed cell layout |
US20100176508A1 (en) * | 2009-01-12 | 2010-07-15 | Ciclon Semiconductor Device Corp. | Semiconductor device package and method of assembly thereof |
US7851897B1 (en) * | 2008-06-16 | 2010-12-14 | Maxim Integrated Products, Inc. | IC package structures for high power dissipation and low RDSon |
US20110075392A1 (en) * | 2009-09-29 | 2011-03-31 | Astec International Limited | Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets |
US20110095411A1 (en) * | 2006-08-14 | 2011-04-28 | Texas Instruments Incorporated | Wirebond-less Semiconductor Package |
US20120068329A1 (en) * | 2010-09-16 | 2012-03-22 | Mitsubishi Electric Corporation | Semiconductor device |
US20120286410A1 (en) * | 2010-11-12 | 2012-11-15 | Nxp B.V. | Semiconductor device packaging method and semiconductor device package |
Families Citing this family (141)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69627909D1 (en) | 1995-01-17 | 2003-06-12 | Vlt Corp | Regulation of gepseicherten in the transformers of switching power supplies energy |
US5929520A (en) * | 1998-03-10 | 1999-07-27 | General Electric Company | Circuit with small package for mosfets |
US6054765A (en) * | 1998-04-27 | 2000-04-25 | Delco Electronics Corporation | Parallel dual switch module |
US6144093A (en) * | 1998-04-27 | 2000-11-07 | International Rectifier Corp. | Commonly housed diverse semiconductor die with reduced inductance |
US6476481B2 (en) | 1998-05-05 | 2002-11-05 | International Rectifier Corporation | High current capacity semiconductor device package and lead frame with large area connection posts and modified outline |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
US6396127B1 (en) | 1998-09-25 | 2002-05-28 | International Rectifier Corporation | Semiconductor package |
US6410989B1 (en) | 1999-01-04 | 2002-06-25 | International Rectifier Corporation | Chip-scale package |
KR20000057810A (en) * | 1999-01-28 | 2000-09-25 | 가나이 쓰토무 | Semiconductor device |
US6388319B1 (en) * | 1999-05-25 | 2002-05-14 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
US6448643B2 (en) * | 2000-05-24 | 2002-09-10 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
US6351033B1 (en) * | 1999-10-06 | 2002-02-26 | Agere Systems Guardian Corp. | Multifunction lead frame and integrated circuit package incorporating the same |
KR100379089B1 (en) | 1999-10-15 | 2003-04-08 | 앰코 테크놀로지 코리아 주식회사 | leadframe and semiconductor package using it |
JP4651153B2 (en) * | 1999-10-28 | 2011-03-16 | ローム株式会社 | Semiconductor device |
US6319755B1 (en) * | 1999-12-01 | 2001-11-20 | Amkor Technology, Inc. | Conductive strap attachment process that allows electrical connector between an integrated circuit die and leadframe |
US6762067B1 (en) * | 2000-01-18 | 2004-07-13 | Fairchild Semiconductor Corporation | Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails |
US6421262B1 (en) * | 2000-02-08 | 2002-07-16 | Vlt Corporation | Active rectifier |
US7049761B2 (en) | 2000-02-11 | 2006-05-23 | Altair Engineering, Inc. | Light tube and power supply circuit |
US6282107B1 (en) | 2000-03-07 | 2001-08-28 | Vlt Corporation | Integrated sense and switch circuitry for transformer core resetting |
US6459147B1 (en) * | 2000-03-27 | 2002-10-01 | Amkor Technology, Inc. | Attaching semiconductor dies to substrates with conductive straps |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6930397B2 (en) * | 2001-03-28 | 2005-08-16 | International Rectifier Corporation | Surface mounted package with die bottom spaced from support board |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6627961B1 (en) * | 2000-05-05 | 2003-09-30 | International Rectifier Corporation | Hybrid IGBT and MOSFET for zero current at zero voltage |
DE10022268B4 (en) * | 2000-05-08 | 2005-03-31 | Infineon Technologies Ag | Semiconductor component having two semiconductor bodies in a common housing |
US6521982B1 (en) | 2000-06-02 | 2003-02-18 | Amkor Technology, Inc. | Packaging high power integrated circuit devices |
DE10030875C1 (en) * | 2000-06-23 | 2002-03-07 | Compact Dynamics Gmbh | The half-bridge |
US6661082B1 (en) * | 2000-07-19 | 2003-12-09 | Fairchild Semiconductor Corporation | Flip chip substrate design |
US6566164B1 (en) | 2000-12-07 | 2003-05-20 | Amkor Technology, Inc. | Exposed copper strap in a semiconductor package |
US6433424B1 (en) * | 2000-12-14 | 2002-08-13 | International Rectifier Corporation | Semiconductor device package and lead frame with die overhanging lead frame pad |
US6469384B2 (en) | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
KR100369393B1 (en) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | Lead frame and semiconductor package using it and its manufacturing method |
US6756658B1 (en) | 2001-04-06 | 2004-06-29 | Amkor Technology, Inc. | Making two lead surface mounting high power microleadframe semiconductor packages |
US6593622B2 (en) * | 2001-05-02 | 2003-07-15 | International Rectifier Corporation | Power mosfet with integrated drivers in a common package |
KR100612165B1 (en) * | 2001-05-18 | 2006-08-14 | 산요덴키가부시키가이샤 | Power source circuit device |
US6528880B1 (en) * | 2001-06-25 | 2003-03-04 | Lovoltech Inc. | Semiconductor package for power JFET having copper plate for source and ribbon contact for gate |
JP4097417B2 (en) | 2001-10-26 | 2008-06-11 | 株式会社ルネサステクノロジ | Semiconductor device |
US6552597B1 (en) * | 2001-11-02 | 2003-04-22 | Power Integrations, Inc. | Integrated circuit with closely coupled high voltage output and offline transistor pair |
US6630726B1 (en) | 2001-11-07 | 2003-10-07 | Amkor Technology, Inc. | Power semiconductor package with strap |
US6677669B2 (en) * | 2002-01-18 | 2004-01-13 | International Rectifier Corporation | Semiconductor package including two semiconductor die disposed within a common clip |
US6867489B1 (en) * | 2002-01-22 | 2005-03-15 | Fairchild Semiconductor Corporation | Semiconductor die package processable at the wafer level |
DE10204882A1 (en) * | 2002-02-06 | 2003-08-14 | Compact Dynamics Gmbh | Half-bridge circuit has fast switching diodes connected in parallel with each arm |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
JP3993461B2 (en) * | 2002-05-15 | 2007-10-17 | 株式会社東芝 | Semiconductor module |
US6818973B1 (en) | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US6919620B1 (en) | 2002-09-17 | 2005-07-19 | Amkor Technology, Inc. | Compact flash memory card with clamshell leadframe |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US8188584B1 (en) | 2002-11-08 | 2012-05-29 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6781352B2 (en) | 2002-12-16 | 2004-08-24 | International Rectifer Corporation | One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6927483B1 (en) | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US6963140B2 (en) * | 2003-03-17 | 2005-11-08 | Analog Power Intellectual Properties | Transistor having multiple gate pads |
US6879034B1 (en) | 2003-05-01 | 2005-04-12 | Amkor Technology, Inc. | Semiconductor package including low temperature co-fired ceramic substrate |
US6919625B2 (en) * | 2003-07-10 | 2005-07-19 | General Semiconductor, Inc. | Surface mount multichip devices |
US6921967B2 (en) | 2003-09-24 | 2005-07-26 | Amkor Technology, Inc. | Reinforced die pad support structure |
US6927482B1 (en) * | 2003-10-01 | 2005-08-09 | General Electric Company | Surface mount package and method for forming multi-chip microsensor device |
US7167043B2 (en) * | 2003-11-24 | 2007-01-23 | International Rectifier Corporation | Decoupling circuit for co-packaged semiconductor devices |
US8395253B2 (en) * | 2004-01-28 | 2013-03-12 | International Rectifier Corporation | Hermetic surface mounted power package |
US7301235B2 (en) | 2004-06-03 | 2007-11-27 | International Rectifier Corporation | Semiconductor device module with flip chip devices on a common lead frame |
US7501702B2 (en) * | 2004-06-24 | 2009-03-10 | Fairchild Semiconductor Corporation | Integrated transistor module and method of fabricating same |
JP2006049341A (en) * | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
DE102004047306B4 (en) * | 2004-09-29 | 2008-02-07 | Infineon Technologies Ag | Power semiconductor component with a plurality of device components |
CN100359686C (en) * | 2004-11-30 | 2008-01-02 | 万代半导体元件(上海)有限公司 | Thin and small outer shape package combined by metal oxide semiconductor field effect transistor and schottky diode |
US7884454B2 (en) | 2005-01-05 | 2011-02-08 | Alpha & Omega Semiconductor, Ltd | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
US7230333B2 (en) * | 2005-04-21 | 2007-06-12 | International Rectifier Corporation | Semiconductor package |
US20070023901A1 (en) * | 2005-07-29 | 2007-02-01 | Gerard Mahoney | Microelectronic bond pad |
US7443014B2 (en) * | 2005-10-25 | 2008-10-28 | Infineon Technologies Ag | Electronic module and method of assembling the same |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7582958B2 (en) * | 2005-12-08 | 2009-09-01 | International Rectifier Corporation | Semiconductor package |
US7768075B2 (en) * | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
JP5165214B2 (en) * | 2006-06-26 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device |
US7586156B2 (en) * | 2006-07-26 | 2009-09-08 | Fairchild Semiconductor Corporation | Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
KR101221807B1 (en) | 2006-12-29 | 2013-01-14 | 페어차일드코리아반도체 주식회사 | Power device package |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
JP2008270302A (en) * | 2007-04-16 | 2008-11-06 | Sanyo Electric Co Ltd | Semiconductor device |
JP5106528B2 (en) * | 2007-05-29 | 2012-12-26 | 京セラ株式会社 | Electronic component storing package, and an electronic device |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
JP2009110981A (en) * | 2007-10-26 | 2009-05-21 | Mitsubishi Electric Corp | Semiconductor module |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7898092B2 (en) * | 2007-11-21 | 2011-03-01 | Alpha & Omega Semiconductor, | Stacked-die package for battery power management |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US8125071B2 (en) * | 2008-09-03 | 2012-02-28 | Inergy Technology Inc. | Package structure utilizing high and low side drivers on separate dice |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US9257375B2 (en) | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
US8164199B2 (en) * | 2009-07-31 | 2012-04-24 | Alpha and Omega Semiconductor Incorporation | Multi-die package |
US20110049580A1 (en) * | 2009-08-28 | 2011-03-03 | Sik Lui | Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
US8896131B2 (en) | 2011-02-03 | 2014-11-25 | Alpha And Omega Semiconductor Incorporated | Cascode scheme for improved device switching behavior |
US20120217541A1 (en) * | 2011-02-24 | 2012-08-30 | Force Mos Technology Co., Ltd. | Igbt with integrated mosfet and fast switching diode |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
JP5787784B2 (en) * | 2012-02-15 | 2015-09-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
KR101486790B1 (en) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | Micro Lead Frame for semiconductor package |
US9041460B2 (en) * | 2013-08-12 | 2015-05-26 | Infineon Technologies Ag | Packaged power transistors and power packages |
KR101563911B1 (en) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
US9536800B2 (en) | 2013-12-07 | 2017-01-03 | Fairchild Semiconductor Corporation | Packaged semiconductor devices and methods of manufacturing |
JP2017028195A (en) * | 2015-07-27 | 2017-02-02 | 三菱電機株式会社 | Semiconductor device |
US9540488B1 (en) | 2015-12-16 | 2017-01-10 | Industrial Technology Research Institute | Siloxane resin composition, and photoelectric device employing the same |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4137546A (en) * | 1977-10-14 | 1979-01-30 | Plessey Incorporated | Stamped lead frame for semiconductor packages |
US4641418A (en) * | 1982-08-30 | 1987-02-10 | International Rectifier Corporation | Molding process for semiconductor devices and lead frame structure therefor |
US5083189A (en) * | 1987-03-31 | 1992-01-21 | Kabushiki Kaisha Toshiba | Resin-sealed type IC device |
US5084753A (en) * | 1989-01-23 | 1992-01-28 | Analog Devices, Inc. | Packaging for multiple chips on a single leadframe |
DE8913465U1 (en) * | 1989-11-14 | 1990-04-05 | Siemens Ag, 1000 Berlin Und 8000 Muenchen, De | |
US5049973A (en) * | 1990-06-26 | 1991-09-17 | Harris Semiconductor Patents, Inc. | Heat sink and multi mount pad lead frame package and method for electrically isolating semiconductor die(s) |
JPH04280664A (en) * | 1990-10-18 | 1992-10-06 | Texas Instr Inc <Ti> | Lead frame for semiconductor device |
JP2568748B2 (en) * | 1990-10-30 | 1997-01-08 | 三菱電機株式会社 | Semiconductor device |
US5200640A (en) * | 1991-08-12 | 1993-04-06 | Electron Power Inc. | Hermetic package having covers and a base providing for direct electrical connection |
JPH0582696A (en) * | 1991-09-19 | 1993-04-02 | Mitsubishi Electric Corp | Lead frame of semiconductor device |
JPH05243459A (en) * | 1992-02-27 | 1993-09-21 | Ckd Corp | Hybrid ic |
JPH0689962A (en) * | 1992-02-28 | 1994-03-29 | Mega Chips:Kk | Semiconductor device |
JP2708320B2 (en) * | 1992-04-17 | 1998-02-04 | 三菱電機株式会社 | Multi-chip type semiconductor device and a manufacturing method thereof |
JP2829188B2 (en) * | 1992-04-27 | 1998-11-25 | 株式会社東芝 | Resin-sealed semiconductor device |
US5544038A (en) * | 1992-09-21 | 1996-08-06 | General Electric Company | Synchronous rectifier package for high-efficiency operation |
JPH07130927A (en) * | 1993-11-08 | 1995-05-19 | Omron Corp | Motor driver module |
JP2536436B2 (en) * | 1993-11-19 | 1996-09-18 | 日本電気株式会社 | Mode - field type semiconductor device |
DE19507132A1 (en) * | 1995-03-01 | 1996-09-05 | Siemens Ag | Assembly of electronic components on a carrier strip |
KR100372153B1 (en) * | 1995-04-05 | 2003-06-19 | 내셔널 세미콘덕터 코포레이션 | Multi-layer lead frame |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7166496B1 (en) | 2005-08-17 | 2007-01-23 | Ciclon Semiconductor Device Corp. | Method of making a packaged semiconductor device |
US7504733B2 (en) | 2005-08-17 | 2009-03-17 | Ciclon Semiconductor Device Corp. | Semiconductor die package |
US20070085204A1 (en) * | 2005-10-19 | 2007-04-19 | Cicion Semiconductor Device Corp. | Chip scale power LDMOS device |
US7560808B2 (en) | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
US7446375B2 (en) | 2006-03-14 | 2008-11-04 | Ciclon Semiconductor Device Corp. | Quasi-vertical LDMOS device having closed cell layout |
US20070215939A1 (en) * | 2006-03-14 | 2007-09-20 | Shuming Xu | Quasi-vertical LDMOS device having closed cell layout |
US8304903B2 (en) | 2006-08-14 | 2012-11-06 | Texas Instruments Incorporated | Wirebond-less semiconductor package |
US20110095411A1 (en) * | 2006-08-14 | 2011-04-28 | Texas Instruments Incorporated | Wirebond-less Semiconductor Package |
US7851897B1 (en) * | 2008-06-16 | 2010-12-14 | Maxim Integrated Products, Inc. | IC package structures for high power dissipation and low RDSon |
US20100176508A1 (en) * | 2009-01-12 | 2010-07-15 | Ciclon Semiconductor Device Corp. | Semiconductor device package and method of assembly thereof |
US8049312B2 (en) | 2009-01-12 | 2011-11-01 | Texas Instruments Incorporated | Semiconductor device package and method of assembly thereof |
US20110075392A1 (en) * | 2009-09-29 | 2011-03-31 | Astec International Limited | Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets |
US9706638B2 (en) | 2009-09-29 | 2017-07-11 | Astec International Limited | Assemblies and methods for directly connecting integrated circuits to electrically conductive sheets |
US20120068329A1 (en) * | 2010-09-16 | 2012-03-22 | Mitsubishi Electric Corporation | Semiconductor device |
US9087712B2 (en) * | 2010-09-16 | 2015-07-21 | Mitsubishi Electric Corporation | Semiconductor device |
US20120286410A1 (en) * | 2010-11-12 | 2012-11-15 | Nxp B.V. | Semiconductor device packaging method and semiconductor device package |
Also Published As
Publication number | Publication date | Type |
---|---|---|
JPH10150140A (en) | 1998-06-02 | application |
US6297552B1 (en) | 2001-10-02 | grant |
US6133632A (en) | 2000-10-17 | grant |
JP2896126B2 (en) | 1999-05-31 | grant |
US6404050B2 (en) | 2002-06-11 | grant |
US5814884C1 (en) | 2002-01-29 | grant |
US5814884A (en) | 1998-09-29 | grant |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6373705B1 (en) | Electronic semiconductor module | |
US7271470B1 (en) | Electronic component having at least two semiconductor power devices | |
US6593622B2 (en) | Power mosfet with integrated drivers in a common package | |
US5929514A (en) | Thermally enhanced lead-under-paddle I.C. leadframe | |
US6473304B1 (en) | Thermally conductive case for electrical components and method of manufacture therefor | |
US20010045627A1 (en) | Semiconductor device package with plural pad lead frame | |
US20060237825A1 (en) | Device packages having a III-nitride based power semiconductor device | |
US20040080028A1 (en) | Semiconductor device with semiconductor chip mounted in package | |
US20100133674A1 (en) | Compact Semiconductor Package with Integrated Bypass Capacitor and Method | |
US5920119A (en) | Power semiconductor module employing metal based molded case and screw fastening type terminals for high reliability | |
US20050218489A1 (en) | Semiconductor device | |
US20110227207A1 (en) | Stacked dual chip package and method of fabrication | |
US20060151868A1 (en) | Package for gallium nitride semiconductor devices | |
US7045884B2 (en) | Semiconductor device package | |
US4630174A (en) | Circuit package with external circuit board and connection | |
US20050167849A1 (en) | Semiconductor module | |
US20020021560A1 (en) | Gate driver multi-chip module | |
US5783466A (en) | Semiconductor device and method of manufacturing the same | |
US6885097B2 (en) | Semiconductor device | |
US7542318B2 (en) | Capacitor mounting type inverter unit having a recessed cover | |
US6272015B1 (en) | Power semiconductor module with insulation shell support for plural separate substrates | |
US7618896B2 (en) | Semiconductor die package including multiple dies and a common node structure | |
US20070200537A1 (en) | Semiconductor device | |
US7149088B2 (en) | Half-bridge power module with insert molded heatsinks | |
US6793502B2 (en) | Press (non-soldered) contacts for high current electrical connections in power modules |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BNP PARIBAS (FORMERLY KNOWN AS BANQUE NATIONALE DE PARIS);REEL/FRAME:028315/0386 Effective date: 20110128 |
|
AS | Assignment |
Owner name: GLOBAL LED SOLUTIONS, LLC, VIRGINIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL RECTIFIER CORPORATION;REEL/FRAME:029034/0162 Effective date: 20120824 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: INTELLECTUAL DISCOVERY CO., LTD., KOREA, REPUBLIC Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBAL LED SOLUTIONS, LLC;REEL/FRAME:034292/0501 Effective date: 20141126 |