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US20010048151A1 - Stackable ball grid array semiconductor package and fabrication method thereof - Google Patents

Stackable ball grid array semiconductor package and fabrication method thereof Download PDF

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Publication number
US20010048151A1
US20010048151A1 US09922103 US92210301A US2001048151A1 US 20010048151 A1 US20010048151 A1 US 20010048151A1 US 09922103 US09922103 US 09922103 US 92210301 A US92210301 A US 92210301A US 2001048151 A1 US2001048151 A1 US 2001048151A1
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Prior art keywords
conductive
traces
chip
package
supporting
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Granted
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US09922103
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US6407448B2 (en )
Inventor
Dong Chun
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Conversant Intellectual Property Management Inc
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SK Hynix Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73219Layer and TAB connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Description

  • [0001]
    This application is a divisional of application Ser. No. 09/239,152, filed Jan. 28, 1999.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
  • [0004]
    2. Background of the Related Art
  • [0005]
    Currently, there is an effort to produce a highly integrated semiconductor package having a large number of exterior connections. One example is a BGA semiconductor package in which a plurality of solder balls which are attached to a substrate are used as external terminals. In these BGA packages, a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat. The solder balls, which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
  • [0006]
    [0006]FIG. 1 shows a structure of a background art BGA semiconductor package. As seen in FIG. 1, an elastomer 2 is attached to a center portion of an upper surface of a semiconductor chip 1, and a high strength adhesive resin 3 is formed on the elastomer 2. A plurality of metal traces, which transmit electric signals, are formed on the adhesive resin 3. First ends 4 a of the metal traces extend across a top surface of the adhesive resin 3, and second ends 4 b of each of the metal 5 traces are connected to chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1. A solder resist 5 covers the metal traces 4 a and the adhesive resin 3, except for exposed portions of the first ends 4 a of the metal traces, onto which solder balls will be attached. An encapsulant 7, such as a molding resin, covers the upper surface of the semiconductor chip 1, and the portions of the metal 10 traces that are not covered with the solder resist 5. Conductive balls 8 are then attached to the exposed portions of the metal traces to serve as output terminals.
  • [0007]
    Since the conductive balls are exposed on only one side of the package (in FIG. 1, the conductive balls are exposed at the upper surface thereof), it is impossible to fabricate a stackable package of high mount density.
  • SUMMARY OF THE INVENTION
  • [0008]
    It is an object of the present invention to provide a stackable BGA semiconductor package, and a fabrication method thereof, that maintain advantages of the conventional BGA package.
  • [0009]
    A stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein. A plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns. A chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member. An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed. Exterior leads, in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces. A device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip. The supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
  • [0010]
    In a method embodying the invention, a supporting member having a plurality of conductive patterns is first formed. A plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member. A plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member. A method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces. A method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
  • [0011]
    Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    The accompanying drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawing figures, like elements are identified with like reference numerals, and:
  • [0013]
    [0013]FIG. 1 is a vertical cross-sectional diagram of a background art BGA semiconductor package;
  • [0014]
    [0014]FIG. 2 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a first embodiment of the present invention;
  • [0015]
    [0015]FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention;
  • [0016]
    [0016]FIG. 4 is a vertical cross-sectional diagram of stacked BGA semiconductor packages according to the present invention; and
  • [0017]
    [0017]FIGS. 5A through 5H illustrate steps of a method of manufacturing a stackable BGA semiconductor package according to the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0018]
    [0018]FIG. 2 illustrates a stackable BGA semiconductor package according to a first embodiment of the present invention. As shown in FIG. 2, a supporting member 21 includes a supporting plate 23 surrounded by a supporting frame 25 having a predetermined height. Metal traces 24 a are attached to a lower surface of the supporting plate 23. In addition, a solder resist 27 covers portions of the metal traces 24 a and the supporting plate 23 to prevent short circuiting between solder balls and the metal traces, and to protect the metal traces 24 a from outside impacts. The solder resist 27 is partially removed to expose portions of the metal traces 24 a. The exposed portions of the metal traces 24 a act as connecting portions 24 b. The connecting portions 24 b are used to electrically connect the metal traces 24 a to conductive balls that act as external terminals.
  • [0019]
    Metal patterns 26 are formed between upper and lower surfaces of the supporting frame 25. One end of each of the metal patterns 26 is connected with an end of each of the metal traces 24 a. The other end of each of the metal patterns 26 is exposed at the upper surface of the supporting frame 25.
  • [0020]
    A semiconductor chip 1 is attached by an adhesive onto the supporting plate 23 of the supporting member 21. An elastomer 2 is attached to a center portion of the upper surface of the semiconductor chip 1, and a high strength adhesive resin 3 is formed on the elastomer 2. Metal traces which transmit electric signals are attached onto the adhesive resin 3. First ends 4 a of the metal traces extend over the top surface of the adhesive resin. Middle portions 4 b of the metal traces are connected with chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1. Second ends 4 c of the metal traces are connected with upper surfaces of the metal patterns 26 formed in the supporting frame 25.
  • [0021]
    A solder resist 5 covers the upper surface of the adhesive resin 3 and portions of the first ends 4 a of the metal traces. Conductive balls 8 a are attached to the exposed portions of the first ends 4 a of the metal traces. An encapsulant 28, such as a molding resin, covers exposed portions of the upper surface of the semiconductor chip 1, the metal traces, and the upper portion of the supporting frame 25.
  • [0022]
    Electrical signals which are output by the semiconductor chip 1 through the chip pads 6 can be externally transmitted over the conductive balls 8 a connected with the first ends 4 a of the metal traces. The electrical signals can also be externally transmitted through the connecting portions 24 b on the lower part of the supporting member 21, which are connected to the second ends 4 c of the metal traces through the metal patterns 26.
  • [0023]
    [0023]FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention. The second embodiment is the same as the embodiment shown in FIG. 2, except that conductive balls 8 b are also attached to the exposed portions 24 b, of the metal traces 24 a formed on the lower part of the supporting member 21.
  • [0024]
    With each of the embodiments shown in FIGS. 2 and 3, it becomes possible to stack a plurality of BGA semiconductor packages over a single mounting position on a printed circuit board. Thus, the density of the semiconductor devices on a circuit board can be increased by using BGA packages embodying the invention.
  • [0025]
    [0025]FIG. 4 illustrates stacked BGA semiconductor packages using the stackable BGA semiconductor package according to the first embodiment of the present invention shown in FIG. 2. As shown therein, a plurality of stackable BGA semiconductor packages 100, 110, 120, 130 are stacked. Conductive balls 108 a, which are formed on an upper surface of the first package 100, connect the first ends 4 a of the metal traces on the first package 100 to the connecting portions 24 b formed on a lower surface of the second BGA semiconductor package 110. Conductive balls 118 a formed on an upper surface of the second package 110 connect the first ends 4 a of the metal traces on the second package 110 to the connecting portions 24 b on a lower surface of the third BGA semiconductor package 120. Conductive balls 128 a formed on an upper surface of the third package 120 connect the first ends 4 a of the metal traces on the third package 120 to the connecting portions 24 b on a lower surface of the fourth package 130.
  • [0026]
    [0026]FIG. 4 illustrates four stacked BGA packages, but the actual number of stacked BGA packages may be variously adjusted by a user according to his requirements. Conductive balls 138 a formed on the fourth package 130 can serve as external terminals which transmit signals from all the BGA packages to external circuits. For instance, the conductive balls 138 a could be connected to pads of a printed circuit board.
  • [0027]
    A method of fabricating a stackable BGA semiconductor chip package according to the present invention will now be described with reference to FIGS. 5A-5H.
  • [0028]
    In FIG. 5A, first the supporting member 21 is provided. The supporting member 21, includes the supporting plate 23 and the supporting frame 25. Metal traces 24 a are formed on a lower surface of the supporting plate 23. The solder resist 27 covers portions of the metal traces 24 a, but leaves the connecting portions 24 b exposed. The metal patterns 26 formed in the supporting frame 25, are exposed at the upper surface of the supporting frame 25, and are connected with the metal traces 24 a on the bottom of the supporting plate 23.
  • [0029]
    As shown in FIG. 5B, the semiconductor chip 1, which has chip pads 6 on a marginal portion of an upper surface thereof, is connected to a lower surface of an elastomer 2. A high strength adhesive 3 is attached to an upper surface of the elastomer 2. The metal traces are then attached to the upper surface of the adhesive 3. First end portions of each of the metal traces are attached to the adhesive 3, and the other end portions thereof extend from outer sides of the adhesive 3. Next, a layer of the solder resist 5 is formed on the metal traces and on the adhesive resin 3.
  • [0030]
    Next, as shown in FIG. 5C, the semiconductor chip assembly shown in FIG. 5B is attached to the supporting member 21 shown in FIG. 5A.
  • [0031]
    In FIG. 5D, using a bond tool 30, the chip pads 6 formed on the semiconductor chip 1 are connected to the middle portions 4 b of the metal traces by pressing down the middle portions 4 b.
  • [0032]
    As shown in FIG. 5E, second ends 4 c of the metal traces are cut off by the bond tool 30, and the second ends 4 c are connected with upper surfaces of the metal patterns 26 in the supporting frame 25.
  • [0033]
    As shown in FIG. 5F and 5G, a molding resin 28 is molded over the package so that it covers the exposed portions of the metal traces and the exposed portions of the chip 1 and chip pads 6. Next, portions of the solder resist 5 formed on the metal traces is removed to expose portions of the first ends 4 a of the metal traces that will be connected to conductive balls.
  • [0034]
    As shown in FIG. 5G, the conductive balls 8 a are then placed on the exposed portions of the first ends 4 a of the metal traces, and a reflow process is performed to attach the conductive balls 8 a to the metal traces.
  • [0035]
    One BGA package embodying the invention can be attached to a second BGA package embodying the invention by stacking the second package on the first package so that conductive balls on the first package align with corresponding connecting portions on a bottom surface of the second package, and then performing a reflow process to connect the two packages.
  • [0036]
    The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. For example, although metal traces and a conductive region in a semiconductor may not be structural equivalents in that metal traces use metal as an electrical conductor, whereas the conductive region in a semiconductor relies on charge carriers in the material to provide electrical conductivity, in the environment of conducting electricity, metal traces and a conductive region of a semiconductor may be equivalent structures.

Claims (26)

    What is claimed is:
  1. 1. A stackable chip package, comprising:
    a supporting member having a plurality of conductive patterns formed therein;
    a plurality of first conductive traces formed on a first surface of the supporting member, wherein respective ones first conductive traces are electrically coupled to corresponding ones of the conductive patterns;
    a chip having chip pads, wherein the chip is attached to a second surface of the supporting member; and
    a plurality of second conductive traces, wherein portions of the second conductive traces are arranged over the chip, and wherein respective ones of the second conductive traces are electrically coupled to corresponding ones of the chip pads and corresponding ones of the conductive patterns.
  2. 2. The stackable chip package of
    claim 1
    , wherein first ends of the second conductive traces are arranged over the chip, wherein middle portions of respective ones of the second conductive traces are electrically coupled to corresponding chip pads, and wherein second ends of respective ones of the second conductive traces are electrically coupled to corresponding ones of the conductive patterns.
  3. 3. The stackable chip package of
    claim 1
    , further comprising a solder resist covering portions of the plurality of first conductive traces, wherein the solder resist leaves connecting portions of the first conductive traces exposed.
  4. 4. The stackable chip package of
    claim 3
    , further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the first conductive traces, and wherein the plurality of conductive members act as leads of the chip package.
  5. 5. The stackable chip package of
    claim 1
    , further comprising a solder resist covering portions of the plurality of second conductive traces, wherein the solder resist leaves connecting portions of the second conductive traces exposed.
  6. 6. The stackable chip package of
    claim 5
    , further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the second conductive traces, and wherein the plurality of conductive members act as leads of the chip package.
  7. 7. The stackable chip package of
    claim 6
    , wherein the plurality of conductive members are arranged in an array over the chip.
  8. 8. The stackable chip package of
    claim 1
    , further comprising a molding resin that covers portions of the second conductive traces, and portions of the chip.
  9. 9. The stackable chip package of
    claim 1
    , wherein the supporting member comprises a supporting plate and a supporting frame formed at peripheral portions of the supporting plate.
  10. 10. The stackable chip package of
    claim 9
    , wherein the plurality of conductive patterns are formed in the supporting frame.
  11. 11. The stackable chip package of
    claim 1
    , further comprising an elastomer that attaches the plurality of second conductive traces to the chip.
  12. 12. The stackable chip package of
    claim 11
    , wherein an adhesive is interposed between the second conductive traces and the elastomer.
  13. 13. The stackable chip package of
    claim 1
    , wherein the plurality of first conductive traces are arranged on the first surface of the supporting member in substantially the same pattern as the plurality of second conductive traces are arranged over the chip.
  14. 14. A stackable chip package, comprising:
    a supporting member having a plurality of conductive patterns formed therein;
    a chip having chip pads, wherein the chip is attached to a upper surface of the supporting member;
    a plurality of first conductive traces, wherein a first end of each first conductive trace is electrically coupled to a corresponding conductive pattern and a second end of each first conductive trace terminates below said chip;
    a plurality of second conductive traces, wherein a first end of each second conductive trace terminates above said chip, a middle portion of each second conductive trace is electrically coupled to a corresponding chip pad, and a second end of each second conductive trace is electrically coupled to a corresponding conductive pattern.
  15. 15. The stackable chip package of
    claim 14
    , wherein said plurality of first conductive traces is formed on a lower surface of said supporting member.
  16. 16. The stackable chip package of
    claim 14
    , further comprising a solder resist covering portions of the plurality of first conductive traces, wherein the solder resist leaves connecting portions of the first conductive traces exposed.
  17. 17. The stackable chip package of
    claim 16
    , further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the first conductive traces, and wherein the plurality of conductive members act as leads of the chip package.
  18. 18. The stackable chip package of
    claim 14
    , further comprising a solder resist covering portions of the plurality of second conductive traces, wherein the solder resist leaves connecting portions of the second conductive traces exposed.
  19. 19. The stackable chip package of
    claim 18
    , further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the second conductive traces, and wherein the plurality of conductive members act as leads of the chip package.
  20. 20. The stackable chip package of
    claim 19
    , wherein the plurality of conductive members are arranged in an array over the chip.
  21. 21. The stackable chip package of
    claim 14
    , further comprising a molding resin that covers portions of the second conductive traces, and portions of the chip.
  22. 22. The stackable chip package of
    claim 14
    , wherein the supporting member comprises a supporting plate and supporting frame formed at peripheral portions of the supporting plate.
  23. 23. The stackable chip package of
    claim 22
    , wherein the plurality of conductive patterns are formed in the supporting frame.
  24. 24. The stackable chip package of
    claim 14
    , further comprising an elastomer that attaches the plurality of second conductive traces to the chip.
  25. 25. The stackable chip package of
    claim 24
    , wherein an adhesive is interposed between the second conductive traces and the elastomer.
  26. 26. The stackable chip package of
    claim 14
    , wherein the plurality of first conductive traces are arranged on the lower surface of the supporting member in substantially the same pattern as the plurality of second conductive traces are arranged over the chip.
US09922103 1998-05-30 2001-08-06 Stackable ball grid array semiconductor package and fabrication method thereof Active US6407448B2 (en)

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KR20098/1998 1998-05-30
KR19980020098A KR100266693B1 (en) 1998-05-30 1998-05-30 Stackable ball grid array semiconductor package and fabrication method thereof
KR98-20098U 1998-05-30
US09239152 US6291259B1 (en) 1998-05-30 1999-01-28 Stackable ball grid array semiconductor package and fabrication method thereof
US09922103 US6407448B2 (en) 1998-05-30 2001-08-06 Stackable ball grid array semiconductor package and fabrication method thereof

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US20030057535A1 (en) * 2001-09-24 2003-03-27 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US20030141583A1 (en) * 2002-01-31 2003-07-31 Yang Chaur-Chin Stacked package
US6624507B1 (en) * 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US20030189214A1 (en) * 2000-05-09 2003-10-09 National Semiconductor Corporation, A Delaware Corp. Techniques for joining an opto-electronic module to a semiconductor package
US20050013560A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
US20050013581A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Multi-purpose optical light pipe
US20060046436A1 (en) * 2000-09-11 2006-03-02 Shinji Ohuchi Manufacturing method of stack-type semiconductor device
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US20060140534A1 (en) * 2001-08-03 2006-06-29 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US20060278968A1 (en) * 2005-06-13 2006-12-14 Shinko Electric Industries Co., Ltd. Laminated semiconductor package
KR100658734B1 (en) 2004-11-11 2006-12-19 주식회사 유니세미콘 A stack semiconductor package and its manufacture method
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US6407448B2 (en) 2002-06-18 grant
JP3063032B2 (en) 2000-07-12 grant
DE19845316C2 (en) 2002-01-24 grant
US6291259B1 (en) 2001-09-18 grant
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KR100266693B1 (en) 2000-09-15 grant
DE19845316A1 (en) 1999-12-02 application

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