US20010045611A1 - Via plug adapter - Google Patents

Via plug adapter Download PDF

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Publication number
US20010045611A1
US20010045611A1 US09141217 US14121798A US2001045611A1 US 20010045611 A1 US20010045611 A1 US 20010045611A1 US 09141217 US09141217 US 09141217 US 14121798 A US14121798 A US 14121798A US 2001045611 A1 US2001045611 A1 US 2001045611A1
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Patent type
Prior art keywords
surface
solder
plug
via
circuit
Prior art date
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Granted
Application number
US09141217
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US6400018B2 (en )
Inventor
William J. Clatanoff
Gayle R.T Schueller
Robert J. Schubert
Yusuke Saito
Hideo Yamazaki
Hideaki Yasui
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3M Innovative Properties Co
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3M Innovative Properties Co
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Other shape and layout details not provided for in H05K2201/09009 - H05K2201/09209; Shape and layout details covering several of these groups
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10681Tape Carrier Package [TCP]; Flexible sheet connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/613Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control involving the assembly of several electronic elements

Abstract

A circuit includes a substrate having a dielectric layer with a first surface and a second surface. A conductive layer is formed on the first surface. A beveled via is formed in a dielectric layer of the substrate. The via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width. A conductive plug is connected to the conductive layer. The plug is formed in the via and extends from adjacent the first opening toward the second opening, and terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.

Description

    BACKGROUND
  • [0001]
    The disclosures herein relate generally to solder ball electronic interconnections and more particularly to a via plug adapter for strengthening a solder ball connection in a beveled via.
  • [0002]
    Vertical interconnects between circuit layers is well known. U.S. Pat. No. 3,541,222 discloses a connector screen for interconnecting aligned electrodes of adjacent circuit boards or modules. The connector screen comprises a matrix of spaced conductive connector elements embedded in a supporting non-conducting material with the conductive connector elements protruding from both sides thereof. The size and spacing of the connector elements are chosen so that the connector screen can be disposed between the circuit boards or modules to provide the required interconnections between the electrodes without requiring alignment of the connector screen with respect to the boards or modules. A preferred method of making the connector screen involves forming a conductive mold having a grid pattern of ridges in a non-conductive base. Conductive material is then cast between the ridges of the mold, following which selected portions of the mold are removed to form a web of non-conductive material supporting a matrix of spaced conducting elements protruding from both sides of the web.
  • [0003]
    U.S. Pat. No. 4,830,264 describes a method of forming solder terminals for a pinless module, preferably for a pinless metallized ceramic module. The method is comprised of the following steps: forming a substrate having a pattern of conductors formed onto its top surface and preformed via-holes extending from the top to bottom surface; applying a droplet of flux at at least one of the preformed via-hole openings of the bottom surface of the substrate to fill the via-holes with flux by capillarity and form a glob of flux at the bottom openings; applying a solder preform, i.e. solder balls on each glob of flux to which it will adhere, the volume of the preform being substantially equal to the inner volume of the via-hole plus the volume of the bump to be formed; heating to cause solder reflow of the solder preform to fill the via-hole and the inner volume of the eyelet with solder; and, cooling below the melting point of the solder so that the molten solder solidifies to form solder terminals at the via-hole locations while forming solder columns in the via-holes. The resultant pinless metallized ceramic module has connections between the I/O's of the module interfacing with the next level of packaging (i.e., printed circuit boards), that consist of integral solder terminals. Each integral solder terminal comprises a column in the vias of the metallized ceramic substrate, a mound of solder at the top surface of the substrate and spherical solder bumps on the bottom level for making interconnections with the next level of packaging.
  • [0004]
    In U.S. Pat. No. 5,401,913, a multi-layer circuit board includes electrical interconnections between adjacent circuit board layers of the multi-layer board. A via hole is provided through a circuit board layer. The via hole is filled with a via metal. The via metal is plated with a low melting point metal. An adhesive film is deposited over the circuit board layer. Adjacent layers of the multi-layer circuit board are stacked and aligned together. The layers are laminated under heat and pressure. The low melting point metal provides an electrical interconnection between adjacent layers.
  • [0005]
    U.S. Pat. No. 5,491,303 discloses an interposer for connecting two or more printed circuit boards comprising a circuit-carrying substrate with two or more solder pads on each of two sides. Each of the solder pads are connected to an electrically conductive via in the substrate, providing electrical interconnection from one side to the other side. Each solder pad has a solder bump on it. A circuit assembly is made by soldering the solder bumps on one side of the interposer to corresponding solder pads on a printed circuit board. The solder bumps on the other side of the interposer are likewise soldered to the corresponding solder pads of a second printed circuit board.
  • [0006]
    U.S. Pat. No. 5,600,884 describes an electrical connecting member, one surface of which is connected to a connecting section of a first electrical circuit member and another surface of which is connected to a connecting section of a second electrical circuit member. The electrical connecting member includes a holding member formed of an electrically insulative member. The holding member has a plurality of recess holes. The connecting member also includes a plurality of electrically conductive members provided in the electrically insulative member, insulated from each other. One end of the electrically conductive members is exposed on one surface of the holding member to be connected to the connecting section of the first electrical circuit member. Another end of the electrically conductive members is exposed on another surface of the holding member to be connected to the connecting section of the second electrical circuit member.
  • [0007]
    U.S. Pat. No. 5,726,497 discloses a method of manufacture of a semiconductor device on a silicon semiconductor substrate which comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer, exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.
  • [0008]
    U.S. Pat. No. 5,757,078 discloses a semiconductor device including a semiconductor chip having electrode pads, a package composed of a plurality of insulating films and adhered to the semiconductor chip by an adhesive agent. The package includes wiring patterns interposed between the plurality of insulating films. The wiring patterns are selectively connected to the electrode pads at one end, and to the plurality of electrically conductive protrusions at the other end, by means of via-holes. The semiconductor device further includes a plurality of electrically conductive protrusions extending from the outermost wiring patterns by way of the via-holes provided in the outermost insulating film.
  • [0009]
    Japanese Application JP 10-41356 discloses a tape carrier that is used as the bonding medium when semiconductor elements are bonded to the outer part of a substrate board for a BGA application. An insulating film includes vias having straight or non-tapered walls. A conductive land is formed in the vias and solder balls have one side engaged with the lands inside of the vias. The remainder of each solder ball protrudes from the insulating film.
  • [0010]
    The use of flexible circuitry in IC packaging has been a growing trend for many years where the use of via connections through the flexible circuit dielectric have been employed in Tape Ball Grid Array (TBGA) IC packaging applications and recently, into Chip Scale Packaging (CSP) applications. In Ball Grid Array (BGA) applications, the via interconnection traditionally uses a solder ball reflowed first to connect to the flexible circuitry through the via, then second, reflowed onto the printed circuit board with conventional surface mount assembly practices.
  • [0011]
    This solder ball connection must make a reliable electronic interconnect from the flexible circuitry to the printed circuit board. This reliability is often directly related to the area of the solder connection to the flexible circuitry, as a common failure mode of this interconnection is the solder ball shearing through the solder material at the point of the minimum cross sectional area. Therefore, larger vias are desirable to increase the area in which shear stress is distributed to meet minimum solder ball interconnection reliability requirements.
  • [0012]
    Conversely, the demand for smaller electronic packages and higher input/output (I/O's) requires increased routing density, including smaller via sizes to allow electronic traces to route between solder ball via areas. Smaller vias require smaller via capture pads, thus, allowing more space to route electronic traces between printed circuit board interconnection vias.
  • [0013]
    Traditionally, vias in the dielectric are made by punching, leaving a via through the dielectric with straight walls. Other methods include chemically dissolving the dielectric and laser drilling to expose the metal conductor of the flexible circuitry. Direct solder ball attachment to any of these via methods controls the solder ball interconnection reliability by means of the via size, such that, vias typically have to be larger than 0.200 mm in diameter to meet minimum reliability requirements for the electronic package.
  • [0014]
    Therefore, what is needed is an apparatus and a method for providing a strong and reliable solder ball connection to flexible circuitry with small diameter vias and via capture pads so as to permit more space in which to route more electronic traces.
  • SUMMARY
  • [0015]
    One embodiment, accordingly, provides a strength enhanced solder ball connection to flexible circuitry with small diameter vias which improves the routability of the flexible circuit to address higher I/O and finer pitch flex based BGA packaging applications. To this end, a circuit comprises a substrate including a dielectric layer having a first surface and a second surface. A conductive layer is on the first surface. A beveled via is formed in the dielectric layer and has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, greater than the first width. A conductive plug is formed in the via, connected to the conductive layer, and extends from adjacent the first opening toward the second opening. The plug terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.
  • [0016]
    A principal advantage of this embodiment is that the via adapter plug enables a reliable solder ball connection to flexible circuitry with small (less than 0.200 mm diameter) vias. Using the via plug adapter concept, solder ball interconnection reliability does not have to be compromised to accommodate the routing requirements of high I/O, fine pitch flex based IC packaging applications. Using common design rules for flexible circuitry, a smaller via allows for a smaller via capture pad, thus, more space between via capture pads in which to route electronic traces.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0017]
    [0017]FIG. 1 is a side view illustrating an embodiment of a substrate interconnected to a circuit board by a plurality of solder balls.
  • [0018]
    [0018]FIG. 1A is a top view illustrating a circular via opening.
  • [0019]
    [0019]FIG. 1B is a top view illustrating an oblong via opening.
  • [0020]
    [0020]FIG. 2 is a side view illustrating an embodiment of a plug in a tapered via.
  • [0021]
    [0021]FIG. 3 is another side view illustrating an embodiment of a plug in a tapered via.
  • [0022]
    [0022]FIG. 4 is another side view illustrating an embodiment of a plug in a tapered via.
  • [0023]
    [0023]FIG. 5 is a side view illustrating an embodiment of a substrate interconnected to a circuit board by a solder ball.
  • [0024]
    [0024]FIG. 6 is a side view illustrating an embodiment of a two-layered substrate interconnected to a circuit board by solder ball.
  • [0025]
    [0025]FIG. 7 is a side view illustrating an embodiment of a chip scale package including an IC chip connected to a substrate.
  • [0026]
    [0026]FIG. 8 is a view of the substrate taken along line 8-8 of FIG. 7.
  • DETAILED DESCRIPTION
  • [0027]
    According to one embodiment, FIG. 1, a flexible circuit 10 comprises a substrate 12 formed of a flexible dielectric material. The substrate 12 is of a polymer or other suitable material having a thickness T1 of from about 0.5 mils to about 5.0 mils. The polymer may be a polyimide, a polyester, or other known polymers for electronic applications. Substrate 12 also includes a first surface 14 and a second opposite surface 16. A conductive layer 18, of copper, gold plated copper, gold or other suitable material, is formed on first surface 14 and includes a plurality of conductive capture pads 20 and a plurality of conductive traces 22 routed between the capture pads 20.
  • [0028]
    A plurality of beveled vias 24 are formed in substrate 12. Each via 24 has a first opening 26 of a first width W1, in first surface 14, and a second opening 28 of a second width W2, in the second surface 16. Second width W2 is greater than first width W1. Beveled via 24 includes a sidewall 30 which is sloped away from first surface 14 at an angle α of from about 20 degrees to about 80 degrees, and preferably at an angle of from about 20 degrees to about 45 degrees. First opening 26 is circular, FIG. 1A, or oblong, FIG. 1B or may be of another suitable shape and first width W1 is from about 0.05 mm to about 0.5 mm.
  • [0029]
    A conductive plug 32, FIGS. 1 and 2 is formed in beveled via 24, and extends from a first plug interface surface 34, adjacent first opening 26, toward the second opening 28. Plug 32 terminates adjacent the second opening 28 at a second plug interface surface 36. The first plug interface surface 34 is connected to conductive capture pad 20. The second plug interface surface 36 is of a dome shape. Second plug interface surface 36 may be formed to terminate between first surface 14 and second surface 16, may be formed such that a portion of the dome extends outwardly from the second surface 16, FIG. 3, or may be formed such that the entire dome-like surface extends outwardly from the second surface 16, FIG. 4. Thus, a range of plug thickness or height T2 extending from first plug interface surface 34 to second plug interface surface 36 may vary, but is at least 5 microns, FIG. 2.
  • [0030]
    A conductive solder ball 38, FIG. 5, is connected to second plug interface surface 36 at a first solder ball surface 40, and protrudes from second substrate surface 16. Solder ball 38 terminates at a second solder ball surface 42 which may engage a printed circuit board 44. Plug 32 and solder ball 38 may be formed of various suitable materials. For example, plug 32 may be formed of a high temperature tin-lead solder engaged with solder ball 38 formed of a eutectic tin-lead solder. Also, plug 32 may be formed of copper engaged with solder ball 38 formed of a tin-lead solder. Other combinations may be used which meet the conductivity requirement and meet the condition that they provide the plug material of a stronger shear strength than the solder ball material. As a further example, plug 32 may be formed of nickel engaged with solder ball 38 formed of a tin-lead solder. In addition, for improved bonding, an interface coating 46 may be provided between capture pads 20 and first plug interface surface 34. Coating 46 may be formed of a suitable material selected from gold, paladium and nickel-gold. Furthermore, bonding between plug 32 and solder ball 38 may be improved by another interface coating 48 therebetween. Coating 48 may be formed of a suitable material also selected from gold, paladium and nickel-gold.
  • [0031]
    Beveled vias 24, FIG. 1, are spaced apart in a side-by-side configuration. Capture pads 20 are formed at each first opening 26. Therefore, capture pads 20 are also spaced apart in a side-by-side configuration. Spacing between vias 24 is of a center-to-center distance D of from about 0.25 mm to about 1.27 mm. This spacing permits at least three traces 22 to pass between side-by-side capture pads 20.
  • [0032]
    In FIG. 6, circuit 10 includes a substrate including a first dielectric layer 12 a and a second dielectric layer 13. First dielectric layer 12 a includes a first surface 14 a and a second surface 16 a. A conductive layer 18 a is provided on first surface 14 a between first dielectric layer 12 a and second dielectric layer 13. A beveled via 24 is formed in first dielectric layer 12 a as described and referred to above. Also, the second dielectric layer 13 may be formed of a polymer material as described above. One of the layers 12 a and 13 may be provided as a cover coat for the other layer.
  • [0033]
    Well known tape ball grid array (TBGA) package typically includes a substrate having an integrated circuit (IC) mounted in a cavity that is surrounded by an array of vias. Leads from the IC interconnect to the vias. One embodiment herein, FIGS. 7 and 8, discloses a substantial improvement such that the substrate is substantially of the same surface area as the IC. This is possible due to the reduced size openings of the tapered vias as described above. Thus, the advantages provided by the reduced size openings permits increased trace routing between the vias. Also, the opposite or larger via openings provide increased surface contact to improve solder ball shear strength. The chip scale package 100, FIG. 7, includes a substrate 112 having a first surface 114 and a second surface 116. A surface area A1 of first surface 114 is substantially the same as a second surface area A2 of an IC 150 mounted on substrate 112. A conductive layer 118 on portions of first surface 114 area is connected to IC 150 by leads 152. An adhesive layer 155 on surface 114 of substrate 112, and an adhesive layer 157 on IC 150 are interconnected by an interposer layer 154 therebetween. The interposer layer 154 may, for example, be a compliant material such as a foam or elastomeric material, or a non-compliant material such as a ceramic or a copper sheet. Substrate 112 includes a plurality of beveled vias 124, as described above. Each via includes a first opening 126 in first surface 114 and a second opening 128 in second surface 116. The second width being greater than the first width as herein described. A plug 132 is provided in each via to extend from adjacent the first opening 126 to adjacent the second opening 128 and terminating at a plug interface surface 136. A conductive solder ball 138 is connected to the plug interface surface 136 and extends to protrude from second surface 116 for connection to a printed circuit board 144. Thus, a plurality of solder balls 138 provide an array which is uniform across second surface 116 of substrate 112, without interruption by a commonly heretofore known space required for mounting an IC package on opposite surface 114.
  • [0034]
    As it can be seen, the principal advantages of these embodiments are that the via plug adapter enables a reliable solder ball connection to flexible circuitry with small (less than 0.200 mm diameter) vias. Using the via plug adapter concept, solder ball interconnection reliability does not have to be compromised to accommodate the routing requirements of high I/O, fine pitch flex based IC packaging applications. Using common design rules for flexible circuitry, a smaller via allows for a smaller via capture pad, thus, more space between via capture pads in which to route electronic traces. As an example, using a via plug adapter in a 0.085 mm diameter beveled via, 4 traces can be routed between capture pads with similar solder ball interconnection reliability as with 0.300 mm diameter vias that only allow routing of a single trace.
  • [0035]
    The foregoing describes a flexible circuit with a z-axis via interconnection between fine feature flexible circuitry and gross feature printed circuit board solder ball pads using traditional solder balls with the novel use of a via plug adapter. One such application of this via plug adapter is the flexible circuit application in IC packaging for BGA to printed circuit board interconnection.
  • [0036]
    The via plug adapter is a metal plug additively plated into a beveled via. In addition to forming the plug using an additive plating process, a process such as solder reflow could be used to form the via plug. This via plug adapter is a frustum (the solid of a cone between two parallel planes) shaped metal feature with a slight dome shape at the second interface surface. As the z-direction thickness of the frustum grows within the beveled via, the surface area for traditional solder ball attachment grows dramatically creating a mechanical adapter allowing small vias to have similar solder ball interconnection reliability as with large via applications.
  • [0037]
    Allowing small vias in the flexible circuit improves the routability of the flexible circuit to address higher 1/0 and finer pitch flex based BGA packaging applications.
  • [0038]
    As a result, one embodiment provides a circuit comprising a substrate including a dielectric layer having a first surface and a second surface. A conductive layer is on the first surface. A beveled via is formed in the dielectric layer. The via has a first opening of a first width in the first surface and a second opening of a second width, in the second surface, greater than the first width. A conductive plug is connected to the conductive layer and is formed in the via and extends from adjacent the first opening toward the second opening. The plug terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface, and extends to protrude from the second surface.
  • [0039]
    Another embodiment provides a circuit comprising a substrate including a dielectric layer having a first surface and a second surface. A conducted layer is on the first surface. A beveled via is formed in the dielectric layer. The via has a first opening of a first width in the first surface and a second opening of a second width in the second surface, greater than the first width. A conductive plug is connected to the conductive layer and is formed in the via and extends from adjacent the first opening toward the second opening. The plug terminates adjacent the second opening at a plug interface surface. A conductive solder ball has a first solder ball surface connected to the plug interface surface. The solder ball extends to protrude from the second surface and terminates at a second solder ball surface. A printed circuit board is engaged with the second solder ball surface.
  • [0040]
    In still another embodiment, a circuit comprises a substrate including a dielectric layer having a first surface and a second surface. A pair of side-by-side beveled vias are formed in the dielectric layer. Each via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, greater than the first width. Each via includes a conductive plug having a first plug interface surface adjacent the first opening. Each plug extends from adjacent the first plug interface surface toward the second opening. Each plug terminates adjacent the second opening at a second plug interface surface. A conductive solder ball is formed at each via and has a first solder ball surface engaged with its respective second plug interface surface, and extends to protrude from the second surface. Each solder ball terminates at a second solder ball surface. A printed circuit board is engaged with the second solder ball surface. A conductive capture pad layer is engaged with the first interface surface of each plug to form side-by-side, spaced apart, capture pad layers. A plurality of conductive traces extend between the side-by-side capture pad layers.
  • [0041]
    A further embodiment provides a method of attaching a solder ball to a via in a flexible circuit substrate. This is accomplished by forming a beveled via in the flexible circuit substrate having a first surface and a second surface. A first via opening is formed in the first surface and has a first width. A second via opening is formed in the second surface and has a second width, greater than the first width. A conductive layer is formed at the first opening. A conductive plug is formed in the beveled via connected to the conductive layer so that the plug extends from adjacent the first surface toward the second surface. The plug terminates at a plug interface surface adjacent the second surface. A conductive solder ball is engaged with the plug interface surface. The solder ball extends to protrude from the second surface.
  • [0042]
    Although illustrative embodiments have been shown and described, a wide range of modifications, change and substitution is contemplated in the foregoing disclosure and in some instances, some features of the embodiments may be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein.

Claims (32)

    What is claimed is:
  1. 1. A circuit comprising:
    a substrate including a dielectric layer having a first surface and a second surface;
    a conductive layer on the first surface;
    a beveled via formed in the dielectric layer, the via having a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width;
    a conductive plug connected to the conductive layer, the plug being formed in the via, and extending from adjacent the first opening toward the second opening, and terminating adjacent the second opening at a plug interface surface; and
    a conductive solder ball connected to the plug interface surface and extending to protrude from the second surface.
  2. 2. The circuit as defined in
    claim 1
    wherein the dielectric layer and conductive layer form a flexible circuit.
  3. 3. The circuit as defined in
    claim 2
    wherein the dielectric layer is formed of a polymer material.
  4. 4. The circuit as defined in
    claim 3
    wherein the polymer material is polyimide.
  5. 5. The circuit as defined in
    claim 4
    wherein the polymer material has a thickness of from about 0.5 mils to about 5.0 mils.
  6. 6. The circuit as defined in
    claim 3
    wherein the polymer material is a polyester.
  7. 7. The circuit as defined in
    claim 2
    wherein the beveled via has a sidewall sloped away from the first surface at an angle of from about 20 degrees to about 80 degrees.
  8. 8. The circuit as defined in
    claim 2
    wherein the beveled via has a sidewall sloped away from the first surface at an angle of from about 20 degrees to about 45 degrees.
  9. 9. The circuit as defined in
    claim 2
    wherein the first opening is circular.
  10. 10. The circuit as defined in
    claim 2
    wherein the first opening is oblong.
  11. 11. The circuit as defined in
    claim 9
    wherein the first width is from about 0.05 mm to about 0.5 mm.
  12. 12. The circuit as defined in
    claim 2
    wherein the plug interface surface forms a dome.
  13. 13. The circuit as defined in
    claim 12
    wherein the dome is between the first surface and the second surface.
  14. 14. The circuit as defined in
    claim 12
    wherein a portion of the dome extends outwardly from the second surface.
  15. 15. The circuit as defined in
    claim 12
    wherein the entire dome extends outwardly from the second surface.
  16. 16. The circuit as defined in
    claim 2
    wherein the plug has a thickness dimension extending from the first surface to the dome, the thickness dimension being at least 5 microns.
  17. 17. The circuit as defined in
    claim 2
    wherein the plug is formed of a high temperature tin-lead solder, and the solder ball is formed of a eutectic tin-lead solder.
  18. 18. The circuit as defined in
    claim 2
    wherein the ball is formed of a tin-lead solder and the plug is formed of copper and has a stronger shear strength than the tin-lead solder.
  19. 19. The circuit as defined in
    claim 2
    wherein the ball is formed of a tin-lead solder and the plug is formed of nickel and has a stronger shear strength than the tin-lead solder.
  20. 20. The circuit as defined in
    claim 2
    wherein the conductive layer is formed of copper.
  21. 21. The circuit as defined in
    claim 2
    wherein the conductive layer is formed of gold plated copper.
  22. 22. The circuit as defined in
    claim 2
    wherein the conductive layer is formed of gold.
  23. 23. The circuit as defined in
    claim 20
    further comprising:
    an interface coating between the conductive layer and the plug, the coating being selected from the group consisting of gold, paladium and nickel-gold.
  24. 24. The circuit as defined in
    claim 23
    further comprising:
    an interface coating between the interface surface of the plug and the ball, the coating being selected from the group consisting of gold, paladium and nickel-gold.
  25. 25. A circuit comprising:
    a substrate including a dielectric layer having a first surface and a second surface;
    a conductive layer on the first surface;
    a beveled via formed in the dielectric layer, the via having a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width;
    a conductive plug connected to the conductive layer, the plug being formed in the via and extending from adjacent the first opening toward the second opening, and terminating adjacent the second opening at a plug interface surface;
    a conductive solder ball having a first solder ball surface connected to the plug interface surface, and extending to protrude from the second surface, the solder ball terminating at a second solder ball surface; and
    a printed circuit board engaged with the second solder ball surface.
  26. 26. A circuit comprising:
    a substrate including a dielectric layer having a first surface and a second surface;
    a pair of side-by-side beveled vias formed in the dielectric layer, each via having a first opening of a first width in the first surface and a second opening of a second width in the second surface, the second width being greater than the first width;
    each via including a conductive plug having a first plug interface surface adjacent the first opening, each plug extending from adjacent the first plug interface toward the second opening, each plug terminating adjacent the second opening at a second plug interface surface;
    a conductive solder ball formed at each via, each solder ball having a first solder ball surface engaged with its respective second plug interface surface, and extending to protrude from the second surface, each solder ball terminating at a second solder ball surface;
    a printed circuit board engaged with the second solder ball surface;
    a conductive capture pad layer engaged with the first interface surface of each plug to form side-by-side, spaced apart capture pad layers; and
    a plurality of conductive traces extending between the side-by-side capture pad layers.
  27. 27. The circuit as defined in
    claim 26
    wherein the first width is from about 0.05 mm to about 0.5 mm.
  28. 28. The circuit as defined in
    claim 27
    wherein the pair of side-by-side beveled vias have a center-to-center distance therebetween of from about 0.25 mm to about 1.27 mm.
  29. 29. The circuit as defined in
    claim 28
    wherein the plurality of conductive traces includes at least three traces.
  30. 30. A method of attaching a solder ball to a via in a flexible circuit substrate comprising the steps of:
    forming a beveled via in the flexible substrate, the substrate having a first surface and a second surface;
    forming a first opening of the via in the first surface having a first width, and forming a second opening of the via in the second surface having a second width, greater than the first width;
    forming a conductive layer at the first opening;
    forming a conductive plug in the beveled via connected to the conductive layer so that the plug extends from adjacent the first surface toward the second surface;
    terminating the plug at a plug interface surface adjacent the second surface;
    forming a conductive solder ball engaged with the plug interface surface; and
    extending the solder ball to protrude from the second surface.
  31. 31. A circuit comprising:
    a substrate including a first dielectric layer and a second dielectric layer, the first dielectric layer having a first surface and a second surface;
    a conductive layer on the first surface, between the first and second dielectric layers;
    a beveled via formed in the first dielectric layer, the via having a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width;
    a conductive plug connected to the conductive layer, the plug being formed in the via, and extending from adjacent the first opening toward the second opening and terminating adjacent the second opening at a plug interface surface; and
    a conductive solder ball connected to the plug interface surface and extending to protrude from the second surface.
  32. 32. A chip scale package comprising:
    a substrate including a dielectric layer having a first surface of a first surface area and a second surface;
    a conductive layer on portions of the first surface area;
    an integrated circuit mounted on the first surface area, the integrated circuit having a surface area substantially the same size as the first surface area, the integrated circuit being electrically connected to the conductive layer;
    an array of beveled vias formed in the dielectric layer, each via having an opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width;
    a conductive plug formed in the vias and connected to the conductive layer, the plug extending from adjacent the first opening toward the second opening, and terminating adjacent the second opening at a plug interface surface; and
    a conductive solder ball connected to the plug interface surface and extending to protrude from the second surface.
US09141217 1998-08-27 1998-08-27 Via plug adapter Active US6400018B2 (en)

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US09141217 US6400018B2 (en) 1998-08-27 1998-08-27 Via plug adapter

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US09141217 US6400018B2 (en) 1998-08-27 1998-08-27 Via plug adapter
CA 2338550 CA2338550A1 (en) 1998-08-27 1999-01-15 Through hole bump contact
JP2000568124A JP3898891B2 (en) 1998-08-27 1999-01-15 Via-plug adapter
CN 99810060 CN1192429C (en) 1998-08-27 1999-01-15 line
KR20017002416A KR100367126B1 (en) 1998-08-27 1999-01-15 Through hole bump contact
PCT/US1999/000179 WO2000013232A1 (en) 1998-08-27 1999-01-15 Through hole bump contact
EP19990904023 EP1118119A1 (en) 1998-08-27 1999-01-15 Through hole bump contact
US10132960 US6864577B2 (en) 1998-08-27 2002-04-26 Via plug adapter

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US20010045611A1 true true US20010045611A1 (en) 2001-11-29
US6400018B2 US6400018B2 (en) 2002-06-04

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US10132960 Expired - Fee Related US6864577B2 (en) 1998-08-27 2002-04-26 Via plug adapter

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EP (1) EP1118119A1 (en)
JP (1) JP3898891B2 (en)
KR (1) KR100367126B1 (en)
CN (1) CN1192429C (en)
CA (1) CA2338550A1 (en)
WO (1) WO2000013232A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121695A1 (en) * 2000-05-11 2002-09-05 Stephenson William R. Molded ball grid array
US7544304B2 (en) 2006-07-11 2009-06-09 Electro Scientific Industries, Inc. Process and system for quality management and analysis of via drilling
US20100044092A1 (en) * 2008-08-20 2010-02-25 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US7886437B2 (en) 2007-05-25 2011-02-15 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
US9231357B1 (en) * 2013-09-30 2016-01-05 Emc Corporation Mid-plane assembly
US20160056125A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Interconnect for Chip Stacking
CN105636365A (en) * 2014-10-27 2016-06-01 健鼎(无锡)电子有限公司 Adapter plate manufacturing method
US9754830B2 (en) 2012-07-20 2017-09-05 Fujitsu Limited Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400018B2 (en) * 1998-08-27 2002-06-04 3M Innovative Properties Company Via plug adapter
US6462414B1 (en) * 1999-03-05 2002-10-08 Altera Corporation Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad
JP3844936B2 (en) 1999-03-26 2006-11-15 富士通株式会社 Semiconductor device
US6507118B1 (en) 2000-07-14 2003-01-14 3M Innovative Properties Company Multi-metal layer circuit
US6377475B1 (en) 2001-02-26 2002-04-23 Gore Enterprise Holdings, Inc. Removable electromagnetic interference shield
US6744640B2 (en) 2002-04-10 2004-06-01 Gore Enterprise Holdings, Inc. Board-level EMI shield with enhanced thermal dissipation
JP2003318545A (en) * 2002-04-22 2003-11-07 Sony Corp Multilayer printed wiring board and its manufacturing method
KR100481216B1 (en) * 2002-06-07 2005-04-08 엘지전자 주식회사 Ball Grid Array Package And Method Of Fabricating The Same
US20040099716A1 (en) * 2002-11-27 2004-05-27 Motorola Inc. Solder joint reliability by changing solder pad surface from flat to convex shape
US7060624B2 (en) * 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP2005175128A (en) * 2003-12-10 2005-06-30 Fujitsu Ltd Semiconductor device and manufacturing method thereof
US7446399B1 (en) 2004-08-04 2008-11-04 Altera Corporation Pad structures to improve board-level reliability of solder-on-pad BGA structures
US7267861B2 (en) * 2005-05-31 2007-09-11 Texas Instruments Incorporated Solder joints for copper metallization having reduced interfacial voids
US7382049B2 (en) * 2005-08-30 2008-06-03 Via Technologies, Inc. Chip package and bump connecting structure thereof
DE102005055280B3 (en) * 2005-11-17 2007-04-12 Infineon Technologies Ag Connecting elements for semiconductor components have mushroom shape with first metal area filling out indentations on top of insulating layer and with second metal area on containing refractory inter-metallic phases of metals of solder
JP5010948B2 (en) * 2007-03-06 2012-08-29 オリンパス株式会社 Semiconductor device
US7892441B2 (en) * 2007-06-01 2011-02-22 General Dynamics Advanced Information Systems, Inc. Method and apparatus to change solder pad size using a differential pad plating
JP5501562B2 (en) * 2007-12-13 2014-05-21 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Semiconductor device
JPWO2009122912A1 (en) * 2008-03-31 2011-08-04 三洋電機株式会社 Solder structure, a method of forming a solder structure, the semiconductor module including solder structure, and the portable device
US9107315B2 (en) * 2008-10-31 2015-08-11 Princo Middle East Fze Via structure in multi-layer substrate
US8377506B2 (en) * 2008-12-29 2013-02-19 Advanced Semiconductor Engineering, Inc. Method of manufacturing a substrate structure
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
JP5195821B2 (en) * 2010-06-03 2013-05-15 株式会社村田製作所 A method of manufacturing an electronic device
US8492893B1 (en) * 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
CN103117262A (en) * 2011-11-16 2013-05-22 东琳精密股份有限公司 Electrical device with connection interface, circuit board thereof, and method for manufacturing the same
CN107393899A (en) * 2013-06-11 2017-11-24 肖亚波 Chip package substrate

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541222A (en) 1969-01-13 1970-11-17 Bunker Ramo Connector screen for interconnecting adjacent surfaces of laminar circuits and method of making
JPS6049652A (en) * 1983-08-29 1985-03-18 Seiko Epson Corp Manufacture of semiconductor element
EP0263222B1 (en) 1986-10-08 1992-03-25 International Business Machines Corporation Method of forming solder terminals for a pinless ceramic module
JPH03250628A (en) * 1990-02-28 1991-11-08 Hitachi Ltd Semiconductor device
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
EP0501357B1 (en) 1991-02-25 2003-06-04 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
JP3057130B2 (en) * 1993-02-18 2000-06-26 三菱電機株式会社 Resin sealed semiconductor package and a manufacturing method thereof
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US5491303A (en) 1994-03-21 1996-02-13 Motorola, Inc. Surface mount interposer
US5385868A (en) 1994-07-05 1995-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Upward plug process for metal via holes
JP2595909B2 (en) 1994-09-14 1997-04-02 日本電気株式会社 Semiconductor device
JPH08148603A (en) 1994-11-22 1996-06-07 Nec Kyushu Ltd Ball grid array type semiconductor device and manufacture thereof
JP2763020B2 (en) 1995-04-27 1998-06-11 日本電気株式会社 Semiconductor package and semiconductor device
JP3015712B2 (en) 1995-06-30 2000-03-06 日東電工株式会社 A film carrier and a semiconductor device using the same
JP3176542B2 (en) * 1995-10-25 2001-06-18 シャープ株式会社 Semiconductor device and manufacturing method thereof
US5945741A (en) * 1995-11-21 1999-08-31 Sony Corporation Semiconductor chip housing having a reinforcing plate
JP3238074B2 (en) 1996-07-25 2001-12-10 日立電線株式会社 Tape carrier for semiconductor device
DE19702014A1 (en) 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chip module and to methods for producing a chip module
US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US6114763A (en) * 1997-05-30 2000-09-05 Tessera, Inc. Semiconductor package with translator for connection to an external substrate
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US6400018B2 (en) * 1998-08-27 2002-06-04 3M Innovative Properties Company Via plug adapter

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121695A1 (en) * 2000-05-11 2002-09-05 Stephenson William R. Molded ball grid array
US7544304B2 (en) 2006-07-11 2009-06-09 Electro Scientific Industries, Inc. Process and system for quality management and analysis of via drilling
US20090179017A1 (en) * 2006-07-11 2009-07-16 Electro Scientific Industries, Inc. Process and system for quality management and analysis of via drilling
US8501021B2 (en) 2006-07-11 2013-08-06 Electro Scientific Industries, Inc. Process and system for quality management and analysis of via drilling
US20110131807A1 (en) * 2007-05-25 2011-06-09 Electro Scientific Industries, Inc. Process for Forming an Isolated Electrically Conductive Contact Through a Metal Package
US7886437B2 (en) 2007-05-25 2011-02-15 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
US8117744B2 (en) 2007-05-25 2012-02-21 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
US20110147067A1 (en) * 2008-08-20 2011-06-23 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US7943862B2 (en) 2008-08-20 2011-05-17 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US20100044092A1 (en) * 2008-08-20 2010-02-25 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US8729404B2 (en) 2008-08-20 2014-05-20 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US8735740B2 (en) 2008-08-20 2014-05-27 Electro Scientific Industries, Inc. Method and apparatus for optically transparent via filling
US9754830B2 (en) 2012-07-20 2017-09-05 Fujitsu Limited Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device
US9231357B1 (en) * 2013-09-30 2016-01-05 Emc Corporation Mid-plane assembly
US20160056125A1 (en) * 2014-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Interconnect for Chip Stacking
US9935081B2 (en) * 2014-08-20 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect for chip stacking
CN105636365A (en) * 2014-10-27 2016-06-01 健鼎(无锡)电子有限公司 Adapter plate manufacturing method

Also Published As

Publication number Publication date Type
WO2000013232A1 (en) 2000-03-09 application
JP2002524857A (en) 2002-08-06 application
CA2338550A1 (en) 2000-03-09 application
CN1315055A (en) 2001-09-26 application
CN1192429C (en) 2005-03-09 grant
US6864577B2 (en) 2005-03-08 grant
US20020113312A1 (en) 2002-08-22 application
JP3898891B2 (en) 2007-03-28 grant
US6400018B2 (en) 2002-06-04 grant
KR100367126B1 (en) 2003-01-06 grant
EP1118119A1 (en) 2001-07-25 application

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