US20010043488A1 - Magnetoresistive memory having elevated interference immunity - Google Patents

Magnetoresistive memory having elevated interference immunity Download PDF

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Publication number
US20010043488A1
US20010043488A1 US09821964 US82196401A US2001043488A1 US 20010043488 A1 US20010043488 A1 US 20010043488A1 US 09821964 US09821964 US 09821964 US 82196401 A US82196401 A US 82196401A US 2001043488 A1 US2001043488 A1 US 2001043488A1
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Prior art keywords
layer
memory
line
magnetoresistive
bit
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US09821964
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US6366494B2 (en )
Inventor
Werner Weber
Roland Thewes
Gunther Plasa
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Siemens AG
Polaris Innovations Ltd
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Infineon Technologies AG
Siemens AG
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM

Abstract

The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This is a continuation of copending International Application PCT/DE99/03135, filed Sep. 29, 1999, which designated the United States.
  • BACKGROUND OF THE INVENTION FIELD OF THE INVENTION
  • [0002]
    The present invention relates to a magnetoresistive write-read memory (MRAM) whose storage effect consists in the magnetically controlled electrical resistance of the memory locations.
  • [0003]
    International PCT publication WO 95/10112 and U.S. Pat. No. 5,699,293 teach a non-volatile write/read memory in which a non-magnetic non-conductive layer is present between two ferromagnetic layers, with one layer having a fixed orientation and the other layer having a magnetic orientation that is defined by the operation. The resistance across the two ferromagnetic layers varies with the orientation of the respective magnetic moments.
  • SUMMARY OF THE INVENTION
  • [0004]
    It is accordingly an object of the invention to provide a magnetoresistive read/write memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes it possible to increase the interference immunity given an optimally small chip surface area.
  • [0005]
    With the foregoing and other objects in view there is provided, in accordance with the invention, a magnetoresistive memory, comprising a vertically stacked assembly of a layer for a first bit line, a magnetoresistive layer system of a first memory location, a layer for word lines, a magnetoresistive layer system of a second memory location, and a layer for an second bit line vertically stacked on top of one another, wherein logic states to be stored in the first memory location and the second memory location are inverses of one another.
  • [0006]
    In accordance with an added feature of the invention, the second memory location in a described state always comprises an inverse state of a state of the first location beneath it, and wherein a current in the bit line flows in a direction opposite to a direction of a current in the second bit line situated above it.
  • [0007]
    In accordance with a concomitant feature of the invention, each magnetoresistive layer system comprises a magnetically soft layer, a magnetically hard layer, and a thin tunnel oxide separating the two magnetic layers from one another.
  • [0008]
    Other features which are considered as characteristic for the invention are set forth in the appended claims.
  • [0009]
    Although the invention is illustrated and described herein as embodied in a magnetoresistive memory having elevated interference immunity, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
  • [0010]
    The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0011]
    [0011]FIG. 1 is a sectional view of an MRAM according to the invention; and
  • [0012]
    [0012]FIG. 2 is a sectional view of a magnetoresistive layer system that is present in FIG. 1.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0013]
    The invention may be summarized in that a local reference memory location for each individual memory location is provided and a common word line is disposed between these two memory locations vertically. This makes possible a very compact and effective interference compensation.
  • [0014]
    Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a part of a magnetoresistive memory having two word lines WL and two bit lines BL, {overscore (BL)}. Between the bit line BL and the word lines WL, magnetoresistive layer systems MRS are respectively situated. In the same way, such magnetoresistive layer systems are also situated between the word lines WL and the additional bit line {overscore (BL)}. Consequently, it is possible to achieve a total memory location area of only 4F2, with F being the smallest resolvable structural width. The layer systems between the bit line BL and the word line WL form regular memory locations Z, and the layer systems between the word lines WL and the additional bit line {overscore (BL)} form complementary memory locations {overscore (Z)}. The states stored in the complementary memory locations {overscore (Z)} are the inverse of those stored in the respective underlying memory locations Z; i.e., inverse states are written in by way of the bit lines BL and {overscore (BL)}, respectively. The bit line {overscore (BL)} carries the inverse signal of the signal on the bit line BL, whereby a current {overscore (I)} flowing in the bit line {overscore (BL)} flows in the opposite direction to the direction of a current in the bit line BL. Since the resistances of the magnetoresistive layer systems differ only on the order of approx. 10% in dependence upon their stored status, the influence of interference must be accounted for. Since the signals on the bit lines BL and {overscore (BL)} are the inverse of one another, it is possible to achieve an amplification of the payload signal and an attenuation of the noise quantities that act equally on the two complementary locations, and thus to increase the interference immunity, by difference formation.
  • [0015]
    [0015]FIG. 2 shows the magnetoresistive layer system MRS of the locations Z and {overscore (Z)} of FIG. 1. The layer system MRS essentially consists of a magnetically soft layer WM and a magnetically hard layer HM, which are separated by a tunnel oxide TOX. The ferromagnetic layers typically consist of a material containing at least one substance from a list that includes iron, nickel, and cobalt, with the material of the layer HM having a higher coercive field strength than the material of the layer WM. The tunnel oxide TOX consists of alumina Al2O3, for example. Instead of the tunnel oxide TOX, other thin insulator layers such as silicon nitride or the like can also be used.
  • [0016]
    The magnetoresistive layer system can vary the magnetization direction of the magnetically soft layer WM of a location Z for a long period of time, and can thereby store logical states of zero or one, with sufficient currents in a selected bit line BL and a selected word line WL. The reading of the location Z is then accomplished in that a current flows from the appertaining word line to the appertaining bit line through the location, the intensity of which depends on the magnetization direction of the magnetically soft layer WM. The current intensity differs when the magnetization directions in the layers WM and HM are parallel from when they are antiparallel, because the tunneling probability is different in each case.

Claims (3)

    We claim:
  1. 1. A magnetoresistive memory, comprising a vertically stacked assembly of a layer for a first bit line, a magnetoresistive layer system of a first memory location, a layer for word lines, a magnetoresistive layer system of a second memory location, and a layer for an second bit line vertically stacked on top of one another, wherein logic states to be stored in said first memory location and said second memory location are inverses of one another.
  2. 2. The magnetoresistive memory according to
    claim 1
    , wherein said second memory location in a described state always comprises an inverse state of a state of said first location therebeneath, and wherein a current in said bit line flows in a direction opposite to a direction of a current in said second bit line situated thereabove.
  3. 3. The magnetoresistive memory according to
    claim 1
    , wherein each said magnetoresistive layer system comprises a magnetically soft layer, a magnetically hard layer, and a thin tunnel oxide separating said magnetically soft layer from said magnetically hard layer.
US09821964 1998-09-30 2001-03-30 Magnetoresistive memory having elevated interference immunity Active US6366494B2 (en)

Priority Applications (4)

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DE19845069.9 1998-09-30
DE19845069 1998-09-30
DE19845069 1998-09-30
PCT/DE1999/003135 WO2000019441A3 (en) 1998-09-30 1999-09-29 Magnetoresistive memory having improved interference immunity

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US20010043488A1 true true US20010043488A1 (en) 2001-11-22
US6366494B2 US6366494B2 (en) 2002-04-02

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EP (1) EP1119860B1 (en)
JP (1) JP2002526910A (en)
KR (1) KR100571437B1 (en)
CN (1) CN1211872C (en)
WO (1) WO2000019441A3 (en)

Cited By (5)

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EP1345232A2 (en) * 2002-03-14 2003-09-17 Hewlett-Packard Company Magnetoresistive data storage device
WO2003098637A1 (en) * 2002-05-22 2003-11-27 Koninklijke Philips Electronics N.V. Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference
US20040250052A1 (en) * 2001-10-29 2004-12-09 Joachim Bangert Digital logic unit that can be reconfigured
US6856030B2 (en) 2002-07-08 2005-02-15 Viciciv Technology Semiconductor latches and SRAM devices
US6998722B2 (en) 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices

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JP4726290B2 (en) * 2000-10-17 2011-07-20 ルネサスエレクトロニクス株式会社 The semiconductor integrated circuit
US6430084B1 (en) * 2001-08-27 2002-08-06 Motorola, Inc. Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer
US6545906B1 (en) * 2001-10-16 2003-04-08 Motorola, Inc. Method of writing to scalable magnetoresistance random access memory element
US6724653B1 (en) 2001-12-21 2004-04-20 Kabushiki Kaisha Toshiba Magnetic random access memory
US6795334B2 (en) 2001-12-21 2004-09-21 Kabushiki Kaisha Toshiba Magnetic random access memory
EP1321941B1 (en) 2001-12-21 2005-08-17 Kabushiki Kaisha Toshiba Magnetic random access memory with stacked memory cells
US6839269B2 (en) 2001-12-28 2005-01-04 Kabushiki Kaisha Toshiba Magnetic random access memory
US6912152B2 (en) 2002-02-22 2005-06-28 Kabushiki Kaisha Toshiba Magnetic random access memory
JP3808802B2 (en) 2002-06-20 2006-08-16 株式会社東芝 The magnetic random access memory
US7095646B2 (en) * 2002-07-17 2006-08-22 Freescale Semiconductor, Inc. Multi-state magnetoresistance random access cell with improved memory storage density
US6956763B2 (en) * 2003-06-27 2005-10-18 Freescale Semiconductor, Inc. MRAM element and methods for writing the MRAM element
US6862211B2 (en) * 2003-07-07 2005-03-01 Hewlett-Packard Development Company Magneto-resistive memory device
US6967366B2 (en) * 2003-08-25 2005-11-22 Freescale Semiconductor, Inc. Magnetoresistive random access memory with reduced switching field variation
US7129098B2 (en) * 2004-11-24 2006-10-31 Freescale Semiconductor, Inc. Reduced power magnetoresistive random access memory elements
KR20140052393A (en) 2012-10-24 2014-05-07 삼성전자주식회사 Method and apparatus for controlling amount of light in a visible light communication system

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US20040250052A1 (en) * 2001-10-29 2004-12-09 Joachim Bangert Digital logic unit that can be reconfigured
US7225321B2 (en) 2001-10-29 2007-05-29 Siemens Aktiengesellschaft Reprogrammable microprogram based reconfigurable multi-cell logic concurrently processing configuration and data signals
EP1345232A2 (en) * 2002-03-14 2003-09-17 Hewlett-Packard Company Magnetoresistive data storage device
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EP1345232A3 (en) * 2002-03-14 2004-07-28 Hewlett-Packard Company Magnetoresistive data storage device
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WO2003098637A1 (en) * 2002-05-22 2003-11-27 Koninklijke Philips Electronics N.V. Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference
US20060056223A1 (en) * 2002-05-22 2006-03-16 Ditewig Anthonie M H Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference
US7206220B2 (en) 2002-05-22 2007-04-17 Nxp, B.V. MRAM-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference
US6856030B2 (en) 2002-07-08 2005-02-15 Viciciv Technology Semiconductor latches and SRAM devices
US6998722B2 (en) 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices

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CN1318198A (en) 2001-10-17 application
EP1119860B1 (en) 2002-12-18 grant
WO2000019441A3 (en) 2000-05-25 application
CN1211872C (en) 2005-07-20 grant
US6366494B2 (en) 2002-04-02 grant
JP2002526910A (en) 2002-08-20 application
EP1119860A2 (en) 2001-08-01 application
WO2000019441A2 (en) 2000-04-06 application
KR100571437B1 (en) 2006-04-17 grant

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