US20010040664A1 - Tape carrier package and display device using the same - Google Patents

Tape carrier package and display device using the same Download PDF

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Publication number
US20010040664A1
US20010040664A1 US09873393 US87339301A US2001040664A1 US 20010040664 A1 US20010040664 A1 US 20010040664A1 US 09873393 US09873393 US 09873393 US 87339301 A US87339301 A US 87339301A US 2001040664 A1 US2001040664 A1 US 2001040664A1
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Prior art keywords
chip
tcp
semiconductor
fig
circuit
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Granted
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US09873393
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US6407796B2 (en )
Inventor
Naoyuki Tajima
Yasunori Chikawa
Shunichi Murahashi
Seijirou Gyouten
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Sharp Corp
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Sharp Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387Flexible insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits

Abstract

A tape carrier package is provided, which includes: a line provided on one surface of a tape substrate; and a semiconductor chip mounted on an other surface of the tape substrate, the semiconductor chip having an electrode which is electrically connected to the line. The line extends from one end to an opposite end of the tape substrate and includes a connection where an intermediate line portion provided in a middle between the ends is electrically connected to the electrode.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a liquid crystal display device, or the like, used for a computer, word processor, etc., and also to a tape carrier package mounted on the display device which package includes a semiconductor chip for driving a display medium such as for example a liquid crystal material.
  • [0003]
    2. Description of the Related Art
  • [0004]
    [0004]FIG. 23 illustrates an example of a liquid crystal display device, which includes: a liquid crystal panel including an upper glass plate 15 and a lower glass plate 16 provided so as to interpose a liquid crystal material (not shown); a backlight unit 21 as a light source; a semiconductor chip 5 for driving the liquid crystal material; a tape carrier package (TCP) 7 connecting the semiconductor chip 5 to the wiring (or lines) provided on the lower glass plate 16; a printed board 23 for connecting a plurality of TCPs 7 together; and a vessel 22 for covering the liquid crystal panel.
  • [0005]
    Known methods for mounting a semiconductor chip for driving a liquid crystal material include: mounting the semiconductor chip directly on the liquid crystal panel; and mounting the semiconductor chip supplied in the form of a tape carrier package (TCP) on the liquid crystal panel.
  • [0006]
    In the latter method, as shown in FIG. 23, an electrode provided on the lower glass plate 16 and a patterned portion of a conductive material on the TCP 7 are attached together via an anisotropic conductive film (not shown) by thermocompression bonding, so as to provide a plurality of TCPs along the periphery of the liquid crystal panel. The plurality of TCPs 7 mounted around the liquid crystal panel are connected to the common printed board 23 which is provided with printed lines. Signals for conducting a display via the liquid crystal material are supplied to the TCPs 7 through the printed board 23. Moreover, conventionally, some chip components (e.g., a chip capacitor), are mounted on the printed board 23 if they cannot be included in the semiconductor chip 5. The vessel 22 is provided so as to surround the periphery of the liquid crystal panel.
  • [0007]
    The assembly steps for the liquid crystal display device include: connecting a liquid crystal driving output terminal of the TCP 7 to an electrode provided on the lower glass plate 16 via the anisotropic conductive film (not shown); and thereafter connecting an input signal terminal of the TCP 7 to the printed board 23 by soldering or via the anisotropic conductive film.
  • [0008]
    When a bendable TCP 25 is used, as shown in FIG. 24, the TCP 25 is bent after the above steps so that the printed board 23 matches the shape of the module.
  • [0009]
    On the other hand, the former method includes a Chip On Glass (COG) method, where the semiconductor chip 5 having metal bumps is mounted facing down directly onto the lines provided on the lower glass plate 16. There are different ways for making connections in this COG method such as: one described in Japanese Laid-open Publication No. 4-105331, etc., where connections are directly made by solder bumps after which the gap between the semiconductor chip and the glass plate is filled with a resin; and one described in Japanese Laid-open Publication Nos. 4-76929, 4-71246, 4-317347, etc., where, as shown in FIG. 25, the metal bumps of the semiconductor chip 5 are connected to the lines on the lower glass plate 16 via an anisotropic conductive film (ACF) 20 made of a resin (binder) 20 b including conductive particles 20 a. In the latter method, the resin (binder) 20 b of the anisotropic conductive film 20 is used in place of the filling resin in the former method. Recently, the COG method using the anisotropic conductive film which can be easily repaired and which dose not require the resin filling has been widely used.
  • [0010]
    To each semiconductor chip used in the method where the printed board is used or in the COG method, input signals and power voltages are parallelly input through the lines provided on the printed board or by the ITO lines provided on the liquid crystal panel. However, chip select signals are synchronized with the clock signals parallelly input so that signals are transferred among the semiconductor chips.
  • [0011]
    In recent years, a prevailing technique is to ensure a larger display area for a certain module size by reducing the width by which the liquid crystal panel extends beyond the glass plate (i.e., the frame size). Moreover, the cost of a liquid crystal panel is higher than that of a CRT, and great cost reduction has been demanded for the liquid crystal panels.
  • [0012]
    Under such circumstances, as a method using a TCP, it has been proposed (Japanese Design patent application No. 2-40145) to use a slim-type TCP which is obtained by shaping a semiconductor chip into an elongated shape in order to reduce the width by which the TCP extends beyond the glass plate. Moreover, it has also been proposed (Japanese Laid-open Publication No. 2-132418, etc.) to reduce the frame size by bending a portion of the TCP which extends beyond the glass plate, as described above.
  • [0013]
    However, both of the proposed methods require the printed board, the TCP and the liquid crystal panel, and the assembly process thereof requires two connection steps, i.e., one for connecting the glass plate of the liquid crystal panel with the TCP, and another for connecting the TCP with the printed board. This increases material cost and the number of steps to be performed, thereby presenting a bottleneck in reducing the cost of a liquid crystal module.
  • [0014]
    Moreover, another method has been proposed (Japanese Laid-Open Publication No. 5-297394, Japanese Laid-Open Publication No. 6-258653, etc.) in which a liquid crystal display device includes the liquid crystal panel (reference numeral 15 in FIG. 26A denotes the upper glass plate of the liquid crystal panel) and the TCP 7 but does not include a printed board, as shown in FIG. 26A. In this method, as shown in FIG. 26B, adjoining two TCPs 7 are directly connected to each other, whereby input signals are transmitted/received through only the TCPs 7.
  • [0015]
    In the case of this proposed method, although it is possible to reduce the material cost for the printed board, two connection steps are required; one for connecting the glass plate of the liquid crystal panel with the TCP 7; and another for connecting the TCPs 7 together, thereby providing no cost reduction in terms of the number of steps to be performed. Moreover, in this proposed method, if one of the continuously connected TCPs 7 becomes defective, the defective one of the TCPs 7 has to be removed. Such a removal may give some mechanical damage to the adjacent TCPs 7, and may also present a burden on the process in terms of the number of steps to be performed, requiring disconnection at three positions (at the right and left input terminals and at an output terminal of the defective TCP 7). Moreover, since transmission/reception of input signals is all performed between the TCPs 7, the input terminals thereof need to be arranged respectively on the left and right sides, perpendicular to the side on which the output terminal thereof is provided. The input lines connected respectively to the input terminals will also have to be arranged, thereby increasing the width of the TCP 7, which may then conflict with the frame size limitation of the liquid crystal panel. Moreover, the increased area of the TCP 7 will result in an increased material cost. Thus, the proposed method has some difficulty in repair, does not reduce the number of connection steps; and increases the TCP size.
  • [0016]
    On the other hand, in the COG method, since the semiconductor chip is directly mounted on the glass plate, the packaging cost thereof is lower than that in a method using a TCP. Moreover, when input signals can be supplied to the semiconductor chip via the lines on the glass plate, the printed board may also be eliminated, thereby presenting a significant advantage in terms of cost. In such a case, there is another advantage that the mounting process is done only by mounting the semiconductor chip on the glass plate, thereby reducing the mounting cost.
  • [0017]
    However, in practice, the configuration as described above is only possible for a relatively small liquid crystal panel of up to about 3 to 6 inches, but is not possible for a currently-dominant large liquid crystal panel of about 10 inches or more. The reason therefor is that the sheet material used for the lines provided on the glass plate has a resistance, whereby the wiring resistance of the input signal lines cannot be suppressed to a low level. When the glass plate is small, the wiring length on the glass plate is short. However, when the glass plate is large, the wiring length on the glass plate is long, a voltage across the length on the glass plate drops, and a valid signal is not transmitted to the liquid crystal driving semiconductor chip.
  • [0018]
    Moreover, in view of the above-described wiring resistance, the wiring width on the glass plate may have to be increased even in a small liquid crystal panel, whereby the chip mounting area on the glass plate becomes wider than the TCP. Such an increase in the size of the glass plate may reduce the number of panels which can be produced from one mother glass, whereby the cost reduction may not be achieved in terms of the module as a whole.
  • [0019]
    A method (Japanese Laid-Open Utility Model Publication No. 4-77134, etc.) has been proposed as a countermeasure to the above problem. In the method, as shown in FIG. 27, a flexible wiring board 18 is provided on the lower glass plate 16 of the liquid crystal panel in the vicinity of the mounting portion of each semiconductor chip 5, and the lines of the flexible wiring board 18 are directly connected to the lines provided on the lower glass plate 16, whereby input signals are transmitted through the flexible wiring board 18. This method requires the flexible wiring board which corresponds to the printed board in the method using a TCP, whereby there is no advantage in terms of the cost and process.
  • [0020]
    Moreover, when using a printed board in a large-size liquid crystal panel, a stress is applied to the TCP due to the difference between a linear expansion coefficient of the printed board and a linear expansion coefficient of the glass plate. Consequently, wire breaks may occur in the TCP, thus lowering reliability. Another proposed method (Japanese Laid-Open Publication No. 8-15716) is to use, in place of the printed board, a substrate obtained by providing lines on a glass plate. However, this method also has a problem that the glass plate wiring substrate is costly, while the wiring resistance thereof is also higher than that of the printed board.
  • [0021]
    Furthermore, in the case of the COG method, since chips are provided as bare chips, a test is normally made when it is still in the form of a wafer, but no test will be made after it is diced into individual chips. Therefore, when the semiconductor chip is mounted on the glass plate, it is difficult to ensure the quality of the semiconductor chip (i.e., it is not a Known Good Die). Particularly, in the case of a large panel on which a large number of semiconductor chips are mounted, the repair rate is likely to increase, thereby possibly increasing the cost.
  • [0022]
    In the case of the COG method, or in the case of using the glass wiring substrate in place of the printed board, the resistance between the line for transmitting the input signal can be reduced by providing an aluminum line in the semiconductor chip. Thus, making it possible to reduce the chances of being transmitted an invalid signal because of low resistance in the input signal line. However, the employment of aluminum requires extension of the width of an internal line of the semiconductor chip. The internal line needs to be designed with a large width so that the semiconductor chip is able to flow large current and increase the reliability of the device. As a result of the width increase, a wiring region of the chip becomes large which in turn increases chip area. The increase in chip area results in material costs for the chip to increase. Additionally, by using the above method, a clock signal can not be transmitted, because the semiconductor generates noise which may influence the signal transmitted therethrough. For example, a clock signal being transmitted via the semiconductor chip may become corrupted by noise from the chip.
  • SUMMARY OF THE INVENTION
  • [0023]
    According to one aspect of this invention, a tape carrier package includes: a line provided on one surface of a tape substrate; and a semiconductor chip mounted on an other surface of the tape substrate, the semiconductor chip having an electrode which is electrically connected to the line. The line extends from one end to an opposite end of the tape substrate and includes a connection where an intermediate line portion provided in a middle between the ends is electrically connected to the electrode.
  • [0024]
    In one embodiment of the invention, the connection is formed to overhang substantially at a device hole provided in the tape substrate and is electrically connected to the electrode of the semiconductor chip substantially at the overhang portion.
  • [0025]
    In another embodiment of the invention, the intermediate line portion including the connection is formed to protrude so as to extend over the device hole; and the connection is in the portion overhanging substantially at the device hole.
  • [0026]
    In still another embodiment of the invention, the intermediate line portion formed to protrude is in one of an I shape and a U shape.
  • [0027]
    In still another embodiment of the invention, the device hole is provided as a notch substantially at a location over which the linearly-shaped intermediate line portion extends.
  • [0028]
    In still another embodiment of the invention, the intermediate line portion including the connection is bent in a V shape toward the device hole; and a portion of the intermediate line portion which extends substantially at the device hole is linearly shaped.
  • [0029]
    In still another embodiment of the invention, the linearly-shaped intermediate line portion which extends substantially at the notch is provided with a bent buffering portion.
  • [0030]
    In still another embodiment of the invention, the device hole is formed separately from other openings formed in the tape substrate; and the intermediate line portion is provided so as to run linearly substantially at the device hole.
  • [0031]
    In still another embodiment of the invention, the line is for a power source; and the tape substrate is further provided with a signal line to be electrically connected to the electrode of the semiconductor chip.
  • [0032]
    In still another embodiment of the invention, a plurality of the lines are provided on the tape substrate; and an electronic component different from the semiconductor chip is connected and mounted between the lines.
  • [0033]
    In still another embodiment of the invention, the semiconductor chip includes a buffer circuit for signal connection between the semiconductor chip and a semiconductor chip provided on an other tape carrier package.
  • [0034]
    In still another embodiment of the invention, the buffer circuit included in the semiconductor chip is formed by an input buffer circuit and an output buffer circuit.
  • [0035]
    In still another embodiment of the invention, the buffer circuit included in the semiconductor chip is formed by an input/output buffer circuit.
  • [0036]
    According to another aspect of this invention, a display device is provided, which includes the tape carrier package of present invention provided on a glass plate of a display panel. Adjoining ones of the tape carrier packages are electrically connected to one another via a line provided on the glass plate.
  • [0037]
    In one embodiment of the invention, an anisotropic conductive film is used for the connection between the line provided on the glass plate and the tape carrier package.
  • [0038]
    In another embodiment of the invention, the line provided on the glass plate is a line directly formed on the glass plate.
  • [0039]
    In still another embodiment of the invention, an electronic component different from the semiconductor chip is connected and mounted onto the line provided on the glass plate.
  • [0040]
    In still another embodiment of the invention, the display panel is a liquid crystal panel.
  • [0041]
    In still another embodiment of the invention, the line provided on the glass plate is a line formed on a substrate other than the glass plate.
  • [0042]
    In still another embodiment of the invention, an electronic component different from the semiconductor chip is connected and mounted onto the line provided on the glass plate.
  • [0043]
    Hereinafter, the function of the present invention will be described.
  • [0044]
    In the TCP of the present invention, the input terminals for the lines are provided on a side perpendicular to a side on which an output terminal is provided, whereby it is possible to ensure the quality of the semiconductor chip (i.e., it is possible to determine whether the chip is good or bad), by performing a test using the input terminal.
  • [0045]
    Moreover, in the display device of the present invention, the TCP including the input terminals is mounted on the display panel, where electrical connection between adjoining TCPs is achieved-by the lines provided on the display panel. Therefore, the provision of the lines for input signals (which presents the most significant problem), is required only on the TCP and on the glass plate, whereby it is possible to reduce the material cost, and also to reduce the number of connection steps to be performed to ⅓ of that in the conventional technique, since the connection of the input/output terminals can be done in a single step of mounting the TCP. Therefore, a considerable cost reduction can be realized also in terms of the number of connection steps to be performed.
  • [0046]
    Moreover, according to the present invention, only a defective TCP needs to be removed from the glass plate, and only the surface of the glass plate has to be washed, whereby a repair process can be achieved with half the work of the conventional technique. Moreover, a portion of the TCP extending beyond the glass plate can be bent when mounting a bezel, and the like, whereby the frame size can also be reduced.
  • [0047]
    Since a printed board with a large linear expansion coefficient is not used, reliability against the temperature variation is improved as compared to the conventional technique. Moreover, mechanical reliability against vibration, or the like, can also be increased to a level comparable to that in the COG method, since there is no movable section or no section to be oscillated as compared to the TCP or the printed wiring board in the conventional TCP method.
  • [0048]
    Moreover, a bonding process to the glass plate is performed in a single step via the anisotropic conductive film. Since the lines on the TCP, the lines on the semiconductor chip, and the lines on the glass plate can be electrically connected to one another by the anisotropic conductive film, with which the function of the multi-layer lines of the conventional printed board can be replaced, and it is possible to transmit/receive input signals at a low wiring resistance without using a continuous large external substrate such as the flexible wiring board or the printed board.
  • [0049]
    Furthermore, by providing a buffer circuit in the semiconductor chip while not using the aluminum lines provided in the semiconductor chip, the wiring region inside the semiconductor chip can be reduced, and the chip area can also be reduced, whereby a reduced cost and an improved reliability can both be realized.
  • [0050]
    Furthermore, by transmitting the input signals via the buffer circuit within the semiconductor chip, it is possible to shape the waveform of the input signals, whereby the influence of the noise can be suppressed, and even signals which require a fast operation such as a clock signal can be reliably transmitted in a normal manner.
  • [0051]
    Furthermore, by providing the buffer circuit with a structure of an input/output buffer circuit, it becomes possible to freely and externally alter the signal transmission direction, whereby the semiconductor chip can be shared.
  • [0052]
    Thus, the invention described herein makes possible the advantages of (1) providing a tape carrier package in which the quality of a semiconductor chip can be easily ensured (i.e., it is possible to determine whether the chip is good or bad), before mounting the semiconductor chip; and (2) providing a display device using such a tape carrier package, in which the number of connection steps can be reduced, repair can be easily reformed, and the reliability thereof improved.
  • [0053]
    These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0054]
    [0054]FIGS. 1A to 1D are each a plan view illustrating a TCP according to Example 1 of the present invention, where FIG. 1A is a plan view illustrating the TCP before a cutting process; FIG. 1B is a plan view illustrating a left input terminal section; FIG. 1C is a plan view illustrating a significant feature of the present invention; FIG. 1D is a plan view illustrating a right input terminal section.
  • [0055]
    [0055]FIG. 2 is a cross-sectional view illustrating an intermediate portion of the TCP according to Example 1 between the left and right input terminal sections.
  • [0056]
    [0056]FIG. 3 is a plan view illustrating an important part of a TCP according to Example 2 of the present invention.
  • [0057]
    [0057]FIG. 4 is a cross-sectional view taken along A-A line in FIG. 3.
  • [0058]
    [0058]FIG. 5A is a plan view illustrating a TCP according to Example 3 of the present invention; and FIG. 5B is an enlarged plan view illustrating a portion thereof.
  • [0059]
    [0059]FIG. 6A is a plan view illustrating a TCP according to Example 4 of the present invention; and FIG. 6B is an enlarged plan view illustrating a portion thereof.
  • [0060]
    [0060]FIG. 7 is a plan view illustrating a TCP according to Example 5 of the present invention.
  • [0061]
    [0061]FIG. 8 is a plan view illustrating a TCP according to Example 6 of the present invention.
  • [0062]
    [0062]FIG. 9A is a perspective view illustrating a TCP mounting portion of a liquid crystal display device according to Example 7 of the present invention; and FIG. 9B is a cross-sectional view illustrating an important part thereof.
  • [0063]
    [0063]FIG. 10 is a diagram showing signal flows in an electric connection in the liquid crystal display device according to Example 7.
  • [0064]
    [0064]FIG. 11 is a perspective view illustrating a TCP mounting portion of a liquid crystal display device according to Example 8 of the present invention.
  • [0065]
    [0065]FIGS. 12A and 12B each illustrate a modification of the liquid crystal display device according to Example 8, where FIG. 12A is a perspective view illustrating an electronic component mounted on an TCP connection substrate; and FIG. 12B is a perspective view illustrating an electronic component built within or on a surface of a substrate, with an LTCC substrate being used as the TCP connection substrate.
  • [0066]
    [0066]FIG. 13 is a plan view illustrating a TCP according to Example 9 of the present invention and a semiconductor chip mounted thereon.
  • [0067]
    [0067]FIG. 14 shows an example of a logic circuit diagram of the buffer circuit shown in FIG. 13.
  • [0068]
    [0068]FIG. 15 is a plan view illustrating a TCP where the positions of the buffer circuits have been changed from those in FIG. 13 and a semiconductor chip mounted thereon.
  • [0069]
    [0069]FIG. 16 is a plan view illustrating a TCP according to Example 10 of the present invention and a semiconductor chip mounted thereon.
  • [0070]
    [0070]FIG. 17A shows an example of a logic circuit diagram of the input buffer circuit shown in FIG. 16; and FIG. 17B shows an example of a logic circuit diagram of the output buffer circuit shown in FIG. 16.
  • [0071]
    [0071]FIG. 18 is a plan view illustrating a TCP according to Example 11 of the present invention and a semiconductor chip mounted thereon.
  • [0072]
    [0072]FIG. 19 shows an example of a logic circuit diagram of the input/output buffer circuit shown in FIG. 18.
  • [0073]
    [0073]FIG. 20 is a plan view illustrating another TCP according to Example 11 of the present invention and a semiconductor chip mounted thereon.
  • [0074]
    [0074]FIG. 21 is a plan view illustrating still another TCP according to Example 11 of the present invention and a semiconductor chip mounted thereon.
  • [0075]
    [0075]FIG. 22 shows an example of a logic circuit diagram of the input/output buffer circuit shown in FIGS. 20 and 21.
  • [0076]
    [0076]FIG. 23 is a cross-sectional view illustrating a peripheral portion of a liquid crystal display device obtained by a conventional flat mounting method.
  • [0077]
    [0077]FIG. 24 is cross-sectional view illustrating a peripheral portion of a liquid crystal display device obtained by the conventional bending mounting method.
  • [0078]
    [0078]FIG. 25 is a cross-sectional view illustrating a peripheral portion of a liquid crystal display device obtained by the conventional ACF-COG method.
  • [0079]
    [0079]FIG. 26A is a plan view illustrating a conventional method for mounting TCPs so that adjoining TCPs are directly connected to each other; and FIG. 26B is an enlarged plan view illustrating the TCP shown in FIG. 26A.
  • [0080]
    [0080]FIG. 27 is a perspective view illustrating a conventional liquid crystal display device produced based on the COG method in which input signals are supplied through a flexible wiring board.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0081]
    Hereinafter, the present invention will be described by way of illustrative examples with reference to the accompanying figures.
  • (Example 1)
  • [0082]
    [0082]FIGS. 1A to 1D are each a plan view illustrating a TCP according to Example 1 of the present invention, where FIG. 1A is a plan view illustrating the TCP before a cutting process; FIG. 1B is a plan view illustrating a left input terminal section; FIG. 1C is a plan view illustrating a significant aspect of the present invention; FIG. 1D is a plan view illustrating a right input terminal section. Moreover, FIG. 2 is a cross-sectional view illustrating an intermediate portion of the TCP between the left and right input terminal sections.
  • [0083]
    The TCP 7 used in the present example may be obtained by laminating an electrolytic copper foil 3 (thickness: about 18 μm, minimum wiring width: about 30 μm) to form lines on Upilex as a tape substrate 1 (thickness: about 50 μm, produced by: Ube Industries, Ltd.) via an adhesive layer 2. As the material for the tape substrate 1, polyimide films other than Upilex such as Apical (Kanegafuchi Chemical Ind. Co., Ltd.), Kapton (Du Pont-Toray Co., Ltd.) may also be used. Moreover, a non-polyimide material can also be used. For example, films such as glass epoxy, aramid, BT resin, polyethylene terephthalate, polyphenylether may also be used. Furthermore, it is also applicable to form the TCP such that the electrolytic copper foil 3, being a conductor, is patterned directly on the substrate 1, without using the adhesive layer 2.
  • [0084]
    In the instance shown in FIG. 1A, the electrolytic copper foil 3 forms a group of output terminals 27 which is provided in the lower side of the figure in the central portion of the TCP 7 along the longitudinal direction thereof, and also forms, in the upper side of the figure, power source leads 11 a, input terminals 11 b and 11 c, inner leads 12 b and 12 c, and the like. Moreover, as shown in FIG. 2, a sealing resin 4 is provided above the electrolytic copper foil 3, except for a portion of the electrolytic copper foil 3 (e.g., except for the terminal section thereof). The semiconductor chip 5 is provided below the tape substrate 1, and the sealing resin 4 is provided so as to surround the semiconductor chip 5.
  • [0085]
    As shown in FIG. 1C, the power source leads 11 a overhang over a device hole 8 in the vicinity of the center of the device hole 8, with the overhang pattern 12 a being connected to a power source electrode bump 10 a provided on the semiconductor chip 5 which is located below the device hole 8. An end of a line is connected to each of the input terminals 11 b except for the power source electrode bump 10 a, while the other end of the line is inner-lead-bonded to a bump 10 b formed on the semiconductor chip 5 via the inner lead 12 b provided in the device hole 8. Therefore, the input signal is transmitted to the logic circuit section in the semiconductor chip 5 and is transmitted to a bump 10 c on the opposite side through lines 13 in the chip. A buffer circuit is provided in the semiconductor chip 5, as necessary, so as to take out the input signal from the bump 10 c after synchronizing the input signal. Thereafter, the input signal again passes through the lines on the TCP via the inner lead 12 c so as to go outside through the input terminal 11 c.
  • [0086]
    That is, in the TCP: the left and right input terminals are connected to each other by the continuous lead 11 a on the TCP; the device hole 8 is provided as an opening in the tape substrate so as to run across the continuous lead 11 a, while the electrodes and the bumps are formed on the semiconductor chip 5 so as to oppose the opening; a bonding process is then performed to the continuous lead 11 a which is provided on the TCP 7 so as to overhang over the opening; and a signal is supplied to the semiconductor chip 5. Thus, the lines in the chip do not have to be used as a signal propagation path, for the terminals for which the wiring resistance requirement is strict, e.g., a power source terminal.
  • [0087]
    Each inner lead is plated with tin so as to have a thickness of about 0.2 μm, and is connected to the connection bump on the semiconductor chip 5. Other than tin, Ni/Au or solder may be used as a conductive material to be plated on the TCP. The periphery of the device hole 8 is sealed with the sealing resin 4.
  • [0088]
    In Example 1, the portion of the tape to be cut into a single TCP is indicated by an alternate long and short dash line (7 a). The end on the power source leads 11 a may appropriately be shaped into one of various shapes by changing the cutting location indicated by the dash line (7 a).
  • (Example 2)
  • [0089]
    [0089]FIG. 3 is a plan view illustrating an important part of a TCP according to Example 2 of the present invention; and FIG. 4 is a cross-sectional view taken along the A-A line in FIG. 3.
  • [0090]
    A distinctive feature of Example 2 is how the power source leads 11 a are arranged. Specifically, the overhang pattern 12 a of the outermost power source lead 11 a extending over the device hole 8 is shaped into an I shape. The overhang pattern 12 a of the other power source lead 11 a extending over the device hole 8 is shaped into a U shape. The overhang patterns 12 a are connected respectively to the power source electrode bumps 10 a provided on the semiconductor chip 5. In the figure, the output terminals 27 are partially omitted.
  • [0091]
    In such a case, as compared to Example 1, the wiring length can be reduced by the length of the I-shaped lead 11 a, and the resistance thereof can be reduced, while the wiring region of one U-shaped pattern can also be reduced, whereby the design freedom can be increased.
  • (Example 3)
  • [0092]
    [0092]FIGS. 5A and 5B are each a plan view illustrating a TCP according to Example 3 of the present invention, where FIG. 5A illustrates several TCPs; and FIG. 5B illustrates an important part of the TCP.
  • [0093]
    Example 3 is the same as Example 1 in terms of the flow of the signals and the function thereof. A distinctive feature of Example 3 is that a notch 9 is provided at a certain position along the length of the device hole 8, and the overhang patterns 12 a is linearly shaped over the notch 9, whereby the overhang patterns 12 a and the power source electrode bumps 10 a provided on the semiconductor chip 5 are connected to each other over the notch 9. In Example 3, the power source leads 11 a form a V-like shape in the vicinity of the overhang patterns 12 a thereof.
  • [0094]
    When employing such an overhang pattern 12 a, there is an advantage in that the curved (U-shaped) portion thereof over the device hole 8 may be relatively short, or may even be omitted. However, since the power source electrode bumps 10 a extends perpendicularly to the array of output terminals 27, the width of the semiconductor chip may possibly be increased. Therefore, it is preferable to select one of Examples 1 to 3, which would be advantageous in terms of the manufacturing technology and cost, considering the circumstances in which the TCP will be used and the LSI layout.
  • (Example 4)
  • [0095]
    [0095]FIGS. 6A and 6B are each a plan view illustrating a TCP according to Example 4 of the present invention, where FIG. 6A illustrates several TCPs; and FIG. 6B illustrates an important part of the TCP.
  • [0096]
    In Example 4, as compared to Example 3, the overhang patterns 12 a is provided with a buffering function. Specifically, a portion of the overhang patterns 12 a which is overhanging over the device hole 8 is provided with the buffering function. In the instance shown in FIG. 6B, two S-shaped portions are provided in each lead. Thus, the present example provides some motion freedom between the ends of the overhang patterns 12 a, whereby the power source leads 11 a can easily stretch during the inner-lead-bonding process. Such a structure is resistant against wire breaks.
  • [0097]
    When a sufficient interspace cannot be provided between bumps, for example, the buffering portion does not have to be S-shaped, but may also be “<”-shaped or W-shaped.
  • [0098]
    It should be noted that the present example can be applied not only to Example 3, but also to Examples 1 and 2.
  • (Example 5)
  • [0099]
    [0099]FIG. 7 is a plan view illustrating a TCP according to Example 5 of the present invention.
  • [0100]
    In the TCP of the present example, a chip component (e.g., a chip capacitor) 14 is mounted on the leads 11 a on the tape substrate. In such a case, it is preferable to provide a soldering pad 11 d to each of a power source line Vdd and a ground line GND of the power source leads 11 a, to cover the periphery thereof with a solder resist 6, and to mount the chip component 14 thereon. The mounting process of the chip component 14 may be performed on a tape substrate, on a TCP after mounting the semiconductor chip 5 thereon, or on the TCP after mounting it on a liquid crystal panel.
  • (Example 6)
  • [0101]
    [0101]FIG. 8 is a plan view illustrating a TCP according to Example 6 of the present invention.
  • [0102]
    In the present example, the power source leads 11 a are formed substantially linearly so that the respective intermediate portions thereof run substantially linearly over the device hole 8. Each lead 11 a is electrically connected, via a connection, to power source electrode bumps 10 a of the semiconductor chip 5 at the midpoint of the intermediate line portion. Moreover, the device hole 8 is formed separate from other openings (e.g., another device hole) 8 a. As shown in the present example, the device hole 8 can be shaped into any appropriate shape, as necessary, as long as the shape allows for connection between the semiconductor chip 5 and the power source leads 11 a. The group of output terminals 27 is partially omitted in FIG. 8. Other than this, the configuration of the present example is the same as that shown in FIG. 3 (Example 2), and will not be further described.
  • (Example 7)
  • [0103]
    [0103]FIG. 9A is a perspective view illustrating a TCP mounting portion of a liquid crystal display device according to Example 7 of the present invention; and FIG. 9B is a cross-sectional view illustrating how the TCP is mounted on the liquid crystal display device.
  • [0104]
    In the liquid crystal display device of the present example, the TCPs 7, as being cut from the tape, are connected and secured individually to a wiring pattern 17 formed on the lower glass plate 16 of the liquid crystal panel via the anisotropic conductive film 20. In the figure, the TCP 7 exists entirely over the lower glass plate 16 including the tape. However, a portion of the tape of the TCP 7 or a portion of the semiconductor chip 5 may extend beyond the lower glass plate 16. Even in such a case, there still exists the advantage of the present invention, i.e., not requiring a printed board as a common wiring board.
  • [0105]
    The mounting process is performed as follows. The TCP 7 is first supplied as a tape, and is produced by cutting the tape using a metal mold, or the like. Next, the TCP 7 is aligned and temporally connected to a predetermined wiring connection provided on the lower glass plate of the liquid crystal panel. Then, a production press fit process is performed so as to fix the input/output terminal section of the TCP 7 onto the lower glass plate.
  • [0106]
    The connection between the lower glass plate 16 of the liquid crystal panel and the TCP 7 is achieved by using the anisotropic conductive film 20. It is possible to simultaneously achieve the connection of the output terminal and the connection of input terminal at once by adjusting the shape of a bonding tool or the apparatus. Even if one of the TCPs 7 turns out to be defective at a test conducted after mounting all the TCPs 7, the defective TCP 7 can be removed from the lower glass plate 16 so as to be replaced with a non-defective TCP 7 without damaging the TCPs 7 adjoining the defective TCP 7. For repair, the defective TCP 7 is removed from the lower glass plate 16 by using some heat, and the lower glass plate 16 is then washed with a special-purpose solvent, after which another non-defective TCP 7 is mounted according to the procedure as described above.
  • [0107]
    [0107]FIG. 10 illustrates signal flows in an electric connection between the liquid crystal panel and the TCP. As shown in the figure, electric signals are supplied to a plurality of TCPs 7 partially via the wiring pattern 17 provided on the lower glass plate 16 of the liquid crystal panel. In FIG. 10, reference numeral 26 denotes a TCP upper line; and 13 denotes the line in the chip.
  • [0108]
    Next, a comparison is made, based on calculations, between the input wiring resistance observed in the present example and that in the conventional ACF-COG method shown in FIG. 25, where all the input lines are provided by the lines on the glass plate. An 11.3-inch SVGA simple matrix type liquid crystal panel is assumedly used in the present example for the test calculation. In this case, 10 liquid crystal driving TCPs having 240 outputs are mounted on each side of the liquid crystal panel, whereby the number of input signal lines for each TCP is about 20.
  • [0109]
    Assuming the length of the TCP-mounting section of the 11.3-inch liquid crystal panel is about 220 μm, the length of a single TCP over which components may be mounted is about 22 mm. Assuming the length of one TCP is about 21.5 mm, the average length of the wiring pattern 17 on the lower glass plate 16 is about 0.5 mm.
  • [0110]
    In the present invention, since the electrodes on the opposite sides of one semiconductor chip are connected to each other with the line of the TCP made of a copper foil, the length of the line will be about 23 mm, considering the bending. That is, in the present invention, the wiring length on one side of the liquid crystal panel is 23×10=230 mm for the line of the TCP made of a copper foil, and is 0.5×10=5 mm for the wiring pattern 17 provided on the lower glass plate 16. In the above, “×10” was used in the calculation, though there are only 9 intervals between TCPs, considering the line of a half length existing beyond each of the outermost TCPs. Moreover, there are 2×10=20 connections of the anisotropic conductive film 20 connecting between the line of the TCP made of a copper foil and the wiring pattern 17 provided on the lower glass plate 16.
  • [0111]
    On the other hand, when all the input lines are provided by the lines on the glass plate based on the conventional ACF-COG method shown in FIG. 25, what has to be considered is only the lines on the lower glass plate 16. The length thereof is about 220 mm, and the connection step via the anisotropic conductive film 20 is performed once.
  • [0112]
    Assuming that the specific resistance of copper is about 1.7×10−6 Ω, the sheet resistance of the line on the glass plate is about 1 Ω/□ (Ω/□ means the sheet resistance), the wiring width is about 1 mm, and the connection resistance of the anisotropic conductive film 20 is about 0.1 Ω/connection, then, the total wiring resistance on one side of the liquid crystal panel is about 220 Ω in accordance with the conventional ACF-COG method, and is about 17 Ω in accordance with the present invention. Thus, the present invention provides a great effect in reducing the wiring resistance over the conventional method.
  • [0113]
    Such an effect can be obtained with the TCP 7 according to any one of Examples 1 to 6. Moreover,, with the TCP 7 according to any one of Examples 1 to 6, it is possible to significantly reduce the wire resistance as compared to the case where one end obtained by splitting the lead 11 a is connected to an end of a line provided on the semiconductor chip while connecting the other end to the other end of the line provided on the semiconductor chip (i.e., where power is sent from the lead 11 a to the end of the line provided on the semiconductor chip and also to the other end via a bypass). The reason is that, while the lead of the present invention is relatively thick (e.g., about 18 μm) which is formed by electrolysis (or by rolling, etc.), with the sheet resistance thereof being about 0.01 to 0.003 Ω, the line provided on the semiconductor chip is relatively thick (e.g., about −1 μm) formed by deposition, or the like, with the sheet resistance thereof being very large, i.e., about 0.1 to 0.5 Ω.
  • (Example 8)
  • [0114]
    [0114]FIG. 11 is a perspective view illustrating a TCP mounting portion of a liquid crystal display device according to Example 8 of the present invention.
  • [0115]
    In the present example, particularly in a large panel which requires low wiring resistance, only a power source line is provided without using the lines on the lower glass plate, and the adjoining TCPs 7 are connected to each other via a line 19 a formed on the TCP connection substrate 19. The wiring pattern 17 provided on the lower glass plate 16 is connected to the outermost TCPs 7. Note that reference numeral 26 denotes lines provided on the TCP.
  • [0116]
    In this case, the TCP connection substrate 19 is attached to a location between two TCPs on the lower glass plate 16 of the liquid crystal panel in a direction such that the patterned surface of the line 19 a is exposed. Then, the TCP 7 is mounted according to the same procedure as in Example 7. In this method, when using a line having a sheet resistance of about 0.01 Ω or less (as that used for the TCP of the present invention) as the lines of the TCP connection substrate 19, the wiring resistance is about 1 Ω or less, thereby presenting an effect of preventing the wiring resistance from relatively increasing even when the size of the liquid crystal panel is further increased in the future.
  • [0117]
    Moreover, the chip component (e.g., a chip capacitor) 14 may be mounted on the TCP connection substrate 19, as shown in FIG. 12A, or in the TCP connection substrate 19, as shown in FIG. 12B. When mounting the chip component in the substrate, it is preferable, as shown in FIG. 12B, to use an LTCC (Low Temperature Cofired Ceramic) substrate as the substrate, and to form the chip component (e.g., a chip capacitor) 14 within or on the surface of the substrate by a method such as printing. In this way, the mounting cost can be suppressed while the design freedom can be increased.
  • [0118]
    In the above description, a liquid crystal display device has been described as an example. However, the present invention is not limited thereto, but may also be applied generally to other display devices which use a display medium other than a liquid crystal material.
  • (Example 9)
  • [0119]
    [0119]FIG. 13 is a plan view illustrating a TCP according to Example 9 of the present invention and a semiconductor chip mounted thereon. It should be noted that the TCP portion can be realized by the TCP according to any one of the above-described examples.
  • [0120]
    First, the configuration and operation of the semiconductor chip 5 of FIG. 13 will be described. For purposes of discussion, it is assumed in the description below that a signal input to the semiconductor chip 5 is supplied from the side indicated at (A) in FIG. 13 via a controller, or another semiconductor chip, ITO lines, or the like. The signal is output from the other side indicated at (B) in FIG. 13. Then, the output signal is supplied to another semiconductor chip provided on another TCP 7 via the ITO lines on the glass plate.
  • [0121]
    The signal input via the terminal 11 b is provided to the bump 10 b on the semiconductor chip 5 via the inner lead line on the TCP 7. The bump 10 b is electrically connected to a line 29 a of an aluminum line, or the like, provided in the semiconductor chip 5, which is connected to a buffer circuit 28. The buffer circuit 28 shapes the waveform of the input signal, and drives a transistor connected to an internal logic circuit (not shown) with the input signal whose waveform is shaped. The signal is output through the terminal 11 b on the side (B) via the line 29 a, the bump 10 b, and the inner lead line on the TCP 7. The signal is then supplied to the next semiconductor chip.
  • [0122]
    The line 29 a can be designed with a wiring width determined in view of the discharge and charge current to the transistor of the buffer circuit 28. Moreover, the line 29 a can be designed with a wiring width determined in view of the discharge and charge current to the transistor connected to the internal logic circuit and the transistor of the buffer circuit of the next semiconductor chip and the connection load of the ITO line, and the like. Thus, as compared to the width of a line designed in view of all of the semiconductor chips to be connected and the connection load of the ITO line, and the like, the width can be considerably reduced, and the chip area can also be reduced. Furthermore, since the waveform of a signal is shaped at each semiconductor chip 5 by the buffer circuit 28 thereof, the signal can be sent normally without being influenced by the transistors to be driven and the ITO connection wiring load, and the like, whereby a malfunctioning can be prevented, while the influence of the noise can be suppressed.
  • [0123]
    On the other hand, the signal having passed though the transistor connected to the internal logic circuit goes through various logic circuits and is output through the output terminal so as to drive the display medium in the display device. These circuits will not be further described for sake of brevity.
  • [0124]
    Next, FIG. 14 shows an example of the buffer circuit 28 shown in FIG. 13. Although the buffer circuit 28 is formed by four inverter circuits 30 in FIG. 14, the number of inverter circuits 30 included in the buffer circuit 28 may also be two, six, or any other multiple of 2. Moreover, other circuit configurations are also possible: e.g., the first inverter circuit 30 may be a Schmitt circuit or an input comparator circuit.
  • [0125]
    [0125]FIG. 15 shows an alternative configuration where the positions of the buffer circuits 28 are changed from those in FIG. 13. Even when the positions of the buffer circuits 28 are changed, similar effects as described above can be achieved.
  • (Example 10)
  • [0126]
    [0126]FIG. 16 is a plan view illustrating a TCP according to Example 10 of the present invention and a semiconductor chip mounted thereon. It should be noted that the TCP portion can be realized by the TCP according to any one of the above-described examples.
  • [0127]
    In FIG. 16, each buffer circuit in the semiconductor chip 5 in the example described with reference to FIG. 13 is divided into an input buffer circuit 31 and an output buffer circuit 32, with the buffer circuits 31 and 32 being connected to each other by one of the lines 29 a, 29 b and 29 c of an aluminum line, or the like, provided in the semiconductor chip 5. Moreover, each line 29 connecting the buffer circuits 31 and 32 together is connected to a transistor connected to the internal logic circuit.
  • [0128]
    The operation of the TCP 7 will be described. As described above in Example 9, an input signal input from the terminal 11 b on the side (A) drives the input buffer circuit 31 via the inner lead line on the TCP 7, the bump 10 b, the line 29 a of an aluminum line, or the like, provided in the semiconductor chip 5. The input buffer circuit 31 then drives the output buffer circuit 32 connected thereto via the line 29 b and the transistor connected to the internal logic circuit. Moreover, past the output buffer circuit 32, the signal is output through the terminal 11 b on the side (B) via the inner lead line on the line 29 c, the bump 10 b and the inner lead line on the TCP 7. Then, the signal drives the next semiconductor chip.
  • [0129]
    As in Example 9, the above description is based on the assumption that a signal is input from the side (A) and output from the side (B). However, in practice, a signal may also be input from the side (B) and output from the side (A). When a signal is input from the side (B) and output from the side (A), the position of the input buffer circuit 31 and the position of the output buffer circuit 32 as in FIG. 16 are switched. The line 29 a of an aluminum line, or the like, provided in the semiconductor chip 5 can be designed with a width determined in view of the discharge and charge current to the transistor of the input buffer circuit 31; the line 29 b of an aluminum line, or the like, can be designed with a width determined in view of the discharge and charge current to the transistor connected to the internal logic circuit and the transistor of the buffer circuit 32; and the line 29 c of an aluminum line, or the like, can be designed with a width determined in view of the ITO connection wiring load and the discharge and charge current to the transistor of the input buffer circuit of the next semiconductor chip.
  • [0130]
    The width of each of the lines 29 a, 29 b and 29 c can be made smaller than that when all the semiconductor chips are connected to one another by the lines in the semiconductor chip. Moreover, since the line 29 b is not connected to the outside of the semiconductor chip 5, and the load generated when being driven is small, the wiring width thereof can be made even smaller, while it is not influenced by an external noise. Furthermore, by locating the input buffer circuit 31 and the output buffer circuit 32 closer to the bumps 10 b to which the buffer circuits 31 and 32 are connected by the lines 29 a and 29 c, respectively, the lines 29 a and 29 c between the bumps 10 b and the buffer circuits 31 and 32 can be shortened, whereby the influence of an external noise can be further suppressed, and the wiring region in the semiconductor chip 5 can be reduced. The input buffer circuit 31 and the output buffer circuit 32 provide similar function and effect as those of the buffer circuit described in Example 9.
  • [0131]
    [0131]FIG. 17A shows an example of a logic circuit diagram of the input buffer circuit 31 shown in FIG. 16; and FIG. 17B shows an example of a logic circuit diagram of the output buffer circuit 32 shown in FIG. 16. In FIG. 17A, the input buffer circuit 31 is formed by two inverter circuits 30. In FIG. 17B, the output buffer circuit 32 is formed by four inverter circuits 30. However, the number of inverter circuits 30 included in the input buffer circuit 31 and those included in the output buffer circuit 32 may be changed so that the total number of the inverter circuits 30 used is a multiple of 2. For example, it is applicable to form the input buffer circuit 31 by one inverter circuit 30, while forming the output circuit 32 by three inverter circuits 30. Moreover, each of the first inverter circuit 30 in the input buffer circuit 31 and the first inverter circuit 30 in the output buffer circuit 32 may also be a Schmitt circuit or an input comparator circuit. Any other circuit configuration which would provide similar effects as described above may also be employed.
  • (Example 11)
  • [0132]
    [0132]FIG. 18 is a plan view illustrating an important part of a TCP according to Example 11 of the present invention and a semiconductor chip mounted thereon. It should be noted that the TCP portion can be realized by the TCP according to any one of the above-described examples.
  • [0133]
    In the configuration shown in FIG. 18, the input buffer circuit 31 and the output buffer circuit 32 described with reference to FIG. 16 are each replaced with an input/output buffer circuit 33. When one of a pair of input/output buffer circuits 33 functions as an input buffer circuit, according to the direction in which a signal is input, the other functions as an output buffer circuit. It is also possible to, externally from the outside of the semiconductor chip 5, set the input/output buffer circuit 33 to be either an input buffer circuit or an output buffer circuit, depending upon the direction in which a signal is input. Moreover, when the direction in which a signal is input is fixed, a direction selection signal can be fixed to a certain power level within the semiconductor chip 5 or on the TCP 7. The other features, e.g., the operation, of the present example are the same as in Example 10, and will not be further described below for sake of brevity.
  • [0134]
    [0134]FIG. 19 shows an example of the input/output buffer circuit 33 shown in FIG. 18. Referring to FIG. 19, when one half of the circuit is determined to function as an input buffer circuit, based on a direction selection signal SHL, the other half of the circuit will function as an output buffer circuit. In FIG. 19, reference numeral 30 denotes an inverter circuit; 34 denotes a clocked inverter circuit; 35 denotes an NAND circuit; 36 denotes an NOR circuit; 37 denotes a PMOS transistor; and 38 denotes an NMOS transistor. Moreover, the number of transistors to be provided in one input/output buffer circuit 33 may be changed, and it is also applicable to employ a Schmitt circuit or an input comparator circuit for some of the input/output buffer circuits 33. Description of the number of transistors to be provided has already been provided in Example 10, and will not be further provided.
  • [0135]
    [0135]FIGS. 20 and 21 are each a plan view illustrating an important part of another TCP according to Example 11 of the present invention and a semiconductor chip mounted thereon. It should be noted that the TCP portion can be realized by the TCP according to any one of the above-described examples.
  • [0136]
    In FIG. 20, the buffer circuit 28 described with reference to FIG. 13 is replaced with the input/output buffer circuits 33. In FIG. 21, the buffer circuit 28 described with reference to FIG. 15 is replaced with the input/output buffer circuits 33. The other features, e.g., the operation, are the same as in Example 9, and will not be further described below.
  • [0137]
    [0137]FIG. 22 shows an example of the input/output buffer circuits 33 shown in FIGS. 20 and 21. As described above, in the circuit shown in FIG. 22, the number of transistors to be provided in one input/output buffer circuit 33 may be changed, and it is also applicable to employ a Schmitt circuit or an input comparator circuit for some of the input/output buffer circuits 33. Other circuit configurations may also be applicable.
  • [0138]
    For example, an STN liquid crystal panel, when it is a large panel, is driven based on a dual screen driving method, where one display screen is divided into two (e.g., upper and lower) screens in view of the display quality thereof by employing the above-described configuration of Example 11. In such a case, the direction in which a signal is input is reversed between the semiconductor chip used for the upper half and the semiconductor chip used for the lower half. However, if the direction in which a signal is input can be set externally, a single semiconductor chip can be shared. Moreover, it is not necessary to develop a semiconductor chip for each of the directions of signal input, whereby it is possible to improve the development efficiency and to facilitate the developmental management.
  • [0139]
    As described in detail above, in the TCP of the present invention, the input terminals for the lines are provided on the side perpendicular to the side on which the output terminal is provided, whereby it is possible to ensure the quality of the semiconductor chip, i.e., to determine whether it is good or bad, by performing a test using the input terminal.
  • [0140]
    Moreover, in the display device of the present invention, the TCP including the input terminals is mounted on the display panel, where electrical connection between adjoining TCPs is achieved by the lines provided on the display panel. Therefore, it is possible to reduce the number of connection steps to be performed to ⅓ of that in the conventional tequnique, since the connection of the input/output terminals can be done in a single step of mounting the TCP. Moreover, according to the present invention, only a defective TCP needs to be removed from the glass plate, and only the surface of the glass plate has to be washed, whereby a repair process can be achieved with half the work of the conventional technique. Furthermore, a portion of the TCP extending beyond the glass plate can be bent when mounting a bezel, and the like, whereby the frame size can also be reduced. Since a printed board with a large linear expansion coefficient is not used, the reliability against the temperature variation is improved as compared to the conventional technique. Moreover, the mechanical reliability against vibration, or the like, can also be increased to a level comparable to that in the COG method, since there is no movable section or no section to be oscillated as the TCP or the printed wiring board in the conventional TCP method.
  • [0141]
    Furthermore, in the conventional method, a large stress is applied to the TCP connection due to the difference in linear expansion coefficient between the printed board and the glass plate, thereby increasing the possibility for pattern breaks to occur. However, according to the present invention, since the printed board is not used, such a stress is not created, whereby the mounting process can be safely performed to a large panel.
  • [0142]
    Furthermore, since the semiconductor chip of the present invention includes a buffer circuit provided therein, the semiconductor chip area can be reduced, whereby it is possible to reduce the cost and to increase the reliability. The influence of a noise can also be suppressed, and even signals which requires a fast operation such as a clock signal can be reliably transmitted in a normal manner, whereby it is possible to prevent the semiconductor chip from malfunctioning.
  • [0143]
    Furthermore, by employing an input/output buffer circuit as a buffer circuit, it becomes possible to freely and externally alter the signal transmission direction, whereby the semiconductor chip can be shared.
  • [0144]
    Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.

Claims (20)

    What is claimed is:
  1. 1. A tape carrier package comprising:
    a line provided on one surface of a tape substrate; and
    a semiconductor chip mounted on an other surface of the tape substrate, the semiconductor chip having an electrode which is electrically connected to the line, wherein:
    the line extends from one end to an opposite end of the tape substrate and includes a connection where an intermediate line portion provided in a middle between the ends is electrically connected to the electrode.
  2. 2. A tape carrier package according to
    claim 1
    , wherein the connection is formed to overhang substantially at a device hole provided in the tape substrate and is electrically connected to the electrode of the semiconductor chip substantially at the overhang portion.
  3. 3. A tape carrier package according to
    claim 1
    , wherein:
    the intermediate line portion including the connection is formed to protrude so as to extend over the device hole; and
    the connection is in the portion overhanging substantially at the device hole.
  4. 4. A tape carrier package according to
    claim 3
    , wherein the intermediate line portion formed to protrude is in one of an I shape and a U shape.
  5. 5. A tape carrier package according to
    claim 1
    , wherein the device hole is provided as a notch substantially at a location over which the linearly-shaped intermediate line portion extends.
  6. 6. A tape carrier package according to
    claim 1
    , wherein:
    the intermediate line portion including the connection is bent in a V shape toward the device hole; and
    a portion of the intermediate line portion which extends substantially at the device hole is linearly shaped.
  7. 7. A tape carrier package according to
    claim 5
    , wherein the linearly-shaped intermediate line portion which extends substantially at the notch is provided with a bent buffering portion.
  8. 8. A tape carrier package according to
    claim 1
    , wherein:
    the device hole is formed separately from other openings formed in the tape substrate; and
    the intermediate line portion is provided so as to run linearly substantially at the device hole.
  9. 9. A tape carrier package according to
    claim 1
    , wherein:
    the line is for a power source; and
    the tape substrate is further provided with a signal line to be electrically connected to the electrode of the semiconductor chip.
  10. 10. A tape carrier package according to
    claim 1
    , wherein:
    a plurality of the lines are provided on the tape substrate; and
    an electronic component different from the semiconductor chip is connected and mounted between the lines.
  11. 11. A tape carrier package according to
    claim 1
    , wherein the semiconductor chip includes a buffer circuit for signal connection between the semiconductor chip and a semiconductor chip provided on an other tape carrier package.
  12. 12. A tape carrier package according to
    claim 11
    , wherein the buffer circuit included in the semiconductor chip is formed by an input buffer circuit and an output buffer circuit.
  13. 13. A tape carrier package according to
    claim 11
    , wherein the buffer circuit included in the semiconductor chip is formed by an input/output buffer circuit.
  14. 14. A display device, wherein:
    tape carrier packages according to
    claim 1
    are provided on a glass plate of a display panel;
    adjoining ones of the tape carrier packages are electrically connected to one another via a line provided on the glass plate.
  15. 15. A display device according to
    claim 14
    , wherein an anisotropic conductive film is used for the connection between the line provided on the glass plate and the tape carrier package.
  16. 16. A display device according to
    claim 14
    , wherein the line provided on the glass plate is a line directly formed on the glass plate.
  17. 17. A display device according to
    claim 16
    , wherein an electronic component different from the semiconductor chip is connected and mounted onto the line provided on the glass plate.
  18. 18. A display device according to
    claim 14
    , wherein the display panel is a liquid crystal panel.
  19. 19. A display device according to
    claim 14
    , wherein the line provided on the glass plate is a line formed on a substrate other than the glass plate.
  20. 20. A display device according to
    claim 19
    , wherein an electronic component different from the semiconductor chip is connected and mounted onto the line provided on the glass plate.
US09873393 1996-11-29 2001-06-05 Tape carrier package and display device using the same Expired - Lifetime US6407796B2 (en)

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JP32017496 1996-11-29
JP8-320174 1996-11-29
JP17077497A JP3405657B2 (en) 1996-11-29 1997-06-26 Tape carrier package and a display device using it
JP9-170774 1997-06-26
US97201497 true 1997-11-17 1997-11-17
US09873393 US6407796B2 (en) 1996-11-29 2001-06-05 Tape carrier package and display device using the same

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US09873393 US6407796B2 (en) 1996-11-29 2001-06-05 Tape carrier package and display device using the same

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US97201497 Continuation 1997-11-17 1997-11-17

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US20010040664A1 true true US20010040664A1 (en) 2001-11-15
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JP (1) JP3405657B2 (en)
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US20040183984A1 (en) * 2003-03-20 2004-09-23 Hitachi Displays, Ltd. Display device and manufacturing method thereof
US20050207238A1 (en) * 2002-04-18 2005-09-22 Oleg Siniaguine Clock distribution networks and conductive lines in semiconductor integrated circuits
US20050205888A1 (en) * 2004-03-16 2005-09-22 Nec Corporation Semiconductor chip and display device using the same
US20070035486A1 (en) * 2005-08-12 2007-02-15 Seiko Epson Corporation Signal transmission circuit, electro-optical device, and electronic apparatus
US20070103412A1 (en) * 2005-11-09 2007-05-10 Pao-Yun Tang Liquid crystal display having a voltage divider with a thermistor
US20070103632A1 (en) * 2005-11-07 2007-05-10 Au Optronics Corp. Liquid crystal display panel module and flexible printed circuit board thereof
US20070109484A1 (en) * 2005-11-15 2007-05-17 Sharp Kabushiki Kaisha Drive element mount display
US20090231823A1 (en) * 2008-03-14 2009-09-17 Oki Semiconductor Co., Ltd. Tape wiring substrate and semiconductor chip package
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US20020149921A1 (en) * 2001-04-16 2002-10-17 Nec Corporation Construction and method for interconnecting flexible printed circuit and wiring board, liquid crystal display device, and method for manufacturing the same
US7173327B2 (en) * 2002-04-18 2007-02-06 Tru-Si Technologies, Inc. Clock distribution networks and conductive lines in semiconductor integrated circuits
US20070069377A1 (en) * 2002-04-18 2007-03-29 Oleg Siniaguine Clock distribution networks and conductive lines in semiconductor integrated circuits
US20050207238A1 (en) * 2002-04-18 2005-09-22 Oleg Siniaguine Clock distribution networks and conductive lines in semiconductor integrated circuits
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US20070035486A1 (en) * 2005-08-12 2007-02-15 Seiko Epson Corporation Signal transmission circuit, electro-optical device, and electronic apparatus
US20070103632A1 (en) * 2005-11-07 2007-05-10 Au Optronics Corp. Liquid crystal display panel module and flexible printed circuit board thereof
US20070103412A1 (en) * 2005-11-09 2007-05-10 Pao-Yun Tang Liquid crystal display having a voltage divider with a thermistor
US20070109484A1 (en) * 2005-11-15 2007-05-17 Sharp Kabushiki Kaisha Drive element mount display
US20090231823A1 (en) * 2008-03-14 2009-09-17 Oki Semiconductor Co., Ltd. Tape wiring substrate and semiconductor chip package
US8228677B2 (en) * 2008-03-14 2012-07-24 Lapis Semiconductor Co., Ltd. Tape wiring substrate and semiconductor chip package
US9595222B2 (en) 2012-10-09 2017-03-14 Joled Inc. Image display apparatus
US9734757B2 (en) 2012-10-17 2017-08-15 Joled Inc. Gate driver integrated circuit, and image display apparatus including the same
US9773450B2 (en) 2012-10-17 2017-09-26 Joled Inc. EL display panel with gate driver circuits mounted on flexible board including terminal connection lines connecting connection parts and control terminals

Also Published As

Publication number Publication date Type
JPH10214858A (en) 1998-08-11 application
CN1143170C (en) 2004-03-24 grant
JP3405657B2 (en) 2003-05-12 grant
KR100256510B1 (en) 2000-05-15 grant
CN1184260A (en) 1998-06-10 application
US6407796B2 (en) 2002-06-18 grant

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