US20010022369A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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US20010022369A1
US20010022369A1 US09/854,569 US85456901A US2001022369A1 US 20010022369 A1 US20010022369 A1 US 20010022369A1 US 85456901 A US85456901 A US 85456901A US 2001022369 A1 US2001022369 A1 US 2001022369A1
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formed
insulating film
film
layer
memory cell
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US6423992B2 (en
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Takuya Fukuda
Yuzuru Ohji
Nobuyoshi Kobayashi
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Renesas Electronics Corp
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Takuya Fukuda
Yuzuru Ohji
Nobuyoshi Kobayashi
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Priority to JP35053797A priority Critical patent/JP3697044B2/en
Priority to JP9-350537 priority
Priority to US09/209,013 priority patent/US6255151B1/en
Application filed by Takuya Fukuda, Yuzuru Ohji, Nobuyoshi Kobayashi filed Critical Takuya Fukuda
Priority to US09/854,569 priority patent/US6423992B2/en
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10894Multistep manufacturing methods with simultaneous manufacture of periphery and memory cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • H01L27/10814Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor with capacitor higher than bit line level
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Description

  • This application is a Divisional application of Ser. No. 09/209,013, filed Dec. 11, 1998.[0001]
  • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor; and, more particularly, the invention relates to a technique which is effective for application to a DRAM or a semiconductor integrated circuit device, wherein the DRAM and a logic circuit, such as a logical control circuit or an arithmetic logic circuit or the like, are placed on one semiconductor substrate in mixed form. [0002]
  • Memory cells of a DRAM are generally placed at points where a plurality of word lines and a plurality of bit lines intersect on a principal surface of a semiconductor substrate in matrix form. Each memory cell comprises one memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information storage capacitive element (capacitor) electrically connected in series therewith. The memory cell selection MISFET is formed within an active region whose periphery is surrounded by a device separation region, and principally comprises a gate oxide film, a gate electrode constructed integrally with each word line, and a pair of semiconductor regions constituting a source and a drain. Each bit line is placed in an upper portion of the memory cell selection MISFET and is electrically connected to one of the source and drain shared between two adjacent memory cell selection MISFETs in an extending direction thereof. The information storage capacitive element is similarly placed in the upper portion of the memory cell selection MISFET and is electrically connected to the other of the source and drain. [0003]
  • A DRAM described in Japanese Patent Application Laid-Open No. Hei 7-7084 has been devised to provide a lower electrode (storage electrode) of each capacitor in a cylindrical form having an opening defined thereabove thereby to increase its surface area. Further, a capacitive insulating film is formed on the lower electrode and an upper electrode (plate electrode) is formed over the capacitive insulating film. [0004]
  • In a capacitor having such a lower electrode of cylindrical shape, a steplike offset or difference in level corresponding to the height of the capacitor occurs between a memory cell array region and a region other than a peripheral circuit region or the like. [0005]
  • If such a steplike offset exists, it is then difficult to adjust the exposure focus upon patterning an interconnection layer formed after the formation of the capacitor. As a result, fine wiring patterns cannot be obtained. With developments in miniaturization of a semiconductor integrated circuit device, the storage capacitive value required per unit area has increased and, therefore, the height of the capacitor has further increased. On the other hand, allowable margin values for adjustment of the exposure focus become increasingly more strict due to the miniaturization of each wiring pattern. [0006]
  • Japanese Patent Application Laid-Open No. Hei 4-10651 (corresponding U.S. Pat. No. 5,218,219) discloses a DRAM wherein in order to reduce the steplike offset between the aforementioned memory cell array region and peripheral circuit region, grooves are defined in an insulating film and capacitors are formed along inner walls of the grooves. [0007]
  • SUMMARY OF THE INVENTION
  • In the aforementioned DRAM, however, an insulating film having a thickness equal to the height of each capacitor is left within a region other than the memory cell array region. In the micro-fabricated DRAM, there may be cases in which the thickness of the insulating film reaches 1 μm in terms of the need for increasing the height of the capacitor to ensure its storage capacity. Therefore, when a first layer interconnection formed before a capacitor forming process is connected to a second layer interconnection formed after the formation of the capacitor, it is necessary to define each connecting-hole in the thick insulating film having a thickness equal to the height of the capacitor, so that the aspect ratio (corresponding to the depth of the connecting hole relative to the open diameter of the connecting hole) of the connecting hole increases. Namely, even if the first layer interconnection and the second layer interconnection are connected to one another by a plug, they are inevitably connected to one another by a plug, having a high aspect ratio. Thus, the yield might be reduced because a plug having such a high aspect ratio is formed. Further, the connecting hole reaches a substrate in an etching process for the formation of the connecting hole, so that the second layer interconnection and the substrate are short-circuited. [0008]
  • In a semiconductor integrated circuit device in which a DRAM and a logic circuit, such as a logical control circuit or a logic circuit or the like, are placed on a single semiconductor substrate in mixed form, the logic circuit part has a configuration in which a first layer interconnection and a second layer interconnection are connected by a plug having a high aspect ratio in a manner similar to a peripheral circuit of the DRAM. If the interconnections are connected by the plug having such a high aspect ratio, then the resistance thereof interferes with the performance, such as a quick response or the like of the logic circuit. [0009]
  • Incidentally, Japanese Patent Application Laid-Open No. Hei 9-92794 discloses a method of simultaneously forming capacitor-forming concave portions and plug-forming grooves in an insulating film to reduce a steplike offset and simplify a process for processing storage electrodes. However, the disclosed method has a problem in that, when an interconnection (second layer interconnection) is formed after the formation of each capacitor, a CMP method cannot be used. When a lower electrode of the capacitor is formed simultaneously with the second layer interconnection of a peripheral circuit according to the features described in this publication, a capacitive insulating film of the capacitor is formed after a process for forming the second layer interconnection. When the capacitive insulating film is composed of an oxide metal, such as a tantalum oxide or the like, in order to obtain an increase in the stored charge of the capacitor, it is necessary inevitably to perform a heat treating process at a high temperature. A metal material, such as low-resistance copper or aluminum or the like, used for the second layer interconnection cannot be adopted from the viewpoint of thermal diffusibility and softening. [0010]
  • An object of the present invention is to improve the reliability of connection between a first layer interconnection and a second layer interconnection placed with a thick insulating film having a thickness equal to the height of each capacitor interposed therebetween in a semiconductor integrated circuit device having memory cells containing capacitive elements. [0011]
  • Another object of the present invention is to reduce the resistance of a hole portion for connection between the first layer interconnection and the second layer interconnection. [0012]
  • A further object of the present invention is to reduce the resistance of interconnections of a second or subsequent layer interconnection. [0013]
  • A still further object of the present invention is to provide a technique which is capable of performing a process for forming a second layer interconnection subsequently to a process for forming a capacitor requiring a high heat treating process and for using even a material which has a large thermal diffusion coefficient in the second layer interconnection. [0014]
  • A still further object of the present invention is to improve the quickness of response of a peripheral circuit or logic circuit formed on the same substrate as a DRAM having memory cells. [0015]
  • The above and other objects, and novel features of the present invention will become apparent from the description provided in the present specification and from the accompanying drawings. [0016]
  • Summaries of typical aspects of the invention disclosed in the present application will be described in brief as follows. [0017]
  • (1) A semiconductor integrated circuit device according to the present invention comprises memory cell selection MISFETs formed in a memory cell array region on a semiconductor substrate, peripheral circuit MISFETs formed in a peripheral circuit region around the memory cell array region, a first interlayer insulating film for covering the memory cell selection MISFETs and the peripheral circuit MISFETS, bit lines formed over the first interlayer insulating film lying in the memory cell array region, at least one information storage capacitive element provided with a lower electrode electrically connected to one source-to-drain region of each memory cell selection MISFET, and a second interlayer insulating film including a first portion formed in the same layer as that for the information storage capacitive element and for reducing or eliminating a steplike offset between the memory cell array region and the peripheral circuit region, the offset being caused by the height of the information storage capacitive element, and a second portion for covering the information storage capacitive element, and wherein the surface of the second interlayer insulating film is flattened and wiring or interconnection grooves are defined in the vicinity of the surface thereof, and interconnections having surfaces within the same plane as the surface thereof are formed inside the wiring grooves. [0018]
  • Further, the semiconductor integrated circuit device according to the present invention has a logic circuit region with logic circuit MISFETs constituting an arithmetic circuit or another logic circuit formed therein in addition to the memory cell array region and peripheral circuit region of the semiconductor integrated circuit device. Even in the case of the second interlayer insulating film in the logic circuit region, the surface thereof is flattened and wiring interconnection grooves are defined in the vicinity of the surface thereof. Interconnections having surfaces within the same plane as the surface of the second interlayer insulating film are respectively formed inside the interconnection grooves. [0019]
  • According to such a semiconductor integrated circuit device, since the surface of the second interlayer insulating film is flattened, a steplike offset caused by the information storage capacitive element is not formed between the memory cell array region and other regions. Unfocusing of exposure light, which will be produced when such a steplike offset exists, is not developed. Therefore, the patterning of the interconnections or the like formed over the second interlayer insulating film can be performed precisely. Thus, fine interconnections or the like can be formed so as to cope with high integration and high performance of the semiconductor integrated circuit device. [0020]
  • However, if the surface of the second interlayer insulating film is flattened in this way, then the thickness of the second interlayer insulating film in the peripheral circuit region or logic circuit region is made thick by an amount corresponding to the steplike offset. It is further necessary to process, with a high aspect ratio, each connecting hole for connecting interconnections formed on a second interlayer insulating film and members placed therebelow in the case of the prior art in which no countermeasures are taken thereagainst. This point is as described above. [0021]
  • In accordance with the present invention, however, the surface of the second interlayer insulating film is flattened and the wiring grooves are defined in the vicinity of the surface thereof. Further, interconnections having surfaces within the same plane as the surface of the second interlayer insulating film are formed in the interconnection grooves respectively. Therefore, the distance between each member below the second interlayer insulating film and the bottom of each interconnection becomes short and hence the length of a connecting portion for connecting each interconnection and the member to each other can be shortened. Thus, the length of a connecting hole for forming each connecting portion is shortened to make its processing easy, and the occurrence of a failure in processing is restrained, so that the semiconductor integrated circuit device can be improved in manufacturing yield and reliability. Further, since the length of the connecting portion becomes short, the resistance of the connecting portion is lowered and hence the resistance for connection between each interconnection and the member is reduced, whereby the performance, such as quick response or the like, of the semiconductor integrated circuit device can be improved. [0022]
  • Further, the interconnections can be formed within the peripheral circuit region alone, or the peripheral circuit region and logic circuit region alone without being formed within the memory cell array region. Thus, the resistance values of each interconnection and connecting portion in the peripheral circuit region or logic circuit region can be reduced so as to improve the quickness of response of the peripheral circuit and the logic circuit. In particular, an improvement in the quickness of response of the logic circuit portion exerts a direct influence on an improvement in operation speed and the like, and an improvement in the performance of the semiconductor integrated circuit device as it is and is also of importance thereto. [0023]
  • The bottom face of each interconnection can be placed below the upper surface of the information storage capacitive element. By placing the bottom face of the interconnection below the upper surface of the information storage capacitive element in this way, the length of each connecting portion connected to the member placed in a portion below the bottom face thereof as seen from the bottom face of the interconnection can be made shorter. Since the shortening of the length of each connecting portion contributes to improvements in yield and reliability of the semiconductor integrated circuit device and an improvement in the performance thereof as described above, the further shortening of the length thereof means that the above-described effect can be developed more pronouncedly. [0024]
  • Further, each of the first layer interconnections each composed of the same material as each bit line is formed over the first interlayer insulating film in the peripheral circuit region, or the peripheral circuit region and logic circuit region. Each interconnection can be provided as a second layer interconnection formed at the upper portion of the first layer interconnection. Thus, the formation of the first layer interconnection of the same material as a bit line over the first interlayer insulating film makes it possible to make the process for forming the first layer interconnection identical to the process for forming each bit line and thereby to simplify the processes. By forming the interconnection as the second layer interconnection and forming each lower member connected to the second layer interconnection as the first layer interconnection, the length between the second layer interconnection and the first layer interconnection, i.e., the length of the connecting portion can be shortened. It is thus possible to more remarkably achieve improvements in manufacturing yield and reliability owing to the facilitation of a process for forming each connecting hole, a reduction in series resistance owing to the shortening of the length of each connecting portion, and an improvement in the performance of the semiconductor integrated circuit device based on it. [0025]
  • Incidentally, the interconnection (or second layer interconnection) and the connecting portion are formed in their corresponding wiring or interconnection groove and connecting hole. They can be formed as an integral one. Namely, the connecting hole can be defined in a portion below the interconnection groove, and the interconnection or the second layer interconnection can be regarded as being connected to each peripheral circuit MISFET, each logic-circuit MISFET or the first layer interconnection through the connecting portion formed integrally with the interconnection or the second layer interconnection inside the connecting hole. The above-described interconnection and connecting portion can be formed by a so-called damascene method (dual damascene method for integrally forming the interconnection and the connecting portion in particular) as will be described later. [0026]
  • Further, the interconnection and its connecting portion or the second layer interconnection and its connecting portion can be formed as metal conductive materials or conductors with copper as a principal conductive layer. In this case, any one selected from a tantalum film, a niobium film, a tantalum nitride film, a titanium nitride film and a tungsten nitride film or a plurality of thin films can be formed at an interface between the principal conductive layer composed of copper and the wiring groove and connecting hole. Further, the surface of the interconnection or the second layer interconnection can be covered with a silicon nitride film. [0027]
  • By utilizing copper as the principal conductive layer, the interconnection and the connecting portion are reduced in resistance value so that the performance of the semiconductor integrated circuit device can be improved. There are strong expectations for coping with a demand for an improvement in the performance of the logic circuit portion in particular. The improvement in its performance brings about a great technical effect. Any one selected from the tantalum film, niobium film, tantalum nitride film, titanium nitride film and tungsten nitride film or the plurality of thin films function as a blocking layer against copper. It is thus possible to prevent copper from being diffused into each interlayer insulating film or the like and improve the reliability of the semiconductor integrated circuit device. With respect to the tantalum film and the niobium film in particular, a chemical bond between tantalum and niobium, and copper exists stably and hence the migration of copper atoms at a tantalum/copper interface (niobium/copper interface) is controlled or retarded. Therefore, its retardant effect greatly works not only for electromigration but also for the diffusion of copper. As a result, a highly reliable semiconductor integrated circuit device which is excellent in resistance to electromigration can be obtained. Further, the diffusion of copper upward can be restrained by covering the surface of the interconnection or the second layer interconnection with a silicon nitride film. [0028]
  • Further, the interconnection and its connecting portion or the second layer interconnection and its connecting portion can be formed as metal conductive materials or conductors with aluminum as a principal conductive layer. In this case, a titanium nitride film can be formed at an interface between the principal conductive layer composed of aluminum and the wiring groove and connecting hole. [0029]
  • By utilizing aluminum as the principal conductive layer, the interconnection and the connecting portion are reduced in resistance value so that the performance of the semiconductor integrated circuit device can be improved. There are strong expectations for coping with a demand for an improvement in the performance of the logic circuit portion in particular. The improvement in its performance brings about a great technical effect. It is also possible to use the titanium nitride film as a wetting layer at the time that aluminum is embedded in its corresponding connecting hole under high pressure, as will be described later. [0030]
  • Incidentally, a lower electrode can be formed so as to have a cylindrical shape having an opening defined thereabove. Since the lower electrode shaped in such a cylindrical form can be provided with a large surface area, it has a shape advantageous to high integration of a future DRAM but inevitably results in a solid shape. Therefore, the steplike offset caused by each information storage capacitive element also increases. Thus, an effect at the time that the present invention is applied becomes particularly prominent in the shape of the lower electrode. [0031]
  • Further, an upper interlayer insulating film having each wiring or interconnection groove in the vicinity of the surface of the interlayer insulating film, and an upper interconnection formed within the wiring groove and whose surface is placed substantially in the same plane as that of the upper interlayer insulating film, may be formed in a layer above the interconnection or second layer interconnection. Thus, even a third or fourth interconnection layer above the second layer interconnection can be reduced in series resistance in a manner similar to the second layer interconnection (interconnection) so as to improve the performance of the semiconductor integrated circuit device. [0032]
  • (2) A method of manufacturing a semiconductor integrated circuit device, according to the present invention comprises the following processes: a process for forming memory cell selection MISFETs in a memory cell array region on a principal surface of a semiconductor substrate and for forming peripheral circuit MISFETs or logic circuit MISFETs in a peripheral circuit region or logic circuit region on the semiconductor substrate, respectively; a process for forming a first insulating film for covering the memory cell selection MISFETs and the peripheral circuit MISFETs or logic circuit MISFETS; a process for forming bit lines over the first insulating film in the memory cell array region; a process for forming a second insulating film for covering the bit lines; a process for forming a lower electrode of each information storage capacitive element, a capacitive insulating film for covering the lower electrode, and an upper electrode over the second insulating film in the memory cell array region; a process for forming a third insulating film over the information storage capacitive element; and a process for flattening the surface of the third insulating film by a CMP method, thereafter defining wiring or interconnection grooves and connecting holes in the flattened third insulating film and a lower insulating film thereof in the peripheral circuit region or logic circuit region, successively depositing a first conductive layer and a second conductive layer over the third insulating film containing the interior of the interconnection grooves and connecting holes, removing the first and second conductive layers on the surface of the third insulating film by the CMP method, and forming interconnections comprised of the first and second conductive layers within each interconnection groove and forming connecting portions comprised of the first and second conductive layers within each connecting hole. [0033]
  • According to such a method of manufacturing the semiconductor integrated circuit device, the interconnections are formed by a so-called dual damascene method so that the semiconductor integrated circuit device described in paragraph (1) can be formed. [0034]
  • According to the present manufacturing method as well, since the interconnections are formed after the formation of each information storage capacitive element, no interconnections are affected by heat treatment at a high temperature, which is normally performed upon formation of the information storage capacitive element. Described another way, since the interconnections are not yet formed upon formation of the information storage capacitive element, it is not necessary to restrict the heating process at the time of formation of the information storage capacitive element in consideration of the heat resistance to the interconnections. Thus, heat treatment at a sufficiently high temperature (e.g., about 700° C.) is executed upon formation of the information storage capacitive element, whereby each information storage capacitive element can be formed to have a large in storage capacity. On the other hand, a material, which is inferior in heat resistance, but has high conductivity, e.g., copper, aluminum or the like, is used to reduce the wiring resistance, whereby the performance of the semiconductor integrated circuit device can be improved. Owing to such a manufacturing method, aluminum which has a low melting point or copper having a fast diffusion velocity can be used as the wiring material. [0035]
  • Further, since the connecting holes are defined after the formation of the wiring or interconnection grooves in the present manufacturing method, the depth of each connecting hole is reduced by an amount corresponding to the depth of each wiring hole. Therefore, the processing of each connecting hole can be made easy and a reduction in the yield of the semiconductor integrated circuit device due to a failure in processing can be restrained. Since the length of each connecting portion formed in its corresponding connecting hole is shortened, series resistance between the interconnection and a lower member, to which the interconnection is connected by its corresponding connecting portion, is reduced so that the semiconductor integrated circuit device can be improved in performance. [0036]
  • Although the problem of a steplike offset resulting from the information storage capacitive element is solved upon flattening the third insulating film, a method of forming an insulating film corresponding to the steplike offset in advance before the deposition of the third insulating film is used to solve such a steplike offset. Namely, before the deposition of the third insulating film, a fourth insulating film formed in the same layer as that for each information storage capacitive element is formed within the peripheral circuit region or logic circuit region, thereby making it possible to reduce or eliminate the steplike offset between the memory cell array region and the peripheral circuit region or logic circuit region due to the height of the information storage capacitive element. [0037]
  • As a method of solving the problem of a steplike offset, i.e., a method of forming the fourth insulating film, a method of providing the fourth insulating film as an insulating film, in which a cylindrical groove is defined upon formation of the lower electrode of the information storage capacitive element, can be used. According to this method, it is not necessary to additionally form the fourth insulating film when the lower electrode of the information storage capacitive element is set to a cylindrical shape having an opening defined thereabove. Further, the fourth insulating film required upon formation of the lower electrode is used even for a reduction in the steplike offset, whereby the process can be simplified. Since the reduction in the steplike offset is performed in advance by the fourth insulating film upon depositing the third insulating film and polishing it by a CMP method in particular, the amount of polishing of the third insulating film by a CMP process does not increase, so that the load on the CMP process can be reduced. [0038]
  • Further, the third insulating film covers the information storage capacitive element and is deposited with a thickness greater than or equal to a size corresponding to the height of the information storage capacitive element, whereby the problem of a steplike offset can be also solved. In this case, the solution to the problem of the steplike offset is performed only by the deposition of the third insulating film and polishing of the third insulating film by a CMP method. Since the thickness of the third insulating film on the memory cell array region is so great, there may be cases in which the polishing thereof by the CMP method in this case experiences difficulties in ensuring the flatness thereof by the CMP method. In such a case, a layer (e.g., a silicon nitride film slower in polishing velocity than a silicon oxide film corresponding to a typical material for the third insulating film) for controlling the velocity of polishing by the CMP method can be deposited within the peripheral circuit region or logic circuit region alone. [0039]
  • In the method of manufacturing the semiconductor integrated circuit device, a first layer interconnection composed of the same material as that for each bit line can be formed over the first insulating film in the peripheral circuit region or logic circuit region simultaneously with the formation of the bit lines, and each connecting portion can be electrically connected to the first layer interconnection. According to such a method of manufacturing of the semiconductor integrated circuit device, the length of the connecting portion can be shortened. Namely, the depth of the connecting hole in which the connecting portion is formed is reduced, and the process for forming the connecting hole makes it easy to restrain or control the occurrence of a failure in processing, whereby the yield of the semiconductor integrated circuit device can be improved. [0040]
  • Further, the first conductive layer can be formed as a titanium nitride film and the second conductive layer can be formed as an aluminum film. In this case, after the deposition of the aluminum film, the semiconductor substrate is held under high pressure so that the aluminum film can be embedded in each connecting hole. [0041]
  • Alternatively, the first conductive layer can be formed as any one selected from a tantalum film, a niobium film, a tantalum nitride film, a titanium nitride film or a tungsten nitride film, or a plurality of thin films, and the second conductive layer can be formed as a copper film. In this case, the copper film can be deposited by a plating method. As the plating method, an electrolytic plating method or an electroless plating method can be employed by way of illustrative example. Further, a silicon nitride film can be deposited over the third insulating film and each interconnection.[0042]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description, when taken in connection with the accompanying drawings, in which: [0043]
  • FIG. 1 is a plan view showing one example of the entire semiconductor chip with a DRAM formed therein according to a first embodiment of the present invention; [0044]
  • FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment; [0045]
  • FIG. 3 is a fragmentary cross-sectional view of the DRAM according to the first embodiment; [0046]
  • FIG. 4 is a cross-sectional view illustrating one example of a method of manufacturing the DRAM according to the first embodiment in a process sequence; [0047]
  • FIG. 5 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in another process sequence; [0048]
  • FIG. 6 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a further process sequence; [0049]
  • FIG. 7 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0050]
  • FIG. 8 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0051]
  • FIG. 9 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0052]
  • FIG. 10 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0053]
  • FIG. 11 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0054]
  • FIG. 12 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0055]
  • FIG. 13 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0056]
  • FIG. 14 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0057]
  • FIG. 15 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0058]
  • FIG. 16 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0059]
  • FIG. 17 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0060]
  • FIG. 18 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0061]
  • FIG. 19 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0062]
  • FIG. 20 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0063]
  • FIG. 21 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0064]
  • FIG. 22 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0065]
  • FIG. 23 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0066]
  • FIG. 24 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0067]
  • FIG. 25 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0068]
  • FIG. 26 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0069]
  • FIG. 27 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0070]
  • FIG. 28 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the first embodiment in a still further process sequence; [0071]
  • FIG. 29 is a fragmentary cross-sectional view of a DRAM according to a second embodiment of the present invention; [0072]
  • FIG. 30 is a cross-sectional view showing one example of a method of manufacturing the DRAM according to the second embodiment in a process sequence; [0073]
  • FIG. 31 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the second embodiment in another process sequence; [0074]
  • FIG. 32 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the second embodiment in a further process sequence; [0075]
  • FIG. 33 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the second embodiment in a still further process sequence; [0076]
  • FIG. 34 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the second embodiment in a still further process sequence; [0077]
  • FIG. 35 is a cross-sectional view depicting one example of the method of manufacturing the DRAM according to the second embodiment in a still further process sequence; [0078]
  • FIG. 36 is a cross-sectional view showing one example of the method of manufacturing the DRAM according to the second embodiment in a still further process sequence; [0079]
  • FIG. 37 is a cross-sectional view illustrating one example of the method of manufacturing the DRAM according to the second embodiment in a still further process sequence; [0080]
  • FIG. 38 is a plan view showing one example of the entire semiconductor chip with a semiconductor integrated circuit device formed therein according to a third embodiment of the present invention; and [0081]
  • FIG. 39 is a fragmentary cross-sectional view of a DRAM according to the third embodiment.[0082]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Preferred embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings. In all the drawings for describing the respective embodiments, members or components having the same functions are identified by the same reference numerals and their repetitive description will therefore be omitted. [0083]
  • First Embodiment
  • FIG. 1 is a plan view showing one example of the entire semiconductor chip with a DRAM formed therein according to a first embodiment of the present invention. The DRAM according to the present embodiment has a storage capacity of 256 Mbits. Further, the DRAM has an outside size of 12×5 mm[0084] 2, for example and a memory occupancy rate of 58%. As shown in the drawing, a large number of memory arrays MARY are arranged or placed in matrix form over a principal surface of a semiconductor chip 1A comprised of monocrystalline silicon along an X direction (corresponding to the longitudinal direction of the semiconductor chip 1A) and a Y direction (corresponding to the transverse direction of the semiconductor chip 1A). Sense amplifiers SA are respectively placed between the memory arrays MARY arranged adjacent to each other along the X direction. 512 memory cells are electrically connected to bit lines BL electrically connected to the sense amplifiers SA. When a hierarchical word structure is adopted for the word lines, subword decoders SWD are respectively placed between the memory arrays MARY arranged adjacent to one another along the Y direction. Further, control circuits such as word drivers WD, data line selection circuits, etc., input/output circuits, bonding pads, etc. are arranged in the central portion of the principal surface of the semiconductor chip 1A.
  • FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment. As shown in the drawing, a memory array (MARY) of the present DRAM comprises a plurality of word lines WL (WLn−1, WLn, Wln+1, . . . ) and a plurality of bit lines BL placed in matrix form, and a plurality of memory cells (MC) placed at points where they intersect. One memory cell for storing 1-bit information therein comprises one capacitor C and one memory selection MISFET Qs electrically connected in series with the capacitor C. One of the source and drain of each memory selection MISFET Qs is electrically connected to a corresponding capacitor C and the other thereof is electrically connected to a corresponding bit line BL. One end of each word line WL is electrically connected to a corresponding word driver WD, and one end of each bit line BL is electrically connected to a corresponding sense amplifier SA. [0085]
  • FIG. 3 is a fragmentary cross-sectional view of the DRAM according to the first embodiment. In FIG. 3, an A region indicates some of a memory array MARY and a B region indicates some of a peripheral circuit. [0086]
  • A p-type well [0087] 2 lying within the A region, and a p-type well 3 and an n-type well 4 lying within the B region are formed over a principal surface of a semiconductor substrate 1 comprised of p-type monocrystalline silicon. Further, an n-type deep well 6 is formed so as to surround the p-type well 2. Incidentally, a threshold voltage control layer may be formed within each well.
  • Separation or isolation regions [0088] 7 are formed within principal or main surfaces of the respective wells, respectively. Each isolation region 7 is comprised of a silicon oxide film and is formed within a shallow groove 8 defined in the principal surface of the semiconductor substrate 1 with a thermally-oxidized silicon oxide film 9 interposed therebetween.
  • Memory selection MISFETs Qs of the DRAM are formed over the principal surface of the p-type well [0089] 2. Further, n channel MISFETs Qn and p channel MISFETs Qp are respectively formed over the principal surfaces of the p-type well 3 and the n-type well 4.
  • Each memory cell selection MISFET Qs comprises a gate electrode [0090] 11 formed on the principal surface of the p-type well 2 with a gate insulating film 10 interposed therebetween, and impurity semiconductor regions 12 formed in the principal surface of the p-type well 2 on both sides of each gate electrode 11. Each gate insulating film 10 is comprised of a silicon oxide film formed by thermal oxidation, which has a film thickness ranging from 7 nm to 8 nm, for example. The gate electrode 11 can be formed as a layered film of, for example, a polycrystal silicon film 11 a having a thickness of 70 nm, a titanium nitride film 11 b having a thickness of 50 nm and a tungsten film 11 c having a thickness of 100 nm. Further, an n-type impurity, for example, arsenic or phosphorous is introduced into the impurity semiconductor region 12.
  • A cap insulating film [0091] 13 composed of a silicon nitride film is formed in an upper layer of the gate electrode 11 of each memory cell selection MISFET Qs. Further, an upper layer of each cap insulating film 13 is covered with a silicon nitride film 14. The silicon nitride film 14 is formed even on a side wall of the gate electrode 11 and is used for self-alignment processing at the formation of connecting holes to be described later. Incidentally, the gate electrode 11 of the memory cell selection MISFET Qs functions as a word line of the DRAM. A word line WL is formed on the upper surface of each isolation region 7.