US20010013647A1 - Flexible substrate based ball grid array (BGA) package - Google Patents

Flexible substrate based ball grid array (BGA) package Download PDF

Info

Publication number
US20010013647A1
US20010013647A1 US09/839,212 US83921201A US2001013647A1 US 20010013647 A1 US20010013647 A1 US 20010013647A1 US 83921201 A US83921201 A US 83921201A US 2001013647 A1 US2001013647 A1 US 2001013647A1
Authority
US
United States
Prior art keywords
flexible film
chip
substrate
attaching area
flexible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/839,212
Other versions
US6380002B2 (en
Inventor
Kao-Yu Hsu
Shih-Chang Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/839,212 priority Critical patent/US6380002B2/en
Publication of US20010013647A1 publication Critical patent/US20010013647A1/en
Application granted granted Critical
Publication of US6380002B2 publication Critical patent/US6380002B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal

Definitions

  • This invention generally relates to flexible substrate based ball grid array (BGA) packages, and more particularly to flexible film substrates for use in forming flexible substrate based BGA packages and manufacturing methods thereof.
  • BGA ball grid array
  • FIG. 1 depicts a conventional flexible substrate based BGA package 100 typically utilizing a flexible film substrate 110 (see FIG. 2) for carrying a semiconductor chip 120 .
  • the flexible film substrate 110 is provided with a plurality of chip connection pads 110 a arranged about the periphery of the semiconductor chip 120 .
  • the semiconductor chip 120 is securely attached onto the flexible film substrate 110 through a nonconductive adhesive (e.g., epoxy resin) 122 and electrically connected to the chip connection pads 110 a through a plurality of bonding wires 130 .
  • the chip connection pads 110 a are electrically connected to a plurality of solder pads 110 b through conductive traces 110 d .
  • the flexible film substrate 110 has a plurality of through-hole 110 c disposed corresponding to solder pads 110 b . Each solder pad 110 b has a portion exposed within the corresponding through-hole 110 c for mounting a solder ball 140 .
  • the upper surface of the flexible film substrate 110 , the semiconductor chip 120 and the bonding wires 130 are encapsulated in a package body 150 .
  • the package body 150 is formed from insulating material such as epoxy.
  • the flexible substrate based BGA package 100 is mounted to a substrate (not shown), such as a printed circuit board, through the solder balls 140 .
  • the surfaces of the chip connection pads 110 a and solder pads 110 b are plated with a layer of metal (not shown) such as gold which bonds well with conventional bonding wire material.
  • a layer of metal such as gold which bonds well with conventional bonding wire material.
  • gold does not bond well with the nonconductive adhesive 122 , so the central part of the chip attaching area is not provided with solder pads in order to enhance the adhesion between the flexible film substrate 110 and the nonconductive adhesive 122 , whereby the semiconductor chip 120 is more securely attached onto the flexible film substrate 110 .
  • solder pads 110 b are not evenly distributed on the chip attaching area 160 of the flexible film substrate 110 , the central part thereof is prone to be deformed by the stress due to CTE (coefficient of thermal expansion) mismatch between the central part and other part of the chip attaching area 160 . This may create problems of delamination between the chip and the substrate or die cracking.
  • It is a primary object of the present invention to provide a flexible substrate based BGA package comprising a flexible film substrate having a die attaching area for carrying a semiconductor chip, wherein the flexible film substrate is provided with at least a dummy pad disposed centrally on the chip attaching area, thereby reducing problems of delamination between the chip and the substrate or die cracking.
  • It is another object of the present invention to provide a flexible substrate based BGA package comprising a semiconductor chip securely attached onto a die attaching area of a flexible film substrate through a nonconductive adhesive, wherein the flexible film substrate is provided with at least a dummy pad disposed centrally on the chip attaching area, and the dummy pad has a cupric oxide coating formed thereon for enhancing its adhesion with the nonconductive adhesive.
  • a flexible substrate based BGA package in accordance with a preferred embodiment of the present invention generally comprises a semiconductor chip securely attached onto a flexible film substrate through a nonconductive adhesive.
  • the flexible film substrate includes a flexible film having a chip attaching area for carrying the semiconductor chip.
  • the upper surface of the flexible film is provided with a plurality of chip connection pads, a plurality of solder pads, and at least a dummy pad which is disposed centrally on the chip attaching area.
  • the surface of the dummy pad has a cupric oxide coating for enhancing its adhesion with the nonconductive adhesive.
  • the chip connection pads are arranged about the periphery of the chip attaching area.
  • the solder pads are disposed about the dummy pad(s) and electrically connected to the corresponding chip connection pads.
  • the flexible film has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the corresponding through-hole for mounting a solder ball.
  • a package body is formed over the semiconductor chip and the upper surface of the flexible film substrate.
  • the flexible substrate based BGA package of the present invention since at least a dummy pad is disposed centrally on the chip attaching area of the flexible film substrate, the central part of the chip attaching area of the substrate has a better rigidity and strength to resist external forces thereby reducing the problems of die cracking or delamination.
  • the cupric oxide coating on the surface of the dummy pad has a contour of roughness, so the bonding mechanism of the interface between the cupric oxide coating and the nonconductive adhesive includes chemical bonding as well as mechanical interlock thereby greatly enhancing the adhesion between the dummy pad and the nonconductive adhesive thereby reducing the occurrence of delamination.
  • the present invention further provides a method for producing a flexible film substrate comprising the steps of: (A) providing a flexible film having opposing upper and lower surfaces, the upper surface of the flexible film has a chip attaching area adapted for carrying a semiconductor chip; (B) forming a plurality of through-holes in the flexible film; (C) laminating a metal layer on the upper surface of the flexible film; and (D) etching the metal layer to form a plurality of solder pads, chip connection pads, conductive traces, and at least a dummy pad, wherein the solder pads are disposed corresponding to the through-holes and electrically connected to the chip connection pads through the conductive traces, and the dummy pad is disposed centrally on the chip attaching area.
  • FIG. 1 is a cross sectional view of a conventional flexible substrate based BGA package
  • FIG. 2 is a top plan view of a flexible film substrate employed in the flexible substrate based BGA package of FIG. 1;
  • FIG. 3 is a cross sectional view of a flexible substrate based BGA package according to a preferred embodiment of the present invention.
  • FIGS. 4 - 6 are cross sectional views for illustrating a method for producing a flexible film substrate in accordance with the present invention.
  • FIG. 7 is a top plan view of a flexible film substrate according to a first embodiment of the present invention.
  • FIG. 8 is a top plan view of a flexible film substrate according to a second embodiment of the present invention.
  • FIG. 9 is a top plan view of a flexible film substrate according to a third embodiment of the present invention.
  • FIG. 3 illustrates a flexible substrate based BGA package 200 according to a preferred embodiment of the present invention mainly comprising a semiconductor chip 210 securely attached onto the upper surface of a flexible film substrate 220 by a nonconductive adhesive (e.g. epoxy resin) 212 .
  • a nonconductive adhesive e.g. epoxy resin
  • the flexible film substrate 220 is mainly formed from a flexible film 220 a having a chip attaching area 220 b adapted for carrying the semiconductor chip 210 .
  • the upper surface of flexible film 220 a is provided with a plurality of chip connection pads 220 c electrically connected to the corresponding solder pads 220 d through conductive traces 220 e formed on the upper surface of the flexible film 220 a .
  • the chip connection pads 220 c are arranged about the periphery of the chip attaching area 220 b and electrically connected to the semiconductor chip 210 through a plurality of bonding wires 230 .
  • the flexible film 220 a has a plurality of through-holes formed corresponding to the solder pads 220 d such that each solder pad 220 d has at least a portion exposed within the corresponding through-hole for mounting a solder ball 222 .
  • a package body 240 is formed over the semiconductor chip 210 and the upper surface of the flexible film substrate 220 .
  • the solder balls 222 are provided on the lower surface of the flexible film substrate 220 for making external electrical connection.
  • the present invention is characterized in that the flexible film substrate 220 is provided with at least a dummy pad disposed centrally on the chip attaching area 220 b .
  • the dummy pads 220 f are formed as a discontinuous pattern and evenly distributed on the central part of the chip attaching area (see FIGS. 6 - 9 ), whereby optimum reinforcing effect can be achieved without interfering the flow of the nonconductive adhesive 212 .
  • the dummy pad 220 f in accordance with the present invention may be bar-like, oval-shaped or circular as shown in FIGS. 7 - 9 . It will be appreciated that the number and shapes of the dummy pads are not limited to the embodiments of FIGS. 6 - 9 as long as the flow of the nonconductive adhesive 212 is not interfered and the central part of the chip attaching area of the substrate is reinforced.
  • FIGS. 4 - 6 show a method for producing a flexible film substrate in accordance with the present invention.
  • a plurality of through-holes are formed in the flexible film 220 a by conventional techniques such as punching or laser drilling.
  • the through-holes are formed at locations corresponding to the solder pads 220 d disposed at the bottom section of the package 200 (see FIG. 3).
  • the flexible film 220 a is made of polyimide such that the flexible film is given properties that allow it to pass reliability tests.
  • a metal layer such as a copper foil 221 is laminated on the flexible film 220 a by conventional methods such as thermocompression.
  • the chip connection pads 220 c , the solder pads 220 d , conductive traces 220 e (not shown in FIG. 6), and the dummy pads 220 f are formed by photolithography and etching which comprise the steps of: (A) applying a photoresist layer on the surface of the metal layer; (B) pattern (referring to FIG. 7) transferring by photolithography; (C) removing the unprotected portions of the metal layer to form the corresponding chip connection pads 220 c , solder pads 220 d , conductive traces 220 e , and dummy pads 220 f by etching; and (D) removing the remaining photoresist layer.
  • the chip connection pads 220 c , the solder pads 220 d , and conductive traces 220 e are provided with a metal coating formed on the surfaces thereof which are not covered by the flexible film 220 a .
  • the metal coating may be plated by conventional techniques.
  • a layer of nickel is plated thereon and then a layer of gold is plated on the nickel layer. Since the metal coating is also formed on the connection pads adapted for electrical connecting to the chip, the metal coating should be formed of materials that allow a good bond to the conventional bonding wire material.
  • the dummy pads 220 f are provided with a cupric oxide coating formed on the surface thereof.
  • the cupric oxide coating 220 a is preferably formed by the method of anodic oxidation: (A) Areas on the flexible film substrate at which it is undesired to form a cupric oxide coating are protected by tapes, e.g., the chip connection pads 220 c , the solder pads 220 d , and conductive traces 220 e ; (B) The flexible film substrate with protective tapes is electrolyzed as the anode in an alkaline solution such as sodium hydroxide electrolytic solution, thereby forming a cupric oxide coating on the surface of the flexible film substrate without protection of tapes.
  • an alkaline solution such as sodium hydroxide electrolytic solution
  • the principal crystal structure of the cupric oxide coating layer is composed of acicular crystals which are black in color and densely packed; hence, the cupric oxide coating has a rough appearance with a color of black.
  • the cupric oxide coating on the dummy pads according to the present invention can be formed by the method of chemical oxidation: the step (A) is identical to the method described above; (B′) The flexible film substrate with protective tapes is immersed in a chemical oxidation solution (such as water solution of 3% sodium chloride, 1% sodium hydroxide and 1% sodium phosphate by weight) and heated at 85° C.
  • a chemical oxidation solution such as water solution of 3% sodium chloride, 1% sodium hydroxide and 1% sodium phosphate by weight
  • the central part of the chip attaching area of the substrate since at least a dummy pad is disposed centrally on the chip attaching area of the flexible film substrate, the central part of the chip attaching area of the substrate has a better rigidity and strength to resist external forces. Further, since the dummy pads of the present invention are evenly distributed on the central part of the chip attaching area, the central part of the chip attaching area has a CTE substantially equal to other part thereof thereby reducing the stress due to CTE mismatch therebetween. Thus, the flexible film substrate in accordance with the present invention greatly reduces the problems of die cracking or delamination.
  • the cupric oxide coating on the surface of the dummy pads is composed of acicular crystals which are black in color and densely packed
  • the gaps among the acicular crystals will be filled by the nonconductive adhesive (e.g., epoxy resin) employed in the die attaching process.
  • the nonconductive adhesive will provide mechanical interlock mechanism to enhance the adhesion between the cupric oxide coating and the nonconductive adhesive, thereby reducing the occurrence of delamination between the flexible film substrate and the nonconductive adhesive.

Abstract

A flexible substrate based BGA package mainly comprises a semiconductor chip securely attached onto a flexible film substrate through a nonconductive adhesive. The flexible film substrate is formed from a flexible film having a chip attaching area for carrying the semiconductor chip. The upper surface of the flexible film is provided with a plurality of chip connection pads, a plurality of solder pads, and at least a dummy pad which is disposed centrally on the chip attaching area. The purpose of the dummy pad is to increase the rigidity and strength of the central part of the chip attaching area. The chip connection pads are arranged about the periphery of the chip attaching area for electrically connected to the semiconductor chip. The solder pads are disposed about the dummy pad(s) and electrically connected to the corresponding chip connection pads. The flexible film has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the corresponding through-hole for mounting a solder ball. A package body is formed over the semiconductor chip and the upper surface of the flexible film substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention generally relates to flexible substrate based ball grid array (BGA) packages, and more particularly to flexible film substrates for use in forming flexible substrate based BGA packages and manufacturing methods thereof. [0002]
  • 2. Description of the Related Art [0003]
  • FIG. 1 depicts a conventional flexible substrate based BGA [0004] package 100 typically utilizing a flexible film substrate 110 (see FIG. 2) for carrying a semiconductor chip 120. The flexible film substrate 110 is provided with a plurality of chip connection pads 110 a arranged about the periphery of the semiconductor chip 120. The semiconductor chip 120 is securely attached onto the flexible film substrate 110 through a nonconductive adhesive (e.g., epoxy resin) 122 and electrically connected to the chip connection pads 110 a through a plurality of bonding wires 130. The chip connection pads 110 a are electrically connected to a plurality of solder pads 110 b through conductive traces 110 d. The flexible film substrate 110 has a plurality of through-hole 110 c disposed corresponding to solder pads 110 b. Each solder pad 110 b has a portion exposed within the corresponding through-hole 110 c for mounting a solder ball 140. The upper surface of the flexible film substrate 110, the semiconductor chip 120 and the bonding wires 130 are encapsulated in a package body 150. The package body 150 is formed from insulating material such as epoxy. The flexible substrate based BGA package 100 is mounted to a substrate (not shown), such as a printed circuit board, through the solder balls 140.
  • Typically, the surfaces of the [0005] chip connection pads 110 a and solder pads 110 b are plated with a layer of metal (not shown) such as gold which bonds well with conventional bonding wire material. However, gold does not bond well with the nonconductive adhesive 122, so the central part of the chip attaching area is not provided with solder pads in order to enhance the adhesion between the flexible film substrate 110 and the nonconductive adhesive 122, whereby the semiconductor chip 120 is more securely attached onto the flexible film substrate 110. However, since the solder pads 110 b are not evenly distributed on the chip attaching area 160 of the flexible film substrate 110, the central part thereof is prone to be deformed by the stress due to CTE (coefficient of thermal expansion) mismatch between the central part and other part of the chip attaching area 160. This may create problems of delamination between the chip and the substrate or die cracking.
    • SUMMARY OF THE INVENTION
  • It is a primary object of the present invention to provide a flexible substrate based BGA package comprising a flexible film substrate having a die attaching area for carrying a semiconductor chip, wherein the flexible film substrate is provided with at least a dummy pad disposed centrally on the chip attaching area, thereby reducing problems of delamination between the chip and the substrate or die cracking. [0006]
  • It is another object of the present invention to provide a flexible substrate based BGA package comprising a semiconductor chip securely attached onto a die attaching area of a flexible film substrate through a nonconductive adhesive, wherein the flexible film substrate is provided with at least a dummy pad disposed centrally on the chip attaching area, and the dummy pad has a cupric oxide coating formed thereon for enhancing its adhesion with the nonconductive adhesive. [0007]
  • A flexible substrate based BGA package in accordance with a preferred embodiment of the present invention generally comprises a semiconductor chip securely attached onto a flexible film substrate through a nonconductive adhesive. The flexible film substrate includes a flexible film having a chip attaching area for carrying the semiconductor chip. The upper surface of the flexible film is provided with a plurality of chip connection pads, a plurality of solder pads, and at least a dummy pad which is disposed centrally on the chip attaching area. Preferably, the surface of the dummy pad has a cupric oxide coating for enhancing its adhesion with the nonconductive adhesive. The chip connection pads are arranged about the periphery of the chip attaching area. The solder pads are disposed about the dummy pad(s) and electrically connected to the corresponding chip connection pads. The flexible film has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the corresponding through-hole for mounting a solder ball. A package body is formed over the semiconductor chip and the upper surface of the flexible film substrate. [0008]
  • According to the flexible substrate based BGA package of the present invention, since at least a dummy pad is disposed centrally on the chip attaching area of the flexible film substrate, the central part of the chip attaching area of the substrate has a better rigidity and strength to resist external forces thereby reducing the problems of die cracking or delamination. Further, the cupric oxide coating on the surface of the dummy pad has a contour of roughness, so the bonding mechanism of the interface between the cupric oxide coating and the nonconductive adhesive includes chemical bonding as well as mechanical interlock thereby greatly enhancing the adhesion between the dummy pad and the nonconductive adhesive thereby reducing the occurrence of delamination. [0009]
  • The present invention further provides a method for producing a flexible film substrate comprising the steps of: (A) providing a flexible film having opposing upper and lower surfaces, the upper surface of the flexible film has a chip attaching area adapted for carrying a semiconductor chip; (B) forming a plurality of through-holes in the flexible film; (C) laminating a metal layer on the upper surface of the flexible film; and (D) etching the metal layer to form a plurality of solder pads, chip connection pads, conductive traces, and at least a dummy pad, wherein the solder pads are disposed corresponding to the through-holes and electrically connected to the chip connection pads through the conductive traces, and the dummy pad is disposed centrally on the chip attaching area. [0010]
  • Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. [0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross sectional view of a conventional flexible substrate based BGA package; [0012]
  • FIG. 2 is a top plan view of a flexible film substrate employed in the flexible substrate based BGA package of FIG. 1; [0013]
  • FIG. 3 is a cross sectional view of a flexible substrate based BGA package according to a preferred embodiment of the present invention; [0014]
  • FIGS. [0015] 4-6 are cross sectional views for illustrating a method for producing a flexible film substrate in accordance with the present invention;
  • FIG. 7 is a top plan view of a flexible film substrate according to a first embodiment of the present invention; [0016]
  • FIG. 8 is a top plan view of a flexible film substrate according to a second embodiment of the present invention; and [0017]
  • FIG. 9 is a top plan view of a flexible film substrate according to a third embodiment of the present invention. [0018]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIG. 3 illustrates a flexible substrate based BGA package [0019] 200 according to a preferred embodiment of the present invention mainly comprising a semiconductor chip 210 securely attached onto the upper surface of a flexible film substrate 220 by a nonconductive adhesive (e.g. epoxy resin) 212.
  • Referring to FIG. 3 and FIG. 7, the [0020] flexible film substrate 220 is mainly formed from a flexible film 220 a having a chip attaching area 220 b adapted for carrying the semiconductor chip 210. The upper surface of flexible film 220 a is provided with a plurality of chip connection pads 220 c electrically connected to the corresponding solder pads 220 d through conductive traces 220 e formed on the upper surface of the flexible film 220 a. The chip connection pads 220 c are arranged about the periphery of the chip attaching area 220 b and electrically connected to the semiconductor chip 210 through a plurality of bonding wires 230. The flexible film 220 a has a plurality of through-holes formed corresponding to the solder pads 220 d such that each solder pad 220 d has at least a portion exposed within the corresponding through-hole for mounting a solder ball 222. A package body 240 is formed over the semiconductor chip 210 and the upper surface of the flexible film substrate 220. The solder balls 222 are provided on the lower surface of the flexible film substrate 220 for making external electrical connection.
  • Referring to FIG. 3 and FIG. 7 again, the present invention is characterized in that the [0021] flexible film substrate 220 is provided with at least a dummy pad disposed centrally on the chip attaching area 220 b. Preferably, the dummy pads 220 f are formed as a discontinuous pattern and evenly distributed on the central part of the chip attaching area (see FIGS. 6-9), whereby optimum reinforcing effect can be achieved without interfering the flow of the nonconductive adhesive 212. The dummy pad 220 f in accordance with the present invention may be bar-like, oval-shaped or circular as shown in FIGS. 7-9. It will be appreciated that the number and shapes of the dummy pads are not limited to the embodiments of FIGS. 6-9 as long as the flow of the nonconductive adhesive 212 is not interfered and the central part of the chip attaching area of the substrate is reinforced.
  • FIGS. [0022] 4-6 show a method for producing a flexible film substrate in accordance with the present invention.
  • Referring to FIG. 4, a plurality of through-holes are formed in the [0023] flexible film 220 a by conventional techniques such as punching or laser drilling. The through-holes are formed at locations corresponding to the solder pads 220 d disposed at the bottom section of the package 200 (see FIG. 3). Preferably, the flexible film 220 a is made of polyimide such that the flexible film is given properties that allow it to pass reliability tests.
  • Referring to FIG. 5, a metal layer such as a [0024] copper foil 221 is laminated on the flexible film 220 a by conventional methods such as thermocompression.
  • Referring to FIG. 6, the [0025] chip connection pads 220 c, the solder pads 220 d, conductive traces 220 e (not shown in FIG. 6), and the dummy pads 220 f are formed by photolithography and etching which comprise the steps of: (A) applying a photoresist layer on the surface of the metal layer; (B) pattern (referring to FIG. 7) transferring by photolithography; (C) removing the unprotected portions of the metal layer to form the corresponding chip connection pads 220 c, solder pads 220 d, conductive traces 220 e, and dummy pads 220 f by etching; and (D) removing the remaining photoresist layer. Preferably, the chip connection pads 220 c, the solder pads 220 d, and conductive traces 220 e are provided with a metal coating formed on the surfaces thereof which are not covered by the flexible film 220 a. The metal coating may be plated by conventional techniques. Preferably, a layer of nickel is plated thereon and then a layer of gold is plated on the nickel layer. Since the metal coating is also formed on the connection pads adapted for electrical connecting to the chip, the metal coating should be formed of materials that allow a good bond to the conventional bonding wire material.
  • Preferably, the [0026] dummy pads 220 f are provided with a cupric oxide coating formed on the surface thereof. The cupric oxide coating 220 a is preferably formed by the method of anodic oxidation: (A) Areas on the flexible film substrate at which it is undesired to form a cupric oxide coating are protected by tapes, e.g., the chip connection pads 220 c, the solder pads 220 d, and conductive traces 220 e; (B) The flexible film substrate with protective tapes is electrolyzed as the anode in an alkaline solution such as sodium hydroxide electrolytic solution, thereby forming a cupric oxide coating on the surface of the flexible film substrate without protection of tapes. The principal crystal structure of the cupric oxide coating layer is composed of acicular crystals which are black in color and densely packed; hence, the cupric oxide coating has a rough appearance with a color of black. Alternatively, the cupric oxide coating on the dummy pads according to the present invention can be formed by the method of chemical oxidation: the step (A) is identical to the method described above; (B′) The flexible film substrate with protective tapes is immersed in a chemical oxidation solution (such as water solution of 3% sodium chloride, 1% sodium hydroxide and 1% sodium phosphate by weight) and heated at 85° C.
  • According to one aspect of the present invention, since at least a dummy pad is disposed centrally on the chip attaching area of the flexible film substrate, the central part of the chip attaching area of the substrate has a better rigidity and strength to resist external forces. Further, since the dummy pads of the present invention are evenly distributed on the central part of the chip attaching area, the central part of the chip attaching area has a CTE substantially equal to other part thereof thereby reducing the stress due to CTE mismatch therebetween. Thus, the flexible film substrate in accordance with the present invention greatly reduces the problems of die cracking or delamination. [0027]
  • According to another aspect of the present invention, since the cupric oxide coating on the surface of the dummy pads is composed of acicular crystals which are black in color and densely packed, the gaps among the acicular crystals will be filled by the nonconductive adhesive (e.g., epoxy resin) employed in the die attaching process. After curing, the nonconductive adhesive will provide mechanical interlock mechanism to enhance the adhesion between the cupric oxide coating and the nonconductive adhesive, thereby reducing the occurrence of delamination between the flexible film substrate and the nonconductive adhesive. [0028]
  • Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. [0029]

Claims (15)

What is claimed is:
1. A flexible substrate based ball grid array (BGA) package comprising:
a flexible film substrate comprising a flexible film having opposing upper and lower surfaces, the upper surface of the flexible film has a chip attaching area; at least a dummy pad disposed centrally on the chip attaching area; a plurality of chip connection pads arranged about the periphery of the chip attaching area; and a plurality of solder pads on the upper surface of the flexible film electrically connected to the corresponding chip connection pads, wherein the flexible film has a plurality of through-holes formed corresponding to the solder pads;
a plurality of solder balls mounted to the solder pads of the flexible film substrate for making external electrical connection;
a semiconductor chip securely attached onto the chip attaching area of the flexible film substrate, the chip having a plurality of bonding pads electrically connected to the corresponding chip connection pads; and
a package body formed over the semiconductor chip and the upper surface of the flexible film substrate.
2. The flexible substrate based BGA package as claimed in
claim 1
, wherein the flexible film is made of polyimide.
3. The flexible substrate based BGA package as claimed in
claim 1
, wherein the dummy pad is made of copper.
4. The flexible substrate based BGA package as claimed in
claim 3
, further comprising a cupric oxide coating formed on the dummy pad.
5. A flexible film substrate for use in forming a flexible substrate based BGA package, the flexible film substrate comprising:
a flexible film having opposing upper and lower surfaces, the upper surface of the flexible film has a chip attaching area adapted for supporting a semiconductor chip;
at least a dummy pad disposed centrally on the chip attaching area;
a plurality of chip connection pads arranged about the periphery of the chip attaching area for electrically connected to the semiconductor chip; and
a plurality of solder pads on the upper surface of the flexible film electrically connected to the corresponding chip connection pads, wherein the flexible film has a plurality of through-holes formed corresponding to the solder pads.
6. The flexible film substrate as claimed in
claim 5
, wherein the flexible film is made of polyimide.
7. The flexible film substrate as claimed in
claim 5
, wherein the dummy pad is made of copper.
8. The flexible film substrate as claimed in
claim 7
, further comprising a cupric oxide coating formed on the dummy pad.
9. The flexible film substrate as claimed in
claim 5
, wherein the substrate is one of a plurality of substrates formed in a strip configuration for use in forming a plurality of substrate-based semiconductor chip package.
10. A method for manufacturing a flexible film substrate comprising the steps of:
providing a flexible film having opposing upper and lower surfaces, the upper surface of the flexible film has a chip attaching area adapted for supporting a semiconductor chip;
forming a plurality of through-holes in the flexible film;
laminating a metal layer on the upper surface of the flexible film; and
etching the metal layer to form a plurality of solder pads, chip connection pads, conductive traces, and at least a dummy pad, wherein the solder pads are disposed corresponding to the through-holes and electrically connected to the chip connection pads through the conductive traces, and the dummy pad is disposed centrally on the chip attaching area.
11. The method as claimed in
claim 10
, wherein the flexible film is made of polyimide.
12. The method as claimed in
claim 10
, wherein the metal layer is a copper foil.
13. The method as claimed in
claim 12
, further comprising a step of forming a cupric oxide coating on the surface of the dummy pad.
14. The method as claimed in
claim 13
, wherein the cupric oxide coating is formed by means of anodic oxidation.
15. The method as claimed in
claim 13
, wherein the cupric oxide coating is formed by means of chemical oxidation.
US09/839,212 1999-12-07 2001-04-23 Method for fabricating a flexible substrate based ball grid array (BGA) package Expired - Lifetime US6380002B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/839,212 US6380002B2 (en) 1999-12-07 2001-04-23 Method for fabricating a flexible substrate based ball grid array (BGA) package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/455,918 US6242815B1 (en) 1999-12-07 1999-12-07 Flexible substrate based ball grid array (BGA) package
US09/839,212 US6380002B2 (en) 1999-12-07 2001-04-23 Method for fabricating a flexible substrate based ball grid array (BGA) package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/455,918 Division US6242815B1 (en) 1999-12-07 1999-12-07 Flexible substrate based ball grid array (BGA) package

Publications (2)

Publication Number Publication Date
US20010013647A1 true US20010013647A1 (en) 2001-08-16
US6380002B2 US6380002B2 (en) 2002-04-30

Family

ID=23810753

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/455,918 Expired - Lifetime US6242815B1 (en) 1999-12-07 1999-12-07 Flexible substrate based ball grid array (BGA) package
US09/839,212 Expired - Lifetime US6380002B2 (en) 1999-12-07 2001-04-23 Method for fabricating a flexible substrate based ball grid array (BGA) package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/455,918 Expired - Lifetime US6242815B1 (en) 1999-12-07 1999-12-07 Flexible substrate based ball grid array (BGA) package

Country Status (1)

Country Link
US (2) US6242815B1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573612B1 (en) * 1999-07-30 2003-06-03 Sharp Kabushiki Kaisha Resin-encapsulated semiconductor device including resin extending beyond edge of substrate
WO2004017407A1 (en) * 2002-07-31 2004-02-26 Osram Opto Semiconductors Gmbh Surface-mounted semiconductor component and method for the production thereof
US20080006949A1 (en) * 2006-06-19 2008-01-10 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US20110074037A1 (en) * 2009-09-29 2011-03-31 Elpida Memory, Inc. Semiconductor device
US20110182042A1 (en) * 2007-07-05 2011-07-28 Occam Portfolio Llc Electronic Assemblies without Solder and Methods for their Manufacture
US20120086111A1 (en) * 2010-10-12 2012-04-12 Elpida Memory, Inc. Semiconductor device
CN107801291A (en) * 2016-09-06 2018-03-13 奕力科技股份有限公司 Electrostatic discharge protection device and electrostatic discharge protection method

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236040A (en) * 1999-02-15 2000-08-29 Hitachi Ltd Semiconductor device
JP3403689B2 (en) * 1999-06-25 2003-05-06 沖電気工業株式会社 Semiconductor device
JP3610262B2 (en) * 1999-07-22 2005-01-12 新光電気工業株式会社 Multilayer circuit board and semiconductor device
US6242815B1 (en) * 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package
TW469552B (en) 1999-12-10 2001-12-21 Toshiba Corp TAB type semiconductor device
JP2001284783A (en) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd Substrate for surface-mounting and surface-mounting structure
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
JP3874062B2 (en) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 Semiconductor device
US6403896B1 (en) * 2000-09-27 2002-06-11 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
JP2002118201A (en) * 2000-10-05 2002-04-19 Hitachi Ltd Semiconductor device and method for manufacturing the same
JP4354109B2 (en) * 2000-11-15 2009-10-28 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
KR20020065045A (en) * 2001-02-05 2002-08-13 삼성전자 주식회사 Semiconductor chip package comprising enhanced pads
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
US6528417B1 (en) * 2001-09-17 2003-03-04 Taiwan Semiconductor Manufacturing Company Metal patterned structure for SiN surface adhesion enhancement
JP2003100803A (en) * 2001-09-27 2003-04-04 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US6979894B1 (en) 2001-09-27 2005-12-27 Marvell International Ltd. Integrated chip package having intermediate substrate
US6573595B1 (en) * 2002-04-24 2003-06-03 Scientek Corp. Ball grid array semiconductor package with resin coated metal core
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US6650016B1 (en) * 2002-10-01 2003-11-18 International Business Machines Corporation Selective C4 connection in IC packaging
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
SE0300686D0 (en) * 2003-03-13 2003-03-13 Infineon Technologies Wireless A method and device for protection of a component or module
US6744131B1 (en) * 2003-04-22 2004-06-01 Xilinx, Inc. Flip chip integrated circuit packages accommodating exposed chip capacitors while providing structural rigidity
CN100463125C (en) * 2003-06-25 2009-02-18 宇芯（毛里求斯）控股有限公司 Lead frame routed chip pads for semiconductor packages
US6933596B2 (en) * 2003-07-01 2005-08-23 Northrop Grumman Corporation Ultra wideband BGA
US6992380B2 (en) * 2003-08-29 2006-01-31 Texas Instruments Incorporated Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area
US7019403B2 (en) * 2003-08-29 2006-03-28 Freescale Semiconductor, Inc. Adhesive film and tacking pads for printed wiring assemblies
DE102004020580A1 (en) * 2004-04-27 2005-11-17 Infineon Technologies Ag Method of manufacturing a BGA chip module and BGA chip module
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
TWI246175B (en) * 2004-10-11 2005-12-21 Ind Tech Res Inst Bonding structure of device packaging
CN100416807C (en) * 2004-10-20 2008-09-03 力晶半导体股份有限公司 Semiconductor package structure and producing method thereof
US20060186180A1 (en) * 2005-02-24 2006-08-24 Northrop Grumman Corporation Accurate relative alignment and epoxy-free attachment of optical elements
US8101464B2 (en) * 2006-08-30 2012-01-24 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
JP2009295958A (en) * 2008-05-09 2009-12-17 Panasonic Corp Semiconductor device
US20100052122A1 (en) * 2008-08-27 2010-03-04 Advanced Semiconductor Engineering, Inc. Wire bodning package structure
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US8288869B2 (en) * 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US8367473B2 (en) * 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
TW201041105A (en) * 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
TWI425603B (en) * 2009-09-08 2014-02-01 Advanced Semiconductor Eng Chip package
US8786062B2 (en) * 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (en) 2010-03-22 2013-10-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US20120032327A1 (en) * 2010-08-09 2012-02-09 Fujitsu Limited Systems and methods for reinforcing chip packages
KR20130010359A (en) * 2011-07-18 2013-01-28 삼성전자주식회사 Substrate for semiconductor package and semiconductor package comprising thereof
US9023690B2 (en) 2012-11-19 2015-05-05 United Test And Assembly Center Leadframe area array packaging technology
US9397027B1 (en) * 2014-05-07 2016-07-19 Maxim Integrated Products, Inc. Sacrificial pad on semiconductor package device and method
CN110915305B (en) * 2018-04-09 2023-08-18 北京比特大陆科技有限公司 Circuit board, chip, series circuit, circuit board and electronic device
CN108684141A (en) * 2018-04-20 2018-10-19 胜宏科技（惠州）股份有限公司 A method of improving hole copper copper thickness uniformity

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468908A (en) * 1987-09-09 1989-03-15 Fujikura Ltd Manufacture of oxide superconducting coil
JPH03193896A (en) * 1989-12-25 1991-08-23 Kasei Naoetsu:Kk Metal sheet for plastic working and inner pot for heat cooker
JPH06291153A (en) * 1993-04-06 1994-10-18 Oki Electric Ind Co Ltd Semiconductor chip mounting construction
JPH0763818A (en) * 1993-08-30 1995-03-10 Sharp Corp Burn-in method for flip chip integrated circuit
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
JPH07273243A (en) * 1994-03-30 1995-10-20 Toshiba Corp Semiconductor package
KR100194130B1 (en) * 1994-03-30 1999-06-15 니시무로 타이죠 Semiconductor package
JPH07302858A (en) * 1994-04-28 1995-11-14 Toshiba Corp Semiconductor package
JP3412942B2 (en) * 1995-01-11 2003-06-03 株式会社東芝 Semiconductor device
KR100206866B1 (en) * 1995-10-19 1999-07-01 구본준 Semiconductor apparatus
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
US5756380A (en) * 1995-11-02 1998-05-26 Motorola, Inc. Method for making a moisture resistant semiconductor device having an organic substrate
JP3437369B2 (en) 1996-03-19 2003-08-18 松下電器産業株式会社 Chip carrier and semiconductor device using the same
JP3679199B2 (en) * 1996-07-30 2005-08-03 日本テキサス・インスツルメンツ株式会社 Semiconductor package equipment
US5909058A (en) * 1996-09-25 1999-06-01 Kabushiki Kaisha Toshiba Semiconductor package and semiconductor mounting part
JP2845227B2 (en) * 1996-11-29 1999-01-13 日本電気株式会社 Multi-chip module mounting structure
JP3310617B2 (en) * 1998-05-29 2002-08-05 シャープ株式会社 Resin-sealed semiconductor device and method of manufacturing the same
JP4045648B2 (en) * 1998-06-10 2008-02-13 ソニー株式会社 Semiconductor device
JP2000138251A (en) * 1998-11-04 2000-05-16 Toshiba Corp Semiconductor device and wiring board
US6242815B1 (en) * 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573612B1 (en) * 1999-07-30 2003-06-03 Sharp Kabushiki Kaisha Resin-encapsulated semiconductor device including resin extending beyond edge of substrate
WO2004017407A1 (en) * 2002-07-31 2004-02-26 Osram Opto Semiconductors Gmbh Surface-mounted semiconductor component and method for the production thereof
US20050212098A1 (en) * 2002-07-31 2005-09-29 Osram Opto Semiconductors Gmbh Surface-mountable semiconductor component and method for producing it
US7199470B2 (en) 2002-07-31 2007-04-03 Osram Opto Semiconductors Gmbh Surface-mountable semiconductor component and method for producing it
US20070184629A1 (en) * 2002-07-31 2007-08-09 Georg Bogner Method for producing a surface-mountable semiconductor component
US7488622B2 (en) 2002-07-31 2009-02-10 Osram Opto Semiconductors Gmbh Method for producing a surface-mountable semiconductor component
US20080006949A1 (en) * 2006-06-19 2008-01-10 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US7612450B2 (en) * 2006-06-19 2009-11-03 Samsung Electronics Co., Ltd. Semiconductor package including dummy board and method of fabricating the same
US20110182042A1 (en) * 2007-07-05 2011-07-28 Occam Portfolio Llc Electronic Assemblies without Solder and Methods for their Manufacture
US20110074037A1 (en) * 2009-09-29 2011-03-31 Elpida Memory, Inc. Semiconductor device
US20120086111A1 (en) * 2010-10-12 2012-04-12 Elpida Memory, Inc. Semiconductor device
CN107801291A (en) * 2016-09-06 2018-03-13 奕力科技股份有限公司 Electrostatic discharge protection device and electrostatic discharge protection method

Also Published As

Publication number Publication date
US6242815B1 (en) 2001-06-05
US6380002B2 (en) 2002-04-30

Similar Documents

Publication Publication Date Title
US6242815B1 (en) Flexible substrate based ball grid array (BGA) package
US6291271B1 (en) Method of making semiconductor chip package
US5739588A (en) Semiconductor device
TW561596B (en) Bonding pad of printed circuit board and forming method thereof
US5173844A (en) Integrated circuit device having a metal substrate
US6808962B2 (en) Semiconductor device and method for fabricating the semiconductor device
US20010049156A1 (en) Low-pin-count chip package and manufacturing method thereof
KR101113891B1 (en) Lead frame and method of manufacturing lead frame
US6232661B1 (en) Semiconductor device in BGA package and manufacturing method thereof
KR101604154B1 (en) Lead frame substrate, manufacturing method thereof, and semiconductor apparatus
KR100664500B1 (en) Printed circuit board having metal land with protrusion and manufacturing method thereof
KR20010030395A (en) Resin-encapsulated semiconductor device
WO2006014418A2 (en) Encapsulated semiconductor device with reliable down bonds
US7923835B2 (en) Package, electronic device, substrate having a separation region and a wiring layers, and method for manufacturing
US20040097081A1 (en) Method for manufacturing circuit devices
US6271057B1 (en) Method of making semiconductor chip package
JP4070470B2 (en) Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device
US6348729B1 (en) Semiconductor chip package and manufacturing method thereof
EP1171915B1 (en) Electrical conductor system of a semiconductor device and manufacturing method thereof
EP0971406A2 (en) Chip-sized semiconductor device
US6573123B2 (en) Semiconductor chip package and manufacturing method thereof
US6984877B2 (en) Bumped chip carrier package using lead frame and method for manufacturing the same
US20010010947A1 (en) Film ball grid array (BGA) semiconductor package
US6320250B1 (en) Semiconductor package and process for manufacturing the same
JP2008147266A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12