US20010012660A1 - Methods of forming a capacitor - Google Patents

Methods of forming a capacitor Download PDF

Info

Publication number
US20010012660A1
US20010012660A1 US09/120,045 US12004598A US2001012660A1 US 20010012660 A1 US20010012660 A1 US 20010012660A1 US 12004598 A US12004598 A US 12004598A US 2001012660 A1 US2001012660 A1 US 2001012660A1
Authority
US
United States
Prior art keywords
layer
opening
node
capacitor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/120,045
Other versions
US6376301B2 (en
Inventor
Kunal R. Parekh
John K. Zahurak
Original Assignee
Kunal R. Parekh
John K. Zahurak
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/798,879 priority Critical patent/US5981333A/en
Application filed by Kunal R. Parekh, John K. Zahurak filed Critical Kunal R. Parekh
Priority to US09/120,045 priority patent/US6376301B2/en
Publication of US20010012660A1 publication Critical patent/US20010012660A1/en
Application granted granted Critical
Publication of US6376301B2 publication Critical patent/US6376301B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10888Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line contact
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor
    • H01L27/10811Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor with bit line higher than capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.

Description

    TECHNICAL FIELD
  • This invention pertains to semiconductor capacitor constructions and to methods of forming semiconductor capacitor constructions. The invention is thought to have particular significance in application to methods of forming dynamic random access memory (DRAM) cell structures and to DRAM cell structures. [0001]
  • BACKGROUND OF THE INVENTION
  • A commonly used semiconductor memory device is a DRAM cell. A DRAM cell generally consists of a capacitor coupled through a transistor to a bitline. A continuous challenge in the semiconductor industry is to increase DRAM circuit density. Accordingly, there is a continuous effort to decrease the size of memory cell components. A limitation on the minimal size of cell components is impacted by the resolution of a photolithographic etch during fabrication of the components. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension obtainable in a fabrication process. It would be desirable to form DRAM components having at least some portion with a cross-sectional dimension of less than a given minimum capable photolithographic feature dimension. [0002]
  • Another continuous trend in the semiconductor industry is to minimize processing steps. Accordingly, it is desirable to utilize common steps for the formation of separate DRAM components. For instance, it is desirable to utilize common steps for the formation of DRAM capacitor structures and DRAM bitline contacts. [0003]
  • SUMMARY OF THE INVENTION
  • The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; methods of forming capacitor and bitline constructions; DRAM memory cell constructions; and capacitor constructions. For instance, the invention encompasses a method wherein a first layer is formed over a node location; a semiconductive material masking layer is formed over the first layer; an opening is etched through the semiconductive material masking layer and first layer to the node location; an upwardly open capacitor storage node layer is formed within the opening and in electrical connection with the masking layer; a capacitor storage node is formed comprising the masking layer and the storage node layer; and a capacitor dielectric layer and outer capacitor plate are formed over the capacitor storage node. [0004]
  • As another example, the invention encompasses a capacitor structure which includes an insulative layer over a substrate and a semiconductive material layer over the insulative layer. The capacitor structure further includes an opening which extends through the semiconductive material layer and the insulative layer to an electrical node, and which comprises an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions. The capacitor further comprises a spacer over the step, and a storage node layer over the spacer, semiconductive material layer and electrical node; wherein the storage node layer physically contacts the semiconductive material layer, the spacer, and the electrical node. Additionally, the capacitor comprises a dielectric layer and a cell plate layer capacitively coupled to the storage node layer. [0005]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0006]
  • FIG. 1 is a schematic cross-sectional process view of a semiconductor wafer fragment at a preliminary step of a processing method in accordance with a method of the present invention. [0007]
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 1. [0008]
  • FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 2. [0009]
  • FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 3. [0010]
  • FIG. 5 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 4. [0011]
  • FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 5. [0012]
  • FIG. 7 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 6. [0013]
  • FIG. 8 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 7. [0014]
  • FIG. 9 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 8. [0015]
  • FIG. 10 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 9. [0016]
  • FIG. 11 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 10. [0017]
  • FIG. 12 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 11. [0018]
  • FIG. 13 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 12. FIG. [0019]
  • FIG. 14 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 13. [0020]
  • FIG. 15 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 10 processed according to a second embodiment of the present invention. [0021]
  • FIG. 16 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 15. [0022]
  • FIG. 17 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 8 processed according to a third embodiment of the present invention. [0023]
  • FIG. 18 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 17. [0024]
  • FIG. 19 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 18. [0025]
  • FIG. 20 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 19. [0026]
  • FIG. 21 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 20. [0027]
  • FIG. 22 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 22. [0028]
  • FIG. 23 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 8 processed according to a fourth embodiment of the present invention. [0029]
  • FIG. 24 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 23. [0030]
  • FIG. 25 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 24. [0031]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). [0032]
  • A method of forming DRAM cells of the present invention is described with reference to FIGS. [0033] 1-25, with FIGS. 1-14 pertaining to a first embodiment of the invention, FIGS. 15-16 pertaining to a second embodiment of the invention, FIGS. 17-22 pertaining to a third embodiment of the invention, and FIGS. 23-25 pertaining to a fourth embodiment of the invention.
  • Referring first to FIG. 1, a semiconductor wafer fragment [0034] 10 is illustrated at a preliminary step of a processing sequence of a method of the present invention. Wafer fragment 10 comprises a semiconductive material 12, field oxide regions 14, and a thin gate oxide layer 16. A polysilicon layer 18, silicide layer 20 and silicon oxide layer 22 are formed over gate oxide layer 16. Silicide layer 20 comprises a refractory metal silicide, such as tungsten silicide, and polysilicon layer 18 typically comprises polysilicon doped with a conductivity enhancing dopant.
  • Referring next to FIG. 2, polysilicon layer [0035] 18, silicide layer 20 and silicon oxide layer 22 are etched to form wordlines 24 and 26. Between wordlines 24 and 26 are defined node locations 25, 27 and 29, with wordlines 26 comprising transistor gates which electrically connect node locations 25, 27, and 29. Node location 27 is laterally between node locations 25 and 29, and may lie along an imaginary straight line extending between node locations 25 and 29, or may be offset from such imaginary straight line. Node locations 25, 27 and 29 typically comprise diffusion regions formed within semiconductive material 12 by ion implanting conductivity enhancing dopant into the material 12. Such ion implanting may occur after patterning wordlines 24 and 26, utilizing wordlines 24 and 26 as masks. Alternatively, the diffusion regions may be formed prior to deposition of one or more of layers 18, 20 and 22 (shown in FIG. 1). In yet other alternative methods, the diffusion regions may be formed after formation of doped polysilicon adjacent the regions by out-diffusion of conductivity enhancing dopant from the doped polysilicon.
  • For the above-discussed reasons, node locations [0036] 25, 27, and 29 need not be electrically conductive at the preliminary step of FIG. 2. Nodes 25, 27 and 29 could be conductive at the step of FIG. 2 if formed by ion implanting of dopant into semiconductive material 12. Alternatively, nodes 25, 27 and 29 may be substantially non-conductive at the preliminary step of FIG. 2 in, for-example, embodiments in which nodes 25, 27 and 29 are ultimately doped by out-diffusion of dopant from a conductively doped layer.
  • Referring to FIGS. 3 and 4, a nitride layer [0037] 28 is provided over wordlines 24 and 26, and subsequently etched to form nitride spacers 30 laterally adjacent wordlines 24 and 26.
  • Referring to FIG. 5, an overlying oxide layer [0038] 32 is provided over wordlines 24 and gates 26, and subsequently a borophosphosilicate glass (BPSG) layer 34 is provided over oxide layer 32. Oxide layer 32 functions to prevent the diffusion of phosphorus from the BPSG into underlying materials. As is readily apparent to persons of ordinary skill in the art, other insulative materials may be substituted for the BPSG of layer 34. If such other insulative materials are substituted, it may be desirable to dispense with formation of oxide layer 32.
  • BPSG layer [0039] 34 is planarized by, for example, chemical-mechanical polishing to form a planar upper surface 35. After the planarization of BPSG layer 34, a semiconductive material masking layer 36 is provided over BPSG layer 34, with masking layer 36 comprising a bottom surface 37 adjacent upper surface 35. Preferably, masking layer 36 will comprise undoped polysilicon deposited to a thickness of from about 6000 Angstroms to about 8000 Angstroms. Formation of patterned polysilicon layer 36 may comprise, for example, provision of a patterned photoresist layer over an unpatterned polysilicon layer, followed by a conventional etch of the polysilicon to transfer a pattern from the patterned photoresist layer to the polysilicon. In the shown cross-sectional view, masking layer 36 comprises masking layer segments 41, 42 and 43, with segment 42 laterally between segments 41 and 43. Gaps 44 and 45 are between segments 41 and 42, and 42 and 43, respectively. Gaps 44 and 45 overlie nodes 25 and 29, while segment 42 overlies node 27.
  • Referring to FIG. 6, first and second openings [0040] 38 and 40 are etched through gaps 44 and 45 (shown in FIG. 5), respectively, and into BPSG layer 34, typically using a timed anisotropic dry etch. Openings 38 and 40 comprise bases 60 and 62, respectively, which are preferably above nodes 25 and 29. Accordingly, openings 38 and 40 preferably do not extend to nodes 25 and 29.
  • Referring to FIG. 7, a layer [0041] 64 is provided over segments 42 and within openings 38 and 40. Layer 64 is provided to a thickness which less than completely fills openings 38 and 40. Layer 64 thus narrows openings 38 and 40. Preferably, openings 38 and 40 will comprise a minimum internal dimension approximately equal to the minimum photolithographic feature dimension obtainable during fabrication of the openings. Accordingly, after formation of layer 64, openings 38 and 40 will be narrowed to comprise an internal dimension less than such minimum capable photolithographic feature dimension.
  • Layer [0042] 64 may comprise either an insulative material or a conductive material. A preferred material is the insulative material silicon oxide. An example method for forming a silicon oxide layer 64 is chemical vapor deposition utilizing tetraethylorthosilicate (TEOS).
  • Referring to FIG. 8, layer [0043] 64 is anisotropically etched to leave spacers 66 within openings 38 and 40. Methods for anisotropically etching layer 64 are known to persons of ordinary skill in the art. An example method for anisotropically etching the preferred silicon oxide layer 64 includes a fluorocarbon-based dry etch.
  • Spacers [0044] 66 comprise upper surfaces 67. In the shown preferred embodiment, upper surfaces 67 are below bottom surfaces 37 of segments 42. As will be recognized by persons of ordinary skill in the art, the location of upper surface 67 relative to bottom surface 37 may be adjusted by varying a number of parameters, including: 1) the thickness of layer 64 (shown in FIG. 7); 2) the length of time of the anisotropic etch used to etch layer 64; and 3) the depth of openings 38 and 40.
  • After formation of spacers [0045] 66, third and fourth openings 68 and 70, respectively, are formed by appropriate anisotropic etching. Third opening 68 extends from base 60 (shown in FIG. 6) of first opening 38 to electrical node 25. Fourth opening 70 extends from base 62 (shown in FIG. 6) of second opening 40 to electrical node 29. Openings 68 and 70 comprise internal cross-sectional dimensions about equal to the narrowed cross-sectional dimensions of openings 38 and 40 resulting after deposition of layer 64 (shown in FIG. 7). Openings 68 and 70 are therefore narrower than openings 38 and 40.
  • First opening [0046] 38 and third opening 68 together comprise a first capacitor opening 72. Similarly, second opening 40 and fourth opening 70 together comprise a second capacitor opening 74.
  • Referring to first capacitor opening [0047] 72, the opening comprises a step 76 at the interface of first opening 38 and third opening 68, with step 76 corresponding to a remaining portion of base 60 (shown in FIG. 6) of original opening 38. In the lateral cross-sectional view of FIG. 8, it appears that there are a pair of laterally opposing steps 76 within opening 72. In some embodiments of the invention, there may be distinct laterally opposing steps 76 within opening 38. However, in preferred embodiments of the invention, opening 38 will comprise a circular horizontal cross-sectional shape. In such preferred embodiments, the apparent laterally opposing steps 76 will, in fact, be sections of a continuous step 76 within opening 38.
  • Referring to second capacitor opening [0048] 74, this opening, analogously to first capacitor opening 72, comprises a step 78 at an interface of second opening 40 and fourth opening 70, with step 78 corresponding to base 62 (shown in FIG. 6) of original opening 40.
  • Spacers [0049] 66 within capacitor openings 72 and 74 are atop steps 76 and 78, respectively.
  • Referring to FIG. 9, a storage node layer [0050] 80 is provided over masking layer 36, within capacitor openings 72 and 74, and in contact with segments 41, 42 and 43. Storage node layer 80 preferably comprises a rugged polysilicon, such as a polysilicon selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon, and is preferably provided to a thickness of from about 300 Angstroms to about 700 Angstroms.
  • Referring to FIG. 10, a patterned photoresist layer [0051] 82 is provided over capacitor openings 72 and 74, and over portions of masking layer segments 42, leaving exposed portions of the masking layer segments (not shown). Subsequently, the exposed portions are removed. Removal of an exposed portion of segment 42 (shown in FIG. 9) forms a fifth opening 84 over node 27. Fifth opening 84 divides segment 42 (shown in FIG. 9) into a first portion 86 and a second portion 88. Opening 84 comprises a base 90 above node 27.
  • Adjacent opening [0052] 84 are defined two storage nodes 81 and 83. First storage node 81 comprises storage node layer 80, segment 41 and portion 86. Second storage node 83 comprises storage node layer 80, segment 43 and portion 88. Also, as storage node layer 80 overlies and contacts spacers 66, storage nodes 81 and 83 may comprise spacers 66, particularly if spacers 66 comprise electrically conductive material. Preferably, if spacers 66 are incorporated into storage nodes 81 and 83, spacers 66 will be electrically isolated from wordlines 24 and 26.
  • As discussed above, segment [0053] 42 (shown in FIG. 9) will preferably comprise polysilicon. Methods of etching such preferred segments are known to persons of ordinary skill in the art, and comprise, for example, anisotropic dry etching.
  • Referring to FIG. 11, a capacitor-dielectric layer [0054] 92 and a cell plate layer 94 are provided over segments 41 and 43, over portions 81 and 83, and within capacitor openings 72 and 74. Dielectric layer 92 comprises an electrically insulative material, such as silicon nitride or a composite of silicon nitride and silicon dioxide. Cell plate layer 94 comprises an electrically conductive material, such as polysilicon doped to concentration of greater than 1×1019 ions/cm3. Layers 92 and 94 may be formed by conventional methods.
  • The provision of layers [0055] 92 and 94 forms a first capacitor structure 100 and a second capacitor structure 102. First capacitor structure 100 comprises storage node 81, dielectric layer 92 and cell plate layer 94. Second capacitor 102 comprises storage node 83 dielectric layer 92 and cell plate layer 94.
  • After formation of layers [0056] 92 and 94, a patterned photoresist layer 96 is formed over openings 72 and 74, leaving an exposed area 98 within fifth opening 84 and over node 27.
  • Referring to FIG. 12, exposed portions of cell plate layer [0057] 94 and dielectric layer 92 within area 98 are removed.
  • After removal of the exposed portions of cell plate layer [0058] 94 and dielectric layer 92, photoresist blocks 96 are removed and an insulative layer 104 is formed atop wafer fragment 10. Subsequently, patterned photoresist layer 106 is formed over insulative layer 104, leaving an exposed gap 108 over node 27.
  • Referring to FIG. 13, a bitline contact opening [0059] 110 is etched through insulative layer 104, through layer 34, through oxide 32, and to node 27.
  • After formation of bitline contact opening [0060] 110, photoresist layer 106 (shown in FIG. 12) is removed and a bitline contact layer 112 is formed over insulative material layer 104 and within opening 110. The portion of bitline contact material 112 within opening 110 forms a bitline contact 114.
  • Bitline contact layer [0061] 112 comprises a conductive material, such as tungsten. Methods for forming layer 112 are known to persons of ordinary skill in the art, and include, for example, sputter deposition of tungsten.
  • Referring to FIG. 14, bitline contact layer [0062] 112 is removed from over insulative layer 104, and a bitline 116 is formed over layer 104 and in electrical contact with bitline contact 114. Bitline 116 preferably comprises a conductive material, such as aluminum, and may be formed by conventional methods.
  • The structure shown in FIG. 14 comprises a DRAM array including capacitors [0063] 100 and 102 electrically connected through transistor gates 26 to bitline contact 114 and ultimately to bitline 116. The DRAM array is 15 of FIG. 14 actually comprises two DRAM cell structures, with capacitor 100 and a transistor gate 26 comprising a first DRAM cell structure; and capacitor 102 and a transistor gate 26 comprising a second DRAM cell structure.
  • A second embodiment method of the present invention is described with reference to FIGS. 15 and 16. In the embodiment of FIGS. [0064] 15-16, similar numbering to that of the embodiment of FIGS. 1-14 is utilized, with differences indicated by the suffix “a”, or by different numbers.
  • Referring to FIG. 15, a wafer fragment [0065] 10 a is shown at a step subsequent to the processing step of FIG. 10. A patterned photoresist layer 122 is formed over and within capacitor openings 72 and 74. Unlike the embodiment of FIGS. 1-14, the embodiment of FIG. 15 comprises cavities 120 etched into layer 34, under segments 41 and 43, and under portions 86 and 88. Methods of forming cavities 120 are known to persons of ordinary skill in the art. An example process of forming cavities 120 in a BPSG layer 34 is a wet isotropic etch of oxide selective to polysilicon. Such etch undercuts beneath polysilicon segments 41 and 43, and beneath polysilicon portions 86 and 88.
  • Referring to FIG. 16, the FIG. 15 wafer segment is illustrated after subsequent processing analogous to the processing of FIGS. [0066] 11-14. Specifically, a dielectric layer 92 and cell plate layer 94 are provided within capacitor openings 72 and 74 (shown in FIG. 15), over masking layer segments 41 and 43, over portions 86 and 88, and within cavities 120 to form capacitor structures 100 a and 102 a. An insulative layer 104 and a bitline 116 are formed over capacitor structures 100 a and 102 a, and a bitline contact 114 is formed between capacitor structures 100 a and 102 a. A first storage node 81 a comprises storage node layer 80, segment 41 and portion 86. A second storage node 83 a comprises storage node layer 80, segment 43 and portion 88.
  • The capacitors [0067] 100 a and 102 a of FIG. 16 advantageously differ from the capacitors 100 and 102 of FIG. 14 in that dielectric layer 92 and cell plate layer 94 wrap around storage nodes 81 a and 83 a, and within cavities 120. Accordingly, the capacitive area of capacitors 100 a and 102 a is increased relative to the capacitive area of capacitors 100 and 102 of FIG. 14.
  • A third embodiment of the invention is described with reference to FIGS. [0068] 17-22. In the embodiment of FIGS. 17-22, similar numbering to that of the embodiment of FIGS. 1-14 is utilized, with differences indicated by the suffix “b”, or by different numbers.
  • Referring to FIG. 17, a wafer fragment [0069] 10 b is shown at a processing step subsequent to that of FIG. 8. A fifth opening 84 b is formed over electrical node 27, dividing segment 42 (shown in FIG. 8) into portions 86 b and 88 b. Note that the embodiment of FIGS. 17-22 differs from that of FIGS. 1-14 in that fifth opening 84 b (shown in FIG. 17) is formed prior to deposition of storage node layer 80 b, while fifth opening 84 (shown in FIG. 10) is formed after deposition of storage node layer 80 b. After formation of fifth opening 84 b, a rugged polysilicon storage node layer 80 b is formed over segments 41 and 43, over portions 86 b and 88 b, and over upper surface 35 of insulative layer 34, as well as within capacitor openings 72 and 74. A first storage node 81 b comprises storage node layer 80 b, segment 41 and portion 86 b. A second storage node 83 b comprises storage node layer 80 b, segment 43 and portion 88 b.
  • Referring to FIG. 18, polysilicon layer [0070] 80 b is subjected to an anisotropic dry or wet etch. Such etch removes layer 80 b from over segments 41 and 43, portions 86 b and 88 b, and upper surface 35 of layer 34. Also, the etch transfers roughness from rugged polysilicon layer 80 b to upper surface 35, upper surfaces of segments 41 and 43, and upper surfaces of portions 86 b and 88 b. Removal of layer 80 b from upper surface 35 in gap 84 b electrically isolates portion 86 b from portion 88 b, and thus isolates storage node 81 b from storage node 83 b.
  • Referring to FIG. 19, a dielectric layer [0071] 92 and cell plate layer 94 are provided over storage nodes 81 b and 83 b, and over upper surface 35 of layer 34. Storage node 81 b, dielectric layer 92, and cell plate layer 94 together comprise a capacitor construction 100 b. Similarly, storage node 83 b, dielectric layer 92 and cell plate layer 94 together comprise a capacitor construction 102 b.
  • A patterned photoresist layer [0072] 96 is provided over layers 92 and 94. Patterned photoresist 96 comprises a gap over node 27 and within fifth opening 84 b (shown in FIG. 18) leaving an exposed area 98 over electrical node 27.
  • Referring to FIG. 20, cell plate layer [0073] 94 and dielectric layer 92 are removed from exposed area 98 (shown in FIG. 19). Subsequently, an insulative layer 104 is formed over capacitor structures 100 b and 102 b. A patterned photoresist layer 106 is formed over insulative layer 104, leaving a gap 108 over electrical node 27.
  • Referring to FIG. 21, layers [0074] 104, 34 and 32 are etched through gap 108 to form a bitline contact opening 110 extending through layers 104, 34 and 32 to electrical node 27. After formation of bitline contact opening 110, a bitline contact layer 112 is formed over layer 104 and within opening 110. A portion of bitline contact layer 112 within opening 110 is a bitline contact 114.
  • Referring to FIG. 22, bitline contact layer [0075] 112 is removed from over layer 104. Subsequently, a bitline 116 is formed over layer 104 and in electrical contact with bitline contact 114.
  • A fourth embodiment of the method of the present invention is described with reference to FIGS. [0076] 23-25. The fourth embodiment is effectively a combination of the second and third embodiments described above. Identical numbering is utilized in FIGS. 23-25 as was utilized in FIGS. 1-14, with differences indicated by the suffix “c”, or by different numerals.
  • Referring to FIG. 23, wafer fragment [0077] 10 c is shown at a processing step subsequent to that of FIG. 8. A patterned photoresist layer 122 is formed over and within capacitor openings 72 and 74. Subsequently, cavities 120 are formed beneath the segments 41 and 43, and beneath portions 86 and 88.
  • Referring to FIG. 24, photoresist layer [0078] 122 is removed and storage node layer 80 is formed over segments 41 and 43, over portions 86 and 88, within capacitor openings 72 and 74, and within cavities 120. A first storage node 81 c comprises storage node layer 80, segment 41 and portion 86. A second storage node 83 c comprises storage node layer 80, segment 43 and portion 88.
  • Referring to FIG. 25, subsequent processing analogous to that of FIGS. [0079] 9-14 has occurred to form capacitor structures 100 c and 102 c, bitline contact 114, and bitline 116.
  • The above-described DRAMs and capacitors of the present invention can be implemented into monolithic integrated circuitry, including microprocessors. [0080]
  • To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. [0081]
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0082]

Claims (58)

1. A method of forming a capacitor comprising the following steps:
forming a first layer over a node location;
forming a semiconductive material masking layer over the first layer;
etching an opening through both the semiconductive material masking layer and the first layer to the node location using the semiconductive material masking layer as an etch mask during said etching of said first layer;
forming an upwardly open capacitor storage node layer within the opening and in electrical connection with the masking layer;
patterning at least the masking layer and forming a capacitor storage node comprising the masking layer and the storage node layer;
forming a capacitor dielectric layer operatively proximate the capacitor storage node; and
forming an outer capacitor plate layer operatively proximate the capacitor dielectric layer.
2. The method of
claim 1
wherein the semiconductive material comprises polysilicon.
3. The method of
claim 1
wherein the node location ultimately comprises a diffusion region in a semiconductive substrate.
4. A method of forming a capacitor comprising the following steps:
forming a first layer over a node location;
forming a patterned semiconductive material masking layer over a portion of the first layer to form a masked portion and an unmasked portion of the first layer, the unmasked portion overlying the node location;
removing a part of the unmasked portion of the first layer to form a first opening in the first layer, the first opening having a base above the node location;
forming a second layer within the first opening and over the patterned masking layer, the second layer less than completely filling the first opening and thus narrowing an internal dimension of the first opening;
forming a second opening which extends from the base of the first opening to the node location and which comprises an internal dimension about equal to the narrowed internal dimension of the first opening, the first and second openings together comprising a capacitor opening, the capacitor opening comprising a step at an interface of the first and second openings;
forming a second layer spacer over the step;
forming a storage node layer within the capacitor opening and extending from the semiconductive material masking layer to the node location, the storage node layer physically contacting the semiconductive material masking layer;
forming a capacitor dielectric layer operatively proximate the capacitor storage node; and
forming an outer capacitor plate layer operatively proximate the capacitor dielectric layer; the dielectric layer, cell plate layer and storage node together comprising a capacitor within the capacitor opening.
5. The method of
claim 4
wherein the second layer comprises an electrically insulative material.
6. The method of
claim 4
wherein the second layer comprises silicon oxide.
7. The method of
claim 4
wherein the second layer comprises an electrically conductive material.
8. The method of
claim 4
wherein the node location comprises a diffusion region in a semiconductive substrate.
9. The method of
claim 4
wherein the semiconductive material masking layer comprises a bottom surface, wherein the second layer spacer comprises an upper surface, and wherein the upper surface of the second layer spacer is below the bottom surface of the semiconductive material masking layer.
10. A method of forming a capacitor comprising the following steps:
forming a first layer over a node location;
forming a patterned polysilicon masking layer over a portion of the first layer to form a masked portion and an unmasked portion of the first layer, the unmasked portion overlying the node location;
removing a part of the unmasked portion of the first layer to form a first opening in the first layer, the first opening having a base above the node location;
forming a second layer within the first opening and over the patterned polysilicon layer, the second layer less than completely filling the first opening and thus narrowing an internal dimension of the first opening;
forming a second opening which extends from the bottom of the first opening to the node location and which comprises an internal dimension about equal to the narrowed internal dimension of the first opening, the first and second openings together comprising a capacitor opening;
anisotropically etching the second layer to remove the second layer from over the polysilicon layer and to leave a second layer spacer within the capacitor opening;
electrically connecting the polysilicon layer to the node location to form a storage node comprising the polysilicon layer;
forming a dielectric layer operatively proximate the storage node; and
forming a cell plate layer operatively proximate the dielectric layer; the dielectric layer, cell plate layer and storage node together comprising a capacitor within the capacitor opening.
11. The method of
claim 10
wherein the first layer comprises BPSG.
12. The method of
claim 10
wherein the second layer comprises an electrically insulative material.
13. The method of
claim 10
wherein the second layer comprises silicon oxide.
14. The method of
claim 10
wherein the second layer comprises an electrically conductive material.
15. The method of
claim 10
wherein the polysilicon layer comprises a bottom surface, wherein the second layer spacer comprises an upper surface, and wherein the upper surface of the second layer spacer is below the bottom surface of the polysilicon layer.
16. The method of
claim 10
wherein the polysilicon masking layer is doped with a conductivity enhancing dopant.
17. The method of
claim 10
wherein the step of forming the second opening comprises removing the second layer from the bottom of the first opening and thereafter removing the unmasked portion of the first layer.
18. A method of forming a DRAM array comprising the following steps:
forming a first layer over first, second and third node locations;
forming polysilicon masking layer segments over the first layer to form masked and unmasked portions of the first layer, a first masking layer segment overlying the second node location, the unmasked portions of the first layer overlying the first and third node locations;
removing part of the unmasked portions of the first layer to form a first opening in the first layer over the first node location and a second opening in the first layer over the third node location, the first and second openings having bases above the first and third node locations, respectively;
forming a second layer within the first and second openings and over the first masking layer segment, the second layer less than completely filling the first and second openings and thus narrowing an internal dimension of the first opening and an internal dimension of the second opening;
forming a third opening which extends from the base of the first opening to the first node location and which comprises an internal dimension about equal to the narrowed internal dimension of the first opening, the first and third openings together comprising a first capacitor opening;
forming a fourth opening which extends from the base of the second opening to the third node location and which comprises an internal dimension about equal to the narrowed internal dimension of the second opening, the second and fourth openings together comprising a second capacitor opening;
removing the second layer from over the first masking layer segment;
forming a fifth opening extending through the first masking layer segment, the fifth opening dividing the first masking layer segment into a first portion and a second portion, the fifth opening comprising a base above the second node location;
forming a bitline contact opening, the bitline contact opening extending through the first layer and extending from the bottom of the fifth opening to the second node location;
electrically connecting the first masking layer first portion to the first node location to form a first storage node comprising the first masking layer first portion;
electrically connecting the first masking layer second portion to the third node location to form a second storage node comprising the first masking layer second portion;
forming a first dielectric layer operatively proximate the first storage node;
forming a first cell plate layer operatively proximate the first dielectric layer; the first dielectric layer, first cell plate layer and first storage node together comprising a first capacitor;
forming a second dielectric layer operatively proximate the second storage node;
forming a second cell plate layer operatively proximate the first dielectric layer; the second dielectric layer, second cell plate layer and second storage node together comprising a second capacitor; and
forming an electrically conductive bit line contact within the bit line contact opening.
19. The method of
claim 18
further comprising forming a bit line over the capacitors and in electrical connection with the bit line contact.
20. The method of
claim 18
wherein the second node location is laterally between the first and third node locations.
21. The method of
claim 18
wherein the second node location is along an imaginary straight line extending from the first node location to the third node location.
22. The method of
claim 18
further comprising:
forming a first transistor gate to electrically couple the first and second node locations; and
forming a second transistor gate to electrically couple the second and third node locations.
23. The method of
claim 18
wherein the steps of electrically connecting the first and second masking layer portions to the first and second node locations comprise forming a rugged polysilicon layer over the masking layer segments and within the first and second capacitor openings, the rugged polysilicon layer being formed before formation of the fifth opening, the rugged polysilicon layer comprising at least one material selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon.
24. The method of
claim 18
wherein the steps of electrically connecting the first and second masking layer portions to the first and second node locations comprise forming a rugged polysilicon layer over the masking layer segments and within the first and second capacitor openings, the rugged polysilicon layer being formed after formation of the fifth opening, the rugged polysilicon layer comprising at least one material selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon.
25. The method of
claim 18
wherein the steps of electrically connecting the first and second masking layer portions to the first and second node locations comprise forming a rugged polysilicon layer over the masking layer segments and within the first and second capacitor openings, the fifth opening being formed after formation of the rugged polysilicon layer and after formation of the dielectric layers and cell plate layers, the rugged polysilicon layer comprising at least one material selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon.
26. The method of
claim 18
wherein the step of removing the second layer from over the first masking layer segment occurs before the steps of forming the third and fourth contact openings and further comprises removing the second layer from over the bases of the first and second openings.
27. The method of
claim 18
wherein the step of removing the second layer from over the first masking layer segment occurs before the steps of forming the third and fourth contact openings and further comprises removing the second layer from over the bases of the first and second openings; the step of removing the second layer comprising anisotropically etching the second layer; the step of removing the second layer leaving a portion of the second layer within the first and second openings to form second layer spacers within the first and second openings and laterally adjacent sides of the openings.
28. The method of
claim 18
wherein the first layer comprises BPSG.
29. The method of
claim 18
wherein the second layer comprises an electrically insulative material.
30. The method of
claim 18
wherein the second layer comprises silicon oxide.
31. The method of
claim 18
wherein the second layer comprises an electrically conductive material.
32. The method of
claim 18
further comprising:
forming a first cavity beneath the first masking layer segment first portion;
forming a second cavity beneath the first masking layer segment second portion;
forming a first storage node layer which wraps around an outer surface of the first masking layer segment first portion and within the first cavity; and
forming a second storage node layer which wraps around an outer surface of the first masking layer segment second portion and within the second cavity.
33. The method of
claim 18
further comprising:
forming a second masking layer segment laterally displaced from the first masking layer segment by a gap corresponding to the unmasked portion overlying the first node location;
forming a third masking layer segment laterally displaced from the first masking layer segment by a gap corresponding to the unmasked portion overlying the third node location;
extending a first common storage node layer over the first masking layer first portion, the second masking layer segment and within the first capacitor opening to form the first storage node; and
extending a second common storage node layer over the first masking layer second portion, the third masking layer segment and within the second capacitor opening to form the second storage node.
34. A method of forming a monolithic integrated circuit comprising the following steps:
fabricating integrated circuitry over a portion of a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements;
the fabrication of at least one of the capacitors comprising the following steps:
forming a first layer over a node location;
forming a semiconductive material masking layer over the first layer;
etching an opening through both the semiconductive material masking layer and the first layer to the node location using the semiconductive material masking layer as an etch mask during said etching of said first layer;
forming an upwardly open capacitor storage node layer within the opening and in electrical connection with the masking layer;
patterning at least the masking layer and forming a capacitor storage node comprising the masking layer and the storage node layer;
forming a capacitor dielectric layer operatively proximate the capacitor storage node; and
forming an outer capacitor plate layer operatively proximate the capacitor dielectric layer.
35. The method of
claim 34
wherein the integrated circuit is fabricated as part of a microprocessor circuit.
36. The method of
claim 34
wherein the integrated circuit is fabricated as part of a microprocessor circuit and wherein the at least one capacitor is incorporated into a DRAM cell.
37. A DRAM cell comprising:
a capacitor comprising:
an upwardly open storage node having a top surface and a bottom surface;
a dielectric layer against the storage node top and bottom surfaces; and
a cell plate layer against the dielectric layer and extending along the top and bottom surfaces of the storage node; and
a bitline electrically connected to the capacitor through a transistor gate.
38. A capacitor structure comprising: +p1 an insulative layer over a substrate;
a polysilicon layer over the insulative layer;
an opening extending through the polysilicon layer and the insulative layer to a node;
a spacer within the opening, the spacer comprising an upper surface which is below the bottom surface of the polysilicon layer;
a storage node layer over the spacer, polysilicon layer and the node, the storage node layer physically contacting the polysilicon layer, the spacer, and the node;
a dielectric layer operatively proximate the storage node layer; and a cell plate layer operatively proximate the dielectric layer.
39. The capacitor structure of
claim 38
wherein the spacer comprises an insulative material.
40. The capacitor structure of
claim 38
wherein the spacer comprises a conductive material.
41. A capacitor structure comprising:
an insulative layer over a substrate;
a polysilicon layer over the insulative layer;
an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions;
a spacer over the step, the spacer comprising an upper surface which is below the bottom surface of the polysilicon layer;
a storage node layer over the spacer, polysilicon layer and the node, the storage node layer physically contacting the polysilicon layer, the spacer, and the node;
a dielectric layer operatively proximate the storage node layer; and
a cell plate layer operatively proximate the dielectric layer.
42. The capacitor structure of
claim 41
wherein the spacer comprises an insulative material.
43. The capacitor structure of
claim 41
wherein the spacer comprises a conductive material.
44. The capacitor structure of
claim 41
wherein the storage node layer comprises rugged polysilicon, the rugged polysilicon comprising at least one material selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon.
45. The capacitor structure of
claim 41
wherein the polysilicon layer in lateral cross-section comprises a pair opposing lateral surfaces; the storage node layer, dielectric layer, and cell plate layer extending over both lateral surfaces of the pair of opposing lateral surfaces.
46. The capacitor structure of
claim 41
wherein the polysilicon layer is doped with a conductivity enhancing dopant.
47. A capacitor structure comprising:
an insulative layer over a substrate;
a semiconductive material layer over the insulative layer;
an opening extending through the semiconductive material layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions;
a spacer over the step;
a storage node layer over the spacer, semiconductive material layer and node; the storage node layer physically contacting the semiconductive material layer, the spacer, and the node;
a dielectric layer operatively proximate the storage node layer; and
a cell plate layer operatively proximate the dielectric layer.
48. The capacitor structure of
claim 47
further comprising a cavity under the semiconductive material layer; the storage node layer wrapping around an outer surface of the semiconductive material layer and within the cavity.
49. A DRAM cell comprising:
a capacitor comprising:
an upwardly open storage node having a top surface and a bottom surface;
a dielectric layer against the storage node top and bottom surfaces; and
a cell plate layer against the dielectric layer and extending along the top and bottom surfaces of the storage node;
a transistor gate; and
a bitline electrically connected to the capacitor through the transistor gate.
50. A DRAM array comprising:
an insulative layer over a substrate;
a polysilicon layer over the insulative layer;
a first capacitor opening extending through the polysilicon layer and the insulative layer to a first node, the first capacitor opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the first capacitor opening further comprising a step at an interface of the upper and lower portions;
an electrically conductive bit line extending through the polysilicon layer and the insulative layer to a second node;
a second capacitor opening extending through the polysilicon layer and the insulative layer to a third node, the second capacitor opening comprising an upper portion and a lower portion, the upper portion comprising the first minimum cross-sectional dimension and the lower portion comprising the second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the second capacitor opening further comprising a step at an interface of the upper and lower portions;
a first spacer over the step of the first capacitor opening and a second spacer over the step of the second capacitor opening;
a first storage node layer within the first capacitor contact opening, the first storage node layer extending over the first spacer, the polysilicon layer and the first node, the first storage node layer physically contacting the polysilicon layer, the first spacer, and the first node;
a second storage node layer within the second capacitor contact opening, the second storage node layer extending over the second spacer, the polysilicon layer and the third node, the second storage node layer physically contacting the polysilicon layer, the second spacer, and the third node;
a first dielectric layer and a first cell plate layer capacitively coupled to the first storage node layer to form a first capacitor;
a second dielectric layer and a second cell plate layer capacitively coupled to the second storage node layer to form a second capacitor;
a first transistor gate electrically coupling the first node to the second node; and
a second transistor gate electrically coupling the third node to the second node.
51. The DRAM array of
claim 50
wherein the polysilicon layer comprises a bottom surface, and wherein the first and second spacers comprise upper surfaces which are below the bottom surface of the polysilicon layer.
52. The DRAM array of
claim 50
wherein the first and second storage node layers comprise rugged polysilicon, the rugged polysilicon comprising at least one material selected from the group consisting of hemispherical grain polysilicon and cylindrical grain polysilicon.
53. The DRAM array of
claim 50
wherein the spacer comprises an electrically insulative material.
54. The DRAM array of
claim 50
wherein the spacer comprises an electrically conductive material.
55. The DRAM array of
claim 50
further comprising a bit line electrically connected to the bit line contact and extending over the first and second capacitors.
56. A monolithic integrated circuit comprising:
fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements;
at least one of the capacitors comprising:
an insulative layer over a substrate;
a polysilicon layer over the insulative layer;
an opening extending through the polysilicon layer and the insulative layer to a node;
a spacer within the opening, the spacer comprising an upper surface which is below the bottom surface of the polysilicon layer;
a storage node layer over the spacer, polysilicon layer and the node, the storage node layer physically contacting the polysilicon layer, the spacer, and the node;
a dielectric layer operatively proximate the storage node layer; and
a cell plate layer operatively proximate the dielectric layer.
57. The monolithic integrated circuit of
claim 56
wherein the integrated circuit is part of a microprocessor circuit.
58. The monolithic integrated circuit of
claim 56
wherein the integrated circuit is part of a microprocessor circuit and wherein the at least one capacitor is incorporated into a DRAM cell.
US09/120,045 1997-02-11 1998-07-21 Methods of forming a capacitor and methods of forming a monolithic integrated circuit Expired - Fee Related US6376301B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US08/798,879 US5981333A (en) 1997-02-11 1997-02-11 Methods of forming capacitors and DRAM arrays
US09/120,045 US6376301B2 (en) 1997-02-11 1998-07-21 Methods of forming a capacitor and methods of forming a monolithic integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/120,045 US6376301B2 (en) 1997-02-11 1998-07-21 Methods of forming a capacitor and methods of forming a monolithic integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/798,879 Division US5981333A (en) 1997-02-11 1997-02-11 Methods of forming capacitors and DRAM arrays

Publications (2)

Publication Number Publication Date
US20010012660A1 true US20010012660A1 (en) 2001-08-09
US6376301B2 US6376301B2 (en) 2002-04-23

Family

ID=25174499

Family Applications (4)

Application Number Title Priority Date Filing Date
US08/798,879 Expired - Lifetime US5981333A (en) 1997-02-11 1997-02-11 Methods of forming capacitors and DRAM arrays
US08/951,855 Expired - Fee Related US6329684B1 (en) 1997-02-11 1997-10-16 Capacitor structures, DRAM cells and integrated circuitry
US09/120,045 Expired - Fee Related US6376301B2 (en) 1997-02-11 1998-07-21 Methods of forming a capacitor and methods of forming a monolithic integrated circuit
US09/291,423 Expired - Fee Related US6228710B1 (en) 1997-02-11 1999-04-13 Methods of forming capacitors and DRAM arrays

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US08/798,879 Expired - Lifetime US5981333A (en) 1997-02-11 1997-02-11 Methods of forming capacitors and DRAM arrays
US08/951,855 Expired - Fee Related US6329684B1 (en) 1997-02-11 1997-10-16 Capacitor structures, DRAM cells and integrated circuitry

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/291,423 Expired - Fee Related US6228710B1 (en) 1997-02-11 1999-04-13 Methods of forming capacitors and DRAM arrays

Country Status (1)

Country Link
US (4) US5981333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266103A1 (en) * 2003-06-30 2004-12-30 Min-Yong Lee Method for fabricating capacitor using metastable-polysilicon process

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6238971B1 (en) * 1997-02-11 2001-05-29 Micron Technology, Inc. Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures
US5998257A (en) 1997-03-13 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
JP3028080B2 (en) * 1997-06-18 2000-04-04 日本電気株式会社 Structure and a manufacturing method thereof of the semiconductor device
US6207523B1 (en) 1997-07-03 2001-03-27 Micron Technology, Inc. Methods of forming capacitors DRAM arrays, and monolithic integrated circuits
US6020236A (en) * 1999-02-25 2000-02-01 Semiconductor Manufacturing Company Method to form capacitance node contacts with improved isolation in a DRAM process
TW409412B (en) * 1999-05-21 2000-10-21 Taiwan Semiconductor Mfg Manufacture method of dynamic random access memory capacitor
KR100339244B1 (en) 1999-06-30 2002-05-31 박종섭 A method of fabricating high load register type SRAM
JP3998373B2 (en) * 1999-07-01 2007-10-24 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6403442B1 (en) * 1999-09-02 2002-06-11 Micron Technology, Inc. Methods of forming capacitors and resultant capacitor structures
US6468859B1 (en) 1999-09-20 2002-10-22 Micron Technology, Inc. Method of reducing electrical shorts from the bit line to the cell plate
US6171948B1 (en) 1999-11-02 2001-01-09 Micron Technology, Inc. Method for filling structural gaps and intergrated circuitry
US6190962B1 (en) * 1999-12-20 2001-02-20 United Microelectronics Corp. Method of fabricating capacitor
US6451646B1 (en) * 2000-08-30 2002-09-17 Micron Technology, Inc. High-k dielectric materials and processes for manufacturing them
US6835645B2 (en) * 2000-11-29 2004-12-28 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US7378719B2 (en) * 2000-12-20 2008-05-27 Micron Technology, Inc. Low leakage MIM capacitor
TW544840B (en) 2002-06-27 2003-08-01 Intelligent Sources Dev Corp A stack-type DRAM memory structure and its manufacturing method
US20060208871A1 (en) * 2003-06-27 2006-09-21 Hansen James R Screen sharing
US6710398B2 (en) 2002-07-23 2004-03-23 Intelligent Sources Development Corp. Scalable stack-type DRAM memory structure and its manufacturing methods
US6921692B2 (en) 2003-07-07 2005-07-26 Micron Technology, Inc. Methods of forming memory circuitry
US7098105B2 (en) * 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US9654108B2 (en) * 2008-01-11 2017-05-16 Intel Mobile Communications GmbH Apparatus and method having reduced flicker noise
KR101883380B1 (en) * 2011-12-26 2018-07-31 삼성전자주식회사 Semiconductor device having capacitors
US9805934B2 (en) * 2013-11-15 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of contact/via hole with self-alignment

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088357B2 (en) * 1986-12-01 1996-01-29 三菱電機株式会社 Vertical mos transistor
US4864374A (en) * 1987-11-30 1989-09-05 Texas Instruments Incorporated Two-transistor dram cell with high alpha particle immunity
US5170233A (en) * 1991-03-19 1992-12-08 Micron Technology, Inc. Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor
US5229310A (en) * 1991-05-03 1993-07-20 Motorola, Inc. Method for making a self-aligned vertical thin-film transistor in a semiconductor device
JP2602132B2 (en) * 1991-08-09 1997-04-23 三菱電機株式会社 A thin film field effect device and a manufacturing method thereof
KR950001159B1 (en) * 1991-12-27 1995-02-11 김광호 Tft and its manufacturing method for memory device
US5391511A (en) 1992-02-19 1995-02-21 Micron Technology, Inc. Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor
US5206183A (en) * 1992-02-19 1993-04-27 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells
US5227325A (en) * 1992-04-02 1993-07-13 Micron Technology, Incl Method of forming a capacitor
US5244826A (en) * 1992-04-16 1993-09-14 Micron Technology, Inc. Method of forming an array of finned memory cell capacitors on a semiconductor substrate
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
JP2865155B2 (en) * 1992-07-23 1999-03-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5401681A (en) * 1993-02-12 1995-03-28 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells
US5605857A (en) 1993-02-12 1997-02-25 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5563089A (en) 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5498562A (en) 1993-04-07 1996-03-12 Micron Technology, Inc. Semiconductor processing methods of forming stacked capacitors
US5338700A (en) * 1993-04-14 1994-08-16 Micron Semiconductor, Inc. Method of forming a bit line over capacitor array of memory cells
US5318927A (en) 1993-04-29 1994-06-07 Micron Semiconductor, Inc. Methods of chemical-mechanical polishing insulating inorganic metal oxide materials
US5334862A (en) * 1993-08-10 1994-08-02 Micron Semiconductor, Inc. Thin film transistor (TFT) loads formed in recessed plugs
KR970000229B1 (en) * 1993-08-30 1997-01-06 김주용 Method for manufacturing dram capacitor
US5508218A (en) 1993-12-28 1996-04-16 Lg Semicon Co., Ltd. Method for fabricating a semiconductor memory
US5714780A (en) 1993-12-28 1998-02-03 Lg Semicon Co., Ltd. Semiconductor memory and method of fabricating the same
US5444013A (en) * 1994-11-02 1995-08-22 Micron Technology, Inc. Method of forming a capacitor
US5438011A (en) 1995-03-03 1995-08-01 Micron Technology, Inc. Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples
US5604147A (en) 1995-05-12 1997-02-18 Micron Technology, Inc. Method of forming a cylindrical container stacked capacitor
KR100199094B1 (en) 1995-10-18 1999-06-15 구본준 Capacitor fabrication method of semiconductor device
US5661064A (en) 1995-11-13 1997-08-26 Micron Technology, Inc. Method of forming a capacitor having container members
US5700731A (en) * 1995-12-07 1997-12-23 Vanguard International Semiconductor Corporation Method for manufacturing crown-shaped storage capacitors on dynamic random access memory cells
US5543345A (en) * 1995-12-27 1996-08-06 Vanguard International Semiconductor Corp. Method for fabricating crown capacitors for a dram cell
US6218237B1 (en) 1996-01-03 2001-04-17 Micron Technology, Inc. Method of forming a capacitor
US5786249A (en) 1996-03-07 1998-07-28 Micron Technology, Inc. Method of forming dram circuitry on a semiconductor substrate
US6083831A (en) 1996-03-26 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266103A1 (en) * 2003-06-30 2004-12-30 Min-Yong Lee Method for fabricating capacitor using metastable-polysilicon process
US6951795B2 (en) * 2003-06-30 2005-10-04 Hynix Semiconductor Inc. Method for fabricating capacitor using metastable-polysilicon process

Also Published As

Publication number Publication date
US6228710B1 (en) 2001-05-08
US6376301B2 (en) 2002-04-23
US5981333A (en) 1999-11-09
US6329684B1 (en) 2001-12-11

Similar Documents

Publication Publication Date Title
US5688713A (en) Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers
US5270241A (en) Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
KR100431656B1 (en) Method of manufacturing semiconductor device
US5780338A (en) Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits
US5162248A (en) Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5962885A (en) Method of forming a capacitor and a capacitor construction
US5240871A (en) Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor
JP3935991B2 (en) DRAM cell device and method of manufacturing the DRAM cell device
US5168073A (en) Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate
KR930002292B1 (en) Semiconductor device and method for manufacturing thereof
US5252517A (en) Method of conductor isolation from a conductive contact plug
US6620680B2 (en) Method of forming a contact structure and a container capacitor structure
US5262662A (en) Storage node capacitor having tungsten and etched tin storage node capacitor plate
US20020187598A1 (en) DRAM device and method of manufacturing the same
US6083831A (en) Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor
US6383887B1 (en) Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits
US5643819A (en) Method of fabricating fork-shaped stacked capacitors for DRAM cells
US6809918B2 (en) Method for improved processing and etchback of a container capacitor
US5817555A (en) Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon
US5858829A (en) Method for fabricating dynamic random access memory (DRAM) cells with minimum active cell areas using sidewall-spacer bit lines
KR100418573B1 (en) Method for fabricating semiconductor device
US5936272A (en) DRAM transistor cells with a self-aligned storage electrode contact
US5700709A (en) Method for manufacturing a capacitor for a semiconductor device
US5889301A (en) Semiconductor memory device having an E-shaped storage node
US6794238B2 (en) Process for forming metallized contacts to periphery transistors

Legal Events

Date Code Title Description
CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20140423