US20010009784A1 - Structure and method of making a sub-micron MOS transistor - Google Patents

Structure and method of making a sub-micron MOS transistor Download PDF

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US20010009784A1
US20010009784A1 US09/783,760 US78376001A US2001009784A1 US 20010009784 A1 US20010009784 A1 US 20010009784A1 US 78376001 A US78376001 A US 78376001A US 2001009784 A1 US2001009784 A1 US 2001009784A1
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Yanjun Ma
David Evans
Yoshi Ono
Sheng Hsu
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Sharp Laboratories of America Inc
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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    • H01L29/4975Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Abstract

A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Description

    RELATED APPLICATION
  • This Application is a continuation-in-part of Ser. No. 09/004,991, filed Jan. 9, 1998, for “Metal Gate Sub-micron MOS Transistor and Method of Making Same” of Evans et al., and is incorporated herein by reference. [0001]
  • FIELD OF THE INVENTION
  • This invention relates to MOS Transistor and IC fabrication method, and specifically to the use of a nitride undercut to form a sub-micron MOS. [0002]
  • BACKGROUND OF THE INVENTION
  • The use of chemical etching to provide a controllable undercut has been used to produce conventional MOS transistors, which is known as a “T-gate” structure. A nitride undercut, using phosphoric acid, has been used specifically in the fabrication of triple implanted bipolar transistors, however, this process is not widely used now because of controllability issues required to manufacture ICs using current technology. The nitride undercutting process may remain a useful process in a certain application, such as in the manufacture of sub-micron MOS transistors. [0003]
  • Lightly doped (LDD) structures are widely used in state-of-the-art IC fabrication. The usual LDD process requires two implantation steps, however, one of the implantation steps is eliminated using the LDD method of the invention. [0004]
  • SUMMARY OF THE INVENTION
  • A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure [0005]
  • A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region. [0006]
  • An object of the invention is to provide a method of fabrication for sub-micron transistors [0007]
  • Another object of the invention is to provide a simplified LDD process [0008]
  • This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings. [0009]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0010] 1-4 depicts steps in the method of the invention.
  • FIG. 5 depicts a sub-micron MOS transistor constructed according to the method of the invention [0011]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • An n-channel MOS transistor is used as an example to describe the method of the invention, however, the structure and fabrication process is also applicable to p-channel MOS transistors and CMOS integration. [0012]
  • Referring to FIG. 1, a structure [0013] 10 constructed according to the method of the invention is fabricated using state-of-the-art processes on a p-type substrate 12 to form an n-well, a p-well, to adjust the voltage threshold in an active region 14, and to provide device isolation, as by oxide regions 16.
  • Turning to FIG. 2, a gate oxide layer [0014] 18 is formed, and a layer of silicon nitride (Si3N4), or polysilicon, 20, also refereed to herein as a first selective etchable layer is deposited to a thickness of between about 200 nm to 500 nm. A thin layer of oxide 22, also referred to herein as a second selective etchable layer, is deposited over the nitride layer to a thickness of between about 20 nm to 100 nm.
  • This is followed by photo lithography and anisotropic plasma etching of oxide layer [0015] 22 and silicon nitride, or polysilicon, layer 20, or polysilicon, wherein the etching stops at the level of gate oxide 18. Gate oxide layer 18 may be partially etched, or may be completely removed during this etching process. The remaining silicon nitride, or polysilicon, layer forms a replacement cast for a gate electrode, which will be formed in a subsequent step. Any remaining, photoresist is then removed, resulting in the structure shown generally at 10 in FIG. 2
  • Referring now to FIG. 3, nitride layer [0016] 20 is partially etched using phosphoric acid, which has a high selectivity over oxide, i.e., the phosphoric acid will remove silicon nitride considerably faster than it will remove silicon oxide, resulting in the structure of FIG. 3. The gate length is shortened by two-times the thickness of the nitride etched, resulting in a device having a shorter channel, for instance, a gate length of 100 nm results from an initial nitride deposition having a length of 200 nm, of which 50 nm is removed by etching.
  • In the case where polysilicon is used as a replacement cast, the gate oxide must not be completely removed during the gate etching process. Polysilicon may be selectively etched by using diluted HNO[0017] 3/HF solution. Additionally, the oxide layer 22 may be replaced with silicon nitride to achieve higher etching selectivity. In this case, silicon nitride is deposited to a thickness of between about 20 nm to 100 nm.
  • A source region [0018] 24 and a drain region 26 is formed in active region 16 by ion implantation adjacent a gate region 27. In the preferred embodiment, Arsenic ions are implanted at a dose of between about 1·1015 cm−2 to 5·1015 cm−2, and an energy level of between about 30 keV to 70 keV. Because of overhanging oxide 22, the implantation depth and dose is reduced in the region under the overhanging oxide, which results in an LDD source region 24 a and an LDD drain region 26 a adjacent gate region 27, without an additional implantation step. The implanted profile in this region is a function of implant energy, dose, and the thickness of the oxide. For instance, the ion concentration in the source region 24 and drain region 26 is between about 1·1020 cm−3 to 1·1021 cm−3, while the ion concentration in LDD source region 24 a and LDD drain region 26 a is between about 5·1018 cm−3 to 5·1019 cm−3 The gate may be heavily doped polysilicon or metal.
  • The next step is to CVD an oxide layer [0019] 28 to a thickness of between about 15 times to two times the thickness of silicon nitride layer 20 The structure is planarized by CMP, stopping at the level of silicon nitride layer 20. A high selectivity slurry is desirable for this process. Nitride layer 20 is etched to remove it, and doped polysilicon or metal 30 is deposited and CMP planarized to form a gate electrode. An oxide layer 32 is deposited by CVD, and a source electrode 34 and a drain electrode is formed, resulting in the structure shown generally at 38 in FIG. 5.
  • The remainder of the process proceeds as described in an earlier patent disclosure by Hsu and Evans describing the nitride replacement or “cast” process. For conventional polysilicon gate fabrication, standard processing, which is well known to those of ordinary skill in the art, is performed. [0020]
  • Thus, a structure and a method for fabricating a sub-micron MOS transistor using a silicon nitride or polysilicon undercut process has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims. [0021]

Claims (17)

We claim:
1. A method of fabricating a sub-micron MOS transistor comprising.
preparing a substrate, including isolating an active region therein;
depositing a gate oxide layer;
depositing a first selective etchable layer over the gate oxide layer;
depositing a second selective etchable layer over the first selective etchable layer;
etching the structure to undercut the first selective etchable layer;
implanting ions in the active region to form a source region and a drain region,
removing the remaining first selective etchable layer and the second selective etchable layer;
depositing a gate electrode; and
depositing oxide and metallizing the structure.
2. The method of
claim 1
wherein said depositing a first selective etchable layer includes depositing a layer of silicon nitride, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide.
3. The method of
claim 1
wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon nitride
4. The method of
claim 1
wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide.
5. The method of
claim 1
wherein said depositing a gate electrode includes depositing a layer of material taken from the group of materials consisting of doped polysilicon and metal.
6. The method of
claim 1
wherein said implanting includes implanting Arsenic ions at a dose of between about 1·1015 cm−2 to 5·1015 cm−2, and an energy level of between about 30 keV to 70 keV.
7. The method of
claim 6
wherein said implanting includes forming a LDD source region and an LDD drain region adjacent the gate region.
8. The method of
claim 7
wherein said implanting includes implanting ions to provide an ion concentration in the source region and in the drain region of between about 1·1020 cm−3 to 1·1021 cm−3, and wherein the ion concentration the LDD source region and in the LDD drain region is between about 5·1018 cm−3 to 5·1018 cm−3.
9. A method of fabricating a sub-micron MOS transistor comprising:
preparing a substrate, including isolating an active region therein;
depositing a gate oxide layer;
depositing a first selective etchable layer over the gate oxide layer,
depositing a second selective etchable layer over the first selective etchable layer;
etching the structure to undercut the first selective etchable layer;
implanting ions in the active region to form a source region and a drain region, including forming a LDD source region and an LDD drain region adjacent the gate region;
removing the remaining first selective etchable layer and the second selective etchable layer;
depositing a gate electrode; and
depositing oxide and metallizing the structure.
10. The method of
claim 9
wherein said depositing a first selective etchable layer includes depositing a layer of silicon nitride to a thickness of between about 200 nm to 500 nm, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide to a thickness of between about 20 nm to 100 nm.
11. The method of
claim 9
wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon nitride, wherein the thickness of both layers is between about 200 nm and 500 nm.
12. The method of
claim 9
wherein said depositing a first selective etchable layer includes depositing a layer of polysilicon to a thickness of between about 200 nm to 500 nm, and wherein said depositing a second selective etchable layer includes depositing a layer of silicon oxide to a thickness of between about 20 nm to 100 nm.
13. The method of
claim 9
wherein said depositing a gate electrode includes depositing a layer of material taken from the group of materials consisting of doped polysilicon and metal.
14. The method of
claim 9
wherein said implanting includes implanting Arsenic ions at a dose of between about 1·1015 cm−2 to 5·1015 cm−2, and an energy level of between about 30 keV to 70 keV.
15. The method of
claim 9
wherein said implanting includes implanting ions to provide an ion concentration in the source region and in the drain region of between about 1·1020 cm−3 to 1·1021 cm−3, and wherein the ion concentration the LDD source region and in the LDD drain region is between about 5·1018 cm−3 to 5·1019 cm−3.
16. A sub-micron MOS transistor comprising:
a substrate; and
an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region, wherein the ion concentration in said source region and in said drain region is between about 1·1020 cm−3 to 1·1021 cm−3, and wherein the ion concentration in said LDD source region and in said LDD drain region is between about 5·1018 cm−3 to 5·1019 cm−1.
17. The MOS transistor of
claim 16
which further includes an insulating oxide layer thereover and a source electrode, a gate electrode and a drain electrode.
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US10/621,852 US20040014292A1 (en) 1998-01-09 2003-07-16 Sub-micron MOS transistor

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