US20010001292A1 - Through-chip conductors for low inductance chip-to-chip integration and off-chip connections - Google Patents

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections Download PDF

Info

Publication number
US20010001292A1
US20010001292A1 US09746534 US74653400A US2001001292A1 US 20010001292 A1 US20010001292 A1 US 20010001292A1 US 09746534 US09746534 US 09746534 US 74653400 A US74653400 A US 74653400A US 2001001292 A1 US2001001292 A1 US 2001001292A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
chip
conductor
device
back surface
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09746534
Other versions
US6410431B2 (en )
Inventor
Claude Bertin
Wayne Howell
William Tonti
Jerzy Zalesinski
Original Assignee
Bertin Claude Louis
Howell Wayne John
Tonti William R.
Zalesinski Jerzy Maria
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • H01L2223/6622Coaxial feed-throughs in active or passive substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701Structure
    • H01L2224/1703Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or sold-state device [i.e. passive-on-chip]

Abstract

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Description

    BACKGROUND OF THE INVENTION
  • 1. 1. Technical Field
  • 2. The invention relates generally to semiconductor interconnects, and more specifically, to chip-to-chip integration and off-chip connection schemes for semiconductor devices.
  • 3. 2. Background Art
  • 4. A typical electronic system may comprise a variety of electronic components, fabricated on a variety of material. Very often, it is impossible for these various components to be integrated on a single substrate due to performance considerations or cost concerns. Consequently, these electronic components are packaged and externally electrically interconnected to function as a unit.
  • 5. In the past, semiconductor packages have been electrically interconnected through wire bonding and/or the use of a C4 flip chip. Unfortunately, as packages become more dense and total performance gain becomes more important for high power chips in the system, the use of wire bonding and flip chips to form off-chip connections is not practical in many applications. Specifically, a significant performance degradation is caused by a wire bond induced parasitic inductance from a chip to a printed circuit board. Although a flip chip overcomes the parasitic inductance problem, the thermal properties of the flip chip severely limit the ability to cool high power chips, and adding an external heat sink to provide thermal conduction causes packaging constraint and increased chip operation ambient temperature.
  • 6. There are inventions in the past with electronic components stacked together, whereby electrical communication between components are made possible via feed-throughs in the semiconductor bodies. Examples are found in the following U.S. Patents: U.S. Pat. No. 5,128,831, issued to Fox, III et al. in July 1992; U.S. Pat. No. 5,481,133, issued to Hsu in January 1996; U.S. Pat. No. 5,424,245, issued to Gurtler et al. in June 1995; U.S. Pat. No. 5,202,754, issued to Bertin et al. in April 1993; and U.S. Pat. No. 5,270,261, issued to Bertin et al. in December 1993. Although feed-throughs are used in the stacks, the assembled stacks are then attached onto a printed circuit board with the off-chip wiring schemes, long routing traces and all the associated prior art shortfalls. Furthermore, the aforementioned patents do not provide proper heat dissipation for high power chips, and low inductance connections to different levels of packaging, such as a circuit board.
  • SUMMARY OF THE INVENTION
  • 7. It is thus an advantage of the present invention to provide a through-chip conductors and chip-to-chip and off-chip connections for a semiconductor device and the method for making the same that eliminates the above described defects.
  • 8. The advantages of the invention are realized by a semiconductor device having active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.
  • 9. The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • 10. The preferred exemplary embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
  • 11.FIG. 1 is a simplified diagram of through-chip conductors and connectors for a semiconductor structure in accordance with a preferred embodiment of the present invention;
  • 12.FIGS. 2, 3 and 4 are cross-sectional views showing a fabrication sequence of the through-chip conductors of FIG. 1 in accordance with an embodiment of the present invention;
  • 13.FIG. 5 is a cross-sectional view of a second embodiment of the through-chip conductor of FIG. 1;
  • 14.FIG. 6 is a perspective view of the cross-section illustrated in FIG. 5 taken along line 6-6;
  • 15.FIGS. 7, 8, and 9 are cross-sectional views showing exemplary off-chip connections to various heat sinks and circuit boards using the through-chip conductors of FIG. 1;
  • 16.FIG. 10 is a cross-sectional view illustrating a fabrication of the chip-to-chip connectors of FIG. 1;
  • 17.FIGS. 11, 12, 13 and 14 are cross-sectional views illustrating a second and third embodiment of the chip-to-chip connectors of FIG. 1;
  • 18.FIGS. 15, 16, 17, and 18 are cross-sectional views of chip-to-chip connectors of FIG. 1 and respective connections thereof, and
  • 19.FIGS. 19, 20, 21 and 22 illustrate exemplary devices using the chip-to-chip connectors and through-chip conductors of FIG. 1.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • 20. Referring to FIG. 1, a simplified diagram of a portion of a semiconductor package 10 in accordance with a preferred embodiment of the present invention is shown. For this example, semiconductor package 10 includes, but is not limited to, semiconductor chips 50 and 15, with active regions at the front surfaces 60 and 61 of the chips, contact pads 71, insulated through-chip conductors 30, thermal through-chip conductor 20, chip-to-chip connectors 40, and off-chip connectors 74. As shown, insulated through-chip conductors 30 may be coupled to off-chip connector 74 at the back surfaces of chips 50 and 15 in order to pass or receive electrical and/or physical characteristics (not shown) from the back surface to the front surface of the chips 50 and 15. Furthermore, insulated through-chip conductors 30 may be coupled to chip-to-chip connectors at the front surface of chips 50 and 15 through contact pads 71. Chip-to-chip connectors 40 allow electrical characteristics of the active regions at the front surfaces 60, 61 or electrical/physical characteristics of the back surface of chips 50 and 15 to be passed from one chip to the other. In this example, thermal through-chip conductor 20 acts as a heat sink, providing heat dissipation for chip 15. As can be seen, the interconnections of the present invention provide high system packing densities and, as will be disclosed in greater detail below, also provide low inductance, high performance inter-chip and intra-chip communication and heat dissipation.
  • 21. FIGS. 2-4 illustrate exemplary fabrication processes for the through-chip conductors 20 and 30 according to a first embodiment of the present invention. As seen in FIG. 2, an exemplary completed wafer for a chip comprises wafer substrate 26 on the back surface of the chip, active silicon layer 28, additional metal and inter-layer devices 32, an optional nitride and/or laser stop 34, last metal layer 36, and final passivation layer 38. As aforementioned, these layers are exemplary layers for a completed wafer, wherein appropriate layers may be added or removed without changing the scope of the present invention. Also, although the final passivation layer 38 is not explicitly shown in other figures (e.g., FIGS. 1, 7, 8 etc.), it is to be understood that the final passivation layer 38 exists on each chip for the protection and isolation of the chip and only where contact is to be made, such as with a contact pad 71, a portion of the final passivation layer 38 will be removed (e.g., see FIG. 10). The thickness of the wafer is typically in the range of 250-300 micrometers (μm). Last metal layer 36 may consist of metals such as copper, aluminum, palladium, tungsten, or similar material, and may contain contact pad features, which will be shown further in reference to FIG. 4.
  • 22. The through-chip conductors 20 and 30 are formed by first drilling holes 18 and 19 into the semiconductor substrate as shown in FIG. 3. The holes may be drilled by a variety of methods. Examples include laser drilling, abrasive jet blasting, or chemical etching. The side-walls of the holes are then insulated with insulating material 33 for the insulated through-chip conductor 30 as seen in FIG.4. No insulation is needed for thermal through-chip conductors 20, since only heat dissipation is desired. An etch may be applied to the insulated through-chip conductor 30 or to the thermal through-chip conductor (see element 20A in FIG. 8) to couple the conductor to a contact pad 71. Finally, conductive materials 31, such as copper, are plated from the contact pad 71 or deposited into the holes to transform the vias into electrically and/or thermally conductive paths. Although copper plating is the preferred method of forming through-chip conductors 20 and 30, other appropriate processes, such as soldering a rod or wire to contact pad 71 after the holes are drilled, may also be used to achieve electrical/thermal conductivity.
  • 23. A cross-section of a second embodiment of through-chip conductor 30A is shown in FIG. 5. Through-chip conductor 30A is fabricated for very high speed interconnections to support high performance operation and is interchangeable with any through-chip conductor 30 illustrated. Through-chip conductor 30A has an inner conductor 114, an insulation layer 116 (e.g., SiO2), and an outer conductor 112. Inner and outer conductors extend out 122, 123 from the substrate for accessibility. FIG. 6 illustrates the perspective view of the cross-section illustrated in FIG. 5 taken along line 6-6. The inductance for a line segment length X (FIG. 5) is given by the equation:
  • L=(uX/2Π)1n(r1/r2)
  • 24. wherein:
  • 25. L=inductance;
  • 26. u=magnetic permeability;
  • 27. X=line segment length;
  • 28. r1=inner conductor radius; and
  • 29. r2=outer conductor radius.
  • 30. The typical wirebond inductance is approximately 5 to 7 nanohenry (nhy). In comparison, with an inner radius r1=21.2 micrometers (μm), an outer radius r2=31.2 μm, a segment length X=250 μm, and a magnetic permeability of free space, u=u0 (there is no magnetic material in the structure), the value of the inductance L for this example of the present invention is approximately 0.02 nhy. The extension 122 of the inner conductor 114 will add to the series inductance, and may add up to twenty percent of the segment for each line segment. However, even if L is increased from 0.02 nhy to 0.024 nhy, L is still more than 100 times smaller than the inductance of a wirebond connection.
  • 31. The capacitance value for the segment of length X is given by the equation:
  • C=(ε/t0X)(2Πr1)X
  • 32. wherein:
  • 33. C=capacitance;
  • 34. ε=electrical permitivity;
  • 35. t0X=dielectric thickness;
  • 36. r1=inner conductor radius; and
  • 37. X=line segment length.
  • 38. Typical chip input capacitance is approximately 5 to 7 picofarads (pf). In this example, the approximate value of the capacitance C equals 0.2 pf for a dielectric thickness t0X=10 μm, a relative dielectric constant εr=4 (e.g., SiO2), r1=21.2 μm and X=250 μm. The capacitance of segment X is at least 25 times smaller than the chip input capacitance, therefore, the additional capacitive loading of the through chip connection is negligible.
  • 39. The resistance value for the segment of length X is given by the equation:
  • R=(Rho)(X/Area); Area=2Πr12
  • 40. wherein:
  • 41. R=resistance;
  • 42. Rho=conductivity of the conductor;
  • 43. X=line segment length; and
  • 44. r1=inner conductor radius.
  • 45. The resistance of a copper segment X=250 μm in length, with a radius r1=21.2 μm is approximately R=1.4 miliohms, which is a negligible increase in resistance.
  • 46. FIGS. 7-9 illustrate exemplary chip-to-circuit board connections using through-chip conductors in accordance with the present invention. As seen in FIG. 7, chip 15 comprises insulated through-chip conductors 30, contact pads 71 and active region 61. The integrated copper (or copper-invar-copper) core board 16 comprises an embedded heat sink 41, insulating layer 48 and electrical region 52. Chip 15 is connected to the integrated copper core board 16 through interconnect material 44 (e.g., solder) and insulated through-chip conductors 30. That is, insulated through-chip conductors 30 provide a low inductance electrical connection between the chip's active region 61 and the electrical region 52 of the circuit board 16. A thermal bond 46 is created between heat sink 41 and the back surface of chip 15 allowing for removal of additional heat in high power applications. Although only two through-chip conductors are shown in this and other examples, it is to be understood that any desired amount of through-chip conductors may be used.
  • 47. Heat transfer may be maximized through use of thermal through-chip conductors 20A connecting to an external heat sink 56 and the integrated copper core board 16 through thermal interconnects 51 and 45 (e.g., solder), and thermal path 53 as shown in FIG. 8. Thermal through-chip conductor 20, which does not penetrate the front surface of the chip but terminates close to the active circuit region 61, directly connects to heat sink 41 to provide additional and enhanced localized cooling. Although thermal through-chip conductors 20A and 20 are shown, insulated through-chip conductors 30 may also be used to dissipate heat, or to pass electrical power through either heat sink into the chip for system use. Heat is now removed from chip 15 through external heat sink 56, heat sink 41, which directly connects to the chip's back surface, and through the thermal path 53 to the copper core of circuit board 16. The thermal through-chip conductors 20A maintain a uniform temperature distribution within chip 15, and allow the integration of a three-dimensional external heat sink 56 to conduct heat from regions which require such cooling.
  • 48. Chip 15 may also be connected to a circuit board 17 without a heat sink as shown in FIG. 9. In this case, thermal conductivity is moderate, thus a thermal through-chip conductor 20 connected to a thermal path 55, or one that does not contact the circuit board (not shown) may be used as a heat sink 54. In this example, an insulated through-chip conductor 30 is also used as an electrical conductive path from circuit board 17 to front surface 61 of chip 15.
  • 49. FIGS. 10-22 illustrate the fabrication of chip-to-chip connectors and the use thereof with through-chip conductors to connect two or more chips or similar devices.
  • 50.FIG. 10 illustrates an example of the fabrication of chip-to-chip connectors 40. Although for this example only two sizes 40A and 40B of chip-to-chip connectors are shown, it is to be understood that any appropriate amount and size of chip-to-chip connector may be used for this and subsequent examples. Before fabrication of chip-to-chip connectors 40, a dielectric layer 97, (e.g., a silicon-nitride layer (SiN)), may be deposited over other existing dielectric layers, such as silicon-oxide (SiO) layer 91, SiN layer 93 and SiO layer 95 of chip 15 to act as a barrier layer. The contact pads 71 are then exposed through an etching process and a first sacrificial insulation layer 101 is deposited to define the height of the smallest chip-to-chip connector 40B. Via holes 77 are then etched into the first sacrificial insulation layer 101 and copper 79 is plated to the surface of the via hole 77. As aforementioned in reference to the through-chip conductors, although copper is shown and preferred for this and other examples, other conductive materials and metals may also be used. The sacrificial insulation 101 undergoes a chemical mechanical polish (CMP), and a second sacrificial insulation layer 103 is deposited thereupon. A via hole is etched wherein a solder layer of uniform thickness 75 is plated. A second, taller chip-to-chip connector 40A is then similarly fabricated by depositing a third sacrificial layer 105, etching via hole 87, plating the hole with copper plating 89, depositing a fourth sacrificial layer 107 and plating a second solder layer 85. All sacrificial insulating layers are then removed, with dielectric layer 97, or optionally dielectric layer 95 acting as an etch stop.
  • 51. Using sacrificial insulating layers and via etching as described above provides multiple chip-to-chip connectors of the same height. This process also allows for chip-to-chip connectors of varying heights, which can accommodate chips of different sizes, decoupling capacitors for power supply decoupling, heat sinks, etc. as will be illustrated in FIGS. 19 and 20. Additionally, the process allows for much tighter connector-to-connector spacings, less than 10 μm for example.
  • 52. As shown in FIGS. 11-14, a chip-to-chip connector 40C or 40D may also be fabricated to form a coaxial high performance connection between chips. FIG. 11 illustrates a chip-to-chip connector 40C comprising a center conductor/connector 40A and an outer conductor 152. Connector 40A connects the signal pad 158 of chip 15 to pad 160 on chip 50. Outer conductor 152 is connected to ground pads, 154 and 156, although other options are possible. FIG. 12 illustrates the perspective view of the cross-section illustrated in FIG. 11 taken along line 12-12.
  • 53. In FIG. 13, chip-to-chip connector 40D comprises two center connectors 40A and outer conductor 152. Connectors 40A connects two different signal pads 158 and 159 of chip 15 to pads 160 and 161, respectively, on chip 50. Again, outer conductor 152 is connected to ground pads, 154 and 156. FIG. 14 illustrates the perspective view of the cross-section illustrated in FIG. 13 taken along line 14-14. Although not shown, other arrangements may be made to improve conduction of chip-to-chip electrical characteristics, for example, conductors connecting signal pads may alter with conductors connecting ground pads. Thus, chip-to-chip connectors as shown in FIGS. 11-14, or other suitable arrangements, provide substantial improved electrical characteristics of connections between chips 15 and 50. As an example, for FIG. 11, if the center connector 40A is 500 μm long, the time delay between chips 15 and 50 is less than 2 ps.
  • 54. As shown in FIGS. 15-18, chip-to-chip connector 40 may be used to connect chips with contact pads having the same periodicity (i.e., the contact pads line up with each other, see FIGS. 15 and 16), or different periodicities (see FIGS. 17 and 18). Although specific examples and connections are shown for FIGS. 15-18, other appropriate examples may also be used.
  • 55. As seen in FIG. 15, with similar periodicities, the contact pads 71 of chip 15 may be directly connected to the contact pads 128 of chip 50 with chip-to-chip connectors 40. Although elements 128 and 71 are described in this specific example as contact pads, elements 128 and 71 may also be a relatively wide buslines connected directly by chip-to-chip connector 40. FIG. 16 shows the top view of contact pads 128 on chip 50.
  • 56.FIG. 17 illustrates how to connect chip 15 to chip wiring or busline 130 in chip 51 with a much tighter periodicity. The contact pads are connected by using a stud 131 between the busline 130 and a pad layer 132. The pad layers 132 are then staggered as shown in FIG. 18, which permits the connection of the contact pads 71 of chip 15 with the busline 130 of chip 51. FIG. 18 shows the top view of this arrangement. With such an arrangement, it would be possible, for example, to connect array drivers in one technology in a first chip to array lines in a memory chip, thus providing higher performance of the system.
  • 57.FIGS. 19 and 20 illustrate the use of chip-to-chip connectors of mixed heights to accommodate different chip sizes and structures. As seen in FIG. 19, the active region of chip 50 is connected via chip-to-chip connectors 40 to the active region of chip 15. The external connections and electrical connections such as power, ground and signal (not shown) are made from the back surface of chip 15, and are conducted to the active regions of chip 50 and 15 via through-chip conductors 30. The thermal path is shown from the back surface of chip 15 through thermal through-chip conductors 20A, chip-to-chip connectors 40A, thermal adhesive 149, to external heat sink 56. Heat sink 56 provides cooling of chip 15 through the tall chip-to-chip connectors 40A, and direct cooling to chip 50. The taller connectors 40A have more ability to flex than the smaller connectors, and thus can support greater mechanical stress.
  • 58.FIG. 20 illustrates a power supply decoupling capacitor configuration with mixed tall and short chip-to-chip connectors 40A and 40 on chip 15. Chip 15 may receive external electrical connections (not shown) through the back surface that includes power supply, ground and signal. The electrical characteristics are then conducted to the active regions of chip 50 and chip 15 through through-chip conductors 30 and chip-to-chip connectors 40A. Decoupling capacitors 136 are mounted on the front surface of chip 15 and on the back surface of chip 50. Chip-to-chip connectors 40A have sufficient height to accommodate the decoupling capacitors 136. The connections in FIGS. 19 and 20 are point-to-point connections, wherein only one connection is made to each of the chips in the stack. Point-to-point connections allow for minimized loading at each of the stack connections and thus faster performance of the system. More connections, though, and consequently, more space is required for point-to-point connections.
  • 59.FIGS. 21 and 22 illustrate the ability to stack similar chips while providing high speed chip-to-chip connections through the silicon. As seen in FIG. 21, a stack of chips 142, 144, 146 and 148 is mounted directly on device 140, such as a logic chip, carry-card, microprocessor, controller, etc. , to minimize latency between the device and chips and to maximize bandwidth. Each chip is mounted with the active area facing down, and is configured for its position in the stack. The first four connections connect the device 140 to each chip, wherein the first connection connects to a receiver on chip 148 and requires three chip-to-chip connectors to reach it, the second connection connects to chip 146, the third connection to chip 144 and the fourth connection to a low capacitance receiver on chip 142. Each of the next four connections shown connect to all four chips. These last four connections allow for parallel input/output connections. FIG. 22 shows device 140 having through-chip conductors , such that the stack may be mounted with two chips on each side of the processor for even higher performance.
  • 60. In the chip stacks of FIGS. 21 and 22, or similar stack structures, the knowledge of whether these interconnections through multiple chips behave as lumped capacitances and inductance, or as transmission lines is important. That is, high speed transmission lines usually require termination to avoid reflection while lumped capacitive and inductive elements do not. The electrical behavior is determined by the round trip delay time in relation to the rise time (or fall time) of the waveform. If the rise (or fall) time trt of the waveform is greater than two times the round trip transmission line delay td (trt>2td), lumped capacitance and inductance assumptions may be used (as described in “Cross Talk and Reflections in High Speed Digital Systems”, Feller et al, RCA, Proceedings-Fall Joint Computer Conference, 1965).
  • 61. For chips 250 μm thick, the round trip delay through one segment is less than 2 picoseconds (ps). For a stack of chips 4 high, the round trip delay is less than 8 ps, and for a stack of chips as high as 20, the round trip delay is less than 40 ps. In the case of a 20 chip stack, the inductance for a 20 chip stack, with 20 segments, is less than ½nhy, and the capacitance for 20 segments is less than 4 pf. Thus, the combined inductance and capacitance of a stack of 20 chips may be treated as lumped elements up to a frequency of 4 Giga Hertz (GHz). Above 4 GHz, the segments would behave as transmission lines requiring terminations. Furthermore, connections inside silicon are capable of very high frequency characteristics without cross talk and without radiation.
  • 62. Thus, the through-chip conductors and connectors according to an embodiment of the present invention provides high system packing densities, as well as low inductance, high performance inter-chip and intra-chip communication and heat dissipation.
  • 63. While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims (30)

    What is claimed is:
  1. 1. A semiconductor device comprising:
    a substrate having a back surface and active devices on a front surface;
    at least one first through-chip conductor passing a first electrical/physical characteristic from said front surface to said back surface of the substrate; and
    at least one chip connector electrically connected to said active devices of said substrate and to a conductor on a different level of packaging.
  2. 2. The device of
    claim 1
    , further comprising at least one second through-chip conductor passing a second electrical/physical characteristic to said back surface of the substrate.
  3. 3. The device of
    claim 1
    , wherein said chip connector is coupled to said first through-chip conductor at said back surface of said substrate.
  4. 4. The device of
    claim 1
    , wherein said different level of packaging comprises a circuit board.
  5. 5. The device of
    claim 1
    , wherein said different level of packaging comprises a heat sink.
  6. 6. The device of
    claim 5
    , wherein said heat sink is in thermal contact to said back surface of said substrate.
  7. 7. The device of
    claim 1
    , wherein the different level of packaging comprises decoupling capacitors.
  8. 8. The device of
    claim 1
    , wherein said at least one chip connector comprises a plurality of chip connectors of mixed heights.
  9. 9. The device of
    claim 2
    , wherein said first electrical/physical characteristics are electrical and said second electrical/physical characteristics are thermal.
  10. 10. The device of
    claim 1
    , wherein said first through-chip conductor comprises an inner conductor surrounded by an insulator.
  11. 11. The device of
    claim 1
    , wherein said first through-chip conductor comprises an outer conductor and an inner conductor separated by an insulator.
  12. 12. The device of
    claim 1
    , wherein said conductor is copper.
  13. 13. The device of
    claim 1
    , wherein said chip connector comprises a conductor of plated copper.
  14. 14. The device of
    claim 1
    , wherein said chip connector comprises an outer conductor of plated copper and at least one inner conductor of plated copper separated by an insulator.
  15. 15. A method of electrically and thermally connecting a semiconductor device having a front surface with active devices and a back surface to a different level of packaging, comprising the steps of:
    a) providing at least one first through-chip conductor; and
    b) electrically passing a first electrical/physical characteristic from said active devices of said semiconductor device to said different level of packaging with said first through-chip conductor.
  16. 16. The method of
    claim 15
    , further comprising the steps of:
    c) providing at least one second through-chip conductor; and
    d) passing thermal characteristics of said semiconductor device to said back surface of said semiconductor device with said second through-chip conductor.
  17. 17. The method of
    claim 15
    , further comprising the steps of:
    coupling said different level of packaging to said back surface of said semiconductor device.
  18. 18. The method of
    claim 17
    , wherein said different level of packaging is a circuit board.
  19. 19. The method of
    claim 15
    , wherein step b) further comprises the steps of:
    b1) providing at least one chip connector; and
    b2) electrically connecting said active devices of said semiconductor device to said different level of packaging with said chip connector.
  20. 20. The method of
    claim 19
    , wherein step b1) further comprises the steps of:
    1) depositing a first sacrificial layer on said semiconductor device;
    2) etching a first via hole in said first sacrificial layer;
    3) plating a first conductive material in said first via hole;
    4) depositing a second sacrificial layer on said first sacrificial layer;
    5) etching a second via hole in said second sacrificial layer;
    6) plating a second conductive material in said second via hole; and
    7) removing said first and second sacrificial layer.
  21. 21. The method of
    claim 20
    , wherein said first conductive material is copper.
  22. 22. A method of fabricating a chip connector for a semiconductor device, comprising the steps of:
    a) depositing a first sacrificial layer on said semiconductor device;
    b) etching a first via hole in said first sacrificial layer;
    c) plating a first conductive material in said first via hole;
    d) depositing a second sacrificial layer on said first sacrificial layer;
    e) etching a second via hole in said second sacrificial layer;
    f) plating a second conductive material in said second via hole; and
    g) removing said first and second sacrificial layer.
  23. 23. The method of
    claim 22
    , wherein said first conductive material is copper.
  24. 24. A semiconductor package comprising:
    an active semiconductor device having a back surface and active devices on a front surface;
    a first set of through-chip conductors passing from the front surface of the device to the back surface of the device;
    chip connectors connected to the through-chip conductors on the back surface of the device; and
    a different level of packaging in contact with the back surface of the device.
  25. 25. The package of
    claim 24
    , wherein said different level of packaging comprises a heat sink in thermal contact with the back surface of the device.
  26. 26. The package of
    claim 24
    , wherein said different level of packaging comprises a circuit board.
  27. 27. The package of
    claim 24
    , wherein said first through-chip conductor comprises an inner conductor surrounded by an insulator.
  28. 28. The package of
    claim 24
    , wherein said first through-chip conductor comprises an outer conductor and an inner conductor separated by an insulator.
  29. 29. The package of
    claim 24
    , wherein said chip connector comprises a conductor of plated copper.
  30. 30. The package of
    claim 24
    , wherein said chip connector comprises an outer conductor of plated copper and at least one inner conductor of plated copper separated by an insulator.
US09746534 1998-04-07 2000-12-19 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections Expired - Lifetime US6410431B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09056277 US6222276B1 (en) 1998-04-07 1998-04-07 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US09746534 US6410431B2 (en) 1998-04-07 2000-12-19 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09746534 US6410431B2 (en) 1998-04-07 2000-12-19 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09056277 Division US6222276B1 (en) 1998-04-07 1998-04-07 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Publications (2)

Publication Number Publication Date
US20010001292A1 true true US20010001292A1 (en) 2001-05-17
US6410431B2 US6410431B2 (en) 2002-06-25

Family

ID=22003353

Family Applications (2)

Application Number Title Priority Date Filing Date
US09056277 Expired - Lifetime US6222276B1 (en) 1998-04-07 1998-04-07 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US09746534 Expired - Lifetime US6410431B2 (en) 1998-04-07 2000-12-19 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09056277 Expired - Lifetime US6222276B1 (en) 1998-04-07 1998-04-07 Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Country Status (1)

Country Link
US (2) US6222276B1 (en)

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040018693A1 (en) * 2001-01-26 2004-01-29 Fujitsu Limited Capacitor and semiconductor device and method for fabricating the semiconductor device
US20040259292A1 (en) * 2003-04-03 2004-12-23 Eric Beyne Method for producing electrical through hole interconnects and devices made thereof
EP1465246A3 (en) * 2003-04-03 2005-03-16 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
US20050056944A1 (en) * 2001-02-27 2005-03-17 Chippac, Inc. Super-thin high speed flip chip package
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US20060278992A1 (en) * 2005-06-14 2006-12-14 John Trezza Post & penetration interconnection
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US20060281307A1 (en) * 2005-06-14 2006-12-14 John Trezza Post-attachment chip-to-chip connection
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20060293727A1 (en) * 2002-05-09 2006-12-28 Greg Spooner System and method for treating exposed tissue with light emitting diodes
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20070281466A1 (en) * 2006-06-06 2007-12-06 John Trezza Front-end processed wafer having through-chip connections
US20080090413A1 (en) * 2006-10-17 2008-04-17 John Trezza Wafer via formation
US20080157787A1 (en) * 2007-01-03 2008-07-03 Cubic Wafer, Inc. Sensitivity capacitive sensor
US20080197488A1 (en) * 2007-02-15 2008-08-21 John Trezza Bowed wafer hybridization compensation
US20080197508A1 (en) * 2007-02-16 2008-08-21 John Trezza Plated pillar package formation
US20080200022A1 (en) * 2007-02-15 2008-08-21 John Callahan Post-seed deposition process
US20080197893A1 (en) * 2007-02-15 2008-08-21 Wyman Theodore J Ted Variable off-chip drive
US20080242220A1 (en) * 2007-03-29 2008-10-02 Research In Motion Limited Method, system and mobile device for prioritizing a discovered device list
US20080246145A1 (en) * 2007-04-05 2008-10-09 John Trezza Mobile binding in an electronic connection
US20080245846A1 (en) * 2007-04-05 2008-10-09 John Trezza Heat cycle-able connection
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
US20090020855A1 (en) * 2007-12-20 2009-01-22 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US20090057872A1 (en) * 2007-08-29 2009-03-05 Ehlers Eric R Through-Chip Via Interconnects for Stacked Integrated Circuit Structures
US20090161402A1 (en) * 2007-12-20 2009-06-25 Hakjune Oh Data storage and stackable configurations
US20090267219A1 (en) * 2007-04-23 2009-10-29 John Trezza Ultra-thin chip packaging
US20100078808A1 (en) * 2008-09-29 2010-04-01 Burch Kenneth R Packaging having two devices and method of forming thereof
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US20100213592A1 (en) * 2009-02-24 2010-08-26 International Business Machines Corporation Semiconductor Module, Terminal Strip, Method for Manufacturing Terminal Strip, and Method for Manufacturing Semiconductor Module
US20110068437A1 (en) * 2009-09-23 2011-03-24 Chi-Tsung Chiu Semiconductor Element Having a Conductive Via and Method for Making the Same and Package Having a Semiconductor Element with a Conductive Via
US20110074028A1 (en) * 2004-10-07 2011-03-31 Stats Chippac, Ltd. Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
USRE44438E1 (en) * 2001-02-27 2013-08-13 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US8946757B2 (en) * 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997035010A8 (en) * 1996-03-19 2004-06-03 Reiner L Gentz Chemokine alpha 2
EP1061578A4 (en) * 1998-12-16 2001-07-18 Seiko Epson Corp Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them
JP2000243900A (en) * 1999-02-23 2000-09-08 Rohm Co Ltd Semiconductor chip, semiconductor device using it, and manufacture of semiconductor chip
JP3879816B2 (en) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof, a stacked semiconductor device, the circuit board and electronic equipment
JP2004510145A (en) * 2000-09-20 2004-04-02 モレキュラー・リフレクションズ Microfabricated ultrasonic array for use as a resonance sensor
JP4422323B2 (en) * 2000-12-15 2010-02-24 株式会社ルネサステクノロジ Semiconductor device
DE10107839A1 (en) * 2001-02-16 2002-09-05 Philips Corp Intellectual Pty Arrangement with a mounted on a support integrated circuit and a power supply assembly arrangement
JP2002305282A (en) * 2001-04-06 2002-10-18 Shinko Electric Ind Co Ltd Semiconductor element and structure for connecting the same, and semiconductor device with stacked semiconductor elements
JP4408006B2 (en) * 2001-06-28 2010-02-03 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6759275B1 (en) * 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
JP3908146B2 (en) * 2002-10-28 2007-04-25 シャープ株式会社 A semiconductor device and a stacked type semiconductor device
US6756664B2 (en) * 2002-11-22 2004-06-29 Via Technologies, Inc. Noise eliminating system on chip and method of making same
JP4057921B2 (en) * 2003-01-07 2008-03-05 株式会社東芝 Semiconductor device and method Assembly
US6849951B1 (en) 2003-02-28 2005-02-01 Xilinx, Inc. Bypass capacitor solution for integrated circuit dice
US6917219B2 (en) * 2003-03-12 2005-07-12 Xilinx, Inc. Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice
JP2004356618A (en) * 2003-03-19 2004-12-16 Ngk Spark Plug Co Ltd Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, structure having semiconductor element, intermediate substrate, and substrate, and method for manufacturing intermediate substrate
US6756305B1 (en) 2003-04-01 2004-06-29 Xilinx, Inc. Stacked dice bonded with aluminum posts
US7068072B2 (en) 2003-06-30 2006-06-27 Xilinx, Inc. Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit
WO2005065336A3 (en) * 2003-12-30 2005-09-09 Tessera Inc High-frequency chip packages
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
JP4528100B2 (en) * 2004-11-25 2010-08-18 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
JP4311376B2 (en) 2005-06-08 2009-08-12 セイコーエプソン株式会社 Semiconductor device, method of manufacturing a semiconductor device, electronic components, circuit boards and electronic devices
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7332799B2 (en) * 2005-12-28 2008-02-19 Tessera, Inc. Packaged chip having features for improved signal transmission on the package
JP4753725B2 (en) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 Stacked semiconductor device
US7663232B2 (en) * 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
JP2008053693A (en) * 2006-07-28 2008-03-06 Sanyo Electric Co Ltd Semiconductor module, portable device, and manufacturing method of semiconductor module
US20080092015A1 (en) * 2006-09-28 2008-04-17 Yigal Brandman Nonvolatile memory with adaptive operation
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
JP2009147218A (en) * 2007-12-17 2009-07-02 Toshiba Corp Semiconductor device, and method for manufacturing the same
US7701251B1 (en) * 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
KR100959606B1 (en) * 2008-03-12 2010-05-27 주식회사 하이닉스반도체 Stack package and method for fabricating of the same
KR20100079183A (en) * 2008-12-30 2010-07-08 주식회사 동부하이텍 Semiconductor package apparatus and manufacturing method of the semiconductor package apparatus
US7894230B2 (en) * 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
US8296578B1 (en) 2009-08-03 2012-10-23 Xilinx, Inc. Method and apparatus for communicating data between stacked integrated circuits
US20110057321A1 (en) * 2009-09-08 2011-03-10 Industrial Technology Research Institute 3-d multi-wafer stacked semiconductor structure and method for manufacturing the same
US8242604B2 (en) 2009-10-28 2012-08-14 International Business Machines Corporation Coaxial through-silicon via
US8102058B2 (en) * 2009-11-12 2012-01-24 Industrial Technology Research Institute Chip package structure and method for fabricating the same
US8455936B2 (en) * 2010-02-25 2013-06-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Configurable memory sheet and package assembly
US20110304010A1 (en) * 2010-06-11 2011-12-15 Industrial Technology Research Institute Electrostatic discharge protection scheme for semiconductor device stacking process
US8405203B2 (en) * 2010-09-10 2013-03-26 Cisco Technology, Inc. Semiconductor package with integrated substrate thermal slug
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9299572B2 (en) * 2014-03-07 2016-03-29 Invensas Corporation Thermal vias disposed in a substrate without a liner layer
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
CN105742254A (en) 2014-12-30 2016-07-06 精材科技股份有限公司 Chip Package And Fabrication Method Thereof
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9401323B1 (en) 2015-04-03 2016-07-26 International Business Machines Corporation Protected through semiconductor via (TSV)
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9859896B1 (en) 2015-09-11 2018-01-02 Xilinx, Inc. Distributed multi-die routing in a multi-chip module
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US20170181286A1 (en) * 2015-12-21 2017-06-22 Intel Corporation Development of the advanced component in cavity technology
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614541A (en) 1969-04-08 1971-10-19 North American Rockwell Package for an electronic assembly
US4954458A (en) 1982-06-03 1990-09-04 Texas Instruments Incorporated Method of forming a three dimensional integrated circuit structure
US5166097A (en) 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5202754A (en) 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5270261A (en) 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5128831A (en) 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5199165A (en) 1991-12-13 1993-04-06 Hewlett-Packard Company Heat pipe-electrical interconnect integration method for chip modules
US5432999A (en) 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5406120A (en) 1992-10-20 1995-04-11 Jones; Robert M. Hermetically sealed semiconductor ceramic package
US5322816A (en) 1993-01-19 1994-06-21 Hughes Aircraft Company Method for forming deep conductive feedthroughs
EP0610709B1 (en) 1993-02-11 1998-06-10 Siemens Aktiengesellschaft Process of manufacturing tri-dimensional circuit devices
US5447871A (en) 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5502667A (en) 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5917707A (en) * 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
EP0658937A1 (en) 1993-12-08 1995-06-21 Hughes Aircraft Company Vertical IC chip stack with discrete chip carriers formed from dielectric tape
US5640051A (en) 1993-12-13 1997-06-17 Matsushita Electric Industrial Co., Ltd. Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex
US5424245A (en) 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5455445A (en) 1994-01-21 1995-10-03 Kulite Semiconductor Products, Inc. Multi-level semiconductor structures having environmentally isolated elements
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5585675A (en) 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
EP0708481A3 (en) 1994-10-20 1997-04-02 Hughes Aircraft Co Improved flip chip high power monolithic integrated circuit thermal bumps and fabrication method
US5621616A (en) 1995-09-29 1997-04-15 Lsi Logic Corporation High density CMOS integrated circuit with heat transfer structure for improved cooling
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
JP4011695B2 (en) * 1996-12-02 2007-11-21 株式会社東芝 Chip and forming method for a multi-chip semiconductor device
JPH11121897A (en) * 1997-10-14 1999-04-30 Fujitsu Ltd Structure and production of printed wiring board mounting a plurality of circuit elements

Cited By (121)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156279A1 (en) * 2001-01-26 2005-07-21 Fujitsu Limited Capacitor and semiconductor device and method for fabricating the semiconductor device
US20040018693A1 (en) * 2001-01-26 2004-01-29 Fujitsu Limited Capacitor and semiconductor device and method for fabricating the semiconductor device
US7339277B2 (en) 2001-01-26 2008-03-04 Fujitsu Limited Semiconductor device having passive component and support substrate with electrodes and through electrodes passing through support substrate
US6873038B2 (en) * 2001-01-26 2005-03-29 Fujitsu Limited Capacitor and semiconductor device and method for fabricating the semiconductor device
US20050056944A1 (en) * 2001-02-27 2005-03-17 Chippac, Inc. Super-thin high speed flip chip package
US8941235B2 (en) * 2001-02-27 2015-01-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US20120175769A1 (en) * 2001-02-27 2012-07-12 Stats Chippac, Ltd. Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
USRE44438E1 (en) * 2001-02-27 2013-08-13 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US20060293727A1 (en) * 2002-05-09 2006-12-28 Greg Spooner System and method for treating exposed tissue with light emitting diodes
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
EP1465246A3 (en) * 2003-04-03 2005-03-16 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
US20040259292A1 (en) * 2003-04-03 2004-12-23 Eric Beyne Method for producing electrical through hole interconnects and devices made thereof
US8143108B2 (en) * 2004-10-07 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US20110074028A1 (en) * 2004-10-07 2011-03-31 Stats Chippac, Ltd. Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US20060278980A1 (en) * 2005-06-14 2006-12-14 John Trezza Patterned contact
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment
US20060278966A1 (en) * 2005-06-14 2006-12-14 John Trezza Contact-based encapsulation
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20060278988A1 (en) * 2005-06-14 2006-12-14 John Trezza Profiled contact
WO2006138489A2 (en) * 2005-06-14 2006-12-28 Cubic Wafer, Inc. Chip-based thermo-stack
US20060281243A1 (en) * 2005-06-14 2006-12-14 John Trezza Through chip connection
US20070138562A1 (en) * 2005-06-14 2007-06-21 Cubic Wafer, Inc. Coaxial through chip connection
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070182020A1 (en) * 2005-06-14 2007-08-09 John Trezza Chip connector
US20070196948A1 (en) * 2005-06-14 2007-08-23 John Trezza Stacked chip-based system and method
US20070197013A1 (en) * 2005-06-14 2007-08-23 Cubic Wafer, Inc. Processed Wafer Via
US20070228576A1 (en) * 2005-06-14 2007-10-04 John Trezza Isolating chip-to-chip contact
US20060281307A1 (en) * 2005-06-14 2006-12-14 John Trezza Post-attachment chip-to-chip connection
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US20080171174A1 (en) * 2005-06-14 2008-07-17 John Trezza Electrically conductive interconnect system and method
US8643186B2 (en) 2005-06-14 2014-02-04 Cufer Asset Ltd. L.L.C. Processed wafer via
WO2006138489A3 (en) * 2005-06-14 2007-11-15 Cubic Wafer Inc Chip-based thermo-stack
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US9754907B2 (en) 2005-06-14 2017-09-05 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US8232194B2 (en) 2005-06-14 2012-07-31 Cufer Asset Ltd. L.L.C. Process for chip capacitive coupling
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
US8197626B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US7482272B2 (en) 2005-06-14 2009-01-27 John Trezza Through chip connection
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US7521806B2 (en) 2005-06-14 2009-04-21 John Trezza Chip spanning connection
US7538033B2 (en) * 2005-06-14 2009-05-26 John Trezza Post-attachment chip-to-chip connection
US8154131B2 (en) 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US20060278992A1 (en) * 2005-06-14 2006-12-14 John Trezza Post & penetration interconnection
US8093729B2 (en) 2005-06-14 2012-01-10 Cufer Asset Ltd. L.L.C. Electrically conductive interconnect system and method
US7659202B2 (en) 2005-06-14 2010-02-09 John Trezza Triaxial through-chip connection
US8084851B2 (en) 2005-06-14 2011-12-27 Cufer Asset Ltd. L.L.C. Side stacking apparatus and method
US8067312B2 (en) 2005-06-14 2011-11-29 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US20110212573A1 (en) * 2005-06-14 2011-09-01 John Trezza Rigid-backed, membrane-based chip tooling
US7847412B2 (en) * 2005-06-14 2010-12-07 John Trezza Isolating chip-to-chip contact
US20100148343A1 (en) * 2005-06-14 2010-06-17 John Trezza Side stacking apparatus and method
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US20100197134A1 (en) * 2005-06-14 2010-08-05 John Trezza Coaxial through chip connection
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7932584B2 (en) * 2005-06-14 2011-04-26 Cufer Asset Ltd. L.L.C. Stacked chip-based system and method
US7919870B2 (en) 2005-06-14 2011-04-05 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US7808111B2 (en) 2005-06-14 2010-10-05 John Trezza Processed wafer via
US20100261297A1 (en) * 2005-06-14 2010-10-14 John Trezza Remote chip attachment
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20070281466A1 (en) * 2006-06-06 2007-12-06 John Trezza Front-end processed wafer having through-chip connections
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US7871927B2 (en) 2006-10-17 2011-01-18 Cufer Asset Ltd. L.L.C. Wafer via formation
US20080090413A1 (en) * 2006-10-17 2008-04-17 John Trezza Wafer via formation
US20100055838A1 (en) * 2007-01-03 2010-03-04 Abhay Misra Sensitivity capacitive sensor
US8499434B2 (en) 2007-01-03 2013-08-06 Cufer Asset Ltd. L.L.C. Method of making a capacitive sensor
US20080157787A1 (en) * 2007-01-03 2008-07-03 Cubic Wafer, Inc. Sensitivity capacitive sensor
US7705613B2 (en) 2007-01-03 2010-04-27 Abhay Misra Sensitivity capacitive sensor
US20080197488A1 (en) * 2007-02-15 2008-08-21 John Trezza Bowed wafer hybridization compensation
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US20100176844A1 (en) * 2007-02-15 2010-07-15 Wyman Theodore J Ted Variable off-chip drive
US7969192B2 (en) 2007-02-15 2011-06-28 Cufer Asset Ltd. L.L.C. Variable off-chip drive
US20080200022A1 (en) * 2007-02-15 2008-08-21 John Callahan Post-seed deposition process
US7598163B2 (en) 2007-02-15 2009-10-06 John Callahan Post-seed deposition process
US20080197893A1 (en) * 2007-02-15 2008-08-21 Wyman Theodore J Ted Variable off-chip drive
US20080197508A1 (en) * 2007-02-16 2008-08-21 John Trezza Plated pillar package formation
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US20080242220A1 (en) * 2007-03-29 2008-10-02 Research In Motion Limited Method, system and mobile device for prioritizing a discovered device list
US20080245846A1 (en) * 2007-04-05 2008-10-09 John Trezza Heat cycle-able connection
US20080246145A1 (en) * 2007-04-05 2008-10-09 John Trezza Mobile binding in an electronic connection
US7748116B2 (en) 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US7850060B2 (en) 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US20090267219A1 (en) * 2007-04-23 2009-10-29 John Trezza Ultra-thin chip packaging
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
US7960210B2 (en) 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US7911066B2 (en) * 2007-08-29 2011-03-22 Agilent Technologies, Inc. Through-chip via interconnects for stacked integrated circuit structures
US20090057872A1 (en) * 2007-08-29 2009-03-05 Ehlers Eric R Through-Chip Via Interconnects for Stacked Integrated Circuit Structures
US20090161402A1 (en) * 2007-12-20 2009-06-25 Hakjune Oh Data storage and stackable configurations
US20090020855A1 (en) * 2007-12-20 2009-01-22 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US8399973B2 (en) 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US9183892B2 (en) 2007-12-20 2015-11-10 Conversant Intellectual Property Management Inc. Data storage and stackable chip configurations
US7791175B2 (en) * 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US7923370B2 (en) * 2007-12-20 2011-04-12 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US20100297812A1 (en) * 2007-12-20 2010-11-25 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US8383514B2 (en) 2007-12-20 2013-02-26 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US20110163423A1 (en) * 2007-12-20 2011-07-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US8415203B2 (en) * 2008-09-29 2013-04-09 Freescale Semiconductor, Inc. Method of forming a semiconductor package including two devices
US20100078808A1 (en) * 2008-09-29 2010-04-01 Burch Kenneth R Packaging having two devices and method of forming thereof
US20100213592A1 (en) * 2009-02-24 2010-08-26 International Business Machines Corporation Semiconductor Module, Terminal Strip, Method for Manufacturing Terminal Strip, and Method for Manufacturing Semiconductor Module
US20110068437A1 (en) * 2009-09-23 2011-03-24 Chi-Tsung Chiu Semiconductor Element Having a Conductive Via and Method for Making the Same and Package Having a Semiconductor Element with a Conductive Via
US8350361B2 (en) * 2009-09-23 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via
US8486829B2 (en) 2009-09-23 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via
US8946757B2 (en) * 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects

Also Published As

Publication number Publication date Type
US6410431B2 (en) 2002-06-25 grant
US6222276B1 (en) 2001-04-24 grant

Similar Documents

Publication Publication Date Title
US6268660B1 (en) Silicon packaging with through wafer interconnects
US4695870A (en) Inverted chip carrier
US4811082A (en) High performance integrated circuit packaging structure
US5475264A (en) Arrangement having multilevel wiring structure used for electronic component module
US7795721B2 (en) Semiconductor device and method for manufacturing the same
US6362525B1 (en) Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6218731B1 (en) Tiny ball grid array package
US5646067A (en) Method of bonding wafers having vias including conductive material
US5703747A (en) Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore
US5786630A (en) Multi-layer C4 flip-chip substrate
US6365975B1 (en) Chip with internal signal routing in external element
US5654221A (en) Method for forming semiconductor chip and electronic module with integrated surface interconnects/components
US6982869B2 (en) Folded interposer
US5618752A (en) Method of fabrication of surface mountable integrated circuits
US6172305B1 (en) Multilayer circuit board
US6762076B2 (en) Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6730540B2 (en) Clock distribution networks and conductive lines in semiconductor integrated circuits
US4722914A (en) Method of making a high density IC module assembly
US6806559B2 (en) Method and apparatus for connecting vertically stacked integrated circuit chips
US4695872A (en) High density micropackage for IC chips
US6472293B2 (en) Method for manufacturing an interconnect structure for stacked semiconductor device
US6570248B1 (en) Structure and method for a high-performance electronic packaging assembly
US6221769B1 (en) Method for integrated circuit power and electrical connections via through-wafer interconnects
US5157588A (en) Semiconductor package and manufacture thereof
US4875087A (en) Integrated circuit device having strip line structure therein

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11