US12422907B2 - Semiconductor package and thermal management method thereof - Google Patents

Semiconductor package and thermal management method thereof

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Publication number
US12422907B2
US12422907B2 US17/879,089 US202217879089A US12422907B2 US 12422907 B2 US12422907 B2 US 12422907B2 US 202217879089 A US202217879089 A US 202217879089A US 12422907 B2 US12422907 B2 US 12422907B2
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temperature
semiconductor chip
power
electrodes
upper semiconductor
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US20230121072A1 (en
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Jungpil LEE
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K1/00—Details of thermometers not specially adapted for particular types of thermometer
    • G01K1/16—Special arrangements for conducting heat from the object to the sensitive element
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/203—Cooling means for portable computers, e.g. for laptops
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • H01L23/34—
    • H01L23/481—
    • H01L25/0652—
    • H01L25/0657—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H01L2224/16148—
    • H01L2224/16227—
    • H01L2224/16238—
    • H01L2224/32225—
    • H01L2224/73204—
    • H01L2225/06513—
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    • H01L24/73—
    • H01L2924/1426—
    • H01L2924/1431—
    • H01L2924/1436—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present inventive concepts relate to a semiconductor package including stacked semiconductor chips and a thermal management method thereof.
  • the electronic devices include semiconductor devices such as working memories (e.g., DRAM), nonvolatile memories, and application processors (AP) to drive various application programs.
  • working memories e.g., DRAM
  • nonvolatile memories e.g., NAND
  • AP application processors
  • a thermal management of an electronic device is extremely essential to improve an overall performance and to reduce power consumption of the electronic device.
  • the thermal management may rely on an accurate measurement of temperature and a prompt appropriate control based on the measured temperature.
  • an unintended abrupt variation in temperature may significantly affect the performance and reliability of compact-sized electronic devices.
  • a function is required to maintain a minimum operation mode even when external temperature is remarkably increased. Accordingly, a technique is needed to exactly measure temperatures of specific portions and to effectively control the temperature in electronic devices such as mobile devices.
  • Some example embodiments of the present inventive concepts provide a semiconductor package with improved performance and reliability.
  • a semiconductor package may include an upper semiconductor chip; and a lower semiconductor chip connected via a plurality of through electrodes to the upper semiconductor chip.
  • the lower semiconductor chip may include at least one temperature sensor configured to sense a temperature of the upper semiconductor chip, a power control unit connected to the at least one temperature sensor, a power switching element connected to at least a first one of the plurality of through electrodes, and a clock control element connected to at least a second one of the plurality of through electrodes.
  • a semiconductor package may include a package substrate; a lower semiconductor chip on the package substrate; first and second upper semiconductor chips on the lower semiconductor chip and connected, via a plurality of through electrodes, to the lower semiconductor chip; and a molding layer on the package substrate and covering the lower semiconductor chip and the first and second upper semiconductor chips.
  • the lower semiconductor chip may include a plurality of upper pads and a plurality of lower pads, a plurality of temperature sensors configured to sense temperatures of the first and second upper semiconductor chips, a power control unit connected to the temperature sensors, a power switching element connected to at least a first one of the plurality of through electrodes and to one of the plurality of upper pads, and a clock control element connected to at least a second one of the plurality of through electrodes and to another of the plurality of upper pads.
  • a thermal management method of a semiconductor package including a lower semiconductor chip and an upper semiconductor chip connected, via a plurality of through electrodes, to the lower semiconductor chip.
  • the method may comprise measuring, by a temperature sensor corresponding to the upper semiconductor chip, a temperature of the upper semiconductor chip; classifying, by the lower semiconductor, a power control based on the temperature measured at the temperature sensor; and based on the classification of the power control, interrupting a power provided to the upper semiconductor chip via a first one of the plurality of through electrodes or adjusting a period of a clock signal provided to the upper semiconductor chip via a second one of the plurality of through electrodes.
  • FIG. 1 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 2 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 3 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 4 illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 5 illustrates an enlarged cross-sectional view partially showing a lower semiconductor chip of a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 6 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 7 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 8 illustrates a flow chart showing a thermal management method of a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 9 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 1 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • a semiconductor package 1000 may include a lower semiconductor chip 100 , first and second upper semiconductor chips 210 and 220 , a package substrate 500 , and a molding layer 510 .
  • the semiconductor package 1000 may have various intellectual property (IP) function blocks, such as central processing units (CPU) and/or graphics processing units (GPU), which are integrated thereon.
  • IP intellectual property
  • CPU central processing units
  • GPU graphics processing units
  • the semiconductor package 1000 may include semiconductor chips having various functions.
  • the lower semiconductor chip 100 may sense temperatures, e.g., when the first and second upper semiconductor chips 210 and 220 operate, and based on measured temperatures, may control whether power and clock signals are provided to the first and/or second upper semiconductor chips 210 and 220 via through electrodes TSV which will be discussed below.
  • the lower semiconductor chip 100 may include lower pads 101 , upper pads 105 , and through electrodes TSV that connect the lower pads 101 to the upper pads 105 .
  • the lower and upper pads 101 and 105 may include a power pad, a control signal pad, a data signal pad, a clock signal pad, and/or the like.
  • At least one of the first and second upper semiconductor chips 210 and 220 may be a flip-chip mounted on the lower semiconductor chip 100 .
  • the first and second upper semiconductor chips 210 and 220 are stacked on the lower semiconductor chip 100 , but the present inventive concepts are not limited thereto.
  • the lower semiconductor chip 100 may be provided thereon with four, six, eight, and/or more semiconductor chips.
  • the first and second upper semiconductor chips 210 and 220 may respectively include chip pads 211 and 221 .
  • the chip pads 211 and 221 may include a power pad, a control signal pad, a data signal pad, a clock signal pad, and/or the like.
  • the chip pads 211 and 221 may, for example, correspond to at least one of the lower and/or upper pads 101 and 105 .
  • the chip pads 211 and 221 of the first and second upper semiconductor chips 210 and 220 may be connected through connection bumps 250 to the upper pads 105 of the lower semiconductor chip 100 .
  • operating states of the first and second upper semiconductor chips 210 and 220 may be determined based on power and clock signals provided through the through electrodes TSV (e.g., from the lower semiconductor chip 100 ).
  • the power and clock signals provided to the first and second upper semiconductor chips 210 and 220 may be controlled based on operating temperatures of the first and second upper semiconductor chips 210 and 220 .
  • the first and second upper semiconductor chips 210 and 220 may each be a logic chip including a processor (such as microelectromechanical system (MEMS) device, optoelectronic device, central processing unit (CPU), graphic processing unit (GPU), mobile application, or digital signal processor (DSP)), and/or the first and second upper semiconductor chips 210 and 220 may each be a memory chip (such as dynamic random access memory (DRAM), static random access memory (SRAM), NAND Flash memory, or resistive random access memory (RRAM)).
  • a processor such as microelectromechanical system (MEMS) device, optoelectronic device, central processing unit (CPU), graphic processing unit (GPU), mobile application, or digital signal processor (DSP)
  • the first and second upper semiconductor chips 210 and 220 may each be a memory chip (such as dynamic random access memory (DRAM), static random access memory (SRAM), NAND Flash memory, or resistive random access memory (RRAM)).
  • DRAM dynamic random access memory
  • SRAM static random access
  • the package substrate 500 may be a printed circuit board, a flexible substrate, and/or a tape substrate.
  • the package substrate 500 may be at least one of a flexible printed circuit board, a rigid printed circuit board, and/or a combination thereof.
  • the package substrate 500 may have top and bottom surfaces that are opposite to each other, and may include lower bonding pads 511 , upper bonding pads 515 , and internal wiring lines 513 .
  • the internal wiring lines may be formed in the package substrate 500 .
  • the upper bonding pads 515 may be arranged on the top surface of the package substrate 500
  • the lower bonding pads 511 may be arranged on the bottom surface of the package substrate 500 .
  • the upper bonding pads 515 may be electrically connected through the internal wiring lines 513 to the lower bonding pads 511 .
  • the upper bonding pads 515 may be connected to the lower pads 101 of the lower semiconductor chip 100 through connection terminals 150 .
  • the connection terminals may be (and/or include) a conductive material, such as solder, and may be (and/or include) solder balls, solder pillars, and/or solder bumps.
  • the lower bonding pads 511 may be provided thereon with external bonding terminals 550 attached thereto.
  • a ball grid array (BGA) may be provided as the external bonding terminals 550 .
  • the external bonding terminals 550 may be electrically connected through the lower bonding pads 511 and the internal wiring lines 513 t the upper bonding pads 515 of the package substrate 500 .
  • the external bonding terminals 550 may be used to connect the semiconductor package 1000 with an external device (not illustrated).
  • FIG. 2 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 3 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • the lower semiconductor chip 100 may include a plurality of temperature sensors 111 and 113 , a power control unit 120 , a plurality of clock control elements 131 and 133 , a plurality of power switching elements 141 and 143 , and a plurality of through electrodes TSV 1 , TSV 2 , TSV 3 , and TSV 4 .
  • the plurality of temperature sensors 111 and 113 may sense temperatures of the first and second upper semiconductor chips 210 and 220 (which are disposed on the lower semiconductor chip 100 ), and the power control unit 120 may receive temperature signals measured at the temperature sensors 111 and 113 .
  • the temperature sensors 111 and 113 may include, for example, a thermo-electromotive force (or thermo-electric couple) sensor that senses an electromotive force changed based on temperature or a pyro-conductivity sensor that senses a magnitude of resistance and/or resistance changed based on temperature.
  • the temperature sensors 111 and 113 according to some embodiments are not limited thereto and may be variously changed.
  • the plurality of temperature sensors 111 and 113 may include a first temperature sensor 111 that corresponds to the first upper semiconductor chip 210 and a second temperature sensor 113 that corresponds to the second upper semiconductor chip 220 . As shown in FIG. 3 , the first and second temperature sensors 111 and 113 may be disposed on the lower semiconductor chip 100 to vertically overlap the first and second upper semiconductor chips 210 and 220 , respectively. Though only the first and second temperature sensors 111 and 113 are illustrated, for clarity, the embodiments are not limited thereto. For example, in some embodiments the number of the plurality of temperature sensors 111 and 113 may match the number of upper semiconductor chips 210 and 220 . In some embodiments the number of the plurality of temperature sensors 111 and 113 may be greater than the number of upper semiconductor chips 210 and 220 .
  • the power control unit 120 may be connected to the temperature sensors 111 and 113 .
  • the power control unit 120 may (e.g., through the connection) receive temperatures signals from the temperature sensors 111 and 113 . Based on temperatures of the first and second upper semiconductor chips 210 and 220 measured at the temperature sensors 111 and 113 , the power control unit 120 may control the power and clock signals provided to the first and second upper semiconductor chips 210 and 220 . For example, based on the temperatures measured at the temperature sensors 111 and 113 , the power control unit 120 may control electrical connections between the clock control elements 131 and 133 , the power switching elements 141 and 143 , and the through electrodes TSV 1 , TSV 2 , TSV 3 , and TSV 4 .
  • the power control unit 120 may control operations of the first and/or second upper semiconductor chips 210 and 220 whose temperatures are increased.
  • the power control unit 120 may compare temperature signals of the temperature sensors 111 and 113 with a reference temperature, and based on an increase in temperature and the degree of temperature increase, may interrupt a power provided to the first and second upper semiconductor chips 210 and 220 and/or may control the first and second upper semiconductor chips 210 and 220 to operate in idle modes, low power modes, and/or normal modes.
  • An operating state of each of the first and second upper semiconductor chips 210 and 220 may be classified into first, second, third, and fourth operating states based on a certain reference temperature.
  • the first operating state may be a state where a normal operation is impossible and/or detrimental
  • the second operating state may be a state where an idle state is maintained
  • the third operating state may be a state where an optimum performance is not achieved
  • the fourth operating state may be a state where a normal performance is achieved.
  • the power control unit 120 may be configured to turn off the power switching elements 141 and 143 .
  • a first reference temperature e.g., about 115° C.
  • the power control unit 120 may be configured to turn off the clock control elements 131 and 133 to interrupt clock signals that are provided through the clock control elements 131 and 133 to the first and second upper semiconductor chips 210 and 220 .
  • the power control unit 120 may be configured to adjust a period of clock that is output from the clock control elements 131 and 133 .
  • the clock control elements 131 and 133 may adjust a period of clock that is provided to the first and second upper semiconductor chips 210 and 220 .
  • the clock control elements 131 and 133 may divide and/or interrupt clock signals provided to the first and second upper semiconductor chips 210 and 220 , thereby controlling operations of the first and second upper semiconductor chips 210 and 220 .
  • the clock control elements 131 and 133 may be connected via the through electrodes TSV 1 and TSV 3 to the first and second upper semiconductor chips 210 and 220 .
  • the power switching elements 141 and 143 may provide and/or interrupt powers provided to the first and second upper semiconductor chips 210 and 220 .
  • the power switching elements 141 and 143 may be connected via the through electrodes TSV 1 and TSV 3 to the first and second upper semiconductor chips 210 and 220 .
  • the plurality of through electrodes TSV 1 , TSV 2 , TSV 3 , and TSV 4 may include first and second through electrodes TSV 1 and TSV 2 that are connected to the first upper semiconductor chip 210 , and may also include third and fourth through electrodes TSV 3 and TSV 4 that are connected to the second upper semiconductor chip 220 .
  • FIG. 4 illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • the lower semiconductor chip 100 may include a clock control element 130 and a power switching element 140 that are formed on a semiconductor substrate 110 .
  • the cross-sectional view illustrates a functional block representing the clock control element 130 and/or a power switching element 140 . Which of the clock control element 130 and/or a power switching element 140 is represented by the functional block may vary depending the position of the cross-section.
  • the clock control element 130 and the power switching element 140 may, respectively, correspond to the clock control element 131 and the power switching elements 141 (as illustrated in FIG. 2 ).
  • the semiconductor substrate 110 may have a first surface and a second surface. The first surface and the second surface may be opposite to each other.
  • the clock control element 130 and/or the power switching element 140 may be formed on the first surface of the semiconductor substrate 110 .
  • the lower pads 101 may be formed on the second surface of the semiconductor substrate 110 , and may be connected through the connection terminals 150 to the upper bonding pads 515 of the package substrate 500 .
  • the lower pads 101 may be provided with power signals or clock signals from the package substrate 500 .
  • Dielectric layers ILD may be provided on the first surface of the semiconductor substrate 110 .
  • the dielectric layers ILD may cover the clock control element 130 and/or the power switching element 140 .
  • the dielectric layers ILD may include wiring structures electrically connected to the clock control element 130 and/or the power switching element 140 .
  • the clock control element 130 and/or the power switching element 140 may be electrically connected between the through electrodes TSV and the upper pads 105 through the wiring structures.
  • the clock control element 130 may interrupt a clock signal and/or may change a period of clock signal provided to the upper semiconductor chip. For example, when a measured temperature is greater than a reference temperature, the clock signal may increase in period.
  • the dielectric layers ILD may be provided thereon with wiring patterns ICL.
  • the wiring patterns ICL may be electrically connected to the through electrodes TSV and the lower and upper pads 101 and 105 .
  • the wiring patterns ICL may include, for example, a conductive material (such as at least one metal and/or its alloy).
  • the wiring patterns ICL may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), and/or a combination thereof.
  • the through electrodes TSV may penetrate the dielectric layers ILD and the semiconductor substrate 110 to be coupled to the metal wiring patterns ICL.
  • the through electrodes TSV may each have a pillar shape, and may be spaced apart from the clock control element 130 and the power switching element 140 .
  • the through electrode TSV may include a barrier layer and a conductive (e.g., metal) layer.
  • the barrier layer may include, for example, a double layer (and/or a mixture layer other than the double layer).
  • the double (and/or mixture) layer may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or titanium/titanium nitride.
  • the barrier layer may reduce metal from diffusing from the through electrode TSV into the semiconductor substrate 110 .
  • the conductive layer may include, for example, a metal such as silver (Ag), gold (Au), aluminum (Al), tungsten (W), indium (In), and/or the like.
  • a sidewall dielectric layer may surround a sidewall of each of the through electrodes TSV, and may be interposed between the semiconductor substrate 110 and the through electrodes TSV.
  • the sidewall dielectric layer may include silicon oxide, silicon oxynitride, silicon nitride, and/or a combination thereof.
  • FIG. 5 illustrates an enlarged cross-sectional view partially showing a lower semiconductor chip of a semiconductor package according to some embodiments of the present inventive concepts.
  • the lower semiconductor chip 100 may include a semiconductor substrate 110 , power and/or clock gating transistors TR integrated on the semiconductor substrate 110 , and metal wiring patterns ICL connected to the power and/or clock gating transistors TR.
  • the semiconductor substrate 110 may be one of a semiconductor material (e.g., silicon wafer), a dielectric material (e.g., glass), a semiconductor covered with a dielectric material, and a conductor.
  • the semiconductor substrate 110 may be a silicon wafer having a first conductivity type.
  • the semiconductor substrate 110 may have a first surface and a second surface that are opposite to each other.
  • the power and/or clock gating transistors TR may be formed on the first surface of the semiconductor substrate 110 .
  • the lower pads 101 may be formed on the second surface of the semiconductor substrate 110 .
  • the power and/or clock gating transistors TR may include a gate electrode on the semiconductor substrate 110 , a gate dielectric layer between the gate electrode and the semiconductor substrate 110 , and source/drain impurity regions in the semiconductor substrate 110 on opposite sides of the gate electrode.
  • power gating transistors may be power gating switches to provide upper semiconductor chips with power.
  • a first terminal of the power gating transistor may be connected to at least one of the upper pads 105
  • a second terminal of the power gating transistor may be connected to at least one of the through electrodes TSV.
  • the power gating transistor may be provided with a power voltage through the lower pad 101 and the through electrode TSV.
  • clock gating transistor may interrupt clock signals and/or adjust a period of clock signal provided to upper semiconductor chips.
  • a first terminal of the clock gating transistor TR may be connected to at least one of the upper pads 105
  • a second terminal of the clock gating transistor TR may be connected to at least one of the through electrodes TSV.
  • the clock gating transistor TR may be provided with a clock signal through the lower pad 101 and the through electrode TSV.
  • the clock gating transistor TR may increase a period of clock signal and/or may interrupt a clock signal.
  • the power and/or clock gating transistors TR may be formed of PMOS or NMOS transistors.
  • the semiconductor substrate 110 may be provided on its first surface with dielectric layers ILD that cover the power and/or clock gating transistors TR, and passivation layers PSV may be provided on an uppermost dielectric layer ILD and the second surface of the semiconductor substrate 110 .
  • the passivation layers PSV may expose the lower pads 101 and the upper pads 105 .
  • the through electrodes TSV may penetrate the dielectric layers ILD and the semiconductor substrate 110 to be coupled to the metal wiring patterns ICL.
  • the metal wiring patterns ICL may electrically connect the through electrodes TSV to the second terminals of the power or clock gating transistors TR.
  • FIG. 6 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
  • FIG. 7 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • the same technical features as those of the embodiments discussed above may be omitted in the interest of brevity of description.
  • each of the first and second upper semiconductor chips 210 and 220 may include a plurality of regions R 1 , R 2 , R 3 , and R 4 .
  • each of the first and second upper semiconductor chips 210 and 220 may include first, second, third, and fourth regions R 1 , R 2 , R 3 , and R 4 .
  • the lower semiconductor chip 100 may have temperature sensors 111 a to 111 d and 113 a to 113 d that are disposed to correspond to the plurality of regions R 1 , R 2 , R 3 , and R 4 of the first and second upper semiconductor chips 210 and 220 .
  • first, second, third, and fourth temperature sensors 111 a to 111 d and 113 a to 113 d may vertically overlap the first, second, third, and fourth regions R 1 , R 2 , R 3 , and R 4 of the first and second upper semiconductor chips 210 and 220 .
  • the first temperature sensors 111 a and 113 a may be disposed to correspond to the first regions R 1 of the first and second upper semiconductor chips 210 and 220
  • the second temperature sensors 111 b and 113 b may be disposed to correspond to the second regions R 2 of the first and second upper semiconductor chips 210 and 220
  • the third temperature sensors 111 c and 113 c may be disposed to correspond to the third regions R 3 of the first and second upper semiconductor chips 210 and 220
  • the fourth temperature sensors 111 d and 113 d may be disposed to correspond to the fourth regions R 4 of the first and second upper semiconductor chips 210 and 220 .
  • the temperature sensors 111 a to 111 d and 113 a to 113 d are individually provided for the regions R 1 , R 2 , R 3 , and R 4 of the first and second upper semiconductor chips 210 and 220 , the temperature sensors 111 a to 111 d and 113 a to 113 d may detect specific areas of the first and second upper semiconductor chips 210 and 220 , in which specific areas there are increased in operating temperatures.
  • FIG. 8 illustrates a flow chart showing a thermal management method of a semiconductor package according to some embodiments of the present inventive concepts.
  • a temperature of the semiconductor package may be checked in real-time or periodically in order to control temperatures of upper semiconductor chips or first and second upper semiconductor chips (S 110 ).
  • a state of the semiconductor package may be classified into a plurality of states (e.g., first, second, third, and/or fourth states) based on a certain criterion.
  • the first state may be a state where an operation (e.g., a normal operation) is impossible and/or detrimental
  • the second state may be a state where an idle state is maintained
  • the third state may be a state where an optimum performance is not achieved
  • the fourth state may be a state where a normal performance is achieved.
  • the power control unit 120 may search the temperature sensors 111 and 113 of the package substrate (S 120 ).
  • the temperature sensors 111 and 113 may be searched such that the upper semiconductor chip under increased temperature may be controlled its temperature, and the upper semiconductor chip under normal temperature may be possible to operate.
  • the search of the temperature sensors 111 and 113 may include determining a temperature at the temperature sensors 111 and 113 based on a temperature signal received from the temperature sensors 111 and 113 and/or requesting a temperature signal from the temperature sensors 111 and 113 .
  • the results of the search of the temperature sensor S 120 may be used to ascertain whether there are increased temperatures of the upper semiconductor chips (e.g., the first and second upper semiconductor chips) of the semiconductor package. For example, it may be determined whether a measurement temperature Tj sensed at a temperature sensor is a normal temperature or not (S 130 ).
  • the power control unit 120 may allow the upper semiconductor chip to maintain its normal operating state (S 160 ). Afterwards, there may be maintained a standby state until a temperature check period is reached (S 170 ). Then, the temperature-sensor search step may be performed again (S 120 ).
  • the power control unit 120 may control the clock control elements 131 and 133 and the power switching elements 141 and 143 .
  • the degree of power control may depend on the measurement temperature Tj.
  • the power control unit 120 may determine whether the measurement temperature Tj is greater than a first reference temperature (e.g., about 115° C.) (pers).
  • a first reference temperature e.g., about 115° C.
  • the upper semiconductor chips may be controlled to reduce an operating temperature at one or more of the upper semiconductor chips and/or an operating temperature at a specific region of one or more of the upper semiconductor chips (S 131 ).
  • a thermal radiation region may be searched (S 141 ). Afterwards, the power switching elements 141 and 143 of the thermal radiation region may interrupt power supply to the thermal radiation region (S 151 ).
  • shut down state of the upper semiconductor chip under increased temperature or of a specific region of the upper semiconductor chip (S 161 ). There may be maintained a standby state until a temperature of the thermal radiation region is reduced to a normal temperature (S 171 ). After the temperature has returned to normal, the power switching elements 141 and 143 of the thermal radiation region may reinstate power to the thermal radiation region. After that, the temperature-sensor search step may be performed again (S 120 ).
  • the power control unit 120 may determine whether or not the measurement temperature Tj is greater than a second reference temperature (e.g., about 95° C.) (S 132 ).
  • a second reference temperature e.g., about 95° C.
  • a thermal radiation region may be searched (S 142 ).
  • the clock control elements 131 and 133 of the thermal radiation region may interrupt the supply of clock signals to the thermal radiation region (S 152 ). Then, there may occur an idle state of the upper semiconductor chip under increased temperature and/or of a specific region of the upper semiconductor chip (S 162 ).
  • the power control unit 120 may determine whether the measurement temperature Tj is greater than a third reference temperature (e.g., about 85° C.) (S 133 ).
  • a thermal radiation region may be searched (S 143 ).
  • the clock control elements 131 and 132 may divide a period of clock signal, and the divided clock signal may be provided to the upper semiconductor chip and/or the thermal radiation region (S 153 ). Then, there may occur a state in which the upper semiconductor chip under increased temperature or the specific region is operated at a low power (S 163 ).
  • a clock or power may be controlled based on measurement temperatures of upper semiconductor chips included in a semiconductor package, and thus it may be possible to limit an operation of a region or chip under increased temperature and to secure an operation of a region or chip under normal temperature. Consequently, the semiconductor package may improve in performance, reliability, and/or durability.
  • FIG. 9 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
  • a semiconductor package 1000 may include a package substrate 500 , a lower semiconductor chip 100 mounted on the package substrate 500 , and first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 that are vertically stacked on the lower semiconductor chip 100 .
  • the package substrate 500 may have top and bottom surfaces, and may include lower bonding pads 511 , upper bonding pads 515 , and internal wiring lines 513 .
  • the upper bonding pads 515 may be arranged on the top surface of the package substrate 500
  • the lower bonding pads 511 may be arranged on the bottom surface of the package substrate 500 .
  • the upper bonding pads 515 may be electrically connected through the internal wiring lines 513 to the lower bonding pads 511 .
  • the lower bonding pads 511 may be attached thereon with external bonding terminals 550 such as solder balls or solder bumps.
  • the lower semiconductor chip 100 may be a flip-chip mounted on the package substrate 500 .
  • the lower semiconductor chip 100 may be a logic chip and/or a controller chip.
  • the lower semiconductor chip 100 may include a plurality of through electrodes TSV, and the through electrodes TSV may be coupled to the package substrate 500 through connection terminals 150 such as solder bumps.
  • the lower semiconductor chip 100 may be electrically connected via the through electrodes TSV to the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 .
  • the lower semiconductor chip 100 may include a plurality of temperature sensors 111 and 113 , the power control unit 120 , clock control elements 131 and 133 , power switching elements 141 and 143 , and through electrodes TSV.
  • the temperature sensors 111 and 113 of the lower semiconductor chip 100 may sense operating temperatures of the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 . Based on temperatures measured at the temperature sensors 111 and 113 , the lower semiconductor chip 100 may control whether clock signals and power signals are provided via the through electrodes TSV to the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 .
  • Each of the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 may include lower and upper pads (not designated by reference numerals) and a plurality of through electrodes TSV, and may be electrically connected through the through electrodes TSV to the lower semiconductor chip 100 .
  • the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 may be logic chips or memory chips.
  • the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 may be electrically connected through connection bumps 250 .
  • An adhesion layer may be correspondingly provided between the lower semiconductor chip 100 and the first, second, third, and fourth upper semiconductor chips 210 , 220 , 230 , and 240 .
  • the adhesion layer may be, for example, a polymer tape and/or a resin including a dielectric material.
  • the adhesion layer may be interposed between the connection bumps 250 , and may prevent the occurrence of electrical short between the connection bumps 250 .
  • the package substrate 500 may be provided thereon with a molding layer 510 that covers sidewalls of the lower and upper semiconductor chips 100 , 210 , 220 , 230 , and 240 .
  • the molding layer 510 may have a top surface coplanar with that of the fourth upper semiconductor chip 240 .
  • a semiconductor package in which semiconductor chips are stacked may be configured to control clocks and powers provided via through electrodes, based on measurement temperatures of upper semiconductor chips. Therefore, it may be possible to limit an operation of the upper semiconductor chip or its region under increased temperature and to secure an operation of the upper semiconductor chip or its specific region under normal temperature. Consequently, the semiconductor package may improve in performance and reliability.

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Abstract

Disclosed are semiconductor packages and thermal management methods thereof. The semiconductor package includes an upper semiconductor chip; and a lower semiconductor chip connected via a plurality of through electrodes to the upper semiconductor chip. The lower semiconductor chip may include at least one temperature sensor configured to sense a temperature of the upper semiconductor chip, a power control unit connected to the at least one temperature sensor, a power switching element connected to at least a first one of the plurality of through electrodes, and a clock control element connected to at least a second one of the plurality of through electrodes.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2021-0138940 filed on Oct. 19, 2021 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND
The present inventive concepts relate to a semiconductor package including stacked semiconductor chips and a thermal management method thereof.
In recent years, the use of electronic devices such as smart phones, tablet PCs, digital cameras, MP3 players, and personal digital assistants (PDAs) has rapidly increased. Such electronic devices necessitate a high-speed processor due to multimedia processing and an increase in throughput of various types of data, and various application programs are executed in the electronic devices.
The electronic devices include semiconductor devices such as working memories (e.g., DRAM), nonvolatile memories, and application processors (AP) to drive various application programs. With an increase in demand for high performance, e.g., at mobile environments, it is increasingly expected to increase integration and driving frequencies of the semiconductor devices.
A thermal management of an electronic device is extremely essential to improve an overall performance and to reduce power consumption of the electronic device. The thermal management may rely on an accurate measurement of temperature and a prompt appropriate control based on the measured temperature. In particular, an unintended abrupt variation in temperature may significantly affect the performance and reliability of compact-sized electronic devices. For example, a function is required to maintain a minimum operation mode even when external temperature is remarkably increased. Accordingly, a technique is needed to exactly measure temperatures of specific portions and to effectively control the temperature in electronic devices such as mobile devices.
SUMMARY
Some example embodiments of the present inventive concepts provide a semiconductor package with improved performance and reliability.
The object of the present inventive concepts is not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description.
According to some embodiments of the present inventive concepts, a semiconductor package may include an upper semiconductor chip; and a lower semiconductor chip connected via a plurality of through electrodes to the upper semiconductor chip. The lower semiconductor chip may include at least one temperature sensor configured to sense a temperature of the upper semiconductor chip, a power control unit connected to the at least one temperature sensor, a power switching element connected to at least a first one of the plurality of through electrodes, and a clock control element connected to at least a second one of the plurality of through electrodes.
According to some embodiments of the present inventive concepts, a semiconductor package may include a package substrate; a lower semiconductor chip on the package substrate; first and second upper semiconductor chips on the lower semiconductor chip and connected, via a plurality of through electrodes, to the lower semiconductor chip; and a molding layer on the package substrate and covering the lower semiconductor chip and the first and second upper semiconductor chips. The lower semiconductor chip may include a plurality of upper pads and a plurality of lower pads, a plurality of temperature sensors configured to sense temperatures of the first and second upper semiconductor chips, a power control unit connected to the temperature sensors, a power switching element connected to at least a first one of the plurality of through electrodes and to one of the plurality of upper pads, and a clock control element connected to at least a second one of the plurality of through electrodes and to another of the plurality of upper pads.
According to some embodiments of the present inventive concepts, a thermal management method of a semiconductor package including a lower semiconductor chip and an upper semiconductor chip connected, via a plurality of through electrodes, to the lower semiconductor chip. The method may comprise measuring, by a temperature sensor corresponding to the upper semiconductor chip, a temperature of the upper semiconductor chip; classifying, by the lower semiconductor, a power control based on the temperature measured at the temperature sensor; and based on the classification of the power control, interrupting a power provided to the upper semiconductor chip via a first one of the plurality of through electrodes or adjusting a period of a clock signal provided to the upper semiconductor chip via a second one of the plurality of through electrodes.
Details of some example embodiments are included in the description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 2 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 3 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 4 illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 5 illustrates an enlarged cross-sectional view partially showing a lower semiconductor chip of a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 6 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 7 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 8 illustrates a flow chart showing a thermal management method of a semiconductor package according to some embodiments of the present inventive concepts.
FIG. 9 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
 DETAIL PARTED DESCRIPTION OF EMBODIMENTS
It will be hereinafter discussed a semiconductor package and a thermal management method thereof according to some example embodiments of the present inventive concepts in conjunction with the accompanying drawings. The thickness of layers, films, panels, regions, etc., may be exaggerated for clarity in the drawings, and like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
FIG. 1 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIG. 1 , a semiconductor package 1000 may include a lower semiconductor chip 100, first and second upper semiconductor chips 210 and 220, a package substrate 500, and a molding layer 510.
The semiconductor package 1000 may have various intellectual property (IP) function blocks, such as central processing units (CPU) and/or graphics processing units (GPU), which are integrated thereon. For example, the semiconductor package 1000 may include semiconductor chips having various functions.
The lower semiconductor chip 100 may sense temperatures, e.g., when the first and second upper semiconductor chips 210 and 220 operate, and based on measured temperatures, may control whether power and clock signals are provided to the first and/or second upper semiconductor chips 210 and 220 via through electrodes TSV which will be discussed below.
The lower semiconductor chip 100 may include lower pads 101, upper pads 105, and through electrodes TSV that connect the lower pads 101 to the upper pads 105. The lower and upper pads 101 and 105 may include a power pad, a control signal pad, a data signal pad, a clock signal pad, and/or the like.
At least one of the first and second upper semiconductor chips 210 and 220 may be a flip-chip mounted on the lower semiconductor chip 100. In some embodiments, the first and second upper semiconductor chips 210 and 220 are stacked on the lower semiconductor chip 100, but the present inventive concepts are not limited thereto. For example, the lower semiconductor chip 100 may be provided thereon with four, six, eight, and/or more semiconductor chips.
In some embodiments, the first and second upper semiconductor chips 210 and 220 may respectively include chip pads 211 and 221. For the first and second upper semiconductor chips 210 and 220, the chip pads 211 and 221 may include a power pad, a control signal pad, a data signal pad, a clock signal pad, and/or the like. The chip pads 211 and 221 may, for example, correspond to at least one of the lower and/or upper pads 101 and 105. The chip pads 211 and 221 of the first and second upper semiconductor chips 210 and 220 may be connected through connection bumps 250 to the upper pads 105 of the lower semiconductor chip 100.
According to some embodiments, operating states of the first and second upper semiconductor chips 210 and 220 may be determined based on power and clock signals provided through the through electrodes TSV (e.g., from the lower semiconductor chip 100). For example, the power and clock signals provided to the first and second upper semiconductor chips 210 and 220 may be controlled based on operating temperatures of the first and second upper semiconductor chips 210 and 220.
The first and second upper semiconductor chips 210 and 220 may each be a logic chip including a processor (such as microelectromechanical system (MEMS) device, optoelectronic device, central processing unit (CPU), graphic processing unit (GPU), mobile application, or digital signal processor (DSP)), and/or the first and second upper semiconductor chips 210 and 220 may each be a memory chip (such as dynamic random access memory (DRAM), static random access memory (SRAM), NAND Flash memory, or resistive random access memory (RRAM)). In some example embodiments, one of the first and second upper semiconductor chips 210 and 220 may be a logic chip and the other a memory chip.
In some embodiments, the package substrate 500 may be a printed circuit board, a flexible substrate, and/or a tape substrate. For example, the package substrate 500 may be at least one of a flexible printed circuit board, a rigid printed circuit board, and/or a combination thereof.
For example, the package substrate 500 may have top and bottom surfaces that are opposite to each other, and may include lower bonding pads 511, upper bonding pads 515, and internal wiring lines 513. The internal wiring lines may be formed in the package substrate 500. The upper bonding pads 515 may be arranged on the top surface of the package substrate 500, and the lower bonding pads 511 may be arranged on the bottom surface of the package substrate 500. The upper bonding pads 515 may be electrically connected through the internal wiring lines 513 to the lower bonding pads 511.
The upper bonding pads 515 may be connected to the lower pads 101 of the lower semiconductor chip 100 through connection terminals 150. The connection terminals may be (and/or include) a conductive material, such as solder, and may be (and/or include) solder balls, solder pillars, and/or solder bumps.
The lower bonding pads 511 may be provided thereon with external bonding terminals 550 attached thereto. A ball grid array (BGA) may be provided as the external bonding terminals 550. The external bonding terminals 550 may be electrically connected through the lower bonding pads 511 and the internal wiring lines 513 t the upper bonding pads 515 of the package substrate 500. The external bonding terminals 550 may be used to connect the semiconductor package 1000 with an external device (not illustrated).
FIG. 2 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts. FIG. 3 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIGS. 2 and 3 , the lower semiconductor chip 100 may include a plurality of temperature sensors 111 and 113, a power control unit 120, a plurality of clock control elements 131 and 133, a plurality of power switching elements 141 and 143, and a plurality of through electrodes TSV1, TSV2, TSV3, and TSV4.
The plurality of temperature sensors 111 and 113 may sense temperatures of the first and second upper semiconductor chips 210 and 220 (which are disposed on the lower semiconductor chip 100), and the power control unit 120 may receive temperature signals measured at the temperature sensors 111 and 113. The temperature sensors 111 and 113 may include, for example, a thermo-electromotive force (or thermo-electric couple) sensor that senses an electromotive force changed based on temperature or a pyro-conductivity sensor that senses a magnitude of resistance and/or resistance changed based on temperature. However, the temperature sensors 111 and 113 according to some embodiments are not limited thereto and may be variously changed.
In some embodiment, the plurality of temperature sensors 111 and 113 may include a first temperature sensor 111 that corresponds to the first upper semiconductor chip 210 and a second temperature sensor 113 that corresponds to the second upper semiconductor chip 220. As shown in FIG. 3 , the first and second temperature sensors 111 and 113 may be disposed on the lower semiconductor chip 100 to vertically overlap the first and second upper semiconductor chips 210 and 220, respectively. Though only the first and second temperature sensors 111 and 113 are illustrated, for clarity, the embodiments are not limited thereto. For example, in some embodiments the number of the plurality of temperature sensors 111 and 113 may match the number of upper semiconductor chips 210 and 220. In some embodiments the number of the plurality of temperature sensors 111 and 113 may be greater than the number of upper semiconductor chips 210 and 220.
The power control unit 120 may be connected to the temperature sensors 111 and 113. The power control unit 120 may (e.g., through the connection) receive temperatures signals from the temperature sensors 111 and 113. Based on temperatures of the first and second upper semiconductor chips 210 and 220 measured at the temperature sensors 111 and 113, the power control unit 120 may control the power and clock signals provided to the first and second upper semiconductor chips 210 and 220. For example, based on the temperatures measured at the temperature sensors 111 and 113, the power control unit 120 may control electrical connections between the clock control elements 131 and 133, the power switching elements 141 and 143, and the through electrodes TSV1, TSV2, TSV3, and TSV4.
Thereby, the power control unit 120 may control operations of the first and/or second upper semiconductor chips 210 and 220 whose temperatures are increased. The power control unit 120 may compare temperature signals of the temperature sensors 111 and 113 with a reference temperature, and based on an increase in temperature and the degree of temperature increase, may interrupt a power provided to the first and second upper semiconductor chips 210 and 220 and/or may control the first and second upper semiconductor chips 210 and 220 to operate in idle modes, low power modes, and/or normal modes.
An operating state of each of the first and second upper semiconductor chips 210 and 220 may be classified into first, second, third, and fourth operating states based on a certain reference temperature. For example, the first operating state may be a state where a normal operation is impossible and/or detrimental, the second operating state may be a state where an idle state is maintained, the third operating state may be a state where an optimum performance is not achieved, and the fourth operating state may be a state where a normal performance is achieved.
When temperatures measured at the temperature sensors 111 and 113 are equal to or greater than about a first reference temperature (e.g., about 115° C.), the power control unit 120 may be configured to turn off the power switching elements 141 and 143. When temperatures measured at the temperature sensors 111 and 113 are equal to or greater than about a second reference temperature (e.g., about 95° C.) and less than the first reference temperature, the power control unit 120 may be configured to turn off the clock control elements 131 and 133 to interrupt clock signals that are provided through the clock control elements 131 and 133 to the first and second upper semiconductor chips 210 and 220.
When temperatures measured at the temperature sensors 111 and 113 are equal to or greater than about a third reference temperature (e.g., about 85° C.) and less than the second reference temperature, the power control unit 120 may be configured to adjust a period of clock that is output from the clock control elements 131 and 133.
Based on temperatures measured at the temperature sensors 111 and 113, the clock control elements 131 and 133 may adjust a period of clock that is provided to the first and second upper semiconductor chips 210 and 220. The clock control elements 131 and 133 may divide and/or interrupt clock signals provided to the first and second upper semiconductor chips 210 and 220, thereby controlling operations of the first and second upper semiconductor chips 210 and 220. The clock control elements 131 and 133 may be connected via the through electrodes TSV1 and TSV3 to the first and second upper semiconductor chips 210 and 220.
The power switching elements 141 and 143 may provide and/or interrupt powers provided to the first and second upper semiconductor chips 210 and 220. The power switching elements 141 and 143 may be connected via the through electrodes TSV1 and TSV3 to the first and second upper semiconductor chips 210 and 220.
The plurality of through electrodes TSV1, TSV2, TSV3, and TSV4 may include first and second through electrodes TSV1 and TSV2 that are connected to the first upper semiconductor chip 210, and may also include third and fourth through electrodes TSV3 and TSV4 that are connected to the second upper semiconductor chip 220.
FIG. 4 illustrates an enlarged cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIG. 4 , the lower semiconductor chip 100 may include a clock control element 130 and a power switching element 140 that are formed on a semiconductor substrate 110. For simplicity, the cross-sectional view illustrates a functional block representing the clock control element 130 and/or a power switching element 140. Which of the clock control element 130 and/or a power switching element 140 is represented by the functional block may vary depending the position of the cross-section. The clock control element 130 and the power switching element 140 may, respectively, correspond to the clock control element 131 and the power switching elements 141 (as illustrated in FIG. 2 ).
The semiconductor substrate 110 may have a first surface and a second surface. The first surface and the second surface may be opposite to each other. The clock control element 130 and/or the power switching element 140 may be formed on the first surface of the semiconductor substrate 110. The lower pads 101 may be formed on the second surface of the semiconductor substrate 110, and may be connected through the connection terminals 150 to the upper bonding pads 515 of the package substrate 500. The lower pads 101 may be provided with power signals or clock signals from the package substrate 500.
Dielectric layers ILD may be provided on the first surface of the semiconductor substrate 110. The dielectric layers ILD may cover the clock control element 130 and/or the power switching element 140. The dielectric layers ILD may include wiring structures electrically connected to the clock control element 130 and/or the power switching element 140. The clock control element 130 and/or the power switching element 140 may be electrically connected between the through electrodes TSV and the upper pads 105 through the wiring structures.
Based on an operating temperature of an upper semiconductor chip measured at temperature sensors, the clock control element 130 may interrupt a clock signal and/or may change a period of clock signal provided to the upper semiconductor chip. For example, when a measured temperature is greater than a reference temperature, the clock signal may increase in period.
The dielectric layers ILD may be provided thereon with wiring patterns ICL. The wiring patterns ICL may be electrically connected to the through electrodes TSV and the lower and upper pads 101 and 105. The wiring patterns ICL may include, for example, a conductive material (such as at least one metal and/or its alloy). For example, the wiring patterns ICL may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), and/or a combination thereof.
The through electrodes TSV may penetrate the dielectric layers ILD and the semiconductor substrate 110 to be coupled to the metal wiring patterns ICL. The through electrodes TSV may each have a pillar shape, and may be spaced apart from the clock control element 130 and the power switching element 140. The through electrode TSV may include a barrier layer and a conductive (e.g., metal) layer. The barrier layer may include, for example, a double layer (and/or a mixture layer other than the double layer). The double (and/or mixture) layer may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or titanium/titanium nitride. The barrier layer may reduce metal from diffusing from the through electrode TSV into the semiconductor substrate 110. The conductive layer may include, for example, a metal such as silver (Ag), gold (Au), aluminum (Al), tungsten (W), indium (In), and/or the like. A sidewall dielectric layer may surround a sidewall of each of the through electrodes TSV, and may be interposed between the semiconductor substrate 110 and the through electrodes TSV. For example, the sidewall dielectric layer may include silicon oxide, silicon oxynitride, silicon nitride, and/or a combination thereof.
FIG. 5 illustrates an enlarged cross-sectional view partially showing a lower semiconductor chip of a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIG. 5 , the lower semiconductor chip 100 may include a semiconductor substrate 110, power and/or clock gating transistors TR integrated on the semiconductor substrate 110, and metal wiring patterns ICL connected to the power and/or clock gating transistors TR.
The semiconductor substrate 110 may be one of a semiconductor material (e.g., silicon wafer), a dielectric material (e.g., glass), a semiconductor covered with a dielectric material, and a conductor. For example, the semiconductor substrate 110 may be a silicon wafer having a first conductivity type.
The semiconductor substrate 110 may have a first surface and a second surface that are opposite to each other. The power and/or clock gating transistors TR may be formed on the first surface of the semiconductor substrate 110. The lower pads 101 may be formed on the second surface of the semiconductor substrate 110.
The power and/or clock gating transistors TR may include a gate electrode on the semiconductor substrate 110, a gate dielectric layer between the gate electrode and the semiconductor substrate 110, and source/drain impurity regions in the semiconductor substrate 110 on opposite sides of the gate electrode.
Herein, power gating transistors may be power gating switches to provide upper semiconductor chips with power. A first terminal of the power gating transistor may be connected to at least one of the upper pads 105, and a second terminal of the power gating transistor may be connected to at least one of the through electrodes TSV. The power gating transistor may be provided with a power voltage through the lower pad 101 and the through electrode TSV.
Herein, clock gating transistor may interrupt clock signals and/or adjust a period of clock signal provided to upper semiconductor chips. A first terminal of the clock gating transistor TR may be connected to at least one of the upper pads 105, and a second terminal of the clock gating transistor TR may be connected to at least one of the through electrodes TSV. The clock gating transistor TR may be provided with a clock signal through the lower pad 101 and the through electrode TSV. The clock gating transistor TR may increase a period of clock signal and/or may interrupt a clock signal.
In some embodiments, the power and/or clock gating transistors TR may be formed of PMOS or NMOS transistors.
The semiconductor substrate 110 may be provided on its first surface with dielectric layers ILD that cover the power and/or clock gating transistors TR, and passivation layers PSV may be provided on an uppermost dielectric layer ILD and the second surface of the semiconductor substrate 110. The passivation layers PSV may expose the lower pads 101 and the upper pads 105.
The through electrodes TSV may penetrate the dielectric layers ILD and the semiconductor substrate 110 to be coupled to the metal wiring patterns ICL. The metal wiring patterns ICL may electrically connect the through electrodes TSV to the second terminals of the power or clock gating transistors TR.
FIG. 6 illustrates a simplified block diagram showing a semiconductor package according to some embodiments of the present inventive concepts. FIG. 7 illustrates a simplified perspective view showing a semiconductor package according to some embodiments of the present inventive concepts. The same technical features as those of the embodiments discussed above may be omitted in the interest of brevity of description.
Referring to FIGS. 6 and 7 , each of the first and second upper semiconductor chips 210 and 220 may include a plurality of regions R1, R2, R3, and R4. For example, each of the first and second upper semiconductor chips 210 and 220 may include first, second, third, and fourth regions R1, R2, R3, and R4.
The lower semiconductor chip 100 may have temperature sensors 111 a to 111 d and 113 a to 113 d that are disposed to correspond to the plurality of regions R1, R2, R3, and R4 of the first and second upper semiconductor chips 210 and 220. For example, first, second, third, and fourth temperature sensors 111 a to 111 d and 113 a to 113 d may vertically overlap the first, second, third, and fourth regions R1, R2, R3, and R4 of the first and second upper semiconductor chips 210 and 220. For example, the first temperature sensors 111 a and 113 a may be disposed to correspond to the first regions R1 of the first and second upper semiconductor chips 210 and 220, and the second temperature sensors 111 b and 113 b may be disposed to correspond to the second regions R2 of the first and second upper semiconductor chips 210 and 220. The third temperature sensors 111 c and 113 c may be disposed to correspond to the third regions R3 of the first and second upper semiconductor chips 210 and 220, and the fourth temperature sensors 111 d and 113 d may be disposed to correspond to the fourth regions R4 of the first and second upper semiconductor chips 210 and 220.
As the temperature sensors 111 a to 111 d and 113 a to 113 d are individually provided for the regions R1, R2, R3, and R4 of the first and second upper semiconductor chips 210 and 220, the temperature sensors 111 a to 111 d and 113 a to 113 d may detect specific areas of the first and second upper semiconductor chips 210 and 220, in which specific areas there are increased in operating temperatures.
FIG. 8 illustrates a flow chart showing a thermal management method of a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIGS. 1, 2, and 8 , when a semiconductor package operates, a temperature of the semiconductor package may be checked in real-time or periodically in order to control temperatures of upper semiconductor chips or first and second upper semiconductor chips (S110).
A state of the semiconductor package may be classified into a plurality of states (e.g., first, second, third, and/or fourth states) based on a certain criterion. For example, the first state may be a state where an operation (e.g., a normal operation) is impossible and/or detrimental, the second state may be a state where an idle state is maintained, the third state may be a state where an optimum performance is not achieved, and/or the fourth state may be a state where a normal performance is achieved.
The power control unit 120 may search the temperature sensors 111 and 113 of the package substrate (S120). The temperature sensors 111 and 113 may be searched such that the upper semiconductor chip under increased temperature may be controlled its temperature, and the upper semiconductor chip under normal temperature may be possible to operate. In some example embodiments, the search of the temperature sensors 111 and 113 may include determining a temperature at the temperature sensors 111 and 113 based on a temperature signal received from the temperature sensors 111 and 113 and/or requesting a temperature signal from the temperature sensors 111 and 113.
The results of the search of the temperature sensor S120 may be used to ascertain whether there are increased temperatures of the upper semiconductor chips (e.g., the first and second upper semiconductor chips) of the semiconductor package. For example, it may be determined whether a measurement temperature Tj sensed at a temperature sensor is a normal temperature or not (S130).
When the measurement temperature Tj is a normal temperature, the power control unit 120 may allow the upper semiconductor chip to maintain its normal operating state (S160). Afterwards, there may be maintained a standby state until a temperature check period is reached (S170). Then, the temperature-sensor search step may be performed again (S120).
When the measurement temperature Tj is equal to or greater than a normal temperature, based on the measurement temperature Tj, the power control unit 120 may control the clock control elements 131 and 133 and the power switching elements 141 and 143. The degree of power control may depend on the measurement temperature Tj.
For example, the power control unit 120 may determine whether the measurement temperature Tj is greater than a first reference temperature (e.g., about 115° C.) (pers). When the measurement temperature Tj is greater than the first reference temperature, the upper semiconductor chips may be controlled to reduce an operating temperature at one or more of the upper semiconductor chips and/or an operating temperature at a specific region of one or more of the upper semiconductor chips (S131). When the measurement temperature Tj is the same as or greater than the first reference temperature, a thermal radiation region may be searched (S141). Afterwards, the power switching elements 141 and 143 of the thermal radiation region may interrupt power supply to the thermal radiation region (S151). Then, there may occur a shut down state of the upper semiconductor chip under increased temperature or of a specific region of the upper semiconductor chip (S161). There may be maintained a standby state until a temperature of the thermal radiation region is reduced to a normal temperature (S171). After the temperature has returned to normal, the power switching elements 141 and 143 of the thermal radiation region may reinstate power to the thermal radiation region. After that, the temperature-sensor search step may be performed again (S120).
When the measurement temperature Tj is less than the first reference temperature, the power control unit 120 may determine whether or not the measurement temperature Tj is greater than a second reference temperature (e.g., about 95° C.) (S132). When the measurement temperature Tj is greater than the second reference temperature (and less than the first reference temperature), a thermal radiation region may be searched (S142). Afterwards, the clock control elements 131 and 133 of the thermal radiation region may interrupt the supply of clock signals to the thermal radiation region (S152). Then, there may occur an idle state of the upper semiconductor chip under increased temperature and/or of a specific region of the upper semiconductor chip (S162). After that, there may be maintained a standby state until a temperature of the thermal radiation region is reduced to a normal temperature (S172). After the temperature has returned to normal, the clock control elements of the thermal radiation region may reinstate power to the thermal radiation region. Then, the temperature-sensor search step may be performed again (S120).
When the measurement temperature Tj is less than the second reference temperature, the power control unit 120 may determine whether the measurement temperature Tj is greater than a third reference temperature (e.g., about 85° C.) (S133). When the measurement temperature Tj is greater than the third reference temperature (and less than the second reference temperature), a thermal radiation region may be searched (S143). The clock control elements 131 and 132 may divide a period of clock signal, and the divided clock signal may be provided to the upper semiconductor chip and/or the thermal radiation region (S153). Then, there may occur a state in which the upper semiconductor chip under increased temperature or the specific region is operated at a low power (S163). Afterwards, there may be maintained a standby state until a temperature of the thermal radiation region is reduced to a normal temperature (S173). After the temperature has returned to normal, the clock signal may be provided to the upper semiconductor chip and/or thermal radiation region. Then, the temperature-sensor search step may be performed again (S120).
A clock or power may be controlled based on measurement temperatures of upper semiconductor chips included in a semiconductor package, and thus it may be possible to limit an operation of a region or chip under increased temperature and to secure an operation of a region or chip under normal temperature. Consequently, the semiconductor package may improve in performance, reliability, and/or durability.
FIG. 9 illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.
Referring to FIG. 9 , a semiconductor package 1000 may include a package substrate 500, a lower semiconductor chip 100 mounted on the package substrate 500, and first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240 that are vertically stacked on the lower semiconductor chip 100.
The package substrate 500 may have top and bottom surfaces, and may include lower bonding pads 511, upper bonding pads 515, and internal wiring lines 513. The upper bonding pads 515 may be arranged on the top surface of the package substrate 500, and the lower bonding pads 511 may be arranged on the bottom surface of the package substrate 500. The upper bonding pads 515 may be electrically connected through the internal wiring lines 513 to the lower bonding pads 511. The lower bonding pads 511 may be attached thereon with external bonding terminals 550 such as solder balls or solder bumps.
The lower semiconductor chip 100 may be a flip-chip mounted on the package substrate 500. The lower semiconductor chip 100 may be a logic chip and/or a controller chip. The lower semiconductor chip 100 may include a plurality of through electrodes TSV, and the through electrodes TSV may be coupled to the package substrate 500 through connection terminals 150 such as solder bumps. The lower semiconductor chip 100 may be electrically connected via the through electrodes TSV to the first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240.
As discussed with reference to FIG. 2 , the lower semiconductor chip 100 may include a plurality of temperature sensors 111 and 113, the power control unit 120, clock control elements 131 and 133, power switching elements 141 and 143, and through electrodes TSV. The temperature sensors 111 and 113 of the lower semiconductor chip 100 may sense operating temperatures of the first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240. Based on temperatures measured at the temperature sensors 111 and 113, the lower semiconductor chip 100 may control whether clock signals and power signals are provided via the through electrodes TSV to the first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240.
Each of the first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240 may include lower and upper pads (not designated by reference numerals) and a plurality of through electrodes TSV, and may be electrically connected through the through electrodes TSV to the lower semiconductor chip 100. The first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240 may be logic chips or memory chips.
The first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240 may be electrically connected through connection bumps 250.
An adhesion layer may be correspondingly provided between the lower semiconductor chip 100 and the first, second, third, and fourth upper semiconductor chips 210, 220, 230, and 240. The adhesion layer may be, for example, a polymer tape and/or a resin including a dielectric material. The adhesion layer may be interposed between the connection bumps 250, and may prevent the occurrence of electrical short between the connection bumps 250.
The package substrate 500 may be provided thereon with a molding layer 510 that covers sidewalls of the lower and upper semiconductor chips 100, 210, 220, 230, and 240. The molding layer 510 may have a top surface coplanar with that of the fourth upper semiconductor chip 240.
According to some embodiments of the present inventive concepts, a semiconductor package in which semiconductor chips are stacked may be configured to control clocks and powers provided via through electrodes, based on measurement temperatures of upper semiconductor chips. Therefore, it may be possible to limit an operation of the upper semiconductor chip or its region under increased temperature and to secure an operation of the upper semiconductor chip or its specific region under normal temperature. Consequently, the semiconductor package may improve in performance and reliability.
Although the present inventive concepts have been described in connection with some embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of the present inventive concepts. It will be apparent to those skilled in the art that various substitution, modifications, and changes may be thereto without departing from the scope and spirit of the present inventive concepts.

Claims (17)

What is claimed is:
1. A semiconductor package, comprising:
a lower semiconductor chip including a plurality of through electrodes; and
an upper semiconductor chip mounted to an upper surface of the lower semiconductor chip,
wherein the lower semiconductor chip is electrically connected to the upper semiconductor chip via the plurality of through electrodes, and
wherein the lower semiconductor chip includes
at least one temperature sensor configured to sense a temperature of the upper semiconductor chip,
a power control unit connected to the at least one temperature sensor,
a power switching element connected to at least a first one of the plurality of through electrodes, and
a clock control element connected to at least a second one of the plurality of through electrodes, and
wherein the upper semiconductor chip includes a plurality of regions,
the at least one temperature sensor includes a plurality of temperature sensors corresponding to the plurality of regions, and
the plurality of temperature sensors vertically overlap the plurality of regions of the upper semiconductor chip, respectively.
2. The semiconductor package of claim 1, wherein the power control unit is configured to, based on a temperature sensed at the at least one temperature sensor, control a connection between the power switching element and the first one of the plurality of through electrodes and a connection between the clock control element and the second one of the plurality of through electrode.
3. The semiconductor package of claim 1, wherein, when a temperature measured at the at least one temperature sensor is equal to or greater than a first reference temperature, the power control unit is configured to turn off the power switching element.
4. The semiconductor package of claim 3, wherein the power control unit is configured to turn off the clock control element such that a clock signal provided through the clock control element to the upper semiconductor chip is interrupted when the temperature measured at the at least one temperature sensor is equal to or greater than a second reference temperature, wherein the second reference temperature is less than the first reference temperature.
5. The semiconductor package of claim 4, wherein the power control unit is configured to adjust a period of a clock signal that is output from the clock control element when the temperature measured at the at least one temperature sensor is equal to or greater than a third reference temperature, wherein the third reference temperature is less than the second reference temperature.
6. The semiconductor package of claim 1, wherein the power switching element is configured to control power supplied to the upper semiconductor chip.
7. The semiconductor package of claim 1, wherein the clock control element is configured to adjust a period of a clock signal provided to the upper semiconductor chip based on a temperature measured at the at least one temperature sensor.
8. The semiconductor package of claim 1, wherein the lower semiconductor chip includes:
a semiconductor substrate; and
a plurality of internal wiring lines, and
wherein the power switching element includes a power gating transistor on the semiconductor substrate and connected to at least one of the plurality of internal wiring elements, and the plurality of through electrodes penetrate the semiconductor substrate to connect with the plurality of internal wiring lines.
9. The semiconductor package of claim 1, wherein the lower semiconductor chip includes:
a semiconductor substrate;
a plurality of upper pads on the semiconductor substrate; and
a plurality of lower pads on the semiconductor substrate, and
wherein the power switching element includes a power gating transistor on the semiconductor substrate,
wherein a first terminal of the power gating transistor is connected to one of the plurality of upper pads, and
wherein a second terminal of the power gating transistor is connected to one of the plurality of through electrodes.
10. The semiconductor package of claim 1, wherein
the lower semiconductor chip includes a semiconductor substrate, a plurality of upper pads, and a plurality of lower pads, and
the plurality of through electrodes vertically penetrate the semiconductor substrate to be connected to the lower pads, and
at least one of the power switching element or the clock control element is connected to the upper pads.
11. A semiconductor package, comprising:
a package substrate;
a lower semiconductor chip on the package substrate;
first and second upper semiconductor chips mounted to an upper surface of the lower semiconductor chip and electrically connected to the lower semiconductor chip via a plurality of through electrodes; and
a molding layer on the package substrate and covering side surfaces of the lower semiconductor chip and side surfaces of the first and second upper semiconductor chips,
wherein the lower semiconductor chip includes
a semiconductor substrate,
a plurality of upper pads and a plurality of lower pads,
a plurality of temperature sensors configured to sense temperatures of the first and second upper semiconductor chips,
a power control unit connected to the temperature sensors,
a power switching element connected to at least a first one of the plurality of through electrodes and to one of the plurality of upper pads, and
a clock control element connected to at least a second one of the plurality of through electrodes and to another of the plurality of upper pads, and
wherein the power switching element includes a power gating transistor on the semiconductor substrate, and
wherein a first terminal of the power gating transistor is connected to the one of the plurality of upper pads and a second terminal of the power gating transistor is connected to the first one of the plurality of through electrodes.
12. The semiconductor package of claim 11, wherein the power control unit is configured to, based on a temperature measured at the temperature sensors, control an electrical connection between the power switching element and the first one of the plurality of through electrodes and between the clock control element and the second one of the plurality of through electrodes.
13. The semiconductor package of claim 11, wherein
the plurality of temperature sensors comprise a first temperature sensor corresponding to the first upper semiconductor chip and a second temperature sensor corresponding to the second upper semiconductor chip, and
the first and second temperature sensors vertically overlap the first and second upper semiconductor chips, respectively.
14. A thermal management method of a semiconductor package including a lower semiconductor chip and an upper semiconductor chip connected, via a plurality of through electrodes, to the lower semiconductor chip, the method comprising:
measuring, by a temperature sensor corresponding to the upper semiconductor chip, a temperature of the upper semiconductor chip;
classifying, by the lower semiconductor chip, a power control based on the temperature measured at the temperature sensor; and
based on the classification of the power control, interrupting a power provided to the upper semiconductor chip via a first one of the plurality of through electrodes or adjusting a period of a clock signal provided to the upper semiconductor chip via a second one of the plurality of through electrodes,
wherein the classifying the power control includes determining whether the measured temperature is equal to or greater at least one of a plurality of reference temperatures,
wherein the plurality of reference temperatures includes a first reference temperature and a second reference temperature less than the first reference temperature, and
when the measured temperature is equal to or greater than the second reference temperature and less than the first reference temperature, interrupting, by a power control unit, an electrical connection of a clock control element connected to the second one of the plurality of through electrodes.
15. The method of claim 14, wherein
when the measured temperature is equal to or greater than the first reference temperature, the interrupting the power provided to the upper semiconductor chip includes the power control unit interrupting an electrical connection between the first one of the plurality of through electrodes and a power terminal of the lower semiconductor chip.
16. The method of claim 14, wherein
the classifying the power control includes determining whether the measured temperature is equal to or greater than a third reference temperature, and
when the measured temperature is equal to or greater than the third reference temperature and less than the second reference temperature, the power control unit adjusts a period of a clock signal output from the clock control element connected to the second one of the plurality of through electrodes.
17. The method of claim 14, wherein
the temperature sensor is included in a plurality of temperature sensors,
each of the plurality of the temperature sensors is configured to individually sense temperatures of corresponding regions of the upper semiconductor chip, and
a clock period or a power for each of the regions of the upper semiconductor chip is controlled based on the classification of the power control.
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