US12408405B2 - Device comprising spacers including a localised airgap and associated manufacturing methods - Google Patents

Device comprising spacers including a localised airgap and associated manufacturing methods

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US12408405B2
US12408405B2 US17/966,217 US202217966217A US12408405B2 US 12408405 B2 US12408405 B2 US 12408405B2 US 202217966217 A US202217966217 A US 202217966217A US 12408405 B2 US12408405 B2 US 12408405B2
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active region
height
plane
spacer
gate stack
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US20230120901A1 (en
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Fabrice Nemouchi
Cyrille Le Royer
Nicolas Posseme
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/402—Single electron transistors; Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • H10D48/3835—Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H01L21/76283—
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the technical field of the invention is that of semiconductor devices, particularly for applications to spin qubits.
  • the present invention relates to a device comprising spacers including an airgap and in particular to a device in which the airgaps are located.
  • the present invention also relates to two manufacturing methods for obtaining such a device.
  • the distance separating the qubits generally imposes a high density at the gates (typically a pitch of less than 100 nm) so that there is a strong coupling between the different gates, in particular at the active region of the device (the channel), that is, the region in which the spin qubits will be formed. This is even more true since, for manufacturing reasons, the materials used to make the spacers are not low-k materials, which tends to reinforce the coupling between adjacent gates.
  • spacers comprising an airgap. This is, for example, provided in document US 2015/0091089 A1 or document US 2014/0110798.
  • the methods described in these documents are relatively complex to implement and do not enable the life zone of each spacer to be localised, as this life zone is then present over the entire length of the spacer.
  • the invention provides a solution to the above-mentioned problems, by making it possible to easily obtain localised airgaps by playing on the form aspect between the height of the gate stacks and the distance separating them.
  • spacers comprising airgaps localised at the active region of the device.
  • making localised airgaps is greatly facilitated by the clever use of the aspect ratio between the height of the gate stacks and the distance separating said stacks.
  • These vacuum zones make it possible to limit capacitive coupling between gates during electrical operation. They have to be inside the spacer (covered and not uncovered) so as not to lead to the inclusion of metal during the formation of the metal contacts/electrodes
  • the device according to a first aspect of the invention may have one or more of the following additional characteristics, considered individually or in any technically possible combination.
  • the surface of the active region is located in a first plane and the surface of the non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, the difference in height ⁇ h between the first plane and the second plane being equal to the difference between the height h 2 of the gate stacks on the active region and the height h 1 of the gate stacks on the non-active region.
  • the spacers are formed by a layer of spacer material having a thickness t greater than or equal to 0.3 ⁇ e, for example 0.4 ⁇ e, or even 0.5 ⁇ e.
  • the spacer material is silicon nitride.
  • the device comprises a plurality of active regions.
  • the height h 1 is between 30 and 50 nm
  • the height h 2 is between 60 and 100 nm
  • the distance e separating two successive gate stacks is between 20 and 40 nm.
  • a second aspect of the invention relates to a method for manufacturing a semiconductor device from a substrate including at least one active region and one non-active region at least partially surrounding the active region, the surface of the active region being located in a first plane and the surface of the non-active region being located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising:
  • the mechanical-chemical polishing step comprises:
  • a third aspect of the invention relates to a method for manufacturing a semiconductor device from a substrate having at least one active region and one non-active region at least partially surrounding the active region, the surface of the active region being located in a first plane and the surface of the non-active region being located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising:
  • the method according to a second or third aspect of the invention may have one or more of the following additional characteristics, considered individually or in any technically possible combination.
  • the spacer material is silicon nitride.
  • a thickness t of spacer material such that t ⁇ 0.3 ⁇ e, for example t ⁇ 0.4 ⁇ e, or even t ⁇ 0.5 ⁇ e, is deposited in the step of depositing a layer of spacer material.
  • the step of depositing the spacer material is performed by plasma-enhanced chemical vapour deposition (PECVD), low-pressure chemical vapour deposition (LPCVD) or sub-atmospheric pressure chemical vapour deposition (SACVD).
  • PECVD plasma-enhanced chemical vapour deposition
  • LPCVD low-pressure chemical vapour deposition
  • SACVD sub-atmospheric pressure chemical vapour deposition
  • FIG. 1 A to FIG. 1 E illustrate a semiconductor device according to an embodiment of the invention.
  • FIG. 2 A shows the formation of an airgap in the spacer when the form factor of the structure is sufficiently high.
  • FIG. 2 B shows the absence of formation of an airgap in the spacer when the form factor of the structure is not sufficiently high.
  • FIG. 3 shows a graphical representation of the form aspects for obtaining an airgap when forming spacers.
  • FIG. 4 shows a flow chart of a manufacturing method according to a second aspect of the invention.
  • FIG. 5 to FIG. 9 B schematically show the steps of a manufacturing method according to a second aspect of the invention.
  • FIG. 10 shows a flow chart of a manufacturing method according to a third aspect of the invention.
  • FIG. 11 A to FIG. 14 B schematically show the steps of a manufacturing method according to a third aspect of the invention.
  • a first aspect of the invention illustrated in [ FIG. 1 A ] to [ FIG. 1 E ] relates to a semiconductor device DI made on a substrate comprising at least one active region RA and one non-active region RA at least partially surrounding the active region RA. As illustrated in [ FIG. 1 E ], when several active regions RA are present, then the non-active region RN at least partially surrounds said active regions RA.
  • active region RA it is meant a region which comprises a layer of semiconductor material, for example silicon, capable of forming, together with the gate stacks EG, a channel as well as the transistor sources and drains.
  • non-active region RN it is meant a region that does not comprise semiconductor material capable of forming, together with the gate stacks EG, a transistor channel.
  • a non-active region RN also known as an isolation zone
  • the substrate is an SOI type substrate.
  • the active region RA is then formed by a layer of silicon and the non-active region RN is then formed by an STI on SOI.
  • the device DI comprises a plurality of gate stacks EG, each gate stack EG of the plurality of gate stacks EG being parallel to the other gate stacks EG of the plurality of gate stacks EG.
  • each gate stack EG is separated from the adjacent gate stacks EG by a distance equal to e by means of a spacer ES.
  • a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME.
  • a gate oxide OG for example silicon oxide
  • metal ME on the gate oxide OG
  • polysilicon PS on the layer of metal ME.
  • other configurations may be considered.
  • each gate stack EG is disposed such that a part of the stack EG under consideration is on the active region RA.
  • each gate stack EG is also disposed such that a part of the gate stack EG under consideration is on the non-active region RN.
  • FIG. 1 D which represents a view of the device along section C 3
  • the difference between the second height h 2 and the first height h 1 will be denoted as ⁇ h.
  • the surface of the active region RA is located in a first plane P 1 and the surface of the non-active region RN is located in a second plane P 2 , the first plane P 1 being located at a height lower by ⁇ h than that of the second plane P 2 .
  • each spacer ES separating one gate stack EG from the next has, at the active region RA, an airgap VO.
  • the aspect ratios a 1 and a 2 can be easily determined experimentally by depositing the material used to form the spacers ES with different values of the aspect ratio and by noting for which values of the aspect ratio an airgap VO is formed during said deposition.
  • a graph illustrating such a determination is illustrated in [ FIG. 3 ].
  • the pairs of values (e, h) corresponding to points located in the upper zone OK enable the formation of an airgap VO. Therefore, a 2 can be chosen among all the aspect ratios associated with the pairs (h, e) located in this upper zone OK.
  • the pairs of values (e, h) corresponding to points located in the lower zone KO do not enable the formation of an airgap VO.
  • a 1 can be chosen from all the aspect ratios associated with the pairs (h, e) located in this lower zone KO.
  • the pair (e, h 2 ) corresponds to a point located in the upper zone OK whereas the pair (e, h 1 ) corresponds to a point located in the lower zone KO.
  • the aspect ratio a 2 is equal to 1.5 and/or the aspect ratio a 1 is equal to 1.
  • the height h 1 is between 30 and 50 nm (limits included). In an embodiment, the height h 2 is between 60 and 100 nm (limits included). In an embodiment, the distance e separating two successive gate stacks EG is between 20 and 40 nm (limits included).
  • each gate stack EG has a width (measured in the same direction as the distance e) of between 10 and 40 nm (limits included).
  • the spacers ES are formed by a layer of spacer material, for example nitride, having a thickness t greater than or equal to 0.3 ⁇ e, for example greater than or equal to 0.4 ⁇ e, or even greater than or equal to 0.5 ⁇ e. This ensures that sufficient spacer material is deposited to form a spacer ES comprising an airgap VO.
  • the thickness t of the layer of spacer material is between 15 and 20 nm (limits included).
  • the thickness of the layer of spacer material is between 15 and 20 nm (limits included), the distance e separating two successive gate stacks is between 20 and 30 nm (limits included), the height h 2 is between 60 and 80 nm and the height h 1 is between 30 and 40 nm.
  • the spacer material is a nitride, such as a silicon nitride.
  • a second aspect of the invention illustrated in [ FIG. 4 ] to [ FIG. 9 B ] relates to a method 100 for manufacturing a semiconductor device DI from a substrate (illustrated in [ FIG. 5 ]), for example an SOI substrate, including at least one active region RA and one non-active region RN at least partially surrounding the active region RA.
  • the surface of the active region RA is located in a first plane P 1 and the surface of the non-active region is located in a second plane P 2 , the first plane P 1 being located at a height lower than that of the second plane P 2 .
  • the difference in height between the first plane P 1 and the second plane P 2 is denoted as ⁇ h in the following.
  • the method 100 comprises a step 1 E 1 of forming a plurality of gate stacks EG parallel to each other, each gate stack EG having a height h (higher than the height h 2 introduced below) and being separated from the nearest gate stack(s) EG by a distance e.
  • a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME.
  • the plurality of gate stacks EG can for example be obtained by depositing the different layers forming a gate stack EG, the layers being subsequently etched so as to obtain the plurality of gate stacks EG. As these steps are well known in the art, they are not detailed in the following.
  • the method 100 then comprises a step 1 E 2 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack ES, the thickness t of the deposited layer for example being greater than or equal to 0.3 ⁇ e.
  • the height h of the gate stacks EG during this step 1 E 2 is such that h/e ⁇ a 2 where a 2 is the previously introduced aspect ratio enabling the formation of airgaps VO.
  • an airgap VO is formed within the spacers ES between each gate stack EG.
  • the method also comprises a step 1 E 3 of depositing a layer of a dielectric material OX.
  • this step is performed in two sub-steps: a first mechanical-chemical polishing sub-step so as to level the layer of dielectric material OX and then a second mechanical-chemical polishing sub-step so as to expose the top of the gate stacks EG.
  • the mechanical-chemical polishing step 1 E 4 is implemented such that the airgaps VO formed in the spacers ES at the non-active region become exposed (cf. [ FIG. 9 A ]) while those formed in the spacers ES at the active region RA remain (cf. [ FIG. 9 B ]—that is, are not exposed).
  • the method 100 then comprises a step of depositing a layer of material so as to fill the airgaps VO thus exposed. This may be a deposition of a passivation layer.
  • a third aspect of the invention illustrated in [ FIG. 10 ] to [ FIG. 13 B ] relates to a method 200 for manufacturing a semiconductor device DI from a substrate (illustrated in [ FIG. 4 ]) having at least one active region RA and one non-active region RA at least partially surrounding the active region RA.
  • the surface of the active region RA is located in a first plane P 1 and the surface of the non-active region RN is located in a second plane P 2 , the first plane P 1 being located at a height lower than that of the second plane P 2 .
  • the difference in height between the first plane P 1 and the second plane P 2 is denoted as ⁇ h in the following.
  • the method 200 comprises a step 2 E 1 of full plate depositing a layer of gate stacks EG.
  • the layer of gate stack comprises a gate oxide OG (for example, silicon oxide), a layer of metal ME on the gate oxide OG (for example, titanium nitride) and a layer of polysilicon PS on the layer of metal ME.
  • the method 200 comprises a mechanical-chemical polishing step 2 E 2 such that the layer of gate stacks EG located on the active region RA has, at the end of this step 2 E 2 , a thickness h 2 .
  • the method 200 comprises a step 2 E 3 of forming, from the layer of gate stack EG, a plurality of gate stacks EG parallel to each other, each gate stack EG being separated from the nearest gate stack(s) EG by a distance e.
  • the method comprises a step 2 E 4 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack EG.
  • the thickness t of the deposited layer is in an embodiment greater than or equal to 0.3 ⁇ e.

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  • Manufacturing & Machinery (AREA)

Abstract

A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and h2/e=a2 and h1/e=a1<alim where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to French Patent Application No. 2110869, filed Oct. 14, 2021, the entire content of which is incorporated herein by reference in its entirety.
FIELD
The technical field of the invention is that of semiconductor devices, particularly for applications to spin qubits.
The present invention relates to a device comprising spacers including an airgap and in particular to a device in which the airgaps are located. The present invention also relates to two manufacturing methods for obtaining such a device.
BACKGROUND
In the field of semiconductor devices for making spin qubits, it is known to use a plurality of gates disposed one after the other so as to make a plurality of spin qubits which it is then possible to couple together by playing on the potential barriers separating two adjacent qubits.
The distance separating the qubits generally imposes a high density at the gates (typically a pitch of less than 100 nm) so that there is a strong coupling between the different gates, in particular at the active region of the device (the channel), that is, the region in which the spin qubits will be formed. This is even more true since, for manufacturing reasons, the materials used to make the spacers are not low-k materials, which tends to reinforce the coupling between adjacent gates.
In order to reduce the coupling, it is known to make spacers comprising an airgap. This is, for example, provided in document US 2015/0091089 A1 or document US 2014/0110798. However, the methods described in these documents are relatively complex to implement and do not enable the life zone of each spacer to be localised, as this life zone is then present over the entire length of the spacer.
There is therefore a need for a method that allows for the easy manufacture of spacers comprising an airgap and that also enables this airgap to be localised to only a part of the spacer.
SUMMARY
The invention provides a solution to the above-mentioned problems, by making it possible to easily obtain localised airgaps by playing on the form aspect between the height of the gate stacks and the distance separating them.
To this end, a first aspect of the invention relates to a semiconductor device made on a substrate comprising at least one active region and one non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack of the plurality of gate stacks being on the active region and a part of said gate stacks being on the non-active region, each gate stack being separated from at least one adjacent gate stack, for example from each adjacent gate stack, by means of a spacer by a distance e, wherein, for each gate stack of the plurality of gate stacks, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and in that h2/e=a2 and h1/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in said spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in said spacer.
By means of the invention, it is possible to obtain spacers comprising airgaps localised at the active region of the device. Moreover, as will be shown in the section devoted to the manufacture of such a device, making localised airgaps is greatly facilitated by the clever use of the aspect ratio between the height of the gate stacks and the distance separating said stacks. These vacuum zones make it possible to limit capacitive coupling between gates during electrical operation. They have to be inside the spacer (covered and not uncovered) so as not to lead to the inclusion of metal during the formation of the metal contacts/electrodes
In addition to the characteristics just discussed in the preceding paragraph, the device according to a first aspect of the invention may have one or more of the following additional characteristics, considered individually or in any technically possible combination.
In an embodiment, the surface of the active region is located in a first plane and the surface of the non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, the difference in height Δh between the first plane and the second plane being equal to the difference between the height h2 of the gate stacks on the active region and the height h1 of the gate stacks on the non-active region.
In an embodiment, the spacers are formed by a layer of spacer material having a thickness t greater than or equal to 0.3×e, for example 0.4×e, or even 0.5×e.
In an embodiment, the spacer material is silicon nitride.
In an embodiment, the device comprises a plurality of active regions.
In an embodiment, a2≥1.5 and a1≤1.
In an embodiment, the height h1 is between 30 and 50 nm, the height h2 is between 60 and 100 nm and/or the distance e separating two successive gate stacks is between 20 and 40 nm.
A second aspect of the invention relates to a method for manufacturing a semiconductor device from a substrate including at least one active region and one non-active region at least partially surrounding the active region, the surface of the active region being located in a first plane and the surface of the non-active region being located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising:
    • a step of forming a plurality of gate stacks parallel to each other, each gate stack being separated from the nearest gate stack(s) by a distance e;
    • a step of depositing a layer of a spacer material so as to form a spacer between each gate stack;
    • a step of depositing a layer of a dielectric material;
    • a mechanical-chemical polishing step so that, at the end of this step, the part of the gate stacks located on the active region has a height h2;
    • the height between the first plane and the second plane being equal to Δh, the height h2, the difference in height Δh and the distance e separating two gate stacks being chosen so that h2/e=a2 and (h2−Δh)/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within said spacer.
In an embodiment, the mechanical-chemical polishing step comprises:
    • a first mechanical-chemical polishing sub-step so as to level the layer of dielectric material;
    • a second mechanical-chemical polishing sub-step so that, at the end of this sub-step, the part of the gate stacks located on the active region has a height h2.
A third aspect of the invention relates to a method for manufacturing a semiconductor device from a substrate having at least one active region and one non-active region at least partially surrounding the active region, the surface of the active region being located in a first plane and the surface of the non-active region being located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising:
    • a step of full plate depositing a layer of gate stack;
    • a mechanical-chemical polishing step so that, at the end of this step, the layer of gate stack located on the active region has a thickness h2;
    • a step of forming, from the layer of gate stack, a plurality of gate stacks parallel to each other, each gate stack being separated from the nearest gate stack(s) by a distance e;
    • a step of depositing a layer of a spacer material so as to form a spacer between each gate stack;
    • the difference in height between the first plane and the second plane being equal to Δh, the thickness h2, the difference in height Δh and the distance e separating two gate stacks being chosen such that h2/e=a2 and (h2−Δh)/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within said spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within the spacer.
In addition to the characteristics just discussed in the preceding paragraphs, the method according to a second or third aspect of the invention may have one or more of the following additional characteristics, considered individually or in any technically possible combination.
In an embodiment, the spacer material is silicon nitride.
In an embodiment, a thickness t of spacer material such that t≥0.3×e, for example t≥0.4×e, or even t≥0.5×e, is deposited in the step of depositing a layer of spacer material.
In an embodiment, a2≥1.5 and a1≤1.
In an embodiment, the step of depositing the spacer material is performed by plasma-enhanced chemical vapour deposition (PECVD), low-pressure chemical vapour deposition (LPCVD) or sub-atmospheric pressure chemical vapour deposition (SACVD).
The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures.
BRIEF DESCRIPTION OF THE FIGURES
The figures are set forth as an indication and in no way as a limitation of the invention.
FIG. 1A to FIG. 1E illustrate a semiconductor device according to an embodiment of the invention.
FIG. 2A shows the formation of an airgap in the spacer when the form factor of the structure is sufficiently high.
The FIG. 2B shows the absence of formation of an airgap in the spacer when the form factor of the structure is not sufficiently high.
FIG. 3 shows a graphical representation of the form aspects for obtaining an airgap when forming spacers.
FIG. 4 shows a flow chart of a manufacturing method according to a second aspect of the invention.
FIG. 5 to FIG. 9B schematically show the steps of a manufacturing method according to a second aspect of the invention.
FIG. 10 shows a flow chart of a manufacturing method according to a third aspect of the invention.
FIG. 11A to FIG. 14B schematically show the steps of a manufacturing method according to a third aspect of the invention.
 DETAILED DESCRIPTION
The figures are set forth as an indication and in no way as a limitation of the invention.
Semiconductor Device with Localised Airgaps
A first aspect of the invention illustrated in [FIG. 1A] to [FIG. 1E] relates to a semiconductor device DI made on a substrate comprising at least one active region RA and one non-active region RA at least partially surrounding the active region RA. As illustrated in [FIG. 1E], when several active regions RA are present, then the non-active region RN at least partially surrounds said active regions RA.
By active region RA, it is meant a region which comprises a layer of semiconductor material, for example silicon, capable of forming, together with the gate stacks EG, a channel as well as the transistor sources and drains. By non-active region RN, it is meant a region that does not comprise semiconductor material capable of forming, together with the gate stacks EG, a transistor channel. A non-active region RN (also known as an isolation zone) can for example consist of or comprise an STI (for Shallow Trench Isolation—a well-known feature in the field). In an embodiment, the substrate is an SOI type substrate. In an embodiment, the active region RA is then formed by a layer of silicon and the non-active region RN is then formed by an STI on SOI.
In addition, as illustrated in [FIG. 1A], the device DI according to an embodiment of the invention comprises a plurality of gate stacks EG, each gate stack EG of the plurality of gate stacks EG being parallel to the other gate stacks EG of the plurality of gate stacks EG. In addition, as illustrated in [FIG. 1B] and [FIG. 1C] (which represent the device DI along section C1 and section C2 respectively), each gate stack EG is separated from the adjacent gate stacks EG by a distance equal to e by means of a spacer ES. In general, as illustrated in [FIG. 1B], a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME. However, other configurations may be considered.
Furthermore, as illustrated in [FIG. 1A] to [FIG. 1C], each gate stack EG is disposed such that a part of the stack EG under consideration is on the active region RA. As a result, each gate stack EG is also disposed such that a part of the gate stack EG under consideration is on the non-active region RN.
In addition, as illustrated in [FIG. 1D] which represents a view of the device along section C3, for each gate stack EG, the part of the gate stack EG under consideration located on the non-active region RN at a first height h1 and the part of the gate stack EG under consideration located on the active region RA at a second height h2, the second height h2 being higher than the first height h1. In the following, the difference between the second height h2 and the first height h1 will be denoted as Δh. In an embodiment, the surface of the active region RA is located in a first plane P1 and the surface of the non-active region RN is located in a second plane P2, the first plane P1 being located at a height lower by Δh than that of the second plane P2.
Furthermore, in the device DI according to an embodiment of the invention, for each gate stack EG of the plurality of gate stacks EG, the height h2 of the part of the gate stack EG located on the active region RA and the height h1 of the part of the same gate stack EG located on the non-active region RA satisfy the relationships h2/e=a2 and h1/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, an airgap is in the spacer ES, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, no airgap is in said spacer ES.
The notion of a limit aspect ratio is illustrated in [FIG. 2A] and [FIG. 2B]. The structure represented in [FIG. 2A] has an aspect ratio h1/e equal to the aspect ratio a2 and an airgap VO therefore forms in the spacers ES. In contrast, the structure represented in [FIG. 2B] has an aspect ratio h1/e equal to the aspect ratio a1 and no airgap VO therefore forms in the spacers ES. Thus, in the device DI according to an embodiment of the invention, each spacer ES separating one gate stack EG from the next has, at the active region RA, an airgap VO.
The aspect ratios a1 and a2 can be easily determined experimentally by depositing the material used to form the spacers ES with different values of the aspect ratio and by noting for which values of the aspect ratio an airgap VO is formed during said deposition. A graph illustrating such a determination is illustrated in [FIG. 3 ]. In this figure, the pairs of values (e, h) corresponding to points located in the upper zone OK enable the formation of an airgap VO. Therefore, a2 can be chosen among all the aspect ratios associated with the pairs (h, e) located in this upper zone OK. In contrast, the pairs of values (e, h) corresponding to points located in the lower zone KO do not enable the formation of an airgap VO. Therefore, a1 can be chosen from all the aspect ratios associated with the pairs (h, e) located in this lower zone KO. Thus, the pair (e, h2) corresponds to a point located in the upper zone OK whereas the pair (e, h1) corresponds to a point located in the lower zone KO. In an embodiment, the aspect ratio a2 is equal to 1.5 and/or the aspect ratio a1 is equal to 1. In an embodiment a2≥1.5 and a1≤1, or even a2≥1.5 and a1≤0.9.
In an embodiment, the height h1 is between 30 and 50 nm (limits included). In an embodiment, the height h2 is between 60 and 100 nm (limits included). In an embodiment, the distance e separating two successive gate stacks EG is between 20 and 40 nm (limits included).
In an embodiment, each gate stack EG has a width (measured in the same direction as the distance e) of between 10 and 40 nm (limits included).
In an embodiment, the spacers ES are formed by a layer of spacer material, for example nitride, having a thickness t greater than or equal to 0.3×e, for example greater than or equal to 0.4×e, or even greater than or equal to 0.5×e. This ensures that sufficient spacer material is deposited to form a spacer ES comprising an airgap VO. In an embodiment, the thickness t of the layer of spacer material is between 15 and 20 nm (limits included).
In an example embodiment, the thickness of the layer of spacer material is between 15 and 20 nm (limits included), the distance e separating two successive gate stacks is between 20 and 30 nm (limits included), the height h2 is between 60 and 80 nm and the height h1 is between 30 and 40 nm. In an embodiment, the spacer material is a nitride, such as a silicon nitride.
First Manufacturing Method
A second aspect of the invention illustrated in [FIG. 4 ] to [FIG. 9B] relates to a method 100 for manufacturing a semiconductor device DI from a substrate (illustrated in [FIG. 5 ]), for example an SOI substrate, including at least one active region RA and one non-active region RN at least partially surrounding the active region RA. In addition, the surface of the active region RA is located in a first plane P1 and the surface of the non-active region is located in a second plane P2, the first plane P1 being located at a height lower than that of the second plane P2. As illustrated in [FIG. 5 ], the difference in height between the first plane P1 and the second plane P2 is denoted as Δh in the following.
As illustrated in [FIG. 6A] and [FIG. 6B], the method 100 comprises a step 1E1 of forming a plurality of gate stacks EG parallel to each other, each gate stack EG having a height h (higher than the height h2 introduced below) and being separated from the nearest gate stack(s) EG by a distance e.
In general, as illustrated in [FIG. 6A], a gate stack EG comprises a gate oxide OG (for example silicon oxide), a layer of metal ME on the gate oxide OG (for example titanium nitride) and a layer of polysilicon PS on the layer of metal ME. Also, the plurality of gate stacks EG can for example be obtained by depositing the different layers forming a gate stack EG, the layers being subsequently etched so as to obtain the plurality of gate stacks EG. As these steps are well known in the art, they are not detailed in the following.
As illustrated in [FIG. 7A] and [FIG. 7B], the method 100 then comprises a step 1E2 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack ES, the thickness t of the deposited layer for example being greater than or equal to 0.3×e. In addition, the height h of the gate stacks EG during this step 1E2 is such that h/e≥a2 where a2 is the previously introduced aspect ratio enabling the formation of airgaps VO. Also, during the deposition of the layer of a spacer material, an airgap VO is formed within the spacers ES between each gate stack EG.
As illustrated in [FIG. 8A] and [FIG. 8B], the method also comprises a step 1E3 of depositing a layer of a dielectric material OX.
As illustrated in [FIG. 9A] and [FIG. 9B], the method 100 further comprises a mechanical-chemical polishing step 1E4 such that, at the end of this step 1E4, the part of the gate stacks located on the active region has a height h2 chosen such that h2/e=a2. In an embodiment, this step is performed in two sub-steps: a first mechanical-chemical polishing sub-step so as to level the layer of dielectric material OX and then a second mechanical-chemical polishing sub-step so as to expose the top of the gate stacks EG. Obtaining a height h2 at the part of the gate stacks EG located on the active region RA implies, given the difference in height between the active region RA and the non-active region RN, that the part of the gate stacks EG at the non-active region RN has a height h2−Δh=h1. Furthermore, Δh is chosen such that h1/e=a1 where a1 is the previously introduced aspect ratio and does not enable the formation of airgaps VO.
Also, the mechanical-chemical polishing step 1E4 is implemented such that the airgaps VO formed in the spacers ES at the non-active region become exposed (cf. [FIG. 9A]) while those formed in the spacers ES at the active region RA remain (cf. [FIG. 9B]—that is, are not exposed).
In an embodiment, the method 100 then comprises a step of depositing a layer of material so as to fill the airgaps VO thus exposed. This may be a deposition of a passivation layer.
At the end of this method 100, a device according to the invention is obtained.
Second Manufacturing Method
A third aspect of the invention illustrated in [FIG. 10 ] to [FIG. 13B] relates to a method 200 for manufacturing a semiconductor device DI from a substrate (illustrated in [FIG. 4 ]) having at least one active region RA and one non-active region RA at least partially surrounding the active region RA. In the method 200 according to a third aspect of the invention (as before), the surface of the active region RA is located in a first plane P1 and the surface of the non-active region RN is located in a second plane P2, the first plane P1 being located at a height lower than that of the second plane P2. In addition, as illustrated in [FIG. 4 ], the difference in height between the first plane P1 and the second plane P2 is denoted as Δh in the following.
As illustrated in [FIG. 11A] and [FIG. 11B], the method 200 comprises a step 2E1 of full plate depositing a layer of gate stacks EG. In an embodiment, the layer of gate stack comprises a gate oxide OG (for example, silicon oxide), a layer of metal ME on the gate oxide OG (for example, titanium nitride) and a layer of polysilicon PS on the layer of metal ME.
As illustrated in [FIG. 12A] and [FIG. 12B], the method 200 comprises a mechanical-chemical polishing step 2E2 such that the layer of gate stacks EG located on the active region RA has, at the end of this step 2E2, a thickness h2. Obtaining a thickness h2 implies, given the difference in height between the active region RA and the non-active region RN, that the layer of gate stacks EG at the non-active region RN has a thickness h2−Δh=h1.
As illustrated in [FIG. 13A] and [FIG. 13B], the method 200 comprises a step 2E3 of forming, from the layer of gate stack EG, a plurality of gate stacks EG parallel to each other, each gate stack EG being separated from the nearest gate stack(s) EG by a distance e. Thus, the part of the gate stacks located in the active region RA has a height h2 while the part of the gate stacks located in the non-active region RN has a height h1=h2−Δh. Moreover, h2 is chosen such that h2/e=a2 and Δh is chosen such that h1/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, an airgap VO forms within said spacer ES, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers ES, no airgap VO forms within said spacer ES.
As illustrated in [FIG. 14A] and [FIG. 14B], the method comprises a step 2E4 of depositing a layer of a spacer material, for example nitride, so as to form a spacer ES between each gate stack EG. The thickness t of the deposited layer is in an embodiment greater than or equal to 0.3×e. Furthermore, since this deposition step is performed, h1/e=a1 and h2/e=a2, an airgap VO is formed in each spacer at the part located on the active region RA.
At the end of this method 200, a device according to the invention is also obtained.

Claims (14)

The invention claimed is:
1. A semiconductor device made on a substrate comprising at least one active region and at least one non-active region at least partially surrounding the at least one active region,
a plurality of gate stacks, a part of each gate stack of the plurality of gate stacks being on the at least one active region and a part of said plurality of gate stacks being on the at least one non-active region,
each gate stack being separated from at least one of the adjacent gate stacks by a spacer formed of a spacer material by a distance equal to e,
wherein, for each gate stack of the plurality of gate stacks, the part of the gate stack located on the at least one active region has a height h2, the part of the same gate stack located on the at least one non-active region has a height h1, and wherein h2/e=a2 and h1/e=a1
where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in said spacer,
and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in said spacer.
2. The semiconductor device according to claim 1, wherein a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, a difference in height Δh between the first plane and the second plane being equal to the difference between the height h2 of the gate stacks on the at least one active region and the height h1 of the gate stacks on the non-active region.
3. The semiconductor device according to claim 1, wherein the spacers are formed by a layer of spacer material having a thickness t greater than or equal to 0.3×e.
4. The semiconductor device according to claim 1, comprising a plurality of active regions.
5. The semiconductor device according to claim 1, wherein a2≥1.5 and a1≤1.
6. The semiconductor device according to claim 1, wherein the height h1 is between 30 and 50 nm, the height h2 is between 60 and 100 nm and/or the distance e separating two successive gate stacks is between 20 and 40 nm.
7. The semiconductor device according to claim 1, wherein the spacers are of nitride.
8. A method for manufacturing a semiconductor device from a substrate comprising at least one active region and at least one non-active region at least partially surrounding the active region,
a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane,
the first plane being located at a height lower than that of the second plane, the method comprising:
forming a plurality of gate stacks parallel to each other, a part of each gate stack of the plurality of gate stacks being on the at least one active region and a part of said plurality of gate stacks being on the at least one non-active region, each gate stack being separated from the nearest gate stack(s) by a distance e;
depositing a layer of a spacer material so as to form a spacer between each gate stack;
depositing a layer of a dielectric material;
performing a mechanical-chemical polishing so that, at the end of the mechanical-chemical polishing, the part of the gate stacks located on the active region has a height h2, and the part of the same gate stack located on the at least one non-active region has a height h1;
a height between the first plane and the second plane being equal to Δh=h2−h1, the height h2, the difference in height Δh and the distance e separating two gate stacks being chosen so that h2/e=a2 and (h2−Δh)/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within said spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within said spacer.
9. The method according to claim 8, wherein the mechanical-chemical polishing comprises:
a first mechanical-chemical polishing so as to level the layer of dielectric material;
a second mechanical-chemical polishing so that, at the end of the second mechanical-chemical polishing, the part of the gate stacks located on the active region has a height h2.
10. A method for manufacturing a semiconductor device from a substrate comprising at least one active region and at least one non-active region at least partially surrounding the at least one active region,
a surface of the at least one active region is located in a first plane and a surface of the at least one non-active region is located in a second plane, the first plane being located at a height lower than that of the second plane, the method comprising:
full plate depositing a layer of gate stack a part of each gate stack of the plurality of gate stacks being on the at least one active region and a part of said plurality of gate stacks being on the at least one non-active region;
performing a mechanical-chemical polishing so that the layer of gate stacks located on the active region at the end of the mechanical-chemical polishing has a thickness h2, and the part of the same gate stack located on the at least one non-active region has a height h1;
forming, from the layer of gate stack, a plurality of gate stacks parallel to each other, each gate stack being separated from the nearest gate stack(s) by a distance e;
depositing a layer of a spacer material so as to form a spacer between each gate stack;
the difference in height between the first plane and the second plane being equal to Δh=h2−h1, the thickness h2, a difference in height Δh and the distance e separating two gate stacks being chosen so that h2/e=a2 and (h2−Δh)/e=a1 where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap forms within said spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap forms within said spacer.
11. The method according to claim 10, wherein the spacer material is silicon nitride.
12. The method according to claim 10, wherein a thickness t of the spacer material such that t 0.3×e is deposited in the step of depositing a layer of a spacer material.
13. The method according to claim 10, wherein a2 1.5 and a1≤1.
14. The method according to claim 10, wherein the depositing of the spacer material is performed by plasma-enhanced chemical vapour deposition, low-pressure chemical vapour deposition or sub-atmospheric pressure chemical vapour deposition.
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