US12354693B2 - Memory chip - Google Patents

Memory chip Download PDF

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US12354693B2
US12354693B2 US18/303,580 US202318303580A US12354693B2 US 12354693 B2 US12354693 B2 US 12354693B2 US 202318303580 A US202318303580 A US 202318303580A US 12354693 B2 US12354693 B2 US 12354693B2
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power
memory chip
pads
switch device
data width
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US20240312555A1 (en
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Ying-Te Tu
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Definitions

  • the disclosure relates to a semiconductor chip, and more particularly to a memory chip.
  • a memory chip should be designed to support the requirements of different data widths.
  • an additional bonding pad is usually added for users to determine the data width of the memory chip.
  • the disclosure provides a memory chip, which does not require setting of an additional bonding pad, and allows users to determine the data width of the memory chip.
  • FIG. 1 shows a schematic diagram of a memory chip according to an embodiment of the disclosure.
  • FIG. 2 A is a schematic diagram of a memory chip having a first width when a switch device being turned on according to an embodiment of the disclosure.
  • FIG. 3 shows a schematic diagram of a judgment circuit according to an embodiment of the disclosure.
  • the data pad 130 is configured to transmit the stored data of the memory chip.
  • the data pads 130 marked as DQ 0 , DQ 1 , DQ 2 , DQ 3 , DQ 4 , DQ 5 , DQ 6 , DQ 7 , DQ 8 , DQ 9 , DQ 10 , DQ 11 , DQ 12 , DQ 13 , DQ 14 , and DQ 15 indicate that they are pads configured to transmit data bits DQ 0 to DQ 15 .
  • the memory chip 100 includes 16 data pads 130 , but the disclosure is not limited thereto.
  • the design of the data width of the memory chip may have different requirements depending on the application occasion, and there are several conventional types of ⁇ 4, ⁇ 8, ⁇ 16, and ⁇ 32.
  • the representation of ⁇ 16 means that the maximum transmission number of bits of the memory chip 100 is 16 bits, and the representations of ⁇ 4, ⁇ 8, and ⁇ 32 may be deduced in the same way. Therefore, in other embodiments, the memory chip 100 may have 4, 8 or 32 data pads, but the disclosure is not limited thereto.
  • FIG. 2 A is a schematic diagram of a memory chip having a first width when a switch device being turned on according to an embodiment of the disclosure.
  • FIG. 2 B is a schematic diagram of the memory chip having a second width when the switch device of the embodiment of FIG. 2 A being turned off.
  • FIG. 2 A and FIG. 2 B only show the first power pad 110 and the second power pad 120 , but do not show the data pad, and the first power pad 110 and the second power pad 120 are spaced apart from each other.
  • the data pads for transmitting the stored data may be distributed between the first power pad 110 and the second power pad 120 .
  • the power pad 110 S among the first power pads 110 is coupled to the first bus 141 through the switch device SW, and the data width of the memory chip 100 is determined according to the conduction state of the switch device SW.
  • the data width of the memory chip 100 may be determined to be the first data width, such as 16 bits.
  • the data width of the memory chip 100 may be determined to be the second data width, such as 8 bits.
  • the first data width is larger than the second data width.
  • the memory chip 100 further includes a judgment circuit 140 .
  • the judgment circuit 140 is coupled to the power pad 110 S, that is, the power pad coupled to the switch device SW.
  • the judgment circuit 140 is configured to judge the conduction state of the switch device SW. For example, when the judgment circuit 140 detects that the connection line L has the first power VDD, it means that the switch device SW is turned on, and the power pad 110 S has the first power VDD at this time. When the judgment circuit 140 detects that the connection line L is floating, it means that the switch device SW is turned off, and the power pad 110 S is also in a floating state.
  • FIG. 3 shows a schematic diagram of a judgment circuit according to an embodiment of the disclosure.
  • the judgment circuit 140 also includes a detecting unit 144 and a sampling unit 143 .
  • the detecting unit 144 is coupled to the power pad 110 S.
  • the detecting unit 144 is controlled by the control signal S 1 to generate a detection signal S 2 according to the present state of the power pad 110 S.
  • the present state of the power pad 110 S includes, for example, as shown in FIG. 2 A and FIG. 3 , that the switch device SW is in a conduction state, and the power pad 110 S has a first power VDD; alternatively, the present state of the power pad 110 S includes, for example, as shown in FIG. 2 B , that the switch device SW is in a non-conductive state, and the power pad 110 S is in a floating state.
  • the detection signal S 2 includes the information of the present state of the above-mentioned power pad 110 S.
  • the sampling unit 143 is coupled to the detecting unit 144 .
  • the sampling unit 143 is configured to receive the detection signal S 2 .
  • the sampling unit 143 samples the detection signal S 2 to generate the judgment signal S 3 .
  • the judgment signal S 3 further indicates which data width that the memory chip 100 is in. For example, if the information of the detection signal S 2 is that the power pad 110 S has the first power VDD, the judgment signal S 3 may indicate that the data width of the memory chip 100 is, for example, ⁇ 16 as shown in FIG. 2 A .
  • the judgment signal S 3 may indicate that the data width of the memory chip 100 is, for example, ⁇ 8 as shown in FIG. 2 B .
  • the above-mentioned data widths of ⁇ 16 and ⁇ 8 are used for illustrative purposes only, and are not intended to limit the disclosure.
  • the control signal S 1 is, for example, provided by a controller circuit (not shown) of the memory chip 100
  • the judgment signal S 3 is, for example, output to the controller circuit.
  • the function of the bonding pad is combined into the power pad. That is, the power pad of the embodiment of the disclosure is not only used to receive power, but also endowed with the function of a bonding pad, allowing the user to determine the data width of the memory chip. In this way, in addition to maintaining convenience for users, it does not require an additional area of the memory chip to be occupied, which makes the use and layout of the memory chip more flexible.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Saccharide Compounds (AREA)

Abstract

Disclosed is a memory chip including a plurality of first power pads and a first bus. The first bus is connected to the first power pads. One of the first power pads is coupled to the first bus via a switch device. A data width of the memory chip is determined according to a conduction state of the switch device.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 112109992, filed on Mar. 17, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND Technical Field
The disclosure relates to a semiconductor chip, and more particularly to a memory chip.
Description of Related Art
Generally speaking, different requirements may be applied to the design of data width of memory chips according to application occasions. A memory chip should be designed to support the requirements of different data widths. When designing a memory chip, an additional bonding pad is usually added for users to determine the data width of the memory chip.
However, although adding an additional bonding pad makes it convenient for users to determine the data width, such approach is not suitable for memory chips with low density because a bonding pad meeting the specification of wire bonding will inevitably occupy a fixed area, and any additional bonding pad will cause redundancy. Moreover, the position of the bonding pad will further restrict the use and layout of the memory chip.
SUMMARY
The disclosure provides a memory chip, which does not require setting of an additional bonding pad, and allows users to determine the data width of the memory chip.
The memory chip of the disclosure includes multiple first power pads and a first bus. The first bus is connected to the first power pad. A power pad among the first power pads is coupled to the first bus through the switch device. The data width of the memory chip is determined according to the conduction state of the switch device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a schematic diagram of a memory chip according to an embodiment of the disclosure.
FIG. 2A is a schematic diagram of a memory chip having a first width when a switch device being turned on according to an embodiment of the disclosure.
FIG. 2B is a schematic diagram of the memory chip having a second width when the switch device of the embodiment of FIG. 2A being turned off.
FIG. 3 shows a schematic diagram of a judgment circuit according to an embodiment of the disclosure.
 DESCRIPTION OF THE EMBODIMENTS
Please refer to FIG. 1 , the memory chip 100 includes multiple first power pads 110, multiple second power pads 120, multiple data pads 130, a first bus 141 and a second bus 142. The first bus 141 is connected to the first power pad 110. The second bus 142 is connected to the second power pad 120.
The first bus 141 is configured to transmit the first power VDD, the second bus 142 is configured to transmit the second power VSS, and the first power VDD is greater than the second power VSS. The first power VDD and the second power VSS are, for example, operating voltages of internal circuits of the memory chip 100. In FIG. 1 , the first power pad 110 marked as VDD indicates that it is a pad electrically connected to the first bus 141 and configured to receive the first power VDD; the second power pad 120 marked as VSS indicates that it is a pad electrically connected to the second bus 142 for receiving the second power VSS. The pads labeled as CE and CLK indicate that they are configured to transmit signals CE and CLK.
The data pad 130 is configured to transmit the stored data of the memory chip. In FIG. 1 , the data pads 130 marked as DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, and DQ15 indicate that they are pads configured to transmit data bits DQ0 to DQ15. In this embodiment, it is taken as an example that the memory chip 100 includes 16 data pads 130, but the disclosure is not limited thereto. The design of the data width of the memory chip may have different requirements depending on the application occasion, and there are several conventional types of ×4, ×8, ×16, and ×32. The representation of ×16 means that the maximum transmission number of bits of the memory chip 100 is 16 bits, and the representations of ×4, ×8, and ×32 may be deduced in the same way. Therefore, in other embodiments, the memory chip 100 may have 4, 8 or 32 data pads, but the disclosure is not limited thereto.
Any one of the power pads in the embodiment shown in FIG. 1 may have a function as a bonding pad. That is to say, the power pad having the function of the bonding pad may not only be used to receive power, but also may be used by the user to determine the data width of the memory chip 100. The following will give at least one embodiment to further illustrate this concept.
FIG. 2A is a schematic diagram of a memory chip having a first width when a switch device being turned on according to an embodiment of the disclosure. FIG. 2B is a schematic diagram of the memory chip having a second width when the switch device of the embodiment of FIG. 2A being turned off. For brevity of description, FIG. 2A and FIG. 2B only show the first power pad 110 and the second power pad 120, but do not show the data pad, and the first power pad 110 and the second power pad 120 are spaced apart from each other. The data pads for transmitting the stored data may be distributed between the first power pad 110 and the second power pad 120. In this embodiment, there are, for example, 16 data pads, wherein 8 data pads are distributed between the first power pad 110 and the second power pad 120 of the two groups on the left, and the other 8 data pads are distributed between the first power pad 110 and the second power pads 120 of the two groups on the right.
In this embodiment, the power pad 110S among the first power pads 110 is coupled to the first bus 141 through the switch device SW, and the data width of the memory chip 100 is determined according to the conduction state of the switch device SW. For example, as shown in FIG. 2A, when the switch device SW is turned on, the data width of the memory chip 100 may be determined to be the first data width, such as 16 bits. As shown in FIG. 2B, when the switch device SW is turned off, the data width of the memory chip 100 may be determined to be the second data width, such as 8 bits. The first data width is larger than the second data width.
In this embodiment, it is taken as an example to design one of the first power pads as a bonding pad for users to determine the data width of the memory chip 100, but the disclosure is not limited thereto. In an embodiment, it is also taken as an example to design one of the second power pads as a bonding pad for users to determine the data width of the memory chip 100, the implementation may also be deduced in the same way.
In addition, the memory chip 100 further includes a judgment circuit 140. The judgment circuit 140 is coupled to the power pad 110S, that is, the power pad coupled to the switch device SW. The judgment circuit 140 is configured to judge the conduction state of the switch device SW. For example, when the judgment circuit 140 detects that the connection line L has the first power VDD, it means that the switch device SW is turned on, and the power pad 110S has the first power VDD at this time. When the judgment circuit 140 detects that the connection line L is floating, it means that the switch device SW is turned off, and the power pad 110S is also in a floating state.
Specifically, FIG. 3 shows a schematic diagram of a judgment circuit according to an embodiment of the disclosure. The judgment circuit 140 also includes a detecting unit 144 and a sampling unit 143. The detecting unit 144 is coupled to the power pad 110S. The detecting unit 144 is controlled by the control signal S1 to generate a detection signal S2 according to the present state of the power pad 110S. For example, the present state of the power pad 110S includes, for example, as shown in FIG. 2A and FIG. 3 , that the switch device SW is in a conduction state, and the power pad 110S has a first power VDD; alternatively, the present state of the power pad 110S includes, for example, as shown in FIG. 2B, that the switch device SW is in a non-conductive state, and the power pad 110S is in a floating state. The detection signal S2 includes the information of the present state of the above-mentioned power pad 110S.
The sampling unit 143 is coupled to the detecting unit 144. The sampling unit 143 is configured to receive the detection signal S2. After the detecting unit 144 is enabled by the control signal S1, the sampling unit 143 samples the detection signal S2 to generate the judgment signal S3. The judgment signal S3 further indicates which data width that the memory chip 100 is in. For example, if the information of the detection signal S2 is that the power pad 110S has the first power VDD, the judgment signal S3 may indicate that the data width of the memory chip 100 is, for example, ×16 as shown in FIG. 2A. On the other hand, if the detection signal S2 indicates that the power pad 110S is in a floating state, the judgment signal S3 may indicate that the data width of the memory chip 100 is, for example, ×8 as shown in FIG. 2B. The above-mentioned data widths of ×16 and ×8 are used for illustrative purposes only, and are not intended to limit the disclosure. The control signal S1 is, for example, provided by a controller circuit (not shown) of the memory chip 100, and the judgment signal S3 is, for example, output to the controller circuit.
To sum up, in the embodiment of the disclosure, the function of the bonding pad is combined into the power pad. That is, the power pad of the embodiment of the disclosure is not only used to receive power, but also endowed with the function of a bonding pad, allowing the user to determine the data width of the memory chip. In this way, in addition to maintaining convenience for users, it does not require an additional area of the memory chip to be occupied, which makes the use and layout of the memory chip more flexible.
Although the disclosure has been disclosed above with the embodiments, it is not intended to limit the disclosure. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure should be defined by the scope of the appended patent application.

Claims (9)

What is claimed is:
1. A memory chip, comprising:
a plurality of first power pads, configured to receive a first power;
a plurality of second power pads, configured to receive a second power different from the first power; and
a first bus, connected to the first power pads, wherein a power pad among the plurality of first power pads is coupled to the first bus through a switch device, and the power pad among the plurality of first power pads receiving the first power is disposed between two power pads among the plurality of second power pads receiving the second power, wherein a data width of the memory chip is determined according to a conduction state of the switch device,
wherein when the switch device is turned on, the data width of the memory chip is determined to be a first data width; and
when the switch device is turned off, the data width of the memory chip is determined to be a second data width.
2. The memory chip of claim 1, further comprising:
a second bus connected to the plurality of second power pads, wherein the first bus is configured to transmit the first power, and the second bus is configured to transmit the second power.
3. The memory chip of claim 2, wherein the first power is greater than the second power.
4. The memory chip of claim 2, wherein the plurality of first power pads and the plurality of second power pads are spaced apart from each other.
5. The memory chip of claim 4, further comprising a plurality of data pads for transmitting stored data of the memory chip, wherein the plurality of data pads are distributed between the plurality of first power pads and the plurality of second power pads.
6. The memory chip of claim 1, wherein the first data width is greater than the second data width.
7. The memory chip of claim 1, further comprising a judgment circuit coupled to the power pad coupled to the switch device, and the judgment circuit configured to judge the conduction state of the switch device.
8. The memory chip of claim 7, wherein the judgment circuit further comprises:
a detecting unit coupled to the power pad and being controlled by a control signal to generate a detection signal according to a present state of the power pad coupled to the switch device.
9. The memory chip of claim 8, wherein the judgment circuit further comprises:
a sampling unit, coupled to the detecting unit, configured to receive the detection signal, and sample the detection signal to generate a judgment signal after the control signal being enabled, wherein the judgment signal indicates the data width of the memory chip.
US18/303,580 2023-03-17 2023-04-20 Memory chip Active 2043-09-21 US12354693B2 (en)

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TW112109992 2023-03-17
TW112109992A TWI812578B (en) 2023-03-17 2023-03-17 Memory chip

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TW426519B (en) 1994-03-08 2001-03-21 Genetics Inst Methods and compositions for treatment of periodontal disease and repair of periodontal lesions
US20030080780A1 (en) * 2001-10-26 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Output circuit
US8004870B2 (en) * 2009-12-24 2011-08-23 Winbond Electronics Corp. Memory chips and judgment circuits thereof
US20120025898A1 (en) 2010-07-30 2012-02-02 Richwave Technology Corp. Circuit Device
US8400870B2 (en) * 2011-01-04 2013-03-19 Winbond Electronics Corp. Memory devices and accessing methods thereof

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US20240312555A1 (en) 2024-09-19
TWI812578B (en) 2023-08-11
TW202439157A (en) 2024-10-01

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