US12009817B2 - Flip-flop circuit, semiconductor integrated circuit device, and vehicle - Google Patents

Flip-flop circuit, semiconductor integrated circuit device, and vehicle Download PDF

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US12009817B2
US12009817B2 US17/898,690 US202217898690A US12009817B2 US 12009817 B2 US12009817 B2 US 12009817B2 US 202217898690 A US202217898690 A US 202217898690A US 12009817 B2 US12009817 B2 US 12009817B2
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inverter
flip
tri
flop circuit
pmos transistor
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US20230062075A1 (en
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Kazuya Ioki
Ryuichi Nakajima
Kazutoshi Kobayashi
Jun Furuta
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type

Definitions

  • the present disclosure relates to a flip-flop circuit, a semiconductor integrated circuit device including the flip-flop circuit, and a vehicle.
  • ISO26262 has been standardized for functional safety related to automobile electric/electronic systems, and the level of reliability required for semiconductor integrated circuit devices mounted on vehicles has been increasing.
  • a soft error is attracting attention as a cause of lowering the reliability of flip-flop circuits included in semiconductor integrated circuit devices.
  • the soft error occurs when radiation passes through or collides with a semiconductor integrated circuit device to generate electron-hole pairs and the holding values of memory elements are temporarily inverted.
  • a redundant flip-flop circuit having a configuration in which the flip-flop circuits are tripled and a majority decision circuit is connected to each flip-flop circuit is generally used.
  • the redundant flip-flop circuit even if output inversion occurs due to a soft error in one of three flip-flop circuits, if the remaining two hold a correct output value, a correct signal is output by the majority vote of the majority decision circuit.
  • the redundant flip-flop circuit significantly increases a circuit area, delay time, and power consumption as compared with a single flip-flop circuit. That is, the redundant flip-flop circuit has a problem that overheads of circuit area, delay time, and power consumption are large.
  • a conventional flip-flop circuit improves soft error resistance by generating output data of the flip-flop circuit by a majority decision based on output data from a master latch circuit and two output data from two slave latch circuits.
  • the flip-flop circuit can suppress the overheads of circuit area, delay time, and power consumption as compared with the above-described redundant flip-flop circuit.
  • the flip-flop circuit has room for improvement in terms of overhead suppression of circuit area, delay time, and power consumption. Further, the flip-flop circuit can detect and correct soft errors only in a clock stop state.
  • a flip-flop circuit includes: a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; a slave latch including a second inverter and a second ti-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second
  • a semiconductor integrated circuit device includes the flip-flop circuit.
  • a vehicle includes the semiconductor integrated circuit device.
  • FIG. 1 is a diagram showing a configuration example of a general flip-flop circuit.
  • FIG. 2 is a diagram showing the configuration of a flip-flop circuit according to a first embodiment.
  • FIG. 3 A is a diagram showing the configuration of a flip-flop circuit according to a second embodiment.
  • FIG. 3 B is a diagram showing a configuration example of a circuit having a structure with a set.
  • FIG. 4 is a diagram showing the configuration of a flip-flop circuit according to a third embodiment.
  • FIG. 5 is a diagram showing the configuration of a flip-flop circuit according to a fourth embodiment.
  • FIG. 6 is a diagram showing the configuration of a flip-flop circuit according to a fifth embodiment.
  • FIG. 7 is a diagram showing the schematic configuration of a switching power supply device.
  • FIG. 8 is an external view of a vehicle.
  • a MOS transistor refers to a transistor whose gate structure consists of at least three layers of “a layer formed of a conductor or a semiconductor such as polysilicon having a small resistance value,” an “insulating layer,” and a “P-type, N-type, or intrinsic semiconductor layer.” That is, the gate structure of the MOS transistor is not limited to the three-layer structure of metal, oxide, and semiconductor.
  • FIG. 1 is a diagram showing a configuration example of the general flip-flop circuit.
  • the general flip-flop circuit 100 (hereinafter referred to as a “flip-flop circuit 100 ”) shown in FIG. 1 is a D-type flip-flop circuit.
  • the flip-flop circuit 100 includes inverters INV 0 , INV 1 , INV 2 , and INV 5 , transmission gates TG 1 and TG 2 , a master latch ML 1 , and a slave latch SL 1 .
  • the inverters INV 0 and INV 1 are connected in series in two stages to generate a clock signal CLK and an inverted clock signal CLK , which is an inversion of the clock signal CLK, from an input clock signal CP.
  • the inverter INV 0 includes a PMOS transistor p 0 and an NMOS transistor n 0 which are sequentially connected in series from a power supply potential VC side to a reference potential side.
  • the inverter INV 1 includes a PMOS transistor p 1 and an NMOS transistor n 1 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the reference potential is lower than the power supply potential VC.
  • the inverter INV 2 generates an inversion of a data signal D from the data signal D.
  • the inverter INV 2 includes a PMOS transistor p 2 and an NMOS transistor n 2 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the inversion of the data signal D is supplied to an input terminal of the transmission gate TG 1 .
  • An output terminal of the transmission gate TG 1 is connected to an input terminal of the master latch ML 1 .
  • the transmission gate TG 1 is a switch circuit that turns on when the clock signal CLK is at a LOW level and turns off when the clock signal CLK is at a HIGH level.
  • the transmission gate TG 1 includes a PMOS transistor p 3 and an NMOS transistor n 3 .
  • One of a source and a drain of the PMOS transistor p 3 is the input terminal of the transmission gate TG 1 , and the other is the output terminal of the transmission gate TG 1 .
  • One of a source and a drain of the NMOS transistor n 3 is the input terminal of the transmission gate TG 1 , and the other is the output terminal of the transmission gate TGT.
  • An output terminal of the master latch ML 1 is connected to an input terminal of the transmission gate TG 2 .
  • An output terminal of the transmission gate TG 2 is connected to an input terminal of the slave latch SL 1 .
  • the transmission gate TG 2 is a switch circuit that turns on when the clock signal CLK is at the HIGH level and turns off when the clock signal CLK is at the LOW level.
  • the transmission gate TG 2 includes a PMOS transistor p 7 and an NMOS transistor n 7 .
  • One of a source and a drain of the PMOS transistor p 7 is the input terminal of the transmission gate TG 2 , and the other is the output terminal of the transmission gate TG 2 .
  • One of a source and a drain of the NMOS transistor n 7 is the input terminal of the transmission gate TG 2 , and the other is the output terminal of the transmission gate TG 2 .
  • slave latch SL 1 Details of the slave latch SL 1 will be described later.
  • the inverter INV 5 outputs a signal Q which is an inversion of an output signal of the slave latch SL 1 .
  • the inverter INV 5 includes a PMOS transistor p 11 and an NMOS transistor n 11 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the master latch ML 1 includes an inverter INV 3 and a tri-state inverter TS 1 .
  • the master latch ML 1 maintains (or holds) a signal input to the master latch ML 1 .
  • An input terminal of the inverter INV 3 and an output terminal of the tri-state inverter TS 1 are the input terminal of the master latch ML 1 .
  • An output terminal of the inverter INV 3 and an input terminal of the tri-state inverter TS 1 are the output terminal of the master latch ML 1 .
  • the inverter INV 3 includes a PMOS transistor p 4 and an NMOS transistor n 4 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the tri-state inverter TS 1 outputs a signal, which is an inversion of an output signal of the inverter INV 3 , when the clock signal CLK is at the HIGH level, and is in a high impedance state when the clock signal CLK is at the LOW level.
  • the tri-state inverter TS 1 includes a PMOS transistor p 5 , a PMOS transistor p 6 , an NMOS transistor n 5 , and an NMOS transistor n 6 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the output signal of the inverter INV 3 is supplied to each of gates of the PMOS transistor p 5 and the NMOS transistor n 6 , the inverted clock signal CLK is supplied to a gate of the PMOS transistor p 6 , and the clock signal CLK is supplied to a gate of the NMOS transistor n 5 .
  • the slave latch SL 1 includes an inverter INV 4 and a tri-state inverter TS 2 .
  • the slave latch SL 1 maintains (or holds) a signal input to the slave latch SL 1 .
  • An input terminal of the inverter INV 4 and an output terminal of the tri-state inverter TS 2 are the input terminal of the slave latch SL 1 .
  • An output terminal of the inverter INV 4 and an input terminal of the tri-state inverter TS 2 are the output terminal of the slave latch SL 1 .
  • the inverter INV 4 includes a PMOS transistor p 8 and an NMOS transistor n 8 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • the tri-state inverter TS 2 outputs a signal, which is an inversion of an output signal of the inverter INV 4 , when the clock signal CLK is at the LOW level, and is in a high impedance state when the clock signal CLK is at the HIGH level.
  • the tri-state inverter TS 2 includes a PMOS transistor p 9 , a PMOS transistor p 10 , an NMOS transistor n 9 , and an NMOS transistor n 10 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
  • An output signal of the inverter INV 4 is supplied to each of gates of the PMOS transistor p 9 and the NMOS transistor n 10 , the clock signal CLK is supplied to a gate of the PMOS transistor p 10 , and the inverted clock signal CLK is supplied to a gate of the NMOS transistor n 9 .
  • FIG. 2 is a diagram showing a configuration example of a flip-flop circuit according to a first embodiment.
  • the flip-flop circuit 101 is a D-type flip-flop circuit.
  • the flip-flop circuit 101 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1 A and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1 A.
  • the master latch ML 1 A has a configuration in which a wiring L 1 is added to the tri-state inverter TS 1 in the master latch ML 1 .
  • the wiring L 1 is configured to connect a source of the PMOS transistor p 6 and a source of the NMOS transistor n 5 .
  • the source of the PMOS transistor p 6 and the source of the NMOS transistor n 5 are connected in parallel, so that the amount of current flowing out to an output of the tri-state inverter TS 1 increases. That is, the addition of the wiring L 1 improves a driving force of the tri-state inverter TS 1 .
  • the vulnerability of the tri-state inverter TS 1 to radiation can be improved, and the influence of radiation on the master latch ML 1 A can be suppressed.
  • the slave latch SL 1 A has a configuration in which a wiring L 2 is added to the tri-state inverter TS 2 in the slave latch SL 1 .
  • the wiring L 2 is configured to connect a source of the PMOS transistor p 10 and a source of the NMOS transistor n 9 .
  • the source of the PMOS transistor p 10 and the source of the NMOS transistor n 9 are connected in parallel, so that the amount of current flowing out to an output of the tri-state inverter TS 2 increases. That is, the addition of the wiring L 2 improves a driving force of the tri-state inverter TS 2 .
  • the vulnerability of the tri-state inverter TS 2 to radiation can be improved, and the influence of radiation on the slave latch SL 1 A can be suppressed.
  • a critical charge amount Q crit at each of output points of the tri-state inverters TS 1 and TS 2 of the flip-flop circuit 101 is larger than the critical charge amount Q crit at each of output points of the tri-state inverters TS 1 and TS 2 of the flip-flop circuit 100 . That is, it has been confirmed from the circuit simulation that the addition of the wirings L 1 and L 2 improves the vulnerability of the tri-state inverters TS 1 and TS 2 to radiation.
  • the flip-flop circuit 101 has a configuration in which the wirings L 1 and L 2 are added to the flip-flop circuit 100 , overheads of circuit area, delay time, and power consumption can be suppressed as compared with a redundant flip-flop circuit.
  • the flip-flop circuit 101 has a configuration in which both the wirings L 1 and L 2 are added to the flip-flop circuit 100 , but the flip-flop circuit 101 may have a configuration in which one of the wirings L 1 and L 2 is added to the flip-flop circuit 100 . It is considered that the soft error resistance can be improved as compared with the flip-flop circuit 100 even if one of the wirings L 1 and L 2 is added.
  • FIG. 3 A is a diagram showing a configuration example of a flip-flop circuit according to a second embodiment.
  • the flip-flop circuit 102 is a D-type flip-flop circuit.
  • the flip-flop circuit 102 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1 B and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1 B.
  • the master latch ML 1 B has a configuration in which the tri-state inverter TS 1 in the master latch ML 1 is replaced with a tri-state inverter TS 1 ′.
  • the slave latch SL 1 B has a configuration in which the tri-state inverter TS 2 in the slave latch SL 1 is replaced with a tri-state inverter TS 2 ′.
  • the tri-state inverter TS 1 ′ has a configuration in which an NMOS transistor n 12 is added to the tri-state inverter TS 1 .
  • the NMOS transistor n 12 is provided between the NMOS transistor n 5 and the NMOS transistor n 6 .
  • An output signal of the inverter INV 3 is supplied to a gate of the NMOS transistor n 12 .
  • the tri-state inverter TS 2 ′ has a configuration in which an NMOS transistor n 13 is added to the tri-state inverter TS 2 .
  • the NMOS transistor n 13 is provided between the NMOS transistor n 9 and the NMOS transistor n 10 .
  • An output signal of the inverter INV 4 is supplied to a gate of the NMOS transistor n 13 .
  • a circuit having a structure with a set or with a reset are more resistant to a soft error than a circuit having a structure without a set and a reset.
  • An example of the circuit having a structure with a set or a reset may include a circuit having a structure with a set shown in FIG. 3 B .
  • the circuit shown in FIG. 3 B includes PMOS transistors Q 1 to Q 3 and NMOS transistors Q 4 to Q 6 .
  • an inverted set signal SET which is an inversion of a set signal SET, is at a LOW level
  • the PMOS transistor Q 2 is turned on and the NMOS transistor Q 5 is turned off.
  • the flip-flop circuit 102 adopts the series connection of the NMOS transistors existing in the circuit having the structure with the set or the reset to improve the soft error resistance.
  • NMOS transistor n 12 By providing the NMOS transistor n 12 between the NMOS transistor n 5 and the NMOS transistor n 6 , it is possible to prevent an output point of the tri-state inverter TS 1 ′ from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error due to the parasitic bipolar effect can be suppressed by providing the NMOS transistor n 12 between the NMOS transistor n 5 and the NMOS transistor n 6 . Further, by providing the NMOS transistor n 13 between the NMOS transistor n 9 and the NMOS transistor n 10 , it is possible to prevent an output point of the tri-state inverter TS 2 ′ from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error due to the parasitic bipolar effect can be suppressed by providing the NMOS transistor n 13 between the NMOS transistor n 9 and the NMOS transistor n 10 .
  • the flip-flop circuit 102 has a configuration in which the NMOS transistors n 12 and n 13 are added to the flip-flop circuit 100 , the overheads of circuit area, delay time, and power consumption are suppressed as compared with a redundant flip-flop circuit.
  • the flip-flop circuit 102 has a configuration in which both the NMOS transistors n 12 and n 13 are added to the flip-flop circuit 100 , but the flip-flop circuit 102 may have a configuration in which one of the NMOS transistors n 12 and n 13 is added. It is considered that the soft error resistance can be improved as compared with the flip-flop circuit 100 even if one of the NMOS transistors n 12 and n 13 is added.
  • FIG. 4 is a diagram showing a configuration example of a flip-flop circuit according to a third embodiment.
  • the flip-flop circuit 103 is a D-type flip-flop circuit.
  • the flip-flop circuit 103 has a configuration in which the master latch ML 1 B in the flip-flop circuit 102 is replaced with a master latch ML 1 C and the slave latch SL 1 B in the flip-flop circuit 102 is replaced with a slave latch SL 1 C.
  • the master latch ML 1 C has a configuration in which a PMOS transistor p 12 is added to the master latch ML 1 B.
  • the slave latch SL 1 C has a configuration in which a PMOS transistor p 13 is added to the slave latch SL 1 B.
  • the PMOS transistor p 12 is connected in parallel to the PMOS transistor p 4 .
  • the gate of the PMOS transistor p 12 is connected to the output terminal of the ti-state inverter TS 1 ′.
  • the PMOS transistor p 13 is connected in parallel to the PMOS transistor p 8 .
  • the gate of the PMOS transistor p 13 is connected to the output terminal of the tri-state inverter TS 2 ′.
  • the soft error resistance of the flip-flop circuit 103 is improved as compared with the soft error resistance of the flip-flop circuit 102 .
  • FIG. 5 is a diagram showing a configuration example of a flip-flop circuit according to a fourth embodiment.
  • the flip-flop circuit 104 is a D-type flip-flop circuit.
  • the flip-flop circuit 104 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1 D and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1 D.
  • the master latch ML 1 D has a configuration in which the master latch ML 1 A of the first embodiment and the master latch ML 1 B of the second embodiment are combined.
  • the slave latch SL 1 D has a configuration in which the slave latch SL 1 A of the first embodiment and the slave latch SL 1 B of the second embodiment are combined.
  • the flip-flop circuit 104 is designed to further improve the soft error resistance as compared with the flip-flop circuit 101 .
  • FIG. 6 is a diagram showing a configuration example of a flip-flop circuit according to a fifth embodiment.
  • the flip-flop circuit 105 is a D-type flip-flop circuit.
  • the flip-flop circuit 105 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1 E and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1 E.
  • the master latch ML 1 E has a configuration in which the master latch ML 1 A of the first embodiment and the master latch ML 1 C of the third embodiment are combined.
  • the slave latch SL 1 E has a configuration in which the slave latch SL 1 A of the first embodiment and the slave latch SL 1 C of the third embodiment are combined.
  • the flip-flop circuit 105 is designed to further improve the soft error resistance as compared with the flip-flop circuit 101 .
  • the above-described flip-flop circuits can be used, for example, in a switching power supply device shown in FIG. 7 .
  • the switching power supply device shown in FIG. 7 is a step-down DC/DC converter with a bottom detection on-time fix system that steps down an input voltage Vin to generate a desired output voltage Vout.
  • the driver 22 executes an operation according to an output of a current sensor, a temperature sensor, or the like in order to realize an overcurrent protection function, an overheat protection function, or the like.
  • the driver 22 is a power supply control circuit that controls a state of a bottom detection on-time fix system switching power supply device, and the driver 22 includes the above-described flip-flop circuits.
  • a comparator 21 for comparing the feedback voltage Vfb and the reference voltage Vref, the driver 22 , and the on-time setting circuit 23 are provided in a semiconductor integrated circuit device 24 .
  • the above-described flip-flop circuits can also be used for a switching power supply device other than the bottom detection on-time fix system. Further, the above-described flip-flop circuits can be used not only for a switching power supply device but also for, for example, a motor drive device.
  • FIG. 8 is an external view showing a configuration example of a vehicle equipped with in-vehicle apparatuses.
  • the vehicle 300 of this configuration example is equipped with in-vehicle apparatuses X 11 to X 17 and a battery (not shown) for supplying electric power to these in-vehicle apparatuses X 11 to X 17 .
  • the in-vehicle apparatus X 11 is an electronic controller that performs engine-related control (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).
  • engine-related control injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.
  • the in-vehicle apparatus X 12 is a lamp controller that performs lighting-on/off control of HID [High Intensity Discharged Lamp], DRL [Daytime Running Lamp], etc.
  • the in-vehicle apparatus X 13 is a transmission controller that performs transmission-related control.
  • the in-vehicle apparatus X 14 is a body controller that performs control related to the motion of the vehicle X (ABS [Anti-lock Brake System] control, EPS [Electric Power Steering] control, electronic suspension control, etc.).
  • ABS Anti-lock Brake System
  • EPS Electronic Power Steering
  • the in-vehicle apparatus X 15 is a security controller that performs drive control of a door lock, a security alarm, etc.
  • the in-vehicle apparatus X 16 is an electronic apparatus incorporated in the vehicle X at the factory shipment stage, as standard equipment or manufacturer's options such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, an air conditioner, etc.
  • the in-vehicle apparatus X 17 is an electronic apparatus that is mounted on the vehicle X, as user's options such as an in-vehicle A/V [Audio/Visual] apparatus, a car navigation system, an ETC [Electronic Toll Collection] system, etc.
  • the above-described switching power supply device 200 can be incorporated into any of the in-vehicle apparatuses X 11 to X 17 .
  • the soft error resistance of the flip-flop circuit can be improved.
  • the gate widths of all MOS transistors are increased, the efficiency of improvement of the soft error resistance with respect to the size of the circuit area is not good.
  • a flip-flop circuit ( 101 , 104 , 105 ) has a configuration (first configuration) that includes: a master latch (ML 1 A, ML 1 D, ML 1 E) including a first inverter (INV 3 ) and a first tri-state inverter (TS 1 , TS 1 ′) configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor (n 5 ) configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor (p 6 ) configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; a slave latch (SL 1 A, SL 1 D, SL 1 E) including a second inverter (IN
  • the flip-flop circuit having the first configuration can improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.
  • the flip-flop circuit of the first configuration may have a configuration (second configuration) that the first tri-state inverter includes two NMOS transistors (n 6 , n 12 ) directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.
  • the flip-flop circuit having the second configuration can further improve the soft error resistance as compared with the flip-flop circuit having the first configuration.
  • the flip-flop circuit of the second configuration may have a configuration (third configuration) that further includes: a PMOS transistor (p 12 ) connected in parallel to the PMOS transistor (p 4 ) included in the first inverter and configured such that the output terminal of the first tri-state inverter is connected to a gate of the connected PMOS transistor.
  • the flip-flop circuit having the third configuration can further improve the soft error resistance as compared with the flip-flop circuit having the second configuration.
  • the flip-flop circuit of any one of the first to third configurations may have a configuration (fourth configuration) that the second ti-state inverter includes two NMOS transistors (n 10 , n 13 ) directly connected to each other and configured such that output of the second inverter is input to gates of the two NMOS transistors.
  • the flip-flop circuit having the fourth configuration can further improve the soft error resistance as compared with the flip-flop circuit having the first configuration.
  • the flip-flop circuit of the fourth configuration may have a configuration (fifth configuration) that further includes: a PMOS transistor (p 13 ) connected in parallel to the PMOS transistor (p 8 ) included in the second inverter and configured such that the output terminal of the second tri-state inverter is connected to a gate of the PMOS transistor.
  • the flip-flop circuit having the fifth configuration can further improve the soft error resistance as compared with the flip-flop circuit having the fourth configuration.
  • a flip-flop circuit ( 102 , 103 ) has a configuration (sixth configuration) that includes: a master latch (ML 1 B, ML 1 C) including a first inverter (INV 3 ) and a first tri-state inverter (TS 1 ′) configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor (n 5 ) configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor (p 6 ) configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; and a slave latch (SL 1 B, SL 1 C) including a second inverter (INV 4 ) and a second tri-state inverter (
  • the flip-flop circuit having the sixth configuration can improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.
  • a semiconductor integrated circuit device ( 24 ) has a configuration (seventh configuration) that includes a flip-flop circuit of any one of the first to sixth configurations.
  • the semiconductor integrated circuit device having the seventh configuration can improve soft error resistance of the flip-flop circuit while suppressing the overheads of circuit area, delay time, and power consumption of the flip-flop circuit.
  • a vehicle ( 300 ) has a configuration (eighth configuration) that includes a semiconductor integrated circuit device of the seventh configuration.
  • the vehicle having the eighth configuration can improve soft error resistance of the flip-flop circuit while suppressing the overheads of circuit area, delay time, and power consumption of the flip-flop circuit.
  • the flip-flop circuit the semiconductor integrated circuit device, and the vehicle disclosed in the present disclosure, it is possible to improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.

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  • Static Random-Access Memory (AREA)

Abstract

A flip-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-141436, filed on Aug. 31, 2021, the entire contents of which are incorporated herein by reference.
TECHNICAL FIELD
The present disclosure relates to a flip-flop circuit, a semiconductor integrated circuit device including the flip-flop circuit, and a vehicle.
BACKGROUND
ISO26262 has been standardized for functional safety related to automobile electric/electronic systems, and the level of reliability required for semiconductor integrated circuit devices mounted on vehicles has been increasing.
A soft error is attracting attention as a cause of lowering the reliability of flip-flop circuits included in semiconductor integrated circuit devices. The soft error occurs when radiation passes through or collides with a semiconductor integrated circuit device to generate electron-hole pairs and the holding values of memory elements are temporarily inverted.
As a countermeasure against the soft error in the flip-flop circuits, a redundant flip-flop circuit having a configuration in which the flip-flop circuits are tripled and a majority decision circuit is connected to each flip-flop circuit is generally used. In the redundant flip-flop circuit, even if output inversion occurs due to a soft error in one of three flip-flop circuits, if the remaining two hold a correct output value, a correct signal is output by the majority vote of the majority decision circuit.
However, the redundant flip-flop circuit significantly increases a circuit area, delay time, and power consumption as compared with a single flip-flop circuit. That is, the redundant flip-flop circuit has a problem that overheads of circuit area, delay time, and power consumption are large.
A conventional flip-flop circuit improves soft error resistance by generating output data of the flip-flop circuit by a majority decision based on output data from a master latch circuit and two output data from two slave latch circuits. The flip-flop circuit can suppress the overheads of circuit area, delay time, and power consumption as compared with the above-described redundant flip-flop circuit. However, the flip-flop circuit has room for improvement in terms of overhead suppression of circuit area, delay time, and power consumption. Further, the flip-flop circuit can detect and correct soft errors only in a clock stop state.
SUMMARY
According to one embodiment of the present disclosure, a flip-flop circuit includes: a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; a slave latch including a second inverter and a second ti-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.
According to one embodiment of the present disclosure, a semiconductor integrated circuit device includes the flip-flop circuit.
According to one embodiment of the present disclosure, a vehicle includes the semiconductor integrated circuit device.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a diagram showing a configuration example of a general flip-flop circuit.
FIG. 2 is a diagram showing the configuration of a flip-flop circuit according to a first embodiment.
FIG. 3A is a diagram showing the configuration of a flip-flop circuit according to a second embodiment.
FIG. 3B is a diagram showing a configuration example of a circuit having a structure with a set.
FIG. 4 is a diagram showing the configuration of a flip-flop circuit according to a third embodiment.
FIG. 5 is a diagram showing the configuration of a flip-flop circuit according to a fourth embodiment.
FIG. 6 is a diagram showing the configuration of a flip-flop circuit according to a fifth embodiment.
FIG. 7 is a diagram showing the schematic configuration of a switching power supply device.
FIG. 8 is an external view of a vehicle.
 DETAILED DESCRIPTION
In the present disclosure, a MOS transistor refers to a transistor whose gate structure consists of at least three layers of “a layer formed of a conductor or a semiconductor such as polysilicon having a small resistance value,” an “insulating layer,” and a “P-type, N-type, or intrinsic semiconductor layer.” That is, the gate structure of the MOS transistor is not limited to the three-layer structure of metal, oxide, and semiconductor.
<General Flip-Flop Circuit>
Prior to describing embodiments of the present disclosure, a general flip-flop circuit will be described. FIG. 1 is a diagram showing a configuration example of the general flip-flop circuit.
The general flip-flop circuit 100 (hereinafter referred to as a “flip-flop circuit 100”) shown in FIG. 1 is a D-type flip-flop circuit. The flip-flop circuit 100 includes inverters INV0, INV1, INV2, and INV5, transmission gates TG1 and TG2, a master latch ML1, and a slave latch SL1.
The inverters INV0 and INV1 are connected in series in two stages to generate a clock signal CLK and an inverted clock signal CLK, which is an inversion of the clock signal CLK, from an input clock signal CP. The inverter INV0 includes a PMOS transistor p0 and an NMOS transistor n0 which are sequentially connected in series from a power supply potential VC side to a reference potential side. The inverter INV1 includes a PMOS transistor p1 and an NMOS transistor n1 which are sequentially connected in series from the power supply potential VC side to the reference potential side. The reference potential is lower than the power supply potential VC.
The inverter INV2 generates an inversion of a data signal D from the data signal D. The inverter INV2 includes a PMOS transistor p2 and an NMOS transistor n2 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
The inversion of the data signal D is supplied to an input terminal of the transmission gate TG1. An output terminal of the transmission gate TG1 is connected to an input terminal of the master latch ML1.
The transmission gate TG1 is a switch circuit that turns on when the clock signal CLK is at a LOW level and turns off when the clock signal CLK is at a HIGH level. The transmission gate TG1 includes a PMOS transistor p3 and an NMOS transistor n3. One of a source and a drain of the PMOS transistor p3 is the input terminal of the transmission gate TG1, and the other is the output terminal of the transmission gate TG1. One of a source and a drain of the NMOS transistor n3 is the input terminal of the transmission gate TG1, and the other is the output terminal of the transmission gate TGT.
Details of the master latch ML1 will be described later.
An output terminal of the master latch ML1 is connected to an input terminal of the transmission gate TG2. An output terminal of the transmission gate TG2 is connected to an input terminal of the slave latch SL1.
The transmission gate TG2 is a switch circuit that turns on when the clock signal CLK is at the HIGH level and turns off when the clock signal CLK is at the LOW level. The transmission gate TG2 includes a PMOS transistor p7 and an NMOS transistor n7. One of a source and a drain of the PMOS transistor p7 is the input terminal of the transmission gate TG2, and the other is the output terminal of the transmission gate TG2. One of a source and a drain of the NMOS transistor n7 is the input terminal of the transmission gate TG2, and the other is the output terminal of the transmission gate TG2.
Details of the slave latch SL1 will be described later.
The inverter INV5 outputs a signal Q which is an inversion of an output signal of the slave latch SL1. The inverter INV5 includes a PMOS transistor p11 and an NMOS transistor n11 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
The master latch ML1 includes an inverter INV3 and a tri-state inverter TS1. The master latch ML1 maintains (or holds) a signal input to the master latch ML1.
An input terminal of the inverter INV3 and an output terminal of the tri-state inverter TS1 are the input terminal of the master latch ML1. An output terminal of the inverter INV3 and an input terminal of the tri-state inverter TS1 are the output terminal of the master latch ML1.
The inverter INV3 includes a PMOS transistor p4 and an NMOS transistor n4 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
The tri-state inverter TS1 outputs a signal, which is an inversion of an output signal of the inverter INV3, when the clock signal CLK is at the HIGH level, and is in a high impedance state when the clock signal CLK is at the LOW level. The tri-state inverter TS1 includes a PMOS transistor p5, a PMOS transistor p6, an NMOS transistor n5, and an NMOS transistor n6 which are sequentially connected in series from the power supply potential VC side to the reference potential side. The output signal of the inverter INV3 is supplied to each of gates of the PMOS transistor p5 and the NMOS transistor n6, the inverted clock signal CLK is supplied to a gate of the PMOS transistor p6, and the clock signal CLK is supplied to a gate of the NMOS transistor n5.
The slave latch SL1 includes an inverter INV4 and a tri-state inverter TS2. The slave latch SL1 maintains (or holds) a signal input to the slave latch SL1.
An input terminal of the inverter INV4 and an output terminal of the tri-state inverter TS2 are the input terminal of the slave latch SL1. An output terminal of the inverter INV4 and an input terminal of the tri-state inverter TS2 are the output terminal of the slave latch SL1.
The inverter INV4 includes a PMOS transistor p8 and an NMOS transistor n8 which are sequentially connected in series from the power supply potential VC side to the reference potential side.
The tri-state inverter TS2 outputs a signal, which is an inversion of an output signal of the inverter INV4, when the clock signal CLK is at the LOW level, and is in a high impedance state when the clock signal CLK is at the HIGH level. The tri-state inverter TS2 includes a PMOS transistor p9, a PMOS transistor p10, an NMOS transistor n9, and an NMOS transistor n10 which are sequentially connected in series from the power supply potential VC side to the reference potential side. An output signal of the inverter INV4 is supplied to each of gates of the PMOS transistor p9 and the NMOS transistor n10, the clock signal CLK is supplied to a gate of the PMOS transistor p10, and the inverted clock signal CLK is supplied to a gate of the NMOS transistor n9.
<Flip-Flop Circuit According to First Embodiment>
FIG. 2 is a diagram showing a configuration example of a flip-flop circuit according to a first embodiment.
The flip-flop circuit 101 according to the first embodiment shown in FIG. 2 (hereinafter referred to as a “flip-flop circuit 101”) is a D-type flip-flop circuit. The flip-flop circuit 101 has a configuration in which the master latch ML1 in the flip-flop circuit 100 is replaced with a master latch ML1A and the slave latch SL1 in the flip-flop circuit 100 is replaced with a slave latch SL1A.
The master latch ML1A has a configuration in which a wiring L1 is added to the tri-state inverter TS1 in the master latch ML1. The wiring L1 is configured to connect a source of the PMOS transistor p6 and a source of the NMOS transistor n5. By adding the wiring L1 to the tri-state inverter TS1 which is vulnerable to radiation, the source of the PMOS transistor p6 and the source of the NMOS transistor n5 are connected in parallel, so that the amount of current flowing out to an output of the tri-state inverter TS1 increases. That is, the addition of the wiring L1 improves a driving force of the tri-state inverter TS1. By improving the driving force of the tri-state inverter TS1, the vulnerability of the tri-state inverter TS1 to radiation can be improved, and the influence of radiation on the master latch ML1A can be suppressed.
The slave latch SL1A has a configuration in which a wiring L2 is added to the tri-state inverter TS2 in the slave latch SL1. The wiring L2 is configured to connect a source of the PMOS transistor p10 and a source of the NMOS transistor n9. By adding the wiring L2 to the tri-state inverter TS2 which is vulnerable to radiation, the source of the PMOS transistor p10 and the source of the NMOS transistor n9 are connected in parallel, so that the amount of current flowing out to an output of the tri-state inverter TS2 increases. That is, the addition of the wiring L2 improves a driving force of the tri-state inverter TS2. By improving the driving force of the tri-state inverter TS2, the vulnerability of the tri-state inverter TS2 to radiation can be improved, and the influence of radiation on the slave latch SL1A can be suppressed.
According to a circuit simulation, it has been confirmed that a critical charge amount Qcrit at each of output points of the tri-state inverters TS1 and TS2 of the flip-flop circuit 101 is larger than the critical charge amount Qcrit at each of output points of the tri-state inverters TS1 and TS2 of the flip-flop circuit 100. That is, it has been confirmed from the circuit simulation that the addition of the wirings L1 and L2 improves the vulnerability of the tri-state inverters TS1 and TS2 to radiation.
Further, since the flip-flop circuit 101 has a configuration in which the wirings L1 and L2 are added to the flip-flop circuit 100, overheads of circuit area, delay time, and power consumption can be suppressed as compared with a redundant flip-flop circuit.
The flip-flop circuit 101 has a configuration in which both the wirings L1 and L2 are added to the flip-flop circuit 100, but the flip-flop circuit 101 may have a configuration in which one of the wirings L1 and L2 is added to the flip-flop circuit 100. It is considered that the soft error resistance can be improved as compared with the flip-flop circuit 100 even if one of the wirings L1 and L2 is added.
<Flip-Flop Circuit According to Second Embodiment>
FIG. 3A is a diagram showing a configuration example of a flip-flop circuit according to a second embodiment.
The flip-flop circuit 102 according to the second embodiment shown in FIG. 3A (hereinafter referred to as a “flip-flop circuit 102”) is a D-type flip-flop circuit. The flip-flop circuit 102 has a configuration in which the master latch ML1 in the flip-flop circuit 100 is replaced with a master latch ML1B and the slave latch SL1 in the flip-flop circuit 100 is replaced with a slave latch SL1B.
The master latch ML1B has a configuration in which the tri-state inverter TS1 in the master latch ML1 is replaced with a tri-state inverter TS1′. The slave latch SL1B has a configuration in which the tri-state inverter TS2 in the slave latch SL1 is replaced with a tri-state inverter TS2′.
The tri-state inverter TS1′ has a configuration in which an NMOS transistor n12 is added to the tri-state inverter TS1. The NMOS transistor n12 is provided between the NMOS transistor n5 and the NMOS transistor n6. An output signal of the inverter INV3 is supplied to a gate of the NMOS transistor n12.
The tri-state inverter TS2′ has a configuration in which an NMOS transistor n13 is added to the tri-state inverter TS2. The NMOS transistor n13 is provided between the NMOS transistor n9 and the NMOS transistor n10. An output signal of the inverter INV4 is supplied to a gate of the NMOS transistor n13.
Alpha ray irradiation tests have shown that a circuit having a structure with a set or with a reset are more resistant to a soft error than a circuit having a structure without a set and a reset. An example of the circuit having a structure with a set or a reset may include a circuit having a structure with a set shown in FIG. 3B. The circuit shown in FIG. 3B includes PMOS transistors Q1 to Q3 and NMOS transistors Q4 to Q6. In the circuit shown in FIG. 3B, when an inverted set signal SET, which is an inversion of a set signal SET, is at a LOW level, the PMOS transistor Q2 is turned on and the NMOS transistor Q5 is turned off.
Therefore, the flip-flop circuit 102 adopts the series connection of the NMOS transistors existing in the circuit having the structure with the set or the reset to improve the soft error resistance.
By providing the NMOS transistor n12 between the NMOS transistor n5 and the NMOS transistor n6, it is possible to prevent an output point of the tri-state inverter TS1′ from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error due to the parasitic bipolar effect can be suppressed by providing the NMOS transistor n12 between the NMOS transistor n5 and the NMOS transistor n6. Further, by providing the NMOS transistor n13 between the NMOS transistor n9 and the NMOS transistor n10, it is possible to prevent an output point of the tri-state inverter TS2′ from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error due to the parasitic bipolar effect can be suppressed by providing the NMOS transistor n13 between the NMOS transistor n9 and the NMOS transistor n10.
Further, since the flip-flop circuit 102 has a configuration in which the NMOS transistors n12 and n13 are added to the flip-flop circuit 100, the overheads of circuit area, delay time, and power consumption are suppressed as compared with a redundant flip-flop circuit.
The flip-flop circuit 102 has a configuration in which both the NMOS transistors n12 and n13 are added to the flip-flop circuit 100, but the flip-flop circuit 102 may have a configuration in which one of the NMOS transistors n12 and n13 is added. It is considered that the soft error resistance can be improved as compared with the flip-flop circuit 100 even if one of the NMOS transistors n12 and n13 is added.
<Flip-Flop Circuit According to Third Embodiment>
FIG. 4 is a diagram showing a configuration example of a flip-flop circuit according to a third embodiment.
The flip-flop circuit 103 according to the third embodiment shown in FIG. 4 (hereinafter referred to as a “flip-flop circuit 103”) is a D-type flip-flop circuit. The flip-flop circuit 103 has a configuration in which the master latch ML1B in the flip-flop circuit 102 is replaced with a master latch ML1C and the slave latch SL1B in the flip-flop circuit 102 is replaced with a slave latch SL1C.
The master latch ML1C has a configuration in which a PMOS transistor p12 is added to the master latch ML1B. The slave latch SL1C has a configuration in which a PMOS transistor p13 is added to the slave latch SL1B.
The PMOS transistor p12 is connected in parallel to the PMOS transistor p4. The gate of the PMOS transistor p12 is connected to the output terminal of the ti-state inverter TS1′. The PMOS transistor p13 is connected in parallel to the PMOS transistor p8. The gate of the PMOS transistor p13 is connected to the output terminal of the tri-state inverter TS2′.
By adding the PMOS transistor p12, the amount of current flowing into an output point of the master latch ML1C is larger than the amount of current flowing into an output point of the master latch ML1B. Further, by adding the PMOS transistor p13, the amount of current flowing into an output point of the slave latch SL1C is larger than the amount of current flowing into an output point of the slave latch SL1B. As a result, the soft error resistance of the flip-flop circuit 103 is improved as compared with the soft error resistance of the flip-flop circuit 102.
<Flip-Flop Circuit According to Fourth Embodiment>
FIG. 5 is a diagram showing a configuration example of a flip-flop circuit according to a fourth embodiment.
The flip-flop circuit 104 according to the fourth embodiment shown in FIG. 5 (hereinafter referred to as a “flip-flop circuit 104”) is a D-type flip-flop circuit. The flip-flop circuit 104 has a configuration in which the master latch ML1 in the flip-flop circuit 100 is replaced with a master latch ML1D and the slave latch SL1 in the flip-flop circuit 100 is replaced with a slave latch SL1D.
The master latch ML1D has a configuration in which the master latch ML1A of the first embodiment and the master latch ML1B of the second embodiment are combined.
The slave latch SL1D has a configuration in which the slave latch SL1A of the first embodiment and the slave latch SL1B of the second embodiment are combined.
The flip-flop circuit 104 is designed to further improve the soft error resistance as compared with the flip-flop circuit 101.
<Flip-Flop Circuit According to Fifth Embodiment>
FIG. 6 is a diagram showing a configuration example of a flip-flop circuit according to a fifth embodiment.
The flip-flop circuit 105 according to the fifth embodiment shown in FIG. 6 (hereinafter referred to as a “flip-flop circuit 105”) is a D-type flip-flop circuit. The flip-flop circuit 105 has a configuration in which the master latch ML1 in the flip-flop circuit 100 is replaced with a master latch ML1E and the slave latch SL1 in the flip-flop circuit 100 is replaced with a slave latch SL1E.
The master latch ML1E has a configuration in which the master latch ML1A of the first embodiment and the master latch ML1C of the third embodiment are combined.
The slave latch SL1E has a configuration in which the slave latch SL1A of the first embodiment and the slave latch SL1C of the third embodiment are combined.
The flip-flop circuit 105 is designed to further improve the soft error resistance as compared with the flip-flop circuit 101.
<Switching Power Supply Device and Vehicle>
The above-described flip-flop circuits can be used, for example, in a switching power supply device shown in FIG. 7 . The switching power supply device shown in FIG. 7 is a step-down DC/DC converter with a bottom detection on-time fix system that steps down an input voltage Vin to generate a desired output voltage Vout.
When the switching power supply device 200 shown in FIG. 7 detects that a feedback voltage Vfb drops to a reference voltage Vref, a driver 22 turns on an upper transistor Q7 so that a switch voltage Vsw has a high level by a predetermined on-time Ton, based on output from an on-time setting circuit 23 that sets the predetermined on-time Ton. The driver 22 turns off the upper transistor Q7 except for the predetermined on-time Ton. Further, the upper transistor Q7 and a lower transistor Q8 are complementarily switched by the driver 22.
Further, in the switching power supply device 200 shown in FIG. 7 , the driver 22 executes an operation according to an output of a current sensor, a temperature sensor, or the like in order to realize an overcurrent protection function, an overheat protection function, or the like.
The driver 22 is a power supply control circuit that controls a state of a bottom detection on-time fix system switching power supply device, and the driver 22 includes the above-described flip-flop circuits. A comparator 21 for comparing the feedback voltage Vfb and the reference voltage Vref, the driver 22, and the on-time setting circuit 23 are provided in a semiconductor integrated circuit device 24.
The above-described flip-flop circuits can also be used for a switching power supply device other than the bottom detection on-time fix system. Further, the above-described flip-flop circuits can be used not only for a switching power supply device but also for, for example, a motor drive device.
Next, an application example of the above-described switching power supply device 200 will be described. FIG. 8 is an external view showing a configuration example of a vehicle equipped with in-vehicle apparatuses. The vehicle 300 of this configuration example is equipped with in-vehicle apparatuses X11 to X17 and a battery (not shown) for supplying electric power to these in-vehicle apparatuses X11 to X17.
The in-vehicle apparatus X11 is an electronic controller that performs engine-related control (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).
The in-vehicle apparatus X12 is a lamp controller that performs lighting-on/off control of HID [High Intensity Discharged Lamp], DRL [Daytime Running Lamp], etc.
The in-vehicle apparatus X13 is a transmission controller that performs transmission-related control.
The in-vehicle apparatus X14 is a body controller that performs control related to the motion of the vehicle X (ABS [Anti-lock Brake System] control, EPS [Electric Power Steering] control, electronic suspension control, etc.).
The in-vehicle apparatus X15 is a security controller that performs drive control of a door lock, a security alarm, etc.
The in-vehicle apparatus X16 is an electronic apparatus incorporated in the vehicle X at the factory shipment stage, as standard equipment or manufacturer's options such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, an air conditioner, etc.
The in-vehicle apparatus X17 is an electronic apparatus that is mounted on the vehicle X, as user's options such as an in-vehicle A/V [Audio/Visual] apparatus, a car navigation system, an ETC [Electronic Toll Collection] system, etc.
The above-described switching power supply device 200 can be incorporated into any of the in-vehicle apparatuses X11 to X17.
<Others>
In addition to the above-described embodiments, the configuration of the present disclosure can be modified in various ways without departing from the gist of the disclosure. It should be considered that the embodiments are exemplary in all respects and are not restrictive, and the technical scope of the present disclosure is defined by the claims rather than the description of the embodiments and should be understood to include all changes that fall within the meaning and scope equivalent to the claims.
By increasing the gate width of the MOS transistor, the soft error resistance of the flip-flop circuit can be improved. However, if the gate widths of all MOS transistors are increased, the efficiency of improvement of the soft error resistance with respect to the size of the circuit area is not good.
Among electron-hole pairs generated by radiation passing through or colliding with a semiconductor integrated circuit device, many electrons with high mobility are collected in an NMOS transistor. Therefore, a soft error is likely to occur when the NMOS transistor is turned off Therefore, soft error resistance can be improved by increasing a current that flows when a PMOS transistor that is paired with the NMOS transistor is turned on, so that the electrons collected in the NMOS transistor can be quickly removed.
Therefore, it is possible to efficiently improve the soft error resistance by making the gate width of a PMOS transistor included in a tri-state inverter in a master latch larger than the gate width of an NMOS transistor included in the tri-state inverter in the master latch. Similarly, it is possible to efficiently improve the soft error resistance by making the gate width of a PMOS transistor included in a tri-state inverter in a slave latch larger than the gate width of an NMOS transistor included in the tri-state inverter in the slave latch.
A flip-flop circuit (101, 104, 105) according to the above-described one aspect has a configuration (first configuration) that includes: a master latch (ML1A, ML1D, ML1E) including a first inverter (INV3) and a first tri-state inverter (TS1, TS1′) configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor (p6) configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; a slave latch (SL1A, SL1D, SL1E) including a second inverter (INV4) and a second tri-state inverter (TS2, TS2′) configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor (p10) configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor (n9) configured such that the inverted clock signal is input to the second NMOS transistor; and at least one of a first wiring (L1) configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring (L2) configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.
The flip-flop circuit having the first configuration can improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.
The flip-flop circuit of the first configuration may have a configuration (second configuration) that the first tri-state inverter includes two NMOS transistors (n6, n12) directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.
The flip-flop circuit having the second configuration can further improve the soft error resistance as compared with the flip-flop circuit having the first configuration.
The flip-flop circuit of the second configuration may have a configuration (third configuration) that further includes: a PMOS transistor (p12) connected in parallel to the PMOS transistor (p4) included in the first inverter and configured such that the output terminal of the first tri-state inverter is connected to a gate of the connected PMOS transistor.
The flip-flop circuit having the third configuration can further improve the soft error resistance as compared with the flip-flop circuit having the second configuration.
The flip-flop circuit of any one of the first to third configurations may have a configuration (fourth configuration) that the second ti-state inverter includes two NMOS transistors (n10, n13) directly connected to each other and configured such that output of the second inverter is input to gates of the two NMOS transistors.
The flip-flop circuit having the fourth configuration can further improve the soft error resistance as compared with the flip-flop circuit having the first configuration.
The flip-flop circuit of the fourth configuration may have a configuration (fifth configuration) that further includes: a PMOS transistor (p13) connected in parallel to the PMOS transistor (p8) included in the second inverter and configured such that the output terminal of the second tri-state inverter is connected to a gate of the PMOS transistor.
The flip-flop circuit having the fifth configuration can further improve the soft error resistance as compared with the flip-flop circuit having the fourth configuration.
A flip-flop circuit (102, 103) according to the above-described one aspect has a configuration (sixth configuration) that includes: a master latch (ML1B, ML1C) including a first inverter (INV3) and a first tri-state inverter (TS1′) configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor (p6) configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; and a slave latch (SL1B, SL1C) including a second inverter (INV4) and a second tri-state inverter (TS2′) configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor (p10) configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor (n9) configured such that the inverted clock signal is input to the second NMOS transistor, wherein the first tri-state inverter includes two NMOS transistors (n6, n12) directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.
The flip-flop circuit having the sixth configuration can improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.
A semiconductor integrated circuit device (24) has a configuration (seventh configuration) that includes a flip-flop circuit of any one of the first to sixth configurations.
The semiconductor integrated circuit device having the seventh configuration can improve soft error resistance of the flip-flop circuit while suppressing the overheads of circuit area, delay time, and power consumption of the flip-flop circuit.
A vehicle (300) has a configuration (eighth configuration) that includes a semiconductor integrated circuit device of the seventh configuration.
The vehicle having the eighth configuration can improve soft error resistance of the flip-flop circuit while suppressing the overheads of circuit area, delay time, and power consumption of the flip-flop circuit.
According to the flip-flop circuit, the semiconductor integrated circuit device, and the vehicle disclosed in the present disclosure, it is possible to improve soft error resistance while suppressing the overheads of circuit area, delay time, and power consumption.
While certain embodiments have been described, these embodiments have been presented by way of example, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.

Claims (7)

What is claimed is:
1. A flip-flop circuit comprising:
a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor;
a slave latch including a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor; and
at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor,
wherein the first tri-state inverter further includes two NMOS transistors directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.
2. The flip-flop circuit of claim 1, further comprising a third PMOS transistor connected in parallel to a PMOS transistor included in the first inverter and configured such that the output terminal of the first tri-state inverter is connected to a gate of the third PMOS transistor.
3. The flip-flop circuit of claim 1, wherein the second tri-state inverter includes two NMOS transistors directly connected to each other and configured such that output of the second inverter is input to gates of the two NMOS transistors.
4. The flip-flop circuit of claim 3, further comprising a fourth PMOS transistor connected in parallel to a PMOS transistor included in the second inverter and configured such that the output terminal of the second tri-state inverter is connected to a gate of the fourth PMOS transistor.
5. A semiconductor integrated circuit device comprising the flip-flop circuit of claim 1.
6. A vehicle comprising the semiconductor integrated circuit device of claim 5.
7. A flip-flop circuit comprising:
a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor; and
a slave latch including a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor,
wherein the first tri-state inverter further includes two NMOS transistors directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.
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