US11972804B2

US11972804B2 - Techniques for checking vulnerability to cross-temperature read errors in a memory device

Info

Publication number: US11972804B2
Application number: US17/846,452
Authority: US
Inventors: Xuan Tian; Henry Chin; Liang Li; Vincent Yin; Wei Zhao; Tony Zou
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2024-04-30
Also published as: WO2023249719A1; US20230420053A1

Abstract

The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Description

BACKGROUND

1. Field

The present disclosure is related generally to memory devices and more particularly to improved techniques for checking a memory block's vulnerability to cross-temperature read errors.

2. Related Art

Semiconductor memory is widely used in various electronic devices, such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power, e.g., a battery.

Such non-volatile memory devices generally include a plurality of memory cells that are arranged in memory blocks, which each include a plurality of word lines. The memory cells are configured to be programmed to retain threshold voltages that are associated with programmed data states. After programming, the data contained in the memory cells can be accessed in a read operation whereby the threshold voltages of the memory cells are sensed. In some cases, read errors can occur if programming took place while the memory device was at a high temperature and read takes place while the memory device is at a low temperature.

SUMMARY

One aspect of the present disclosure is related to a method of testing a memory block in a memory device for cross-temperature read error vulnerability. The method includes the step of preparing a memory block including an array of memory cells. The method continues with the step of programming a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution. The method proceeds with the step of calculating an nVt width of the nVt distribution. The method continues with the step of comparing the nVt width to a threshold. The method proceeds with the step of identifying the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

According to another aspect of the present disclosure, the method further includes the step of retiring the memory block in response to the memory block being identified as being vulnerable to cross-temperature read errors.

According to yet another aspect of the present disclosure, the step of transitioning the memory block from multi-bit per memory cell operation to single bit per memory cell operation in response to the memory block being identified as being vulnerable to cross-temperature read errors.

According to still another aspect of the present disclosure, the step of calculating the nVt width of the nVt distribution includes the steps of identifying a lower tail of the nVt distribution and identifying an upper tail of the nVt distribution and calculating a difference between the lower and upper tails of the nVt distribution.

According to a further aspect of the present disclosure, during the step of identifying the lower tail of the nVt distribution, a first bit line voltage is applied to the bit lines coupled to the memory, and during the step of identifying the upper tail of the nVt distribution, a second bit line voltage is applied to the bit lines coupled to the memory cells. The first bit line voltage is different than the second bit line voltage.

According to yet a further aspect of the present disclosure, the first bit line voltage is greater than the second bit line voltage.

According to still a further aspect of the present disclosure, during the step of identifying the lower tail of the nVt distribution, a first set of pass voltages is applied to the unselected word lines of the memory block and during the step of identifying the upper tail of the nVt distribution, a second set of pass voltages is applied to the unselected word lines of the memory block. The first set of pass voltages is different than the second set of pass voltages.

According to another aspect of the present disclosure, the first set of pass voltages is greater than the second set of pass voltages.

According to yet another aspect of the present disclosure, the method further includes the step of erasing the memory cells of the memory block prior to the step of programming the group of memory cells to obtain the nVt distribution.

Another aspect of the present disclosure is related to a memory device that includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

According to another aspect of the present disclosure, the control circuitry is further configured to retire the memory block in response to the memory block being identified as being vulnerable to cross-temperature read errors.

According to yet another aspect of the present disclosure, the control circuitry is further configured to transition the memory block from multi-bit per memory cell operation to single bit per memory cell operation in response to the memory block being identified as being vulnerable to cross-temperature read errors.

According to still another aspect of the present disclosure, the control circuitry is configured to calculate the nVt width of the nVt distribution by identifying a lower tail of the nVt distribution, identifying an upper tail of the nVt distribution, and calculating a difference between the lower and upper tails of the nVt distribution.

According to a further aspect of the present disclosure, when identifying the lower tail of the nVt distribution, the control circuitry applies a first bit line voltage to the bit lines coupled to the memory, and when identifying the upper tail of the nVt distribution, the control circuitry applies a second bit line voltage to the bit lines coupled to the memory cells. The first bit line voltage is different than the second bit line voltage.

According to still a further aspect of the present disclosure, while identifying the lower tail of the nVt distribution, the control circuitry applies a first set of pass voltages to the unselected word lines of the memory block, and while identifying the upper tail of the nVt distribution, the control circuity applies a second set of pass voltages to the unselected word lines of the memory block. The first set of pass voltages is different than the second set of pass voltages.

According to yet another aspect of the present disclosure, the control circuitry is configured to erase the memory cells of the memory block prior to the step of programming the group of memory cells to obtain the nVt distribution.

Yet another aspect of the present disclosure is related to an apparatus that includes a memory block includes an array of memory cells. The apparatus includes a controlling means for detecting vulnerability to cross-temperature in communication with the memory cells. The controlling means is configured to erase the memory cells of the memory block; program the memory cells in a programming operation that does not include verify; determine a first natural threshold voltage (nVt) distribution of a first word line; calculate a first nVt width of the first nVt distribution; determine a second nVt distribution of a second word line; calculate a second nVt width of the second nVt distribution; compare a difference between the first nVt width and the second nVt width to a threshold; and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

According to another aspect of the present disclosure, when determining the first and second nVt widths, the controlling means is configured to determine an upper tail and a lower tail of each of the first and second nVt distributions. When determining the lower tails of the first and second nVt distributions, the controlling means applies a first bit line voltage to the bit lines coupled to the memory cells and applies a first set of pass voltages to a plurality of unselected word lines, and the controlling means applies a second bit line voltage to the bit lines coupled to the memory cells and applies a second set of pass voltages to the plurality of unselected word lines.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed description is set forth below with reference to example embodiments depicted in the appended figures. Understanding that these figures depict only example embodiments of the disclosure and are, therefore, not to be considered limiting of its scope. The disclosure is described and explained with added specificity and detail through the use of the accompanying drawings in which:

FIG. 1A is a block diagram of an example memory device;

FIG. 1B is a block diagram of an example control circuit;

FIG. 2 depicts blocks of memory cells in an example two-dimensional configuration of the memory array of FIG. 1A;

FIG. 3A and FIG. 3B depict cross-sectional views of example floating gate memory cells in NAND strings;

FIG. 4A and FIG. 4B depict cross-sectional views of example charge-trapping memory cells in NAND strings;

FIG. 5 depicts an example block diagram of the sense block SB1 of FIG. 1 ;

FIG. 6A is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array of FIG. 1 ;

FIG. 6B depicts an example cross-sectional view of a portion of one of the blocks of FIG. 6A;

FIG. 6C depicts a plot of memory hole diameter in the stack of FIG. 6B;

FIG. 6D depicts a close-up view of region 622 of the stack of FIG. 6B;

FIG. 7A depicts a top view of an example word line layer WLL0 of the stack of FIG. 6B;

FIG. 7B depicts a top view of an example top dielectric layer DL116 of the stack of FIG. 6B;

FIG. 8 depicts a threshold voltage distribution of a group of memory cells programmed to SLC (one bit of data per memory cell);

FIG. 9 depicts a threshold voltage distribution of a group of memory cells programmed to MLC (two bits of data per memory cell);

FIG. 10 depicts a threshold voltage distribution of a group of memory cells programmed to TLC (three bits of data per memory cell);

FIG. 11 depicts a voltage waveform applied to a selected word line during an example programming operation;

FIG. 12A is a threshold voltage Vt distribution of a plurality of memory cells programmed at a high temperature and read at a high temperature in a memory block that is vulnerable to cross-temperature read errors;

FIG. 12B is a threshold voltage Vt distribution of a plurality of memory cells programmed at a high temperature and read at a low temperature in a memory block that is vulnerable to cross-temperature read errors;

FIG. 13A is a threshold voltage Vt distribution of a plurality of memory cells programmed at a high temperature and read at a high temperature in a memory block that is not vulnerable to cross-temperature read errors;

FIG. 13B is a threshold voltage Vt distribution of a plurality of memory cells programmed at a high temperature and read at a low temperature in a memory block that is not vulnerable to cross-temperature read errors;

FIG. 14 is a schematic view of an example memory hole including an upper memory hole and a lower memory hold;

FIG. 15 is a natural threshold voltage nVt distribution of a plurality of memory cells and illustrating the nVt width;

FIG. 16 is a flow chart depicting the steps of erasing and conducting a cross-temperature sensing operation on a memory block according to a first embodiment;

FIG. 17 is a schematic view of a memory block and illustrating the word line voltages applied during a sensing operation;

FIG. 18 is a plot illustrating the memory blocks that pass and failed a cross-temperature sensing operation following varying numbers of program and erase cycles; and

FIG. 19 is a flow chart depicting the steps of erasing and conducting a cross-temperature sensing operation on a memory block according to a second embodiment.

DESCRIPTION OF THE ENABLING EMBODIMENT

The present disclosure is related to techniques for proactively checking a memory block's vulnerability to cross-temperature read errors before such read errors can result in uncorrectable read failure. According to these techniques, at periodic intervals, the memory cells in the memory block are programmed to a natural threshold voltage (nVt) distribution. An nVt width is then determined and compared to a threshold. If the nVt width exceeds the threshold, then the memory block is identified as being vulnerable to cross-temperature read errors, at which point, the memory block can either be retired or transitioned to SLC operation. If the nVt width is less than the threshold, then operation of the memory block can proceed unchanged. By detecting memory blocks that are vulnerable to cross-temperature read errors prior to uncorrectable read errors occurring, the reliability of a memory device is improved.

FIG. 1A is a block diagram of an example memory device that is capable of conducting the aforementioned cross-temperature vulnerability checking techniques. The memory device 100 may include one or more memory die 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read/write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read/write circuits 128 include multiple sense blocks SB1, SB2, . . . SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory die 108. Commands and data are transferred between the host 140 and controller 122 via a data bus 120, and between the controller and the one or more memory die 108 via lines 118.

The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 may comprise one or more array of memory cells including a three-dimensional array. The memory structure 126 may comprise a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure 126 may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

The control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

A storage region 113 may, for example, be provided for programming parameters. The programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like. The position parameters may indicate a position of a memory cell within the entire array of NAND strings, a position of a memory cell as being within a particular NAND string group, a position of a memory cell on a particular plane, and/or the like. The contact line connector thickness parameters may indicate a thickness of a contact line connector, a substrate or material that the contact line connector is comprised of, and/or the like.

The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller to the hardware address used by the

decoders

124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. The sense blocks can include bit line drivers, in one approach. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

In some embodiments, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure 126, can be thought of as at least one control circuit which is configured to perform the actions described herein. For example, a control circuit may include any one of, or a combination of, control circuitry 110, state machine 112, decoders 114/132, power control module 116, sense blocks SBb, SB2, . . . , SBp, read/write circuits 128, controller 122, and so forth.

The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states; the program and verify operation comprising a plurality of program and verify iterations; and in each program and verify iteration, the programming circuit performs programming for the one selected word line after which the programming circuit applies a verification signal to the selected word line. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, if a programming operation is completed.

For example, FIG. 1B is a block diagram of an example control circuit 150 which comprises a programming circuit 151, a counting circuit 152, and a determination circuit 153.

The off-chip controller 122 may comprise a processor 122 c, storage devices (memory) such as ROM 122 a and RAM 122 b and an error-correction code (ECC) engine 245. The ECC engine can correct a number of read errors which are caused when the upper tail of a Vth distribution becomes too high. However, uncorrectable errors may exist in some cases. The techniques provided herein reduce the likelihood of uncorrectable errors.

The storage device(s) 122 a, 122 b comprise, code such as a set of instructions, and the processor 122 c is operable to execute the set of instructions to provide the functionality described herein. Alternately or additionally, the processor 122 c can access code from a storage device 126 a of the memory structure 126, such as a reserved area of memory cells in one or more word lines. For example, code can be used by the controller 122 to access the memory structure 126 such as for programming, read and erase operations. The code can include boot code and control code (e.g., set of instructions). The boot code is software that initializes the controller 122 during a booting or startup process and enables the controller 122 to access the memory structure 126. The code can be used by the controller 122 to control one or more memory structures 126. Upon being powered up, the processor 122 c fetches the boot code from the ROM 122 a or storage device 126 a for execution, and the boot code initializes the system components and loads the control code into the RAM 122 b. Once the control code is loaded into the RAM 122 b, it is executed by the processor 122 c. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

Generally, the control code can include instructions to perform the functions described herein including the steps of the flowcharts discussed further below and provide the voltage waveforms including those discussed further below.

In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (RAM, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors.

Other types of non-volatile memory in addition to NAND flash memory can also be used.

Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or phase change material, and optionally a steering element, such as a diode or transistor. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors comprising memory cells and SG transistors.

A NAND memory array may be configured so that the array is composed of multiple memory strings in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured. The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-y direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements is formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z-direction is substantially perpendicular and the x- and y-directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

By way of non-limiting example, in a three-dimensional array of NAND strings, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three-dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between memory device levels.

Then again, two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

FIG. 2 illustrates blocks 200, 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG. 1 . The memory array 126 can include many such blocks 200, 210. Each example block 200, 210 includes a number of NAND strings and respective bit lines, e.g., BL0, BL1, . . . which are shared among the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain select gates are connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS) which, in turn, is connected to a common source line 220. One hundred and twelve word lines, for example, WL0-WL111, extend between the SGSs and the SGDs. In some embodiments, the memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines, which contain no user data, can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield the edge data word line from certain edge effects.

One type of non-volatile memory which may be provided in the memory array is a floating gate memory, such as of the type shown in FIGS. 3A and 3B. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in FIGS. 4A and 4B, a charge-trapping memory cell uses a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

In another approach, NROM cells are used. Two bits, for example, are stored in each NROM cell, where an ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

FIG. 3A illustrates a cross-sectional view of example floating

gate memory cells

300, 310, 320 in NAND strings. In this Figure, a bit line or NAND string direction goes into the page, and a word line direction goes from left to right. As an example, word line 324 extends across NAND strings which include

respective channel regions

306, 316 and 326. The memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305 and the channel region 306. The memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315 and the channel region 316. The memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325 and the channel region 326. Each

memory cell

300, 310, 320 is in a different respective NAND string. An inter-poly dielectric (IPD) layer 328 is also illustrated. The

control gates

302, 312, 322 are portions of the word line. A cross-sectional view along contact line connector 329 is provided in FIG. 3B.

The

control gate

302, 312, 322 wraps around the floating

gate

304, 314, 321, increasing the surface contact area between the

control gate

302, 312, 322 and floating

gate

304, 314, 321. This results in higher IPD capacitance, leading to a higher coupling ratio which makes programming and erase easier. However, as NAND memory devices are scaled down, the spacing between neighboring

cells

300, 310, 320 becomes smaller so there is almost no space for the

control gate

302, 312, 322 and the IPD layer 328 between two adjacent floating

gates

302, 312, 322.

As an alternative, as shown in FIGS. 4A and 4B, the flat or

planar memory cell

400, 410, 420 has been developed in which the

control gate

402, 412, 422 is flat or planar; that is, it does not wrap around the floating gate and its only contact with the charge storage layer 428 is from above it. In this case, there is no advantage in having a tall floating gate. Instead, the floating gate is made much thinner. Further, the floating gate can be used to store charge, or a thin charge trap layer can be used to trap charge. This approach can avoid the issue of ballistic electron transport, where an electron can travel through the floating gate after tunneling through the tunnel oxide during programming.

FIG. 4A depicts a cross-sectional view of example charge-trapping

memory cells

400, 410, 420 in NAND strings. The view is in a word line direction of

memory cells

400, 410, 420 comprising a flat control gate and charge-trapping regions as a two-dimensional example of

memory cells

400, 410, 420 in the memory cell array 126 of FIG. 1 . Charge-trapping memory can be used in NOR and NAND flash memory device. This technology uses an insulator such as an SiN film to store electrons, in contrast to a floating-gate MOSFET technology which uses a conductor such as doped polycrystalline silicon to store electrons. As an example, a word line 424 extends across NAND strings which include

respective channel regions

406, 416, 426. Portions of the word line provide

control gates

402, 412, 422. Below the word line is an IPD layer 428, charge-trapping

layers

404, 414, 421, polysilicon layers 405, 415, 425, and tunneling

layers

409, 407, 408. Each charge-

trapping layer

404, 414, 421 extends continuously in a respective NAND string. The flat configuration of the control gate can be made thinner than a floating gate. Additionally, the memory cells can be placed closer together.

FIG. 4B illustrates a cross-sectional view of the structure of FIG. 4A along contact line connector 429. The NAND string 430 includes an SGS transistor 431,

example memory cells

400, 433, . . . 435, and an SGD transistor 436. Passageways in the IPD layer 428 in the SGS and

SGD transistors

431, 436 allow the control gate layers 402 and floating gate layers to communicate. The control gate 402 and floating gate layers may be polysilicon and the tunnel oxide layer may be silicon oxide, for instance. The IPD layer 428 can be a stack of nitrides (N) and oxides (O) such as in a N—O—N—O—N configuration.

The NAND string may be formed on a substrate which comprises a p-type substrate region 455, an n-type well 456 and a p-type well 457. N-type source/drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6 and sd7 are formed in the p-type well. A channel voltage, Vch, may be applied directly to the channel region of the substrate.

FIG. 5 illustrates an example block diagram of the sense block SB1 of FIG. 1 . In one approach, a sense block comprises multiple sense circuits. Each sense circuit is associated with data latches. For example, the

example sense circuits

550 a, 551 a, 552 a, and 553 a are associated with the data latches 550 b, 551 b, 552 b, and 553 b, respectively. In one approach, different subsets of bit lines can be sensed using different respective sense blocks. This allows the processing load which is associated with the sense circuits to be divided up and handled by a respective processor in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with the set of sense circuits and latches. The sense circuit controller 560 may include a pre-charge circuit 561 which provides a voltage to each sense circuit for setting a pre-charge voltage. In one possible approach, the voltage is provided to each sense circuit independently, e.g., via the data bus and a local bus. In another possible approach, a common voltage is provided to each sense circuit concurrently. The sense circuit controller 560 may also include a pre-charge circuit 561, a memory 562 and a processor 563. The memory 562 may store code which is executable by the processor to perform the functions described herein. These functions can include reading the

latches

550 b, 551 b, 552 b, 553 b which are associated with the

sense circuits

550 a, 551 a, 552 a, 553 a, setting bit values in the latches and providing voltages for setting pre-charge levels in sense nodes of the

sense circuits

550 a, 551 a, 552 a, 553 a. Further example details of the sense circuit controller 560 and the

sense circuits

550 a, 551 a, 552 a, 553 a are provided below.

In some embodiments, a memory cell may include a flag register that includes a set of latches storing flag bits. In some embodiments, a quantity of flag registers may correspond to a quantity of data states. In some embodiments, one or more flag registers may be used to control a type of verification technique used when verifying memory cells. In some embodiments, a flag bit's output may modify associated logic of the device, e.g., address decoding circuitry, such that a specified block of cells is selected. A bulk operation (e.g., an erase operation, etc.) may be carried out using the flags set in the flag register, or a combination of the flag register with the address register, as in implied addressing, or alternatively by straight addressing with the address register alone.

FIG. 6A is a perspective view of a set of blocks 600 in an example three-dimensional configuration of the memory array 126 of FIG. 1 . On the substrate are example blocks BLK0, BLK1, BLK2, BLK3 of memory cells (storage elements) and a peripheral area 604 with circuitry for use by the blocks BLK0, BLK1, BLK2, BLK3. For example, the circuitry can include voltage drivers 605 which can be connected to control gate layers of the blocks BLK0, BLK1, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLK0, BLK1, BLK2, BLK3 are commonly driven. The substrate 601 can also carry circuitry under the blocks BLK0, BLK1, BLK2, BLK3, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuitry. The blocks BLK0, BLK1, BLK2, BLK3 are formed in an intermediate region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked area of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing tiered sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks can be used, extending in the x- and/or y-directions.

In one possible approach, the length of the plane, in the x-direction, represents a direction in which signal paths to word lines extend in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane, in the y-direction, represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the memory device.

FIG. 6B illustrates an example cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3 of FIG. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers and four dummy word line layers DWLD0, DWLD1, DWLS0 and DWLS1, in addition to data word line layers (word lines) WL0-WL111. The dielectric layers are labelled as DL0-DL116. Further, regions of the stack 610 which comprise NAND strings NS1 and NS2 are illustrated. Each NAND string encompasses a

memory hole

618, 619 which is filled with materials which form memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in greater detail in FIG. 6D and is discussed in further detail below.

The 610 stack includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source-end 613 at a bottom 614 of the stack and a drain-end 615 at a top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled slits) 617, 620 may be provided periodically across the stack 610 as interconnects which extend through the stack 610, such as to connect the source line to a particular contact line above the stack 610. The

contact line connectors

617, 620 may be used during the formation of the word lines and subsequently filled with metal. A portion of a bit line BL0 is also illustrated. A conductive via 621 connects the drain-end 615 to BL0.

FIG. 6C illustrates a plot of memory hole diameter in the stack of FIG. 6B. The vertical axis is aligned with the stack of FIG. 6B and illustrates a width (wMH), e.g., diameter, of the

memory holes

618 and 619. The word line layers WL0-WL111 of FIG. 6A are repeated as an example and are at respective heights z0-z111 in the stack. In such a memory device, the memory holes which are etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25-30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width can vary along the length of the hole. Typically, the diameter becomes progressively smaller from the top to the bottom of the memory hole. That is, the memory holes are tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate so that the diameter becomes slightly wider before becoming progressively smaller from the top to the bottom of the memory hole.

Due to the non-uniformity in the width of the memory hole, the programming speed, including the program slope and erase speed of the memory cells can vary based on their position along the memory hole, e.g., based on their height in the stack. With a smaller diameter memory hole, the electric field across the tunnel oxide is relatively stronger, so that the programming and erase speed is relatively higher. One approach is to define groups of adjacent word lines for which the memory hole diameter is similar, e.g., within a defined range of diameter, and to apply an optimized verify scheme for each word line in a group. Different groups can have different optimized verify schemes.

FIG. 6D illustrates a close-up view of the region 622 of the stack 610 of FIG. 6B. Memory cells are formed at the different levels of the stack at the intersection of a word line layer and a memory hole. In this example,

SGD transistors

680, 681 are provided above

dummy memory cells

682, 683 and a data memory cell MC. A number of layers can be deposited along the sidewall (SW) of the memory hole 630 and/or within each word line layer, e.g., using atomic layer deposition. For example, each column (e.g., the pillar which is formed by the materials within a memory hole 630) can include a charge-trapping layer or film 663 such as SiN or other nitride, a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word line layer can include a blocking oxide/block high-k material 660, a metal barrier 661, and a conductive metal 662 such as Tungsten as a control gate. For example,

control gates

690, 691, 692, 693, and 694 are provided. In this example, all of the layers except the metal are provided in the memory hole 630. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the memory cell. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a memory cell is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

Each of the memory holes 630 can be filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664 and a channel layer. A core region of each of the memory holes 630 is filled with a body material, and the plurality of annular layers are between the core region and the word line in each of the memory holes 630.

The NAND string can be considered to have a floating body channel because the length of the channel is not formed on a substrate. Further, the NAND string is provided by a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.

FIG. 7A illustrates a top view of an example word line layer WL0 of the stack 610 of FIG. 6B. As mentioned, a three-dimensional memory device can comprise a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates of the SG transistors and memory cells. The layers used for the SG transistors are SG layers and the layers used for the memory cells are word line layers. Further, memory holes are formed in the stack and filled with a charge-trapping material and a channel material. As a result, a vertical NAND string is formed. Source lines are connected to the NAND strings below the stack and bit lines are connected to the NAND strings above the stack.

A block BLK in a three-dimensional memory device can be divided into sub-blocks, where each sub-block comprises a NAND string group which has a common SGD control line. For example, see the SGD lines/control gates SGD0, SGD1, SGD2 and SGD3 in the sub-blocks SBa, SBb, SBc and SBd, respectively. Further, a word line layer in a block can be divided into regions. Each region is in a respective sub-block and can extend between contact line connectors (e.g., slits) which are formed periodically in the stack to process the word line layers during the fabrication process of the memory device. This processing can include replacing a sacrificial material of the word line layers with metal. Generally, the distance between contact line connectors should be relatively small to account for a limit in the distance that an etchant can travel laterally to remove the sacrificial material, and that the metal can travel to fill a void which is created by the removal of the sacrificial material. For example, the distance between contact line connectors may allow for a few rows of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also account for a limit in the number of bit lines which can extend across the region while each bit line is connected to a different memory cell. After processing the word line layers, the contact line connectors can optionally be filed with metal to provide an interconnect through the stack.

In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes which are aligned in the x-direction. Moreover, the rows of memory holes are in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WL0 a, WL0 b, WL0 c and WL0 d which are each connected by a contact line 713. The last region of a word line layer in a block can be connected to a first region of a word line layer in a next block, in one approach. The contact line 713, in turn, is connected to a voltage driver for the word line layer. The region WL0 a has

example memory holes

710, 711 along a contact line 712. The region WL0 b has

example memory holes

714, 715. The region WL0 c has

example memory holes

716, 717. The region WL0 d has

example memory holes

718, 719. The memory holes are also shown in FIG. 7B. Each memory hole can be part of a respective NAND string. For example, the

memory holes

710, 714, 716 and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

Each circle represents the cross-section of a memory hole at a word line layer or SG layer. Example circles shown with dashed lines represent memory cells which are provided by the materials in the memory hole and by the adjacent word line layer. For example,

memory cells

720, 721 are in WL0 a,

memory cells

724, 725 are in WL0 b,

memory cells

726, 727 are in WL0 c, and

memory cells

728, 729 are in WL0 d. These memory cells are at a common height in the stack.

Contact line connectors (e.g., slits, such as metal-filled slits) 701, 702, 703, 704 may be located between and adjacent to the edges of the regions WL0 a-WL0 d. The

contact line connectors

701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device.

FIG. 7B illustrates a top view of an example top dielectric layer DL116 of the stack of FIG. 6B. The dielectric layer is divided into regions DL116 a, DL116 b, DL116 c and DL116 d. Each region can be connected to a respective voltage driver. This allows a set of memory cells in one region of a word line layer being programmed concurrently, with each memory cell being in a respective NAND string which is connected to a respective bit line. A voltage can be set on each bit line to allow or inhibit programming during each program voltage.

The region DL116 a has the

example memory holes

710, 711 along a contact line 712, which is coincident with a bit line BL0. A number of bit lines extend above the memory holes and are connected to the memory holes as indicated by the “X” symbols. BL0 is connected to a set of memory holes which includes the

memory holes

711, 715, 717, 719. Another example bit line BL1 is connected to a set of memory holes which includes the

memory holes

710, 714, 716, 718. The contact line connectors (e.g., slits, such as metal-filled slits) 701, 702, 703, 704 from FIG. 7A are also illustrated, as they extend vertically through the stack. The bit lines can be numbered in a sequence BL0-BL23 across the DL116 layer in the x-direction.

Different subsets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, BL20 are connected to memory cells in a first row of cells at the right-hand edge of each region. BL2, BL6, BL10, BL14, BL18, BL22 are connected to memory cells in an adjacent row of cells, adjacent to the first row at the right-hand edge. BL3, BL7, BL11, BL15, BL19, BL23 are connected to memory cells in a first row of cells at the left-hand edge of each region. BL1, BL5, BL9, BL13, BL17, BL21 are connected to memory cells in an adjacent row of memory cells, adjacent to the first row at the left-hand edge.

The memory cells can be programmed to store one or multiple bits of data in 2ⁿdata states where n is a positive integer. Each data state is associated with a respective threshold voltage Vt. For example, FIG. 8 depicts a threshold voltage Vt distribution of a one bit per memory cell (SLC) storage scheme. In an SLC storage scheme, there are two total data states, including the erased state (Er) and a single programmed data state (S1). FIG. 9 illustrates the threshold voltage Vt distribution of a two bits per cell (MLC) storage scheme that includes four total data states, namely the erased state (Er) and three programmed data states (S1, S2, and S3). FIG. 10 illustrates the Vt distribution of a three bits per memory cell (TLC) storage scheme that includes eight total data states, namely the erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Other storage schemes are also available, such as four bits per cell (QLC) with sixteen data states.

Programming to MLC, TLC or QLC typically occurs in a plurality of program loops, each of which includes the application of a programming pulse Vpgm to the control gate of a selected word line. During the programming pulse Vpgm, the bit lines coupled to the memory holes are either held at a low voltage (for example, zero Volts) to encourage programming or are held at a higher inhibit voltage to discourage programming. Programming occurs when electrons move into the charge trapping materials of the memory cells coupled to the bit lines that are held at a low voltage, thereby raising the threshold voltages Vt of those memory cells. Conversely, the movement of electrons into the memory cells that are coupled to the bit lines at the inhibit voltage is restricted to prevent programming. When programming to TLC or QLC, the programming pulse is typically followed by the application of a verify pulse to sense the threshold voltages Vt of the memory cells to determine if they have completed programming.

FIG. 11 depicts a waveform 1100 of an example memory cell programming operation for programming the memory cells TLC. As depicted, each program loop includes a programming pulse VPGM and one or more verify pulses, depending on which data states are being programmed in a particular program loop. A square waveform is depicted for each pulse for simplicity; however, other shapes are possible, such as a multilevel shape or a ramped shape.

Incremental Step Pulse Programming (ISPP) is used in this example pulse train, which means that the VPGM pulse amplitude steps up in each successive program loop. In other words, the pulse train includes VPGM pulses that increase stepwise in amplitude with each program loop using a fixed step size (dVPGM). A new pulse train starts at an initial VPGM pulse level VPGMU and ends at a final VPGM pulse level, which does not exceed a maximum allowed level. The pulse train 1100 includes a series of Vpgm pulses 1101-1115 that are applied to a selected word line that includes a set of non-volatile memory cells. One or more verify voltage pulses 1116-1129 are provided after each VPGM pulse as an example, based on the target data states which are being verified in the program loop. The verify voltages correspond with the voltages Vv1-Vv7 (shown in FIG. 10 ) depending on the particular data states that are being programmed in a given program loop. Concurrent with the application of the verify voltages, a sensing operation can determine whether a memory cell has a Vt above the associated verify voltage by sensing a current through a memory cell of the selected word line. If the current is relatively high, this indicates the memory cell is in a conductive state, such that the Vt is less than the verify voltage. If the current is relatively low, this indicates the memory cell is in a non-conductive state, such that the Vt is above the control gate voltage. Programming proceeds until all memory cells pass verify for their intended data states or until a predetermined maximum number of program loops is exceeded.

After the memory cells are programmed, the data can be read back in a read operation. A read operation can involve applying a series of read voltages to a word line while sensing circuitry determines whether cells connected to the word line are in a conductive or non-conductive state. If a cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltages are set at levels which are expected to be between the threshold voltage levels of adjacent data states. With reference to FIG. 17 , during a read operation, while a read voltage VCGR is applied to a selected word line WLn, a first pass voltage VREADK is applied to the neighboring word lines WLn−1, WLn+1 and a second pass voltage VREAD is applied to the remaining word lines (WLn−2, WLn−3, etc. and WLn+2, WLn+3, etc.) of the memory block.

One known problem with many NAND memory devices is known as cross-temperature read errors, which occur when memory cells are programmed while the memory device is at a high temperature and read while the memory device is at a low temperature. When a group of memory cells in a memory block that is vulnerable to cross-temperature read errors are programmed at high temperature and read at low temperature, the apparent threshold voltages Vt of memory cells can be altered such that memory cells programmed to one programmed data state (for example, data state S2) are misinterpreted as being in a different data state (for example, data state S1 or S3) during a read operation. For example, FIGS. 12A and 12B illustrate a threshold voltage Vt distribution of the same group of memory cells in a memory block that is vulnerable to cross-temperature read errors. Specifically, FIG. 12A illustrates the Vt distribution when the read operation takes place at eighty-five degrees Celsius (85° C.), and FIG. 12B illustrates the Vt distribution when the read operation takes place at negative twenty degrees Celsius (−20° C.). As illustrated, for each of the programmed data states S1-S7, the Vt width is greater when the read takes place at cold temperatures as compared to warm temperatures such that there is substantial overlap between the Vt distributions of adjacent data states during the cold temperature read. This is in contrast to FIGS. 13A and 13B, which illustrate Vt distributions following reads at high temperature (FIG. 13A) and low temperature (FIG. 13B) in a memory block that is not susceptible to cross-temperature read errors. In many cases, the vulnerability of a memory block to cross-temperature read errors may increase with increasing cycling (programming and erasing) in the memory cells.

A memory block may become more vulnerable to cross-temperature read errors over its operating life with increasing cycles of programming and erasing the memory cells. In other words, a memory block may not be vulnerable to cross-temperature read errors at the beginning of its operating life and may become vulnerable to cross-temperature read errors near the end of its operating life.

In some cases, vulnerability to cross-temperature read errors is caused by a non-uniform poly-channel in the lower memory holes (LMH) of the memory block as compared to the upper memory holes (UMH). Specifically, as illustrated schematically in FIG. 14 , in some cases, the sacrificial amorphous silicon 1400 is not sufficiently removed from the lower memory hole LMH during a wet etching operation, thereby leaving excess amorphous silicon 1400 in the lower memory hole LMH. This excess amorphous silicon 1400 may contribute to the memory cells in that memory hole being vulnerable to cross-temperature read errors.

During a read operation, if a total number of read errors (including cross-temperature read errors) exceeds the capabilities of an error correction code (ECC) engine of the memory device, then uncorrectable read failure (UECC) can result.

One known way of determining if a memory block is vulnerable to cross-temperature read errors is to test the memory block at both high and low temperatures as part of a product qualification test. However, such testing may be expensive and time consuming and may not be successful at detecting memory blocks that are not vulnerable to cross-temperature read errors at the beginning of its operating life but become vulnerable to cross-temperature read errors after repeated cycling.

As discussed in further detail below, the present disclosure is related to system checking techniques whereby a memory block is periodically analyzed for vulnerability to cross-temperature read errors by analyzing a width of its natural threshold voltage nVt distribution at predetermined intervals. It has been found that the nVt width is highly correlated with vulnerability to cross-temperature read errors. More specifically, the greater the nVt width, the more vulnerable a memory block is likely to be to cross-temperature read errors. The cross-temperature checking techniques can be implemented by analyzing the nVt width. By conducting a cross-temperature checking operation at predetermined intervals (for example, upon the memory device passing certain program-erase cycling thresholds), the memory can determine when the memory block is at high risk of UECC error due to cross-temperature read errors and either retire the memory block or convert the memory block from multi-bit per memory cell (for example, MLC, TLC, or QLC) operation to single-bit per memory cells (SLC) operation, which is less sensitive to cross-temperature read errors.

In some embodiments, the cross-temperature checking operation is conducted both at the beginning of the memory block's operating life (0 cycles) and also after every thousand cycles for the memory block (e.g., 1,000 cycles, 2,000 cycles, 3,000 cycles, etc.). In other embodiments, the frequency of the cross-temperature checking operation can be varied or based on a factor other than program-erase cycles. By conducting the cross-temperature checking operation at the beginning of a memory block's operating life, defectively manufactured memory blocks can be caught and either quarantined or converted to SLC operation before data is programmed to its memory cells. By conducting the cross-temperature checking operation at predetermined intervals, the memory device is able to detect if and when a memory block transitions from being not vulnerable to cross-temperature read errors to vulnerable to cross-temperature read errors before UECC failure can occur.

In an example embodiment, the cross-temperature checking operation is implemented into an erase operation, which is typically a time when demand for performance is low. In other words, in this embodiment, the cross-temperature checking operation is performed immediately after the memory cells have been erased following a predetermined number of program-erase cycles.

To obtain the nVt distribution, all of the memory cells in a selected word line in the memory block are programmed in a set number of programming loops with all special device modes being disabled (for example, quick-pass write, program verify, smart verify, etc.). The threshold voltages Vt of those memory cells are then sensed to establish the nVt distribution. With reference to FIG. 15 , the nVt width is then calculated by determining the median voltage of the nVt distribution, the voltage at three times the standard deviation, and the voltage at negative three times the standard deviation (sigma). The nVt width is the difference between the voltage at three times the standard deviation minus the voltage at negative three times the standard deviation, i.e., nVt_Width=Vt_+3_sigma−Vt_−3_sigma. In some embodiments, the start and end points that define the nVt width may be other points in the nVt distribution, e.g., positive and negative four times the standard deviation.

Turning now to FIG. 16 , a flow chart depicting the steps of an example embodiment of an erase operation is provided. At step 1600, a command to erase a memory block is received by the memory device, and the memory cells in memory block “Block n” are erased. At step 1602, a program-erase Cycle Count of the memory cells of Block n is determined.

At decision step 1604, it is determined if the memory block is due for a cross-temperature checking operation. Specifically, in this example embodiment, at step 1604, it is determined if the Cycle Count is equal to a positive integer times a predetermined frequency (“i”, which could be, for example, one thousand cycles).

If the answer at decision step 1604 is “yes,” then at step 1606, the cross-temperature checking operation begins. That is, a group of memory cells (for example, the memory cells of one or more word lines) in Block n are programmed in one or more programming loops while all special device modes are disabled (for example, quick-pass write, program verify, smart verify, etc.) to obtain the nVt distribution. The nVt width of the group of memory cells is then analyzed, and a judgment operation involves comparing the nVt width to predetermined thresholds. As discussed in further detail below, in some embodiments, the cross-temperature checking operation involves determining the nVt widths of two word lines and comparing those nVt widths to predetermined thresholds.

At decision step 1608, it is determined if Block n failed the cross-temperature checking operation. If the answer at decision step 1608 is “yes,” then at step 1610, the memory block is either retired or is switched to SLC operation for the remainder of its operating life.

If the answer at decision step 1604 or step 1608 is “no,” then the erase operation is continued until completion at step 1612.

At step 1606, in some embodiments, the group of cells that are programmed to the nVt distribution are the memory cells of a word line which is in “bad” location that is vulnerable to cross-temperature read errors. For example, in one embodiment, the selected word line is WL79. The nVt judgment operation involves measuring the nVt width of the memory cells of WL79 and comparing the nVt width to a first predetermined threshold, which may be established experimentally. If the nVt width is less than the first predetermined threshold, then the memory block passes the cross-temperature checking operation. If the nVt width is greater than the first predetermined threshold, then the memory block fails the cross-temperature checking operation. The word line in the bad location may be coupled with the lower memory holes.

In some other embodiments, at step 1606, the group of memory cells that are programmed to the nVt distribution include the memory cells of two word lines: a first word line in a bad location (e.g., WL79) and a second word line in a “good” location that is generally protected from cross-temperature read errors. In one example embodiment, the second word line, which is in the good location, is WL24. In some embodiments, the word lines in the good and bad locations can be different than those used in these examples. The word line in the good location may be coupled with the upper memory holes.

In one such example embodiment, at step 1606, the nVt width of the memory cells in the second word line is then subtracted from the nVt width of the memory cells in the first word line, e.g., nVt_WL79−nVt_WL24. The result of this operation is then compared to a second predetermined threshold. If the result is less than the second predetermined threshold, then the memory block passes the cross-temperature checking operation. If the result is greater than the second predetermined threshold, then the memory block fails the cross-temperature checking operation.

In another such embodiment, each of the nVt widths of the memory cells of the first and second word line are squared, e.g., (nVt_WL79)²−(nVt_WL24)². The result of this operation is then compared to a third predetermined threshold. If the result is less than the third predetermined threshold, then the memory block passes the cross-temperature checking operation. If the result is greater than the third predetermined threshold, then the memory block fails the cross-temperature checking operation.

The above example judgment operations are three examples that may have varying degrees of success at identifying memory blocks that are vulnerable to cross-temperature read errors without mistakenly identifying good memory blocks as being bad memory blocks. In some example embodiments, the nVt widths of three or more word lines may be analyzed and the judgment operation may compare the result of a function which utilizes the nVt widths of those three or more word lines to a different pre-determined threshold to determine if the memory block passes the cross-temperature checking operation. For example, the cross-temperature judgment operation could include determining the difference between a maximum nVt width and a minimum nVt width among the three or more word lines.

In some embodiments, certain parameters can be implemented to improve the judgment operation. For example, in one embodiment, during the process of sensing the threshold voltages of the memory cells of a selected word line to establish the nVt distribution, a bit line voltage VBLC applied to the bit lines coupled to the memory holes may be shifted either upwardly or downwardly. Such shifting of VBLC has been found to increase the nVt widths in memory blocks that are vulnerable to cross-temperature read errors (specifically, memory blocks with memory holes that have poly-channels with an increased thickness) by a greater magnitude than in memory blocks that are not vulnerable to cross-temperature read errors. Specifically, a high VBLC has been found to shift a lower tail of the nVt distribution (and thus the Vt_−3_sigma voltage) downwardly, and a low VBLC has been found to shift an upper tail of the nVt distribution (and thus the Vt_+3_sigma voltage) upwardly. Thus, the high VBLC voltage is applied to the bit lines coupled to the memory holes when sensing for the Vt_−3_sigma voltage, and the low VBLC voltage is applied to the bit lines coupled to the memory holes when sensing for the Vt_+3_sigma voltage. Combining these two effects magnifies the nVt widths of memory blocks that are vulnerable to cross-temperature read errors, thereby making those memory blocks easier to distinguish from memory blocks that are not vulnerable to cross-temperature read errors.

Another parameter that may magnify the nVt width in memory blocks that are vulnerable to cross-temperature read errors as compared to memory blocks that are not vulnerable to cross-temperature read errors is to modify the first pass voltage VREADK and the second pass voltage VREAD voltages that are applied to the neighboring word lines during the sensing operation (see FIG. 17 ) based on whether the lower tail (Vt_−3_sigma) or the upper tail (Vt_+3_sigma) is being sensed. Specifically, when sensing the lower tail (Vt_−3 sigma), a first set of pass voltages VREADK_1, VREAD_1 are applied to the neighboring word lines, and when sensing the upper tail (Vt_+3_sigma), a second set of pass voltages VREADK_2, VREAD_2 that is smaller than the first set of pass voltages VREADK_1, VREAD_1 are applied to the neighboring word lines. This has been found to further magnify the nVt widths of word lines that are vulnerable to cross-temperature sensing as compared to the nVt widths of word lines that are not vulnerable to cross-temperature sensing. In other words, by applying the lower set of pass voltages VREADK_1, VREAD_1 while sensing the lower tail and applying the higher set of pass voltages VREADK_2, VREAD_2 while sensing the upper tail, it is easier to distinguish the memory blocks that are vulnerable to cross-temperature read errors from those that are not vulnerable to cross-temperature read errors. In an example embodiment, the first set of pass voltages VREADK_1, VREAD_1 are both greater than ten Volts (10 V), and the second set of pass voltages VREADK_2, VREAD_2 are both less than eight Volts (8 V).

Turning now to FIG. 18 , a plot of cross-temperature sensing operations applied to a plurality of word lines in memory blocks at four different program and erase cycle amounts (1 cycle, 300 cycles, 1,000 cycles, and 3,000 cycles) is provided. During these tests, VBLC, VREADK, and VREAD were all varied when sensing the upper and lower tails of the nVt distributions to determine the nVt widths of those nVt distributions. The X-axis depicts the result of the differences between the nVt width of a word line in a bad location (nVt_WL79) squared and a word line in a good location (nVt_WL24) squared, i.e., (nVt_WL79)²−(nVt_WL24)². As illustrated, zero or very few memory blocks at one and three hundred cycles failed the cross-temperature sensing operation. More memory blocks at one thousand cycles failed the cross-temperature sensing operation, and even more memory blocks at three thousand cycles failed the cross-temperature sensing operation. By allowing the memory device to detect when a memory block becomes vulnerable to cross-temperature read errors, the techniques provided in the present disclosure may protect data by reducing UECC errors.

Turning now to FIG. 19 , provided is a more expanded flow chart depicting a more expanded process of checking the memory block for vulnerability to cross-temperature read errors. At step 1900, a cross-temperature sensing or judgment operation is triggered. A count CNT is set to “1,” i.e., CNT=1. At step 1902, the memory cells of a block N are erased, e.g., from TLC or QLC. At step 1904, a natural program pattern (All00) including one or more programming pulse is performed on the memory cells of the memory block, i.e., program-verify, smart verify, etc. are disabled to program the memory cells to an nVt distribution.

At decision step 1906, it is determined if CNT is equal to “2.” If the answer at decision step 1906 is “no,” then at step 1908, the word line to read to determine the first nVt width (nVt_WL1) is set at a word line in a bad location, e.g., WL83. If the answer at decision step 1906 is “yes,” then at step 1910, the word line to be read to determine the second nVt width (nVt_WL2) is set at a word line in a good location, e.g., WL27.

Following either step 1908 or step 1910, the process begins of identifying the lower tail of the nVt distribution. At step 1912, the control gate voltage is set at an nVt voltage level, i.e., VCGR=NVT_VCGR. At step 1914, the parameters are set to detect the lower tail voltage (Vt_−3 sigma or Low_Vt). Specifically, VBLC is set at a high level, and the pass voltages VREADK, VREAD are set at the first levels VREADK_1, VREAD_1.

At step 1916, the memory cells are read with a bit scan pass fail rate (NVT_BSPF) set at a predetermined level (for example, two hundred). At decision step 1918, it is determined if the sensing operation at step 1916 passed, i.e., did the number of memory cells with Vts below VCGR exceed NVT_BSPF. If the answer at decision step 1918 is “yes,” then the lower tail voltage has not been identified yet and at step 1920, the control gate voltage VCGR is incrementally increased, i.e., VCGR=VCGR+DVCGR. The process then returns to step 1916 to read the word line again. If the answer decision at step 1918 is “no,” then the lower tail voltage has been detected and at step 1922, the lower tail voltage is set at VCGR, i.e., Low_Vt=VCGR.

With the lower tail voltage now identified, the process proceeds to identifying the upper tail voltage of the selected word line. At step 1924, the control gate voltage VCGR is incrementally increased, i.e., VCGR=Low_Vt+NVT_DVT. At step 1926, the parameters are set to detect the upper tail voltage (Vt_+3_sigma or High_Vt). Specifically, VBLC is set at a low level, and the pass voltages VREADK, VREAD are set at the second levels VREADK_2, VREAD_2.

At step 1928, the memory cells are read with a bit scan pass fail rate (NVT_BSPF) set at the predetermined level. At decision step 1930, it is determined if the sensing operation at step 1928 passed. If the answer at decision step 1930 is “no,” then the upper tail voltage has not been detected and at step 1932 the control gate voltage VCGR is incrementally increased, i.e., VCGR=VCGR+DVCGR. The process then returns to step 1928 to read the word line again. If the answer at decision step 1930 is “yes,” then the upper tail voltage has been detected and at step 1934, the upper tail voltage is set at VCGR, i.e., High_Vt=VCGR.

At step 1936, it is determined if the count CNT=2. If the answer at decision step 1936 is “no,” then at step 1938, the first NVT width NVT1 is set at the difference between High_Vt and Low_Vt, i.e., NVT1=High_Vt−Low_Vt. At step 1940, the counter is increased, i.e., CNT=CNT+1. The process then returns to decision step 1906.

If the answer at decision step 1936 is “yes,” then at step 1942, the second NVT width NVT2 is set at the difference between High_Vt and Low_Vt, i.e., NVT2=High_Vt−Low_Vt.

At decision step 1942, it is determined if the difference between NVT1 ²and NVT2 ²is less than a threshold NVT_CRI, i.e., is NVT1 ²−NVT2 ²<NVT_CRI? If the answer at decision step 1942 is “no,” then at step 1944, the cross-temperature sensing operation is determined to have failed. The memory block N is then either retired or transitioned to SLC operation. If the answer at decision step 1942 is “yes,” then at step 1946, the cross-temperature sensing operation is determined to have passed, and the memory block N proceeds operating as normal.

Various terms are used herein to refer to particular system components. Different companies may refer to a same or similar component by different names and this description does not intend to distinguish between components that differ in name but not in function. To the extent that various functional units described in the following disclosure are referred to as “modules,” such a characterization is intended to not unduly restrict the range of potential implementation mechanisms. For example, a “module” could be implemented as a hardware circuit that includes customized very-large-scale integration (VLSI) circuits or gate arrays, or off-the-shelf semiconductors that include logic chips, transistors, or other discrete components. In a further example, a module may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, a programmable logic device, or the like. Furthermore, a module may also, at least in part, be implemented by software executed by various types of processors. For example, a module may comprise a segment of executable code constituting one or more physical or logical blocks of computer instructions that translate into an object, process, or function. Also, it is not required that the executable portions of such a module be physically located together, but rather, may comprise disparate instructions that are stored in different locations and which, when executed together, comprise the identified module and achieve the stated purpose of that module. The executable code may comprise just a single instruction or a set of multiple instructions, as well as be distributed over different code segments, or among different programs, or across several memory devices, etc. In a software, or partial software, module implementation, the software portions may be stored on one or more computer-readable and/or executable storage media that include, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, apparatus, or device, or any suitable combination thereof. In general, for purposes of the present disclosure, a computer-readable and/or executable storage medium may be comprised of any tangible and/or non-transitory medium that is capable of containing and/or storing a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

Similarly, for the purposes of the present disclosure, the term “component” may be comprised of any tangible, physical, and non-transitory device. For example, a component may be in the form of a hardware logic circuit that is comprised of customized VLSI circuits, gate arrays, or other integrated circuits, or is comprised of off-the-shelf semiconductors that include logic chips, transistors, or other discrete components, or any other suitable mechanical and/or electronic devices. In addition, a component could also be implemented in programmable hardware devices such as field programmable gate arrays (FPGA), programmable array logic, programmable logic devices, etc. Furthermore, a component may be comprised of one or more silicon-based integrated circuit devices, such as chips, die, die planes, and packages, or other discrete electrical devices, in an electrical communication configuration with one or more other components via electrical conductors of, for example, a printed circuit board (PCB) or the like. Accordingly, a module, as defined above, may in certain embodiments, be embodied by or implemented as a component and, in some instances, the terms module and component may be used interchangeably.

Where the term “circuit” is used herein, it includes one or more electrical and/or electronic components that constitute one or more conductive pathways that allow for electrical current to flow. A circuit may be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components may provide a return pathway for the electrical current. By contrast, in an open-looped configuration, the circuit components therein may still be regarded as forming a circuit despite not including a return pathway for the electrical current. For example, an integrated circuit is referred to as a circuit irrespective of whether the integrated circuit is coupled to ground (as a return pathway for the electrical current) or not. In certain exemplary embodiments, a circuit may comprise a set of integrated circuits, a sole integrated circuit, or a portion of an integrated circuit. For example, a circuit may include customized VLSI circuits, gate arrays, logic circuits, and/or other forms of integrated circuits, as well as may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In a further example, a circuit may comprise one or more silicon-based integrated circuit devices, such as chips, die, die planes, and packages, or other discrete electrical devices, in an electrical communication configuration with one or more other components via electrical conductors of, for example, a printed circuit board (PCB). A circuit could also be implemented as a synthesized circuit with respect to a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, and/or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and/or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may in certain embodiments, be embodied by or implemented as a circuit.

It will be appreciated that example embodiments that are disclosed herein may be comprised of one or more microprocessors and particular stored computer program instructions that control the one or more microprocessors to implement, in conjunction with certain non-processor circuits and other elements, some, most, or all of the functions disclosed herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), in which each function or some combinations of certain of the functions are implemented as custom logic. A combination of these approaches may also be used. Further, references below to a “controller” shall be defined as comprising individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with controlling software, a digital signal processor (DSP), a field programmable gate array (FPGA), and/or a processor with controlling software, or combinations thereof.

Additionally, the terms “couple,” “coupled,” or “couples,” where may be used herein, are intended to mean either a direct or an indirect connection. Thus, if a first device couples, or is coupled to, a second device, that connection may be by way of a direct connection or through an indirect connection via other devices (or components) and connections.

Regarding, the use herein of terms such as “an embodiment,” “one embodiment,” an “exemplary embodiment,” a “particular embodiment,” or other similar terminology, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with the embodiment is found in at least one embodiment of the present disclosure. Therefore, the appearances of phrases such as “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” etc., may, but do not necessarily, all refer to the same embodiment, but rather, mean “one or more but not all embodiments” unless expressly specified otherwise. Further, the terms “comprising,” “having,” “including,” and variations thereof, are used in an open-ended manner and, therefore, should be interpreted to mean “including, but not limited to . . . ” unless expressly specified otherwise. Also, an element that is preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the subject process, method, system, article, or apparatus that includes the element.

The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. In addition, the phrase “at least one of A and B” as may be used herein and/or in the following claims, whereby A and B are variables indicating a particular object or attribute, indicates a choice of A or B, or both A and B, similar to the phrase “and/or.” Where more than two variables are present in such a phrase, this phrase is hereby defined as including only one of the variables, any one of the variables, any combination (or sub-combination) of any of the variables, and all of the variables.

Further, where used herein, the term “about” or “approximately” applies to all numeric values, whether or not explicitly indicated. These terms generally refer to a range of numeric values that one of skill in the art would consider equivalent to the recited values (e.g., having the same function or result). In certain instances, these terms may include numeric values that are rounded to the nearest significant figure.

In addition, any enumerated listing of items that is set forth herein does not imply that any or all of the items listed are mutually exclusive and/or mutually inclusive of one another, unless expressly specified otherwise. Further, the term “set,” as used herein, shall be interpreted to mean “one or more,” and in the case of “sets,” shall be interpreted to mean multiples of (or a plurality of) “one or more,” “ones or more,” and/or “ones or mores” according to set theory, unless expressly specified otherwise.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or be limited to the precise form disclosed. Many modifications and variations are possible in light of the above description. The described embodiments were chosen to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the technology is defined by the claims appended hereto.

Claims

What is claimed is:

1. A method of testing a memory block in a memory device for cross-temperature read error vulnerability, comprising the steps of:

preparing a memory block including an array of memory cells;

programming a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution;

calculating an nVt width of the nVt distribution;

comparing the nVt width to a threshold; and

identifying the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

2. The method as set forth in claim 1 further including the step of retiring the memory block in response to the memory block being identified as being vulnerable to cross-temperature read errors.

3. The method as set forth in claim 1 further including the step of transitioning the memory block from multi-bit per memory cell operation to single bit per memory cell operation in response to the memory block being identified as being vulnerable to cross-temperature read errors.

4. The method as set forth in claim 1 wherein the step of calculating the nVt width of the nVt distribution includes the steps of identifying a lower tail of the nVt distribution and identifying an upper tail of the nVt distribution and calculating a difference between the lower and upper tails of the nVt distribution.

5. The method as set forth in claim 4 wherein during the step of identifying the lower tail of the nVt distribution, a first bit line voltage is applied to the bit lines coupled to the memory;

wherein during the step of identifying the upper tail of the nVt distribution, a second bit line voltage is applied to the bit lines coupled to the memory cells; and

wherein the first bit line voltage is different than the second bit line voltage.

6. The method as set forth in claim 5 wherein the first bit line voltage is greater than the second bit line voltage.

7. The method as set forth in claim 4 wherein during the step of identifying the lower tail of the nVt distribution, a first set of pass voltages is applied to the unselected word lines of the memory block;

wherein during the step of identifying the upper tail of the nVt distribution, a second set of pass voltages is applied to the unselected word lines of the memory block; and

wherein the first set of pass voltages is different than the second set of pass voltages.

8. The method as set forth in claim 7 wherein the first set of pass voltages is greater than the second set of pass voltages.

9. The method as set forth in claim 1 further including the step of erasing the memory cells of the memory block prior to the step of programming the group of memory cells to obtain the nVt distribution.

10. A memory device, comprising:

a memory block including an array of memory cells;

control circuitry in communication with the memory cells, the control circuitry being configured to:

program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution;

calculate an nVt width of the nVt distribution;

compare the nVt width to a threshold; and

identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

11. The memory device as set forth in claim 10 wherein the control circuitry is further configured to retire the memory block in response to the memory block being identified as being vulnerable to cross-temperature read errors.

12. The memory device as set forth in claim 10 wherein the control circuitry is further configured to transition the memory block from multi-bit per memory cell operation to single bit per memory cell operation in response to the memory block being identified as being vulnerable to cross-temperature read errors.

13. The memory device as set forth in claim 10 wherein the control circuitry is configured to calculate the nVt width of the nVt distribution by identifying a lower tail of the nVt distribution and identifying an upper tail of the nVt distribution and calculating a difference between the lower and upper tails of the nVt distribution.

14. The memory device as set forth in claim 13 wherein when identifying the lower tail of the nVt distribution, the control circuitry applies a first bit line voltage to the bit lines coupled to the memory;

and when identifying the upper tail of the nVt distribution, the control circuitry applies a second bit line voltage to the bit lines coupled to the memory cells; and

15. The memory device as set forth in claim 14 wherein the first bit line voltage is greater than the second bit line voltage.

16. The memory device as set forth in claim 13 wherein while identifying the lower tail of the nVt distribution, the control circuitry applies a first set of pass voltages to the unselected word lines of the memory block;

wherein while identifying the upper tail of the nVt distribution, the control circuity applies a second set of pass voltages to the unselected word lines of the memory block; and

17. The memory device as set forth in claim 16 wherein the first set of pass voltages is greater than the second set of pass voltages.

18. The method as set forth in claim 16 wherein the control circuitry is configured to erase the memory cells of the memory block prior to the step of programming the group of memory cells to obtain the nVt distribution.

19. An apparatus, comprising:

a memory block including an array of memory cells;

a controlling means for detecting vulnerability to cross-temperature in communication with the memory cells, the controlling means configured to:

erase the memory cells of the memory block,

program the memory cells in a programming operation that does not include verify,

determine a first natural threshold voltage (nVt) distribution of a first word line,

calculate a first nVt width of the first nVt distribution,

determine a second nVt distribution of a second word line,

calculate a second nVt width of the second nVt distribution,

compare a difference between the first nVt width and the second nVt width to a threshold, and

20. The apparatus as set forth in claim 19 wherein when determining the first and second nVt widths, the controlling means is configured to determine an upper tail and a lower tail of each of the first and second nVt distributions, and when determining the lower tails of the first and second nVt distributions, the controlling means applies a first bit line voltage to the bit lines coupled to the memory cells and applies a first set of pass voltages to a plurality of unselected word lines, and the controlling means applies a second bit line voltage to the bit lines coupled to the memory cells and applies a second set of pass voltages to the plurality of unselected word lines.