US11869895B2 - Display panel and manufacturing method thereof - Google Patents

Display panel and manufacturing method thereof Download PDF

Info

Publication number
US11869895B2
US11869895B2 US16/311,693 US201816311693A US11869895B2 US 11869895 B2 US11869895 B2 US 11869895B2 US 201816311693 A US201816311693 A US 201816311693A US 11869895 B2 US11869895 B2 US 11869895B2
Authority
US
United States
Prior art keywords
doped region
layer
type
light shielding
glass substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/311,693
Other versions
US20200104008A1 (en
Inventor
Yuan Yan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201811135751.9A external-priority patent/CN109148504A/en
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAN, YUAN
Publication of US20200104008A1 publication Critical patent/US20200104008A1/en
Priority to US18/522,222 priority Critical patent/US20240096899A1/en
Application granted granted Critical
Publication of US11869895B2 publication Critical patent/US11869895B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H01L27/1214—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G06F3/0421—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means by interrupting or reflecting a light beam, e.g. optical touch-screen
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H01L27/1251—
    • H01L31/0284—
    • H01L31/10—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H10F77/1228—Active materials comprising only Group IV materials porous silicon
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds

Definitions

  • the present disclosure relates to a display panel and a manufacturing method thereof, and in particular to a display panel for touchscreen and a manufacturing method thereof.
  • a medical amorphous silicon panel detector is a conventional optical sensor, which comprises amorphous silicon photodiodes and thin film transistors.
  • FIG. 1 a schematic diagram of a panel detector pixel unit is illustrated, wherein pixel units are formed on a substrate 11 .
  • Each of the pixel units comprises a thin film transistor 12 and an amorphous silicon photodiode 13 , wherein the amorphous silicon photodiode 13 includes a first light shielding layer 131 , a first insulating layer 132 , a drain electrode layer 133 , an N-type layer 134 , an intermediate layer 135 , a P-type layer 136 and a contact electrode 137 .
  • an insulating layer 14 insulates the thin film transistor 12 from the amorphous silicon photodiode 13 .
  • a second light shielding layer 15 is formed on the thin film transistor 12 and a portion of the surface of the insulating layer 14 where no light is required.
  • a connection electrode 16 is formed on the contact electrode 137 .
  • a passivation layer 17 is formed on the second light shielding layer 15 and the connection electrode 16 .
  • the first light shielding layer 131 and a gate of the thin film transistor 12 are located on the same metal layer, and the drain electrode layer 133 and a drain of the thin film transistor 12 are located on the same metal layer.
  • the main part of the amorphous silicon photodiode is a stack of the P-type layer 136 , the intermediate layer 135 , and the N-type layer 134 , wherein the intermediate layer 135 is processed by lightly doping. Therefore, the thickness of the panel detector is approximately the thickness of the amorphous silicon photodiode 13 superimposed on the drain of the thin film transistor 12 , and the intermediate layer 135 of the amorphous silicon photodiode has a thickness of about 1 micrometer so that the thickness of the panel detector is larger.
  • the optical path of the incident light in the pixel unit of the panel detector is long, and the incident light easily enters adjacent pixel units to cause interference.
  • the pixel unit includes the thin film transistor 12 and the amorphous silicon photodiode 13 disposed separately, wherein the thin film transistor 12 and the amorphous silicon photodiode 13 are separated by a distance so that the pixel unit has a larger occupied area and a lower resolution.
  • the amorphous silicon photodiode 13 needs to be separately fabricated after forming the thin film transistor 12 , and multiple steps of film formation and lithography are required during the fabrication process so that production cost higher.
  • An object of the present disclosure is to provide a display panel and a manufacturing method thereof, which dispose a thin film transistor with polysilicon on a glass substrate, and forms amorphous silicon photodiode by ion implantation at the same time so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode.
  • the present disclosure provides a display panel, which comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source-drain contacting layer, and a passivation layer, wherein the insulating layer is formed on the glass substrate; the polysilicon layer is formed on the insulating layer; the gate insulating layer is formed on the polysilicon layer; the gate layer is formed on the gate insulating layer; the interlayer insulating layer is formed on the gate layer; the source-drain contacting layer is formed on the interlayer insulating layer; the passivation layer is formed on the source-drain contacting layer and the interlayer insulating layer.
  • the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region; a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure; the doping type of the first doped region and a doping type of the second doped region are same.
  • the first doped region is formed with two N-type heavily doped regions configured to be a N + -type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer.
  • the polysilicon layer is further defined with a non-doped region; the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located at two opposite sides of the non-doped region, respectively.
  • the PN structure formed from the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, and the N-type lightly doped region, the N-type heavily doped region, and the gate layer define as a thin film transistor.
  • a projection of the non-doped region projected on the glass substrate overlaps a projection of the gate layer projected on the glass substrate, and a projection of the P-type doped region projected on the glass substrate overlaps a projection of the N-type heavily doped region projected on the glass substrate.
  • the display panel further comprises a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
  • the present disclosure further provides a manufacturing method of a display panel, the manufacturing method comprises a polysilicon layer forming step, a first doped region doping step, a second doped region doping step, a third doped region doping step, an interlayer insulating layer forming step, and a source-drain contacting layer forming step, wherein the polysilicon layer forming step is configured for depositing an insulating layer on a glass substrate and forming a polysilicon layer on the insulating layer; the first doped region doping step is configured for defining a first doped region in the polysilicon layer and doping the first doped region; the second doped region doping step is configured for depositing a gate insulating layer and a first metal layer in sequence, and patterning the first metal layer as a gate layer, and then defining a second doped region in the polysilicon layer and doping the second doped region, wherein a doping type of the first doped region and a doping type of the second doped region are same;
  • the first doped region in the first doped region doping step, is formed with two N-type heavily doped regions, wherein the N-type heavily doped regions are performed by N-type doping so that the N-type heavily doped regions are converted into a N + -type layer.
  • the second doped region is formed with two N-type lightly doped regions, wherein the N-type lightly doped regions are performed by N-type doping so that the N-type lightly doped regions are converted into a N ⁇ -type layer.
  • the third doped region is formed with a P-type doped region, wherein the P-type doped region is performed by P-type doping so that the P-type doped region is converted into a P-type layer, and the P-type layer is located on the N + -type layer.
  • the present disclosure further provides a display panel, which comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain contacting layer, wherein the insulating layer is formed on the glass substrate; the polysilicon layer is formed on the insulating layer; the gate insulating layer is formed on the polysilicon layer; the gate layer is formed on the gate insulating layer; the interlayer insulating layer is formed on the gate layer; the source-drain contacting layer is formed on the interlayer insulating layer.
  • the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region; a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure; the doping type of the first doped region and a doping type of the second doped region are same.
  • the first doped region is formed with two N-type heavily doped regions configured to be a N + -type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer.
  • the polysilicon layer is further defined with a non-doped region; the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located at two opposite sides of the non-doped region, respectively.
  • the PN structure formed from the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, and the N-type lightly doped region, the N-type heavily doped region, and the gate layer define as a thin film transistor.
  • a projection of the non-doped region projected on the glass substrate overlaps a projection of the gate layer projected on the glass substrate, and a projection of the P-type doped region projected on the glass substrate overlaps a projection of the N-type heavily doped region projected on the glass substrate.
  • the display panel further comprises a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
  • the beneficial effect is that the thin film transistor is formed on the glass substrate by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio. In addition, the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.
  • FIG. 1 is a schematic diagram of a pixel unit of a panel detector in the prior art.
  • FIG. 2 is a schematic diagram of a display panel according to a preferred embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram in a light shielding layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram in a polysilicon layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram in a N-type doping step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram in a gate layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram in a P-type doping step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram in an interlayer insulating layer forming ste of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • the display panel comprises a glass substrate 21 , a light shielding layer 22 , an insulating layer 23 , a polysilicon layer 24 , a gate insulating layer 25 , a gate layer 26 , an interlayer insulating layer 27 , a source-drain contacting layer 28 , and a passivation layer 29 .
  • the detailed structure of each component, assembly relationships, and principles of operation for the present invention will be described in detail hereinafter.
  • the TFT of the top gate structure is used for description in the embodiment, and the same manner can also be applied to the display panel of the TFT structure of the bottom gate structure.
  • TFTs of different semiconductor types are equally applicable to the solution in this application. For example, those skilled in the art can adjust the doping type of the N-type TFT and the P-type TFT.
  • the light shielding layer 22 is formed on the glass substrate 21 , and the light shielding layer 22 comprises a first light shielding portion 221 and a second light shielding portion 222 , wherein the first light shielding portion 221 and the second light shielding portion 222 are spaced to with other and disposed on the glass substrate 21 .
  • the insulating layer 23 is formed on the light shielding layer 22 and the glass substrate 21
  • the polysilicon layer 24 is formed on the insulating layer 23 , wherein the polysilicon layer 24 is defined with a non-doped region 241 , a first doped region 243 , a second doped region 242 , and a third doped region 244 .
  • a doping type of the first doped region 243 and a doping type of the third doped region 244 are different so that the first doped region 243 and the third doped region 244 form a PN structure, and the doping type of the first doped region 243 and a doping type of the second doped region 242 are same.
  • the second doped region 242 is formed with two N-type lightly doped regions processed N-type light doping by ion implantation
  • the first doped region 243 is formed with two N-type heavily doped regions processed N-type heavy doping by ion implantation
  • the third doped region 244 is formed with a P-type doped region processed P-type doping by ion implantation.
  • the doped regions can be doped with different types, such as the second doped region 242 is processed P-type light doping, the first doped region 243 is processed P-type heavy doping, and the third doped region 244 is processed N-type doping.
  • the N-type lightly doped regions of the second doped region 242 are located at two opposite sides of the non-doped region 241 , respectively.
  • the N-type heavily doped regions of the first doped region 243 are adjacent to the side of the N-type lightly doped regions of the second doped region 242 away from the non-doped region 241 , and the third doped region 244 is overlapped on one of the N-type heavily doped regions of the first doped region 243 .
  • a projection of the non-doped region 241 projected on the glass substrate 21 overlaps a projection of the gate layer 26 projected on the glass substrate 21
  • a projection of the second light shielding portion 222 of the light shielding layer 22 projected on the glass substrate 21 overlaps a projection of the N-type lightly doped regions of the second doped region 242 projected on the glass substrate 21
  • a projection of the P-type doped region of the third doped region 244 projected on the glass substrate 21 overlaps a projection of the first light shielding portion 221 of the light shielding layer 22 projected on the glass substrate 21 and a projection of the N-type heavily doped region of the first doped region 243 projected on the glass substrate 21 .
  • the gate insulating layer 25 is formed on the polysilicon layer 24
  • the gate layer 26 is formed on the gate insulating layer 25 , wherein the gate layer 26 is a first metal layer by patterning.
  • the interlayer insulating layer 27 is formed on the gate layer 26 and the gate insulating layer 25 , wherein the interlayer insulating layer 27 is formed with a plurality of holes 271 .
  • the holes 271 are configured to form the source-drain contacting layer 28 so that the source-drain contacting layer 28 is formed on the interlayer insulating layer 27 .
  • the passivation layer 29 is formed on the source-drain contacting layer 28 and the interlayer insulating layer 27 .
  • the first doped region 243 is formed with two N-type heavily doped regions configured to be a N + -type layer
  • the third doped region 244 is formed with a P-type doped region configured to be a P-type layer, so that the first doped region 243 and the third doped region 244 form a PN structure
  • the source-drain contacting layer 28 contacts the N + -type layer of the first doped region 243 and the P-type layer of the third doped region 244 .
  • the PN structure formed from the first doped region 243 and the third doped region 244 is located above the first light shielding portion 221 , and can be defined as an amorphous silicon photodiode to sense the reflected light of the finger, wherein the anode of the amorphous silicon photodiode is the P-type layer provided with a negative voltage between ⁇ 3V to ⁇ 9V.
  • the amorphous silicon photodiode generates electron-hole pairs when an optical signal is incident on the amorphous silicon photodiode. In the electric field, the holes converge to the P-type layer (anode), and electrons converge to the N-type layer (cathode).
  • the second doped region 242 , the first doped region 243 , and the gate layer 26 are located above the second light shielding portion 222 , and can be defined as a thin film transistor, such as a TFT thin film transistor.
  • a thin film transistor such as a TFT thin film transistor.
  • the thin film transistor is formed on the glass substrate 21 by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio.
  • the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.
  • FIG. 3 is a flowchart of a manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
  • the manufacturing method comprises a light shielding layer forming step S 201 , a polysilicon layer forming step S 202 , a first doped region doping step S 203 , a second doped region doping step S 204 , a third doped region doping step S 205 , an interlayer insulating layer forming step S 206 , a source-drain contacting layer forming step S 207 , and a passivation layer forming step S 208 .
  • the detailed principles of operation for the present invention will be described in detail hereinafter.
  • a glass substrate 21 is provided, and an opaque material layer is deposited on the glass substrate 21 , such as metal layer, and then opaque material layer is patterned as a light shielding layer 22 .
  • the light shielding layer 22 comprises a first light shielding portion 221 and a second light shielding portion 222 , wherein the first light shielding portion 221 and the second light shielding portion 222 are spaced to with other and disposed on the glass substrate 21 .
  • an insulating layer 23 is deposited on the glass substrate 21 , and a polysilicon layer 24 is formed on the insulating layer 23 .
  • the polysilicon layer 24 is defined with a first doped region 243 , and the first doped region 243 is processed by N-type doping so that the first doped region 243 is formed with two N-type heavily doped regions and converted to an N + -type layer.
  • a gate insulating layer 25 and a first metal layer are sequentially deposited, and the first metal layer is patterned as a gate layer 26 .
  • the polysilicon layer 24 is defined with a second doped region 242 , and the second doped region 242 is processed by N-type doping so that the second doped region 242 is formed with two N-type lightly doped regions and converted to an N ⁇ -type layer, wherein the doping type of the first doped region 243 and the doping type of the second doped region 242 are same.
  • a portion of a surface of the first doped region 243 is defined a third doped region 244 , and the third doped region 244 is processed by P-type doping so that the third doped region 244 is formed with a P-type doped region and converted to a P-type layer, wherein the doping type of the first doped region 243 and the doping type of the third doped region 244 are different, and the P-type layer is located on the N + -type layer.
  • a interlayer insulating layer 27 is deposited, and a plurality of holes 271 are formed on the interlayer insulating layer 27 .
  • a second metal layer is deposited in the holes 271 , and the second metal layer is patterned as a source-drain contacting layer 28 so that the source-drain contacting layer 28 contacts the N + -type layer of the first doped region 243 and the P-type layer of the third doped region 244 .
  • a layer of high dielectric constant material is deposited through an atomic layer deposition as a passivation layer 29 .
  • the thin film transistor is formed on the glass substrate 21 by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio.
  • the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Thin Film Transistor (AREA)

Abstract

A display panel and a manufacturing method thereof are provided. The display panel comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain contacting layer, wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region. The source-drain contacting layer contacts the first doped region and the third doped region. A doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure. Doping type of the first doped region and a doping type of the second doped region are same.

Description

FIELD OF INVENTION
The present disclosure relates to a display panel and a manufacturing method thereof, and in particular to a display panel for touchscreen and a manufacturing method thereof.
BACKGROUND OF INVENTION
In the prior art, a medical amorphous silicon panel detector is a conventional optical sensor, which comprises amorphous silicon photodiodes and thin film transistors. As shown in FIG. 1 , a schematic diagram of a panel detector pixel unit is illustrated, wherein pixel units are formed on a substrate 11. Each of the pixel units comprises a thin film transistor 12 and an amorphous silicon photodiode 13, wherein the amorphous silicon photodiode 13 includes a first light shielding layer 131, a first insulating layer 132, a drain electrode layer 133, an N-type layer 134, an intermediate layer 135, a P-type layer 136 and a contact electrode 137.
Furthermore, an insulating layer 14 insulates the thin film transistor 12 from the amorphous silicon photodiode 13. A second light shielding layer 15 is formed on the thin film transistor 12 and a portion of the surface of the insulating layer 14 where no light is required. A connection electrode 16 is formed on the contact electrode 137. A passivation layer 17 is formed on the second light shielding layer 15 and the connection electrode 16. The first light shielding layer 131 and a gate of the thin film transistor 12 are located on the same metal layer, and the drain electrode layer 133 and a drain of the thin film transistor 12 are located on the same metal layer.
However, the main part of the amorphous silicon photodiode is a stack of the P-type layer 136, the intermediate layer 135, and the N-type layer 134, wherein the intermediate layer 135 is processed by lightly doping. Therefore, the thickness of the panel detector is approximately the thickness of the amorphous silicon photodiode 13 superimposed on the drain of the thin film transistor 12, and the intermediate layer 135 of the amorphous silicon photodiode has a thickness of about 1 micrometer so that the thickness of the panel detector is larger. The optical path of the incident light in the pixel unit of the panel detector is long, and the incident light easily enters adjacent pixel units to cause interference.
In addition, the pixel unit includes the thin film transistor 12 and the amorphous silicon photodiode 13 disposed separately, wherein the thin film transistor 12 and the amorphous silicon photodiode 13 are separated by a distance so that the pixel unit has a larger occupied area and a lower resolution. Moreover, the amorphous silicon photodiode 13 needs to be separately fabricated after forming the thin film transistor 12, and multiple steps of film formation and lithography are required during the fabrication process so that production cost higher.
As a result, it is necessary to provide a display panel and a manufacturing method thereof to solve the problems existing in the conventional technologies, as described above.
SUMMARY OF INVENTION
An object of the present disclosure is to provide a display panel and a manufacturing method thereof, which dispose a thin film transistor with polysilicon on a glass substrate, and forms amorphous silicon photodiode by ion implantation at the same time so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode.
The present disclosure provides a display panel, which comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source-drain contacting layer, and a passivation layer, wherein the insulating layer is formed on the glass substrate; the polysilicon layer is formed on the insulating layer; the gate insulating layer is formed on the polysilicon layer; the gate layer is formed on the gate insulating layer; the interlayer insulating layer is formed on the gate layer; the source-drain contacting layer is formed on the interlayer insulating layer; the passivation layer is formed on the source-drain contacting layer and the interlayer insulating layer. The polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region; a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure; the doping type of the first doped region and a doping type of the second doped region are same.
In one embodiment of the present disclosure, the first doped region is formed with two N-type heavily doped regions configured to be a N+-type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer.
In one embodiment of the present disclosure, the polysilicon layer is further defined with a non-doped region; the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located at two opposite sides of the non-doped region, respectively.
In one embodiment of the present disclosure, the PN structure formed from the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, and the N-type lightly doped region, the N-type heavily doped region, and the gate layer define as a thin film transistor.
In one embodiment of the present disclosure, a projection of the non-doped region projected on the glass substrate overlaps a projection of the gate layer projected on the glass substrate, and a projection of the P-type doped region projected on the glass substrate overlaps a projection of the N-type heavily doped region projected on the glass substrate.
In one embodiment of the present disclosure, the display panel further comprises a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
The present disclosure further provides a manufacturing method of a display panel, the manufacturing method comprises a polysilicon layer forming step, a first doped region doping step, a second doped region doping step, a third doped region doping step, an interlayer insulating layer forming step, and a source-drain contacting layer forming step, wherein the polysilicon layer forming step is configured for depositing an insulating layer on a glass substrate and forming a polysilicon layer on the insulating layer; the first doped region doping step is configured for defining a first doped region in the polysilicon layer and doping the first doped region; the second doped region doping step is configured for depositing a gate insulating layer and a first metal layer in sequence, and patterning the first metal layer as a gate layer, and then defining a second doped region in the polysilicon layer and doping the second doped region, wherein a doping type of the first doped region and a doping type of the second doped region are same; the third doped region doping step is configured for defining a third doped region in a portion of a surface of the first doped region and doping the third doped region, wherein the doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure; the interlayer insulating layer forming step is configured for depositing an interlayer insulating layer and forming a plurality of holes on the interlayer insulating layer; the source-drain contacting layer forming step is configured for depositing a second metal layer in the holes and patterning the second metal layer as a source-drain contacting layer so that the source-drain contacting layer contacts the first doped region and the third doped region.
In one embodiment of the present disclosure, in the first doped region doping step, the first doped region is formed with two N-type heavily doped regions, wherein the N-type heavily doped regions are performed by N-type doping so that the N-type heavily doped regions are converted into a N+-type layer.
In one embodiment of the present disclosure, in the second doped region doping step, the second doped region is formed with two N-type lightly doped regions, wherein the N-type lightly doped regions are performed by N-type doping so that the N-type lightly doped regions are converted into a N−-type layer.
In one embodiment of the present disclosure, in the third doped region doping step, the third doped region is formed with a P-type doped region, wherein the P-type doped region is performed by P-type doping so that the P-type doped region is converted into a P-type layer, and the P-type layer is located on the N+-type layer.
The present disclosure further provides a display panel, which comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain contacting layer, wherein the insulating layer is formed on the glass substrate; the polysilicon layer is formed on the insulating layer; the gate insulating layer is formed on the polysilicon layer; the gate layer is formed on the gate insulating layer; the interlayer insulating layer is formed on the gate layer; the source-drain contacting layer is formed on the interlayer insulating layer. The polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region; a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure; the doping type of the first doped region and a doping type of the second doped region are same.
In one embodiment of the present disclosure, the first doped region is formed with two N-type heavily doped regions configured to be a N+-type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer.
In one embodiment of the present disclosure, the polysilicon layer is further defined with a non-doped region; the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located at two opposite sides of the non-doped region, respectively.
In one embodiment of the present disclosure, the PN structure formed from the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, and the N-type lightly doped region, the N-type heavily doped region, and the gate layer define as a thin film transistor.
In one embodiment of the present disclosure, a projection of the non-doped region projected on the glass substrate overlaps a projection of the gate layer projected on the glass substrate, and a projection of the P-type doped region projected on the glass substrate overlaps a projection of the N-type heavily doped region projected on the glass substrate.
In one embodiment of the present disclosure, the display panel further comprises a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
The beneficial effect is that the thin film transistor is formed on the glass substrate by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio. In addition, the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.
DESCRIPTION OF DRAWINGS
In order to more clearly illustrate the embodiments or the prior art technical solutions embodiment of the present disclosure, will implement the following figures for the cases described in the prior art or require the use of a simple introduction. Obviously, the following description of the drawings are only some of those of ordinary skill in terms of creative effort without precondition, you can also obtain other drawings based on these drawings embodiments of the present disclosure.
FIG. 1 is a schematic diagram of a pixel unit of a panel detector in the prior art.
FIG. 2 is a schematic diagram of a display panel according to a preferred embodiment of the present disclosure.
FIG. 3 is a flowchart of a manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 4 is a schematic diagram in a light shielding layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 5 is a schematic diagram in a polysilicon layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 6 is a schematic diagram in a N-type doping step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 7 is a schematic diagram in a gate layer forming step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 8 is a schematic diagram in a P-type doping step of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
FIG. 9 is a schematic diagram in an interlayer insulating layer forming ste of the manufacturing method of the display panel according to a preferred embodiment of the present disclosure.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Structure and technical means adopted by the present disclosure to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings. Furthermore, directional terms described by the present disclosure, such as upper, lower, front, back, left, right, inner, outer, side, longitudinal/vertical, transverse/horizontal, etc., are only directions by referring to the accompanying drawings, and thus the used directional terms are used to describe and understand the present disclosure, but the present disclosure is not limited thereto.
Referring to FIG. 2 , a schematic diagram of a display panel according to a preferred embodiment of the present disclosure is illustrated. The display panel comprises a glass substrate 21, a light shielding layer 22, an insulating layer 23, a polysilicon layer 24, a gate insulating layer 25, a gate layer 26, an interlayer insulating layer 27, a source-drain contacting layer 28, and a passivation layer 29. The detailed structure of each component, assembly relationships, and principles of operation for the present invention will be described in detail hereinafter. It should be noted that the TFT of the top gate structure is used for description in the embodiment, and the same manner can also be applied to the display panel of the TFT structure of the bottom gate structure. Similarly, TFTs of different semiconductor types are equally applicable to the solution in this application. For example, those skilled in the art can adjust the doping type of the N-type TFT and the P-type TFT.
Referring to FIG. 2 , the light shielding layer 22 is formed on the glass substrate 21, and the light shielding layer 22 comprises a first light shielding portion 221 and a second light shielding portion 222, wherein the first light shielding portion 221 and the second light shielding portion 222 are spaced to with other and disposed on the glass substrate 21.
Referring to FIG. 2 , the insulating layer 23 is formed on the light shielding layer 22 and the glass substrate 21, and the polysilicon layer 24 is formed on the insulating layer 23, wherein the polysilicon layer 24 is defined with a non-doped region 241, a first doped region 243, a second doped region 242, and a third doped region 244. a doping type of the first doped region 243 and a doping type of the third doped region 244 are different so that the first doped region 243 and the third doped region 244 form a PN structure, and the doping type of the first doped region 243 and a doping type of the second doped region 242 are same. In the embodiment, the second doped region 242 is formed with two N-type lightly doped regions processed N-type light doping by ion implantation, the first doped region 243 is formed with two N-type heavily doped regions processed N-type heavy doping by ion implantation, and the third doped region 244 is formed with a P-type doped region processed P-type doping by ion implantation. In the other embodiment, the doped regions can be doped with different types, such as the second doped region 242 is processed P-type light doping, the first doped region 243 is processed P-type heavy doping, and the third doped region 244 is processed N-type doping.
Furthermore, the N-type lightly doped regions of the second doped region 242 are located at two opposite sides of the non-doped region 241, respectively. The N-type heavily doped regions of the first doped region 243 are adjacent to the side of the N-type lightly doped regions of the second doped region 242 away from the non-doped region 241, and the third doped region 244 is overlapped on one of the N-type heavily doped regions of the first doped region 243. In in the embodiment, a projection of the non-doped region 241 projected on the glass substrate 21 overlaps a projection of the gate layer 26 projected on the glass substrate 21, a projection of the second light shielding portion 222 of the light shielding layer 22 projected on the glass substrate 21 overlaps a projection of the N-type lightly doped regions of the second doped region 242 projected on the glass substrate 21, and a projection of the P-type doped region of the third doped region 244 projected on the glass substrate 21 overlaps a projection of the first light shielding portion 221 of the light shielding layer 22 projected on the glass substrate 21 and a projection of the N-type heavily doped region of the first doped region 243 projected on the glass substrate 21.
Referring to FIG. 2 , the gate insulating layer 25 is formed on the polysilicon layer 24, and the gate layer 26 is formed on the gate insulating layer 25, wherein the gate layer 26 is a first metal layer by patterning.
Referring to FIG. 2 , the interlayer insulating layer 27 is formed on the gate layer 26 and the gate insulating layer 25, wherein the interlayer insulating layer 27 is formed with a plurality of holes 271. The holes 271 are configured to form the source-drain contacting layer 28 so that the source-drain contacting layer 28 is formed on the interlayer insulating layer 27. The passivation layer 29 is formed on the source-drain contacting layer 28 and the interlayer insulating layer 27.
Referring to FIG. 2 , the first doped region 243 is formed with two N-type heavily doped regions configured to be a N+-type layer, the third doped region 244 is formed with a P-type doped region configured to be a P-type layer, so that the first doped region 243 and the third doped region 244 form a PN structure, and the source-drain contacting layer 28 contacts the N+-type layer of the first doped region 243 and the P-type layer of the third doped region 244.
According to the above structure, the PN structure formed from the first doped region 243 and the third doped region 244 is located above the first light shielding portion 221, and can be defined as an amorphous silicon photodiode to sense the reflected light of the finger, wherein the anode of the amorphous silicon photodiode is the P-type layer provided with a negative voltage between −3V to −9V. The amorphous silicon photodiode generates electron-hole pairs when an optical signal is incident on the amorphous silicon photodiode. In the electric field, the holes converge to the P-type layer (anode), and electrons converge to the N-type layer (cathode). In addition, the second doped region 242, the first doped region 243, and the gate layer 26 are located above the second light shielding portion 222, and can be defined as a thin film transistor, such as a TFT thin film transistor. When the thin film transistor is turned off, the signals are continuously accumulated. When the thin film transistor is turned on, the charge outputs to the data line, and the strength of the optical signal is determined according to the detected charge signal to achieve the effect of fingerprint recognition.
As described above, the thin film transistor is formed on the glass substrate 21 by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio. In addition, the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.
Referring to FIGS. 2 to 9 , FIG. 3 is a flowchart of a manufacturing method of the display panel according to a preferred embodiment of the present disclosure. The manufacturing method comprises a light shielding layer forming step S201, a polysilicon layer forming step S202, a first doped region doping step S203, a second doped region doping step S204, a third doped region doping step S205, an interlayer insulating layer forming step S206, a source-drain contacting layer forming step S207, and a passivation layer forming step S208. The detailed principles of operation for the present invention will be described in detail hereinafter.
Referring to FIGS. 3 and 4 , in the light shielding layer forming step S201, a glass substrate 21 is provided, and an opaque material layer is deposited on the glass substrate 21, such as metal layer, and then opaque material layer is patterned as a light shielding layer 22. The light shielding layer 22 comprises a first light shielding portion 221 and a second light shielding portion 222, wherein the first light shielding portion 221 and the second light shielding portion 222 are spaced to with other and disposed on the glass substrate 21.
Referring to FIGS. 3 and 5 , in the polysilicon layer forming step S202, an insulating layer 23 is deposited on the glass substrate 21, and a polysilicon layer 24 is formed on the insulating layer 23.
Referring to FIGS. 3 and 6 , in the first doped region doping step S203, the polysilicon layer 24 is defined with a first doped region 243, and the first doped region 243 is processed by N-type doping so that the first doped region 243 is formed with two N-type heavily doped regions and converted to an N+-type layer.
Referring to FIGS. 3 and 7 , in the second doped region doping step S204, a gate insulating layer 25 and a first metal layer are sequentially deposited, and the first metal layer is patterned as a gate layer 26. The polysilicon layer 24 is defined with a second doped region 242, and the second doped region 242 is processed by N-type doping so that the second doped region 242 is formed with two N-type lightly doped regions and converted to an N−-type layer, wherein the doping type of the first doped region 243 and the doping type of the second doped region 242 are same.
Referring to FIGS. 3 and 8 , in the third doped region doping step S205, a portion of a surface of the first doped region 243 is defined a third doped region 244, and the third doped region 244 is processed by P-type doping so that the third doped region 244 is formed with a P-type doped region and converted to a P-type layer, wherein the doping type of the first doped region 243 and the doping type of the third doped region 244 are different, and the P-type layer is located on the N+-type layer.
Referring to FIGS. 3 and 9 , in the interlayer insulating layer forming step S206, a interlayer insulating layer 27 is deposited, and a plurality of holes 271 are formed on the interlayer insulating layer 27.
Referring to FIGS. 2, 3 and 9 , in the source-drain contacting layer forming step S207, a second metal layer is deposited in the holes 271, and the second metal layer is patterned as a source-drain contacting layer 28 so that the source-drain contacting layer 28 contacts the N+-type layer of the first doped region 243 and the P-type layer of the third doped region 244. In addition, in the passivation layer forming step S208, a layer of high dielectric constant material is deposited through an atomic layer deposition as a passivation layer 29.
As described above, the thin film transistor is formed on the glass substrate 21 by polysilicon, and the amorphous silicon photodiode is formed by ion implantation technology, so that the intensity of the reflected light of the fingerprint can be recognized by the amorphous silicon photodiode. Since the thin film transistor has a low leakage current, and the current of the amorphous silicon photodiode is identified to obtain a better signal to noise ratio. In addition, the PN structure can realize N-type and P-type doping by ion implantation depth and ion complementary effect. Thus, the thin film transistor and the amorphous silicon photodiode are simultaneously prepared in the process without additional complicated structures and processes.
The present disclosure has been described with preferred embodiments thereof and it is understood that many changes and modifications to the described embodiments can be carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.

Claims (2)

What is claimed is:
1. A display panel, comprising:
a glass substrate;
an insulating layer formed on the glass substrate;
a polysilicon layer formed on the insulating layer;
a gate insulating layer formed on the polysilicon layer;
a gate layer formed on the gate insulating layer;
an interlayer insulating layer formed on the gate layer;
a source-drain contacting layer formed on the interlayer insulating layer;
a passivation layer formed on the source-drain contacting layer and the interlayer insulating layer; and
a light shielding layer formed on the glass substrate;
wherein the insulating layer covers the light shielding layer, the light shielding layer comprises a first light shielding portion and a second light shielding portion, and the first light shielding portion and the second light shielding portion are spaced apart from each other and disposed on the glass substrate;
wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region;
wherein the source-drain contacting layer contacts the first doped region and the third doped region; a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure located above the first light shielding portion;
wherein the doping type of the first doped region and a doping type of the second doped region are same;
wherein a projection of the third doped region projected on the glass substrate overlaps a projection of the first light shielding portion of the light shielding layer projected on the glass substrate, and a projection of the second light shielding portion of the light shielding layer projected on the glass substrate overlaps a projection of the second doped region projected on the glass substrate;
wherein the first doped region is formed with two N-type heavily doped regions configured to be an N+-type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer;
wherein the polysilicon layer is further defined with a non-doped region;
wherein the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located at two opposite sides of the non-doped region, respectively;
wherein the two N-type lightly doped regions of the second doped region are located at two opposite sides of the non-doped region; and
wherein each of the two N-type heavily doped regions of the first doped region is adjacent to a side of a corresponding one of the two N-type lightly doped regions of the second doped region away from the non-doped region, and the third doped region is overlapped on one of the N-type heavily doped regions of the first doped region.
2. A display panel, comprising:
a glass substrate;
an insulating layer formed on the glass substrate;
a polysilicon layer formed on the insulating layer;
a gate insulating layer formed on the polysilicon layer;
a gate layer formed on the gate insulating layer;
an interlayer insulating layer formed on the gate layer;
a source-drain contacting layer formed on the interlayer insulating layer; and
a light shielding layer formed on the glass substrate;
wherein the insulating layer covers the light shielding layer, the light shielding layer comprises a first light shielding portion and a second light shielding portion, and the first light shielding portion and the second light shielding portion are spaced apart from each other and disposed on the glass substrate;
wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region;
wherein a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure located above the first light shielding portion;
wherein the doping type of the first doped region and a doping type of the second doped region are same;
wherein a projection of the third doped region projected on the glass substrate overlaps a projection of the first light shielding portion of the light shielding layer projected on the glass substrate, and a projection of the second light shielding portion of the light shielding layer projected on the glass substrate overlaps a projection of the second doped region projected on the glass substrate;
wherein the first doped region is formed with two N-type heavily doped regions configured to be an N+-type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer;
wherein the polysilicon layer is further defined with a non-doped region;
wherein the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located two opposite sides of the non-doped region, respectively;
wherein the two N-type lightly doped regions of the second doped region are located at two opposite sides of the non-doped region; and
wherein each of the two N-type heavily doped regions of the first doped region is adjacent to a side of a corresponding one of the two N-type lightly doped regions of the second doped region away from the non-doped region, and the third doped region is overlapped on one of the N-type heavily doped regions of the first doped region.
US16/311,693 2018-09-28 2018-11-01 Display panel and manufacturing method thereof Active US11869895B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/522,222 US20240096899A1 (en) 2018-09-28 2023-11-29 Display panels

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201811135751.9 2018-09-28
CN201811135751.9A CN109148504A (en) 2018-09-28 2018-09-28 Display panel and its manufacturing method
PCT/CN2018/113268 WO2020062415A1 (en) 2018-09-28 2018-11-01 Display panel and manufacturing method therefor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/113268 A-371-Of-International WO2020062415A1 (en) 2018-09-28 2018-11-01 Display panel and manufacturing method therefor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/522,222 Continuation US20240096899A1 (en) 2018-09-28 2023-11-29 Display panels

Publications (2)

Publication Number Publication Date
US20200104008A1 US20200104008A1 (en) 2020-04-02
US11869895B2 true US11869895B2 (en) 2024-01-09

Family

ID=69945846

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/311,693 Active US11869895B2 (en) 2018-09-28 2018-11-01 Display panel and manufacturing method thereof
US18/522,222 Pending US20240096899A1 (en) 2018-09-28 2023-11-29 Display panels

Family Applications After (1)

Application Number Title Priority Date Filing Date
US18/522,222 Pending US20240096899A1 (en) 2018-09-28 2023-11-29 Display panels

Country Status (1)

Country Link
US (2) US11869895B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110750020B (en) * 2019-10-31 2022-10-18 厦门天马微电子有限公司 Display module and display device
CN111668237B (en) * 2020-06-17 2024-01-26 京东方科技集团股份有限公司 A display substrate and its preparation method, driving method and display device
CN113299674B (en) * 2021-05-08 2022-09-09 武汉华星光电技术有限公司 array substrate
CN115513238A (en) * 2022-09-20 2022-12-23 云谷（固安）科技有限公司 Photoelectric sensor, display device and preparation method of photoelectric sensor

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710606A (en) * 1994-08-24 1998-01-20 Kabushiki Kaisha Toshiba LCD TFT having two layer region adjacent base region in which the layers have opposite conductivities and have two density gradients
CN1678952A (en) 2002-08-24 2005-10-05 皇家飞利浦电子股份有限公司 Manufacture of electronic devices comprising thin-film circuit elements
CN1894798A (en) 2003-12-15 2007-01-10 皇家飞利浦电子股份有限公司 Active matrix pixel device with photo sensor
US20070093007A1 (en) 2003-12-15 2007-04-26 Koninklijke Philips Electronic, N.V. Active matrix pixel device with photo sensor
US20080135851A1 (en) 2006-11-15 2008-06-12 Samsung Electronics Co., Ltd. Display and method of manufacturing the same
CN102253548A (en) 2010-05-21 2011-11-23 奇美电子股份有限公司 Image display system
US20110284851A1 (en) * 2010-05-21 2011-11-24 Chimei Innolux Corporation System for displaying images
US20120043540A1 (en) * 2009-03-16 2012-02-23 Tomohiro Kimura Semiconductor device, method for manufacturing same, and display device
CN102576739A (en) 2009-11-27 2012-07-11 夏普株式会社 Thin film transistor and manufacturing method for same, semiconductor device and manufacturing method for same, and display device
CN107623011A (en) 2017-10-12 2018-01-23 友达光电股份有限公司 Thin film transistor array substrate for X-ray detector and X-ray detector
CN208738250U (en) 2018-09-28 2019-04-12 武汉华星光电技术有限公司 Display panel

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710606A (en) * 1994-08-24 1998-01-20 Kabushiki Kaisha Toshiba LCD TFT having two layer region adjacent base region in which the layers have opposite conductivities and have two density gradients
CN1678952A (en) 2002-08-24 2005-10-05 皇家飞利浦电子股份有限公司 Manufacture of electronic devices comprising thin-film circuit elements
US20060030084A1 (en) * 2002-08-24 2006-02-09 Koninklijke Philips Electronics, N.V. Manufacture of electronic devices comprising thin-film circuit elements
CN1894798A (en) 2003-12-15 2007-01-10 皇家飞利浦电子股份有限公司 Active matrix pixel device with photo sensor
US20070093007A1 (en) 2003-12-15 2007-04-26 Koninklijke Philips Electronic, N.V. Active matrix pixel device with photo sensor
CN101226948A (en) 2006-11-15 2008-07-23 三星电子株式会社 Display and manufacturing method thereof
US20080135851A1 (en) 2006-11-15 2008-06-12 Samsung Electronics Co., Ltd. Display and method of manufacturing the same
US20120043540A1 (en) * 2009-03-16 2012-02-23 Tomohiro Kimura Semiconductor device, method for manufacturing same, and display device
CN102576739A (en) 2009-11-27 2012-07-11 夏普株式会社 Thin film transistor and manufacturing method for same, semiconductor device and manufacturing method for same, and display device
US20120242624A1 (en) 2009-11-27 2012-09-27 Sharp Kabushiki Kaisha Thin film transistor and method for fabricating the same, semiconductor device and method for fabricating the same, as well as display
CN102253548A (en) 2010-05-21 2011-11-23 奇美电子股份有限公司 Image display system
US20110284851A1 (en) * 2010-05-21 2011-11-24 Chimei Innolux Corporation System for displaying images
CN107623011A (en) 2017-10-12 2018-01-23 友达光电股份有限公司 Thin film transistor array substrate for X-ray detector and X-ray detector
CN208738250U (en) 2018-09-28 2019-04-12 武汉华星光电技术有限公司 Display panel

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Chinese Office Action issued in corresponding Chinese Patent Application No. 201811135751.9 dated Aug. 30, 2023, pp. 1-9.
International Search Report in International application No. PCT/CN2018/113268, dated Feb. 22, 2019.
Written Opinion of the International Search Authority in International application No. PCT/CN2018/113268, dated Feb. 22, 2019.

Also Published As

Publication number Publication date
US20240096899A1 (en) 2024-03-21
US20200104008A1 (en) 2020-04-02

Similar Documents

Publication Publication Date Title
US20240096899A1 (en) Display panels
US8067813B2 (en) Integrated MIS photosensitive device using continuous films
US7208810B2 (en) Integrated MIS photosensitive device using continuous films
US9786711B2 (en) Array substrate of X-ray sensor and method for manufacturing the same
CN109858443B (en) Display panel, display device and manufacturing method of display panel
US12027543B2 (en) Array substrate and display panel
US20170092673A1 (en) Light detection device
CN107946324B (en) Light sensing device
US7638354B2 (en) Image sensor and method of fabricating the same
US20190131479A1 (en) Avalanche diode and method of manufacturing an avalanche diode
CN111354756A (en) A light detection substrate, its preparation method, and light detection equipment
CN111129051A (en) Flat panel detector pixel structure and preparation method thereof
US7615838B2 (en) CMOS image sensor and method for manufacturing the same
WO2020062415A1 (en) Display panel and manufacturing method therefor
CN110620125A (en) Structure for reducing random telegraph noise in CMOS image sensor and forming method
WO2021051819A1 (en) Flat panel detector and manufacturing method therefor
US10629834B2 (en) Thin film transistor, method for preparing the same, and display device
CN208738250U (en) Display panel
US20210226079A1 (en) Pin device and manufacturing method thereof, photosensitive device and display device
WO2015067101A1 (en) Vertically configured photosensitive semiconductor device and method for fabrication thereof
CN105702682A (en) Thin film transistor array substrate, manufacturing method, and liquid crystal display panel
US11804508B2 (en) Sensor, manufacturing method thereof, and photoelectric conversion device
CN115775840A (en) Photoelectric sensor and display panel
US11264384B2 (en) CMOS structure and method for manufacturing CMOS structure
US20230387149A1 (en) Optical sensor

Legal Events

Date Code Title Description
AS Assignment

Owner name: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YAN, YUAN;REEL/FRAME:047822/0726

Effective date: 20181217

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: AWAITING RESPONSE FOR INFORMALITY, FEE DEFICIENCY OR CRF ACTION

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: AWAITING RESPONSE FOR INFORMALITY, FEE DEFICIENCY OR CRF ACTION

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

Free format text: AWAITING TC RESP., ISSUE FEE NOT PAID

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE