US11784171B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US11784171B2
US11784171B2 US17/696,157 US202217696157A US11784171B2 US 11784171 B2 US11784171 B2 US 11784171B2 US 202217696157 A US202217696157 A US 202217696157A US 11784171 B2 US11784171 B2 US 11784171B2
Authority
US
United States
Prior art keywords
semiconductor
package
redistribution
electrodes
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/696,157
Other versions
US20220208743A1 (en
Inventor
Ae-nee JANG
Inhyo HWANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US17/696,157 priority Critical patent/US11784171B2/en
Publication of US20220208743A1 publication Critical patent/US20220208743A1/en
Application granted granted Critical
Publication of US11784171B2 publication Critical patent/US11784171B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • Some example embodiments of the inventive concepts relate to semiconductor devices and, more particularly, to semiconductor devices including a wafer-level semiconductor package.
  • semiconductor packages have been variously developed to reduce their sizes, weights and/or manufacturing costs.
  • various kinds of semiconductor packages have been developed to be applied to various fields such as digital imaging devices, MP3 players, mobile phones, and large-capacity storage means.
  • a ball grid array (BGA) package and/or a wafer-level package have been suggested.
  • a redistribution pattern may be formed on a semiconductor chip without a molding process, and a solder ball may be adhered directly to the redistribution pattern.
  • the molding process and a printed circuit board may not be required in the wafer-level package.
  • processes of manufacturing the wafer-level package may be simplified and a thickness of the wafer-level package may be reduced.
  • Some example embodiments of the inventive concepts may provide semiconductor devices with improved electrical characteristics and/or method for manufacturing the same.
  • a semiconductor device may include a first package, and a second package stacked on the first package.
  • Each of the first and second packages may include a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern.
  • the first redistribution pattern of the second package may be electrically connected to the second through-electrode of the first package.
  • a semiconductor device may include semiconductor packages sequentially stacked.
  • Each of the semiconductor packages may include a redistribution substrate having a first redistribution pattern and a second redistribution pattern, the first and second redistribution patterns being insulated from each other, a semiconductor chip on the redistribution substrate, a first molding layer surrounding the semiconductor chip, and through-electrodes penetrating the first molding layer.
  • the through-electrodes may include a first through-electrode on a first sidewall of the semiconductor chip and connected to the first redistribution pattern, and a second through-electrode spaced apart from the first through-electrode and connected to the second redistribution pattern.
  • the first through-electrode of one semiconductor package of the semiconductor packages may be vertically aligned with the second through-electrode of another semiconductor package of the semiconductor packages thereunder.
  • a semiconductor device may include a first package and a second package stacked on the first package.
  • the first package may include a first semiconductor chip, a first molding layer surrounding the first semiconductor chip, a first through-electrode penetrating the first molding layer and connected to the first semiconductor chip through a first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern.
  • the second package may include a second semiconductor chip, a second molding layer surrounding the second semiconductor chip, a third through-electrode penetrating the second molding layer and connected to the second semiconductor chip through a second redistribution pattern, and a fourth through-electrode penetrating the second molding layer and not connected to the second redistribution pattern.
  • the third through-electrode of the second package may be connected to the second through-electrode of the first package.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 2 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • FIG. 3 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • FIGS. 4 and 5 are cross-sectional views illustrating semiconductor devices according to an example embodiment of the inventive concepts.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 7 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • FIG. 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 9 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • FIG. 10 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • FIG. 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIGS. 12 and 13 are schematic plan views illustrating arrangements of through-electrodes of semiconductor packages.
  • FIG. 14 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 2 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • FIG. 3 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • a semiconductor device 10 may include a package stack PS.
  • the package stack PS may include first semiconductor packages 200 stacked in a first direction D 1 .
  • the first semiconductor packages 200 may have the same or substantially similar components and shape. Hereinafter, the components of the first semiconductor packages 200 will be described in detail.
  • each of the first semiconductor packages 200 may include a first redistribution substrate 220 , a first semiconductor chip 210 , a first molding layer 230 , and through-electrodes SV, FV and PGV.
  • the first redistribution substrate 220 may include a plurality of redistribution patterns.
  • the redistribution patterns may include a first redistribution pattern 222 , a second redistribution pattern 224 , and a first insulating pattern 226 .
  • the first insulating pattern 226 may include stacked insulating layers. The number of the stacked insulating layers is 2 in FIG. 1 . However, the number of the stacked insulating layers may be variously changed.
  • the first redistribution pattern 222 and the second redistribution pattern 224 may be buried by the stacked insulating layers.
  • the first redistribution pattern 222 and the second redistribution pattern 224 may be electrically insulated from each other.
  • the first redistribution pattern 222 may include a signal transmission pattern connected to the first semiconductor chip 210
  • the second redistribution pattern 224 may include floating patterns electrically isolated from the first semiconductor chip 210 .
  • a portion of the first redistribution pattern 222 and a portion of the second redistribution pattern 224 may be exposed through a bottom surface of the first insulating pattern 226 , and the exposed portions of the first and second redistribution patterns 222 and 224 may function as conductive pads.
  • first connection terminals 202 may be provided on the exposed portions of the first and second redistribution patterns 222 and 224 .
  • the first connection terminals 202 may be connected to the first and second redistribution patterns 222 and 224 .
  • the first semiconductor chip 210 may be mounted on the first redistribution substrate 220 .
  • the first semiconductor chip 210 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and first chip pads 212 connected to the interconnection lines.
  • the integrated circuits of the first semiconductor chip 210 may include transistors.
  • the first chip pads 212 may be provided on a bottom surface of the first semiconductor chip 210 .
  • the first chip pads 212 may include metal (e.g., copper (Cu) or aluminum (Al)).
  • the first chip pads 212 may be electrically connected to the integrated circuits of the first semiconductor chip 210 through the interconnection lines.
  • the first semiconductor chip 210 may have a polygonal shape when viewed in a plan view. In FIGS. 1 to 3 , the first semiconductor chip 210 having a square shape in a plan view is illustrated as an example.
  • the first semiconductor chip 210 may include first to fourth sidewalls 210 a , 210 b , 210 c and 210 d .
  • the first to fourth sidewalls 210 a , 210 b , 210 c and 210 d may be sequentially arranged in a second direction D 2 corresponding to a counter-clockwise direction around the first direction D 1 .
  • the first to fourth sidewalls 210 a , 210 b , 210 c and 210 d may be disposed adjacent to each other.
  • the first to fourth sidewalls 210 a , 210 b , 210 c and 210 d of the first semiconductor chip 210 may have the same width.
  • the first semiconductor chip 210 may have a thickness of 20 ⁇ m to 40 ⁇ m.
  • the first semiconductor chip 210 may be disposed on the first redistribution substrate 220 in such a way that the first chip pads 212 of the first semiconductor chip 210 face the first redistribution substrate 220 .
  • the first chip pads 212 may be connected to the first redistribution pattern 222 of the first redistribution substrate 220 .
  • the first chip pads 212 may not be connected to the second redistribution pattern 224 .
  • the first semiconductor chip 210 may be electrically insulated from the second redistribution pattern 224 of the first redistribution substrate 220 .
  • the first chip pads 212 of the first semiconductor chip 210 are connected directly to the first redistribution pattern 222 of the first redistribution substrate 220 .
  • the first semiconductor chip 210 may be mounted on the first redistribution substrate 220 through chip terminals.
  • the chip terminals may be formed between the first redistribution pattern 222 and the first chip pads 212 to electrically connect the first chip pads 212 to the first redistribution pattern 222 .
  • the first semiconductor chip 210 may be electrically connected to the first redistribution substrate 220 through the chip terminals.
  • Each of the chip terminals may include at least one of a solder, a pillar, or a bump.
  • the chip terminals may include a conductive material (e.g., metal).
  • the first molding layer 230 may be provided on the first redistribution substrate 220 .
  • the first molding layer 230 may cover the first redistribution substrate 220 .
  • the first semiconductor chip 210 may be buried in the first molding layer 230 .
  • the first molding layer 230 may cover the sidewalls of the first semiconductor chip 210 and a top surface of the first semiconductor chip 210 .
  • the first molding layer 230 may expose the top surface of the first semiconductor chip 210 .
  • the first molding layer 230 may surround the first semiconductor chip 210 on the first redistribution substrate 220 .
  • the first molding layer 230 may cover the sidewalls of the first semiconductor chip 210 but may expose the top surface of the first semiconductor chip 210 .
  • the first molding layer 230 may extend into a gap region between the first semiconductor chip 210 and the first redistribution substrate 220 to seal the chip terminals.
  • the first molding layer 230 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
  • the through-electrodes SV, FV and PGV may be provided in the first molding layer 230 on the first redistribution substrate 220 .
  • the through-electrodes SV, FV and PGV may be laterally spaced apart from the first semiconductor chip 210 .
  • the through-electrodes SV, FV and PGV may penetrate the first molding layer 230 in the first direction D 1 .
  • Each of the through-electrodes SV, FV and PGV may be connected to one of the first redistribution pattern 222 and the second redistribution pattern 224 of the first redistribution substrate 220 .
  • Each of the through-electrodes SV, FV and PGV may be electrically connected to the first connection terminal 202 or the first semiconductor chip 210 through one of the first and second redistribution patterns 222 and 224 .
  • the through-electrodes SV, FV and PGV may be exposed at a top surface of the first molding layer 230 .
  • the through-electrodes SV, FV and PGV may include a conductive material (e.g., metal).
  • the through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV.
  • the first through-electrodes SV may be signal through-electrodes.
  • the signal through-electrode may mean a through-electrode which is used to transmit/receive an electrical signal to/from the first semiconductor chip 210 in the first semiconductor package 200 .
  • the second through-electrodes FV may be floating through-electrodes.
  • the floating through-electrode may mean a through-electrode which is electrically isolated from the first semiconductor chip 210 in the first semiconductor package 200 .
  • the third through-electrodes PGV may be power/ground through-electrodes.
  • the power/ground through-electrode may mean a through-electrode for supplying a ground voltage or a power voltage to the first semiconductor chip 210 .
  • the first through-electrodes SV may be provided in a signal region SR located on the first sidewall 210 a of the first semiconductor chip 210 .
  • the first through-electrodes SV may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220 . Unlike FIG. 2 , the first through-electrodes SV may be arranged in a zigzag form.
  • the first through-electrodes SV may be connected to the first redistribution pattern 222 and may be connected to the first semiconductor chip 210 through the first redistribution pattern 222 .
  • the second through-electrodes FV may be provided in floating regions FR 1 , FR 2 and FR 3 located on the second sidewall 210 b , the third sidewall 210 c and the fourth sidewall 210 d of the first semiconductor chip 210 .
  • the second through-electrodes FV may include first sub-through-electrodes FV 1 , second sub-through-electrodes FV 2 , and third sub-through-electrodes FV 3 .
  • the first sub-through-electrodes FV 1 may be provided in a first floating region FR 1 located on the second sidewall 210 b of the first semiconductor chip 210 .
  • the second sub-through-electrodes FV 2 may be provided in a second floating region FR 2 located on the third sidewall 210 c of the first semiconductor chip 210 .
  • the third sub-through-electrodes FV 3 may be provided in a third floating region FR 3 located on the fourth sidewall 210 d of the first semiconductor chip 210 .
  • the first sub-through-electrodes FV 1 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220 .
  • the second sub-through-electrodes FV 2 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220 .
  • the third sub-through-electrodes FV 3 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220 .
  • the first sub-through-electrodes FV 1 may be arranged in a zigzag form
  • the second sub-through-electrodes FV 2 may be arranged in a zigzag form
  • the third sub-through-electrodes FV 3 may be arranged in a zigzag form.
  • the first to third sub-through-electrodes FV 1 , FV 2 and FV 3 may be connected to the second redistribution pattern 224 and may be electrically insulated from the first semiconductor chip 210 .
  • first to third sub-through-electrodes FV 1 , FV 2 and FV 3 may be respectively connected to the floating patterns electrically isolated from each other in the second redistribution pattern 224 .
  • the first to third sub-through-electrodes FV 1 , FV 2 and FV 3 may be electrically insulated from each other.
  • the third through-electrodes PGV may be provided in a power/ground region PGR.
  • the power/ground region PGR may be spaced apart from the signal region SR and the floating regions FR 1 , FR 2 and FR 3 .
  • the power/ground region PGR may be disposed adjacent to each of corners of the first semiconductor chip 210 .
  • each of the corners of the first semiconductor chip 210 may mean a portion at which two of the sidewalls 210 a , 210 b , 210 c and 210 d of the first semiconductor chip 210 are in contact with (e.g., meet) each other.
  • the third through-electrodes PGV may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220 .
  • the third through-electrodes PGV may be connected to the first semiconductor chip 210 through a redistribution pattern of the first redistribution substrate 220 .
  • the first semiconductor package 200 may be provided as described above.
  • a thickness of the first semiconductor package 200 including the first redistribution substrate 220 , the first semiconductor chip 210 and the first molding layer 230 may range from 30 ⁇ m to 50 ⁇ m.
  • the first semiconductor packages 200 may be stacked.
  • four first semiconductor packages 200 may be stacked.
  • the four first semiconductor packages 200 are stacked.
  • embodiments of the inventive concepts are not limited thereto.
  • two or more first semiconductor packages 200 may be stacked.
  • the embodiments of FIGS. 1 and 3 in which the four first semiconductor packages 200 are stacked will be mainly described.
  • the first semiconductor packages 200 may be stacked.
  • the four first semiconductor packages 200 will be referred to as first to fourth sub-semiconductor packages 200 - 1 , 200 - 2 , 200 - 3 and 200 - 4 for the purpose of ease and convenience in explanation.
  • Each of the first to fourth sub-semiconductor packages 200 - 1 , 200 - 2 , 200 - 3 and 200 - 4 may be the same as the first semiconductor package 200 described above, and the components of the first to fourth sub-semiconductor packages 200 - 1 , 200 - 2 , 200 - 3 and 200 - 4 may be the same as each other.
  • the second sub-semiconductor package 200 - 2 may be mounted on the first sub-semiconductor package 200 - 1 .
  • the second sub-semiconductor package 200 - 2 may not be aligned with the first sub-semiconductor package 200 - 1 .
  • the second sub-semiconductor package 200 - 2 and the first sub-semiconductor package 200 - 1 may be twist-shifted from each other.
  • the one component when one component is ‘twist-shifted’ from (or with respect to) another component, the one component may be rotated (or twisted) around one axis with respect to the other component in a state in which the one and other components overlap with each other along the one axis.
  • the second sub-semiconductor package 200 - 2 may be twist-shifted with respect to the first sub-semiconductor package 200 - 1 in the second direction D 2 corresponding to the counter-clockwise direction rotating around the first direction D 1 .
  • the first sub-semiconductor package 200 - 1 and the second sub-semiconductor package 200 - 2 may overlap with each other in the first direction D 1 , and the first sidewall 210 a of the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D 1 ) as the second sidewall 210 b of the first semiconductor chip 210 of the first sub-semiconductor package 200 - 1 .
  • the second sub-semiconductor package 200 - 2 may be twist-shifted 90 degrees with respect to the first sub-semiconductor package 200 - 1 .
  • first through-electrodes SV of the second sub-semiconductor package 200 - 2 may be aligned with the first sub-through-electrodes FV 1 of the first sub-semiconductor package 200 - 1 .
  • the first sub-through-electrodes FV 1 , the second sub-through-electrodes FV 2 and the third sub-through-electrodes FV 3 of the second sub-semiconductor package 200 - 2 may be aligned with the second sub-through-electrodes FV 2 , the third sub-through-electrodes FV 3 and the first through-electrodes SV of the first sub-semiconductor package 200 - 1 , respectively.
  • the third through-electrodes PGV of the second sub-semiconductor package 200 - 2 may be aligned with and electrically connected to the third through-electrodes PGV of the first sub-semiconductor package 200 - 1 .
  • the first connection terminals 202 of the second sub-semiconductor package 200 - 2 may be connected to the through-electrodes SV, FV 1 , FV 2 , FV 3 and PGV of the first sub-semiconductor package 200 - 1 .
  • the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 may be connected to the first sub-through-electrodes FV 1 of the first sub-semiconductor package 200 - 1 through the first redistribution pattern 222 and the first connection terminals 202 of the second sub-semiconductor package 200 - 2 .
  • the first semiconductor chip 210 of the first sub-semiconductor package 200 - 1 and the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 may be respectively connected to the first redistribution pattern 222 and the second redistribution pattern 224 of the first sub-semiconductor package 200 - 1 which are electrically insulated from each other, and thus a bandwidth of the semiconductor device 10 may be increased.
  • the third sub-semiconductor package 200 - 3 may be mounted on the second sub-semiconductor package 200 - 2 .
  • the third sub-semiconductor package 200 - 3 may not be aligned with the second sub-semiconductor package 200 - 2 .
  • the third sub-semiconductor package 200 - 3 and the second sub-semiconductor package 200 - 2 may be twist-shifted from each other.
  • the third sub-semiconductor package 200 - 3 may be twist-shifted with respect to the second sub-semiconductor package 200 - 2 in the second direction D 2 .
  • the second sub-semiconductor package 200 - 2 and the third sub-semiconductor package 200 - 3 may overlap with each other in the first direction D 1 , and the first sidewall 210 a of the first semiconductor chip 210 of the third sub-semiconductor package 200 - 3 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D 1 ) as the second sidewall 210 b of the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 .
  • the third sub-semiconductor package 200 - 3 may be twist-shifted 90 degrees with respect to the second sub-semiconductor package 200 - 2 .
  • first through-electrodes SV of the third sub-semiconductor package 200 - 3 may be aligned with the first sub-through-electrodes FV 1 of the second sub-semiconductor package 200 - 2 .
  • the first sub-through-electrodes FV 1 , the second sub-through-electrodes FV 2 and the third sub-through-electrodes FV 3 of the third sub-semiconductor package 200 - 3 may be aligned with the second sub-through-electrodes FV 2 , the third sub-through-electrodes FV 3 and the first through-electrodes SV of the second sub-semiconductor package 200 - 2 , respectively.
  • the third through-electrodes PGV of the third sub-semiconductor package 200 - 3 may be aligned with and electrically connected to the third through-electrodes PGV of the second sub-semiconductor package 200 - 2 .
  • the first connection terminals 202 of the third sub-semiconductor package 200 - 3 may be connected to the through-electrodes SV, FV 1 , FV 2 , FV 3 and PGV of the second sub-semiconductor package 200 - 2 .
  • the first semiconductor chip 210 of the third sub-semiconductor package 200 - 3 may be connected to the second sub-through-electrodes FV 2 of the first sub-semiconductor package 200 - 1 through the first redistribution pattern 222 and the first connection terminals 202 of the third sub-semiconductor package 200 - 3 and the first sub-through-electrodes FV 1 of the second sub-semiconductor package 200 - 2 .
  • the first semiconductor chip 210 of the first sub-semiconductor package 200 - 1 , the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 and the first semiconductor chip 210 of the third sub-semiconductor package 200 - 3 may be respectively connected to the first redistribution pattern 222 and the second redistribution patterns 224 of the first sub-semiconductor package 200 - 1 which are electrically insulated from each other, and thus the bandwidth of the semiconductor device 10 may be increased.
  • the fourth sub-semiconductor package 200 - 4 may be mounted on the third sub-semiconductor package 200 - 3 .
  • the fourth sub-semiconductor package 200 - 4 may not be aligned with the third sub-semiconductor package 200 - 3 .
  • the fourth sub-semiconductor package 200 - 4 and the third sub-semiconductor package 200 - 3 may be twist-shifted from each other.
  • the fourth sub-semiconductor package 200 - 4 may be twist-shifted with respect to the third sub-semiconductor package 200 - 3 in the second direction D 2 .
  • the third sub-semiconductor package 200 - 3 and the fourth sub-semiconductor package 200 - 4 may overlap with each other in the first direction D 1 , and the first sidewall 210 a of the first semiconductor chip 210 of the fourth sub-semiconductor package 200 - 4 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D 1 ) as the second sidewall 210 b of the first semiconductor chip 210 of the third sub-semiconductor package 200 - 3 .
  • the fourth sub-semiconductor package 200 - 4 may be twist-shifted 90 degrees with respect to the third sub-semiconductor package 200 - 3 .
  • first through-electrodes SV of the fourth sub-semiconductor package 200 - 4 may be aligned with the first sub-through-electrodes FV 1 of the third sub-semiconductor package 200 - 3 .
  • the first sub-through-electrodes FV 1 , the second sub-through-electrodes FV 2 and the third sub-through-electrodes FV 3 of the fourth sub-semiconductor package 200 - 4 may be aligned with the second sub-through-electrodes FV 2 , the third sub-through-electrodes FV 3 and the first through-electrodes SV of the third sub-semiconductor package 200 - 3 , respectively.
  • the third through-electrodes PGV of the fourth sub-semiconductor package 200 - 4 may be aligned with and electrically connected to the third through-electrodes PGV of the third sub-semiconductor package 200 - 3 .
  • the first connection terminals 202 of the fourth sub-semiconductor package 200 - 4 may be connected to the through-electrodes SV, FV 1 , FV 2 , FV 3 and PGV of the third sub-semiconductor package 200 - 3 .
  • the first semiconductor chip 210 of the fourth sub-semiconductor package 200 - 4 may be connected to the third sub-through-electrodes FV 3 of the first sub-semiconductor package 200 - 1 through the first redistribution pattern 222 and the first connection terminals 202 of the fourth sub-semiconductor package 200 - 4 , the first sub-through-electrodes FV 1 of the third sub-semiconductor package 200 - 3 , and the second sub-through-electrodes FV 2 of the second sub-semiconductor package 200 - 2 .
  • the first semiconductor chip 210 of the first sub-semiconductor package 200 - 1 , the first semiconductor chip 210 of the second sub-semiconductor package 200 - 2 , the first semiconductor chip 210 of the third sub-semiconductor package 200 - 3 and the first semiconductor chip 210 of the fourth sub-semiconductor package 200 - 4 may be respectively connected to the first redistribution pattern 222 and the second redistribution patterns 224 of the first sub-semiconductor package 200 - 1 which are electrically insulated from each other, and thus the bandwidth of the semiconductor device 10 may be increased.
  • the package stack PS may be provided as described above.
  • a semiconductor device 10 ′ may further include a package substrate 100 and a package molding layer 300 .
  • the package substrate 100 may be provided.
  • the package substrate 100 may be a printed circuit board (PCB).
  • the package substrate 100 may have a top surface and a bottom surface.
  • First pads 102 may be provided on the top surface of the package substrate 100
  • second pads 104 may be provided on the bottom surface of the package substrate 100 .
  • the first pads 102 may be pads on which the package stack PS is mounted.
  • External terminals 106 may be disposed on the second pads 104 , respectively.
  • the external terminals 106 may electrically connect the semiconductor device 10 ′ to an external device.
  • the package stack PS may be mounted on the package substrate 100 .
  • the first semiconductor packages 200 may be stacked on the package substrate 100 .
  • the first sub-semiconductor package 200 - 1 disposed at a lowermost end of the package stack PS may be mounted on the package substrate 100 .
  • the first connection terminals 202 of the first sub-semiconductor package 200 - 1 may be connected to the first pads 102 of the package substrate 100 .
  • the first semiconductor chip 210 of the first sub-semiconductor package 200 - 1 may be connected to the package substrate 100 through the first redistribution pattern 222 .
  • the second through-electrodes FV 1 , FV 2 and FV 3 of the first sub-semiconductor package 200 - 1 may be connected to the package substrate 100 through the second redistribution pattern 224 .
  • the third through-electrodes PGV of the first sub-semiconductor package 200 - 1 may be connected to a ground circuit or a power circuit of the package substrate 100 .
  • the package molding layer 300 may be provided on the package substrate 100 .
  • the package molding layer 300 may cover the package stack PS on the package substrate 100 .
  • the package molding layer 300 may cover sidewalls of the first semiconductor packages 200 and may fill spaces between the first semiconductor packages 200 .
  • the package molding layer 300 may protect the package stack PS.
  • the package molding layer 300 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
  • a semiconductor device 10 ′′ may not include the package substrate 100 .
  • the package substrate 100 may not be provided.
  • the first connection terminals 202 of the first sub-semiconductor package 200 - 1 disposed at the lowermost end of the package stack PS may electrically connect the semiconductor device 10 ′′ to an external device.
  • the package molding layer 300 may be provided.
  • the package molding layer 300 may cover the package stack PS.
  • the package molding layer 300 may cover the sidewalls of the first semiconductor packages 200 and may fill the spaces between the first semiconductor packages 200 .
  • the package molding layer 300 may protect the package stack PS.
  • the package molding layer 300 may cover the redistribution substrate 220 of the first sub-semiconductor package 200 - 1 .
  • the package molding layer 300 may protect the redistribution substrate 220 of the first sub-semiconductor package 200 - 1 .
  • the first connection terminals 202 of the first sub-semiconductor package 200 - 1 may penetrate the package molding layer 300 so as to be exposed to the outside.
  • the package molding layer 300 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
  • EMC epoxy molding compound
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 7 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • a semiconductor device 20 may include a package stack PS.
  • the package stack PS may include second semiconductor packages 400 stacked in the first direction D 1 .
  • the second semiconductor packages 400 may be sequentially stacked.
  • two second semiconductor packages 400 may be sequentially stacked.
  • the second semiconductor packages 400 may have the same or substantially similar components and shape.
  • the second semiconductor package 400 may include a second redistribution substrate 420 , a second semiconductor chip 410 , a second molding layer 430 , and through-electrodes SV, FV and PGV.
  • the second redistribution substrate 420 may include a plurality of redistribution patterns.
  • the redistribution patterns may include a third redistribution pattern 422 , a fourth redistribution pattern 424 , and a second insulating pattern 426 .
  • the third redistribution pattern 422 and the fourth redistribution pattern 424 may be buried in the second insulating pattern 426 .
  • the third redistribution pattern 422 and the fourth redistribution pattern 424 may be electrically insulated from each other.
  • the third redistribution pattern 422 may include a signal transmission pattern connected to the second semiconductor chip 410
  • the fourth redistribution pattern 424 may include a floating pattern electrically isolated from the second semiconductor chip 410 .
  • a portion of the third redistribution pattern 422 and a portion of the fourth redistribution pattern 424 may be exposed through a bottom surface of the second insulating pattern 426 , and second connection terminals 402 may be provided on the exposed portions of the third and fourth redistribution patterns 422 and 424 .
  • the second semiconductor chip 410 may be mounted on the second redistribution substrate 420 .
  • the second semiconductor chip 410 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and second chip pads 412 connected to the interconnection lines.
  • the second chip pads 412 may be electrically connected to the integrated circuits of the second semiconductor chip 410 through the interconnection lines.
  • the second semiconductor chip 410 may have a square shape when viewed in a plan view.
  • the second semiconductor chip 410 may be disposed on the second redistribution substrate 420 in such a way that the second chip pads 412 of the second semiconductor chip 410 face the second redistribution substrate 420 .
  • the second chip pads 412 may be connected to the third redistribution pattern 422 of the second redistribution substrate 420 .
  • the second chip pads 412 may not be connected to the fourth redistribution pattern 424 .
  • the second molding layer 430 may be provided on the second redistribution substrate 420 .
  • the second molding layer 430 may cover the second redistribution substrate 420 .
  • the second molding layer 430 may cover the second semiconductor chip 410 .
  • the through-electrodes SV, FV and PGV may be provided in the second molding layer 430 on the second redistribution substrate 420 .
  • the through-electrodes SV, FV and PGV may be laterally spaced apart from the second semiconductor chip 410 .
  • the through-electrodes SV, FV and PGV may penetrate the second molding layer 430 in the first direction D 1 .
  • Each of the through-electrodes SV, FV and PGV may be connected to one of the third redistribution pattern 422 and the fourth redistribution pattern 424 of the second redistribution substrate 420 .
  • Each of the through-electrodes SV, FV and PGV may be electrically connected to the second connection terminal 402 or the second semiconductor chip 410 through one of the third and fourth redistribution patterns 422 and 424 .
  • the through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV.
  • the first through-electrodes SV may be signal through-electrodes.
  • the second through-electrodes FV may be floating through-electrodes.
  • the third through-electrodes PGV may be power/ground through-electrodes.
  • the first through-electrodes SV may be provided on two sidewalls of the second semiconductor chip 410 .
  • the first through-electrodes SV may be connected to the third redistribution pattern 422 and may be connected to the second semiconductor chip 410 through the third redistribution pattern 422 .
  • the second through-electrodes FV may be provided on two sidewalls of the second semiconductor chip 410 .
  • the sidewalls of the second semiconductor chip 410 which are adjacent to the first through-electrodes SV may be different from the sidewalls of the second semiconductor chip 410 which are adjacent to the second through-electrodes FV.
  • the second through-electrodes FV may be connected to the fourth redistribution pattern 424 and may be electrically insulated from the second semiconductor chip 410 .
  • the third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV and FV.
  • the third through-electrodes PGV may be disposed adjacent to a corner of the second semiconductor chip 410 .
  • the third through-electrodes PGV may be connected to the second semiconductor chip 410 through a redistribution pattern of the second redistribution substrate 420 .
  • the second semiconductor packages 400 may be stacked.
  • the second semiconductor packages 400 may not be aligned with each other.
  • the second semiconductor packages 400 may be twist-shifted from each other.
  • An upper one of the second semiconductor packages 400 may be twist-shifted with respect to a lower one of the second semiconductor packages 400 in the second direction D 2 .
  • the second semiconductor packages 400 may overlap with each other in the first direction D 1 , and the upper one of the second semiconductor packages 400 may be twist-shifted 180 degrees with respect to the lower one of the second semiconductor packages 400 .
  • the first through-electrodes SV of the upper one of the second semiconductor packages 400 may be aligned with the second through-electrodes FV of the lower one of the second semiconductor packages 400 .
  • the second connection terminals 402 of the upper one of the second semiconductor packages 400 may be connected to the through-electrodes SV, FV and PGV of the lower one of the second semiconductor packages 400 .
  • the second semiconductor chip 410 of the upper one of the second semiconductor packages 400 may be connected to the second through-electrodes FV of the lower one of the second semiconductor packages 400 .
  • the second semiconductor chips 410 of the second semiconductor packages 400 may be respectively connected to the redistribution patterns electrically insulated from each other, and thus a bandwidth of the semiconductor device 20 may be increased.
  • FIG. 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIG. 9 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
  • FIG. 10 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • a semiconductor device 30 may include a package stack PS.
  • the package stack PS may include third semiconductor packages 500 stacked in the first direction D 1 .
  • the third semiconductor packages 500 may be sequentially stacked.
  • six third semiconductor packages 500 may be sequentially stacked.
  • the third semiconductor packages 500 may have the same or substantially similar components and shape.
  • the third semiconductor package 500 may include a third redistribution substrate 520 , a third semiconductor chip 510 , a third molding layer 530 , and through-electrodes SV, FV and PGV.
  • the third redistribution substrate 520 may include a plurality of redistribution patterns.
  • the redistribution patterns may include a fifth redistribution pattern 522 , a sixth redistribution pattern 524 , and a third insulating pattern 526 .
  • the fifth redistribution pattern 522 and the sixth redistribution pattern 524 may be buried in the third insulating pattern 526 .
  • the fifth redistribution pattern 522 and the sixth redistribution pattern 524 may be electrically insulated from each other.
  • the fifth redistribution pattern 522 may include a signal transmission pattern connected to the third semiconductor chip 510
  • the sixth redistribution pattern 524 may include a floating pattern electrically isolated from the third semiconductor chip 510 .
  • a portion of the fifth redistribution pattern 522 and a portion of the sixth redistribution pattern 524 may be exposed through a bottom surface of the third insulating pattern 526 , and third connection terminals 502 may be provided on the exposed portions of the fifth and sixth redistribution patterns 522 and 524 .
  • the third semiconductor chip 510 may be mounted on the third redistribution substrate 520 .
  • the third semiconductor chip 510 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and third chip pads 512 connected to the interconnection lines.
  • the third chip pads 512 may be electrically connected to the integrated circuits of the third semiconductor chip 510 through the interconnection lines.
  • the third semiconductor chip 510 may have a regular hexagon shape when viewed in a plan view.
  • the third semiconductor chip 510 may include first to sixth sidewalls 510 a , 510 b , 510 c , 510 d , 510 e and 510 f.
  • the third semiconductor chip 510 may be disposed on the third redistribution substrate 520 in such a way that the third chip pads 512 of the third semiconductor chip 510 face the third redistribution substrate 520 .
  • the third chip pads 512 may be connected to the fifth redistribution pattern 522 of the third redistribution substrate 520 .
  • the third chip pads 512 may not be connected to the sixth redistribution pattern 524 .
  • the third molding layer 530 may be provided on the third redistribution substrate 520 .
  • the third molding layer 530 may cover the third redistribution substrate 520 .
  • the third molding layer 530 may cover the third semiconductor chip 510 .
  • the through-electrodes SV, FV and PGV may be provided in the third molding layer 530 on the third redistribution substrate 520 .
  • the through-electrodes SV, FV and PGV may be laterally spaced apart from the third semiconductor chip 510 .
  • Each of the through-electrodes SV, FV and PGV may be connected to one of the fifth redistribution pattern 522 and the sixth redistribution pattern 524 of the third redistribution substrate 520 .
  • Each of the through-electrodes SV, FV and PGV may be electrically connected to the third connection terminal 502 or the third semiconductor chip 510 through one of the fifth and sixth redistribution patterns 522 and 524 .
  • the through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV.
  • the first through-electrodes SV may be signal through-electrodes.
  • the second through-electrodes FV may be floating through-electrodes.
  • the third through-electrodes PGV may be power/ground through-electrodes.
  • the first through-electrodes SV may be provided on the first sidewall 510 a of the third semiconductor chip 510 .
  • the first through-electrodes SV may be connected to the fifth redistribution pattern 522 and may be connected to the third semiconductor chip 510 through the fifth redistribution pattern 522 .
  • the second through-electrodes FV may be provided on the second to sixth sidewalls 510 b , 510 c , 510 d , 510 e and 510 f of the third semiconductor chip 510 .
  • the second through-electrodes FV may be connected to the sixth redistribution pattern 524 and may be electrically insulated from the third semiconductor chip 510 .
  • the third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV and FV.
  • the third through-electrodes PGV may be disposed adjacent to a corner of the third semiconductor chip 510 .
  • the third through-electrodes PGV may be connected to the third semiconductor chip 510 through a redistribution pattern of the third redistribution substrate 520 .
  • the third semiconductor packages 500 may be stacked.
  • the third semiconductor packages 500 may not be aligned with each other.
  • the third semiconductor packages 500 may be twist-shifted from each other.
  • An upper one of the third semiconductor packages 500 vertically adjacent to each other may be twist-shifted in the second direction D 2 with respect to a lower one of the third semiconductor packages 500 vertically adjacent to each other.
  • the third semiconductor packages 500 may overlap with each other in the first direction D 1 , and the upper one of the third semiconductor packages 500 vertically adjacent to each other may be twist-shifted 60 degrees with respect to the lower one of the third semiconductor packages 500 vertically adjacent to each other.
  • the first through-electrodes SV of the upper one of the third semiconductor packages 500 may be aligned with the second through-electrodes FV of the lower one of the third semiconductor packages 500 .
  • the first through-electrodes SV of the upper one of the third semiconductor packages 500 may be aligned with the second through-electrodes FV located on the second sidewall 510 b of the third semiconductor chip 510 of the lower one of the third semiconductor packages 500 .
  • the third connection terminals 502 of the upper one of the third semiconductor packages 500 may be connected to the through-electrodes SV, FV and PGV of the lower one of the third semiconductor packages 500 .
  • the third semiconductor chip 510 of the upper one of the third semiconductor packages 500 may be connected to the second through-electrodes FV of the lower one of the third semiconductor packages 500 .
  • the third semiconductor chips 510 of the third semiconductor packages 500 may be respectively connected to the redistribution patterns electrically insulated from each other, and thus a bandwidth of the semiconductor device 30 may be increased.
  • FIG. 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
  • FIGS. 12 and 13 are schematic plan views illustrating arrangements of through-electrodes of semiconductor packages.
  • FIG. 14 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
  • a semiconductor device may include a package stack PS.
  • the package stack PS may include fourth semiconductor packages 600 and fifth semiconductor packages 700 , which are stacked in the first direction D 1 .
  • the fourth semiconductor packages 600 and the fifth semiconductor packages 700 may be alternately stacked.
  • the fourth semiconductor package 600 and the fifth semiconductor package 700 which are sequentially stacked may constitute a sub-stack SS
  • the package stack PS may include four sub-stacks SS sequentially stacked.
  • the fourth semiconductor packages 600 may have the same or substantially similar components and shape.
  • the fifth semiconductor packages 700 may have the same or substantially similar components and shape.
  • components of the sub-stack SS will be described in detail.
  • the fourth semiconductor package 600 may include a fourth redistribution substrate 620 , a fourth semiconductor chip 610 , a fourth molding layer 630 , and through-electrodes SV 1 , FV and PGV.
  • the fourth redistribution substrate 620 may include a plurality of redistribution patterns.
  • the redistribution patterns may include a seventh redistribution pattern 622 , an eighth redistribution pattern 624 , and a fourth insulating pattern 626 .
  • the seventh and eighth redistribution patterns 622 and 624 may be electrically insulated from each other.
  • the fourth semiconductor chip 610 may be mounted on the fourth redistribution substrate 620 .
  • the fourth semiconductor chip 610 may be connected to the fourth redistribution substrate 620 through fourth chip pads 612 electrically connected to integrated circuits of the fourth semiconductor chip 610 .
  • the fourth chip pads 612 may be connected to the seventh redistribution pattern 622 of the fourth redistribution substrate 620 .
  • the fourth chip pads 612 may not be connected to the eighth redistribution pattern 624 .
  • the fourth semiconductor chip 610 may have a square shape when viewed in a plan view.
  • the fourth semiconductor chip 610 may include first to fourth sidewalls 610 a , 610 b , 610 c and 610 d.
  • the fourth molding layer 630 may cover the fourth semiconductor chip 610 on the fourth redistribution substrate 620 .
  • First through-electrodes SV 1 , second through-electrodes FV and third through-electrodes PGV of the fourth semiconductor package 600 may be provided in the fourth molding layer 630 .
  • the first through-electrodes SV 1 may be signal through-electrodes.
  • the second through-electrodes FV may be floating through-electrodes.
  • the third through-electrodes PGV may be power/ground through-electrodes.
  • the first through-electrodes SV 1 may be provided in a signal region SR 1 located on the first sidewall 610 a of the fourth semiconductor chip 610 .
  • the first through-electrodes SV 1 may be connected to the fourth semiconductor chip 610 through the seventh redistribution pattern 622 .
  • the second through-electrodes FV may be provided on the second sidewall 610 b , the third sidewall 610 c and the fourth sidewall 610 d of the fourth semiconductor chip 610 .
  • some FV 4 of the second through-electrodes FV may be provided in a fourth floating region FR 4 provided on the first sidewall 610 a of the fourth semiconductor chip 610 .
  • the fourth floating region FR 4 may be spaced apart from the signal region SR 1 on the first sidewall 610 a of the fourth semiconductor chip 610 .
  • the second through-electrodes FV may be connected to the eighth redistribution pattern 624 and may be electrically insulated from the fourth semiconductor chip 610 .
  • the third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV 1 and FV.
  • the third through-electrodes PGV may be disposed adjacent to a corner of the fourth semiconductor chip 610 .
  • the fifth semiconductor package 700 may include a fifth redistribution substrate 720 , a fifth semiconductor chip 710 , a fifth molding layer 730 , and through-electrodes SV 2 , FV and PGV.
  • the fifth redistribution substrate 720 may include a plurality of redistribution patterns.
  • the redistribution patterns may include a ninth redistribution pattern 722 , a tenth redistribution pattern 724 , and a fifth insulating pattern 726 .
  • the ninth and tenth redistribution patterns 722 and 724 may be electrically insulated from each other.
  • the fifth semiconductor chip 710 may be mounted on the fifth redistribution substrate 720 .
  • the fifth semiconductor chip 710 may be connected to the fifth redistribution substrate 720 through fifth chip pads 712 electrically connected to integrated circuits of the fifth semiconductor chip 710 .
  • the fifth chip pads 712 may be connected to the ninth redistribution pattern 722 of the fifth redistribution substrate 720 .
  • the fifth chip pads 712 may not be connected to the tenth redistribution pattern 724 .
  • the fifth semiconductor chip 710 may have a square shape when viewed in a plan view.
  • the fifth semiconductor chip 710 may include first to fourth sidewalls 710 a , 710 b , 710 c and 710 d.
  • the fifth molding layer 730 may cover the fifth semiconductor chip 710 on the fifth redistribution substrate 720 .
  • First through-electrodes SV 2 , second through-electrodes FV and third through-electrodes PGV of the fifth semiconductor package 700 may be provided in the fifth molding layer 730 .
  • the first through-electrodes SV 2 may be signal through-electrodes.
  • the second through-electrodes FV may be floating through-electrodes.
  • the third through-electrodes PGV may be power/ground through-electrodes.
  • the first through-electrodes SV 2 may be provided in a signal region SR 2 located on the first sidewall 710 a of the fifth semiconductor chip 710 .
  • the first through-electrodes SV 2 may be connected to the fifth semiconductor chip 710 through the ninth redistribution pattern 722 .
  • the second through-electrodes FV may be provided on the second sidewall 710 b , the third sidewall 710 c and the fourth sidewall 710 d of the fifth semiconductor chip 710 .
  • some FV 5 of the second through-electrodes FV may be provided in a fifth floating region FR 5 provided on the first sidewall 710 a of the fifth semiconductor chip 710 .
  • the fifth floating region FR 5 may be spaced apart from the signal region SR 5 on the first sidewall 710 a of the fifth semiconductor chip 710 .
  • the second through-electrodes FV may be connected to the tenth redistribution pattern 724 and may be electrically insulated from the fifth semiconductor chip 710 .
  • the third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV 2 and FV.
  • the third through-electrodes PGV may be disposed adjacent to a corner of the fifth semiconductor chip 710 .
  • the fifth semiconductor package 700 may be mounted on the fourth semiconductor package 600 .
  • the fourth semiconductor package 600 and the fifth semiconductor package 700 may have the same planar shape and may be aligned with each other in the first direction D 1 .
  • the first sidewall 610 a of the fourth semiconductor chip 610 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D 1 ) as the first sidewall 710 a of the fifth semiconductor chip 710 .
  • the signal region SR 5 and the fifth floating region FR 5 of the fifth semiconductor package 700 may overlap with the fourth floating region FR 4 and the signal region SR 4 of the fourth semiconductor package 600 , respectively.
  • the first through-electrodes SV 2 of the fifth semiconductor package 700 may be aligned with the some FV 4 of the second through-electrodes FV of the fourth semiconductor package 600 in the first direction D 1
  • the some FV 5 of the second through-electrodes FV of the fifth semiconductor package 700 may be aligned with the first through-electrodes SV 1 of the fourth semiconductor package 600 in the first direction D 1 .
  • the fourth semiconductor chip 610 of the fourth semiconductor package 600 may be connected to the seventh redistribution pattern 622
  • the fifth semiconductor chip 710 of the fifth semiconductor package 700 may be connected to the eighth redistribution pattern 624 of the fourth semiconductor package 600 through the ninth redistribution pattern 722 of the fifth semiconductor package 700 and the some FV 4 of the second through-electrodes FV of the fourth semiconductor package 600 .
  • the fourth semiconductor chip 610 and the fifth semiconductor chip 710 may be respectively connected to the seventh redistribution pattern 622 and the eighth redistribution pattern 624 which are electrically insulated from each other, and thus a bandwidth of the semiconductor device may be increased.
  • the sub-stacks SS may be stacked.
  • the sub-stacks SS may not be aligned with each other.
  • the sub-stacks SS may be twist-shifted from each other.
  • An upper one of the sub-stacks SS vertically adjacent to each other may be twist-shifted 90 degrees in the second direction D 2 with respect to a lower one of the sub-stacks SS vertically adjacent to each other.
  • the first through-electrodes SV 1 and SV 2 of the upper one of the sub-stacks SS may be aligned with and connected to the second through-electrodes FV of the lower one of the sub-stacks SS.
  • the sub-stacks SS may be connected to the redistribution patterns electrically insulated from each other, and thus the bandwidth of the semiconductor device may be increased.
  • FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concepts.
  • a support substrate 800 may be prepared.
  • the support substrate 800 may be a carrier or may be an auxiliary member disposed on the carrier.
  • the support substrate 800 may be formed of at least one of various materials such as glass, plastic, and metal.
  • a separation layer 810 may be conformally formed on the support substrate 800 .
  • the separation layer 810 may be a double-sided adhesive tape or an adhesive layer. When the separation layer 810 is the double-sided adhesive tape, the separation layer 810 may be adhered onto the support substrate 800 by a lamination process using a vacuum. When the separation layer 810 is the adhesive layer, the separation layer 810 may be formed by coating the support substrate 800 with an adhesive material.
  • Semiconductor chips 210 may be disposed on the support substrate 800 .
  • the semiconductor chips 210 may be horizontally spaced apart from each other on the separation layer 810 . Bottom surfaces of the semiconductor chips 210 may be adhered to the separation layer 810 .
  • Chip pads 212 may be disposed on the bottom surface of each of the semiconductor chips 210 .
  • a molding layer 1230 may be formed on the support substrate 800 .
  • the molding layer 1230 may be formed to cover the semiconductor chips 210 on the support substrate 800 .
  • the molding layer 1230 may cover top surfaces and sidewalls of the semiconductor chips 210 .
  • the molding layer 1230 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
  • EMC epoxy molding compound
  • First through-electrodes SV and second through-electrodes FV may be formed in the molding layer 1230 .
  • holes may be formed to penetrate the molding layer 1230 , and then, the first and second through-electrodes SV and FV may be formed by filling the holes with a conductive material.
  • the first through-electrodes SV may be formed on one sidewall of the semiconductor chip 210
  • the second through-electrodes FV may be formed on the other sidewalls of the semiconductor chip 210 .
  • the support substrate 800 may be separated from the semiconductor chips 210 by selectively removing the support substrate 800 .
  • the adhesive tape may be weakened by applying heat of 170 degrees Celsius or more, and thus the separation layer 810 may be detached from the semiconductor chips 210 .
  • the support substrate 800 is formed of glass, ultraviolet light may be irradiated to the adhesive tape through a back surface of the support substrate 800 , and thus an adhesive of the adhesive tape may be hardened to weaken adhesive strength of the adhesive tape.
  • the separation layer 810 may be melted using chemicals and thus may be removed.
  • the bottom surfaces of the semiconductor chips 210 and a bottom surface of the molding layer 1230 may be exposed.
  • a redistribution layer 1220 may be formed on the bottom surface of the molding layer 1230 .
  • an insulating layer 1226 may be formed on the bottom surface of the molding layer 1230 .
  • the insulating layer 1226 may be formed by a spin-coating method, a physical vapor deposition (PVD) method (e.g., a sputtering method), a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a printing method.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the insulating layer 1226 may be formed of an inorganic insulating layer (e.g., a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer) or an organic polymer insulating layer (e.g., polyimide).
  • the insulating layer 1226 may include photosensitive polyimide.
  • the insulating layer 1226 e.g., a lower portion of the insulating layer 1226
  • the via holes may expose the chip pads 212 of the semiconductor chips 210 , the first through-electrodes SV, and the second through-electrodes FV.
  • the via holes may be formed by a laser drilling process, a photolithography process, or an etching process.
  • Redistribution patterns 222 and 224 may be formed on the insulating layer 1226 .
  • a conductive layer may be formed on the insulating layer 1226 , and the conductive layer may be patterned to form the redistribution patterns 222 and 224 .
  • the redistribution patterns 222 and 224 may include a conductive material (e.g., copper (Cu)).
  • the redistribution patterns 222 and 224 may include a first redistribution pattern 222 connected to the chip pads 212 and the first through-electrodes SV, and a second redistribution pattern 224 connected to the second through-electrodes FV.
  • An insulating layer 1226 (e.g., an upper portion of the insulating layer 1226 ) covering the redistribution patterns 222 and 224 may be formed by depositing an insulating material on the insulating layer 1226 (e.g., the lower portion of the insulating layer 1226 ).
  • the insulating layer 1226 may be etched to form recesses exposing portions of the redistribution patterns 222 and 224 , and connection terminals 202 may be formed on the portions of the redistribution patterns 222 and 224 , which are exposed by the recesses.
  • the recesses may be formed by a laser drilling process, a photolithography process, or an etching process.
  • the recesses may be formed over the first through-electrodes SV and the second through-electrodes FV to overlap with the first through-electrodes SV and the second through-electrodes FV.
  • the connection terminals 202 may be formed over the first through-electrodes SV and the second through-electrodes FV to overlap with the first through-electrodes SV and the second through-electrodes FV.
  • the molding layer 1230 may be cut to separate semiconductor packages 200 from each other.
  • a singulation process may be performed on the molding layer 1230 and the insulating layer 1226 along a sawing line SL of FIG. 18 .
  • the semiconductor chips 210 may be separated from each other to manufacture the semiconductor packages 200 .
  • the semiconductor packages 200 may be stacked to form a package stack PS.
  • one of the semiconductor packages 200 may be located at a predetermined position, and then, other semiconductor packages 200 may be stacked on the one semiconductor package 200 to connect the connection terminals 202 to the through-electrodes SV and FV of the one semiconductor package 200 .
  • the semiconductor packages 200 may not be aligned with each other, as described with reference to FIG. 3 .
  • the semiconductor packages 200 may be twist-shifted from each other.
  • An upper one of the semiconductor packages 200 vertically adjacent to each other may be twist-shifted 90 degrees with respect to a lower one of the semiconductor packages 200 vertically adjacent to each other.
  • the first through-electrodes SV of the upper one of the semiconductor packages 200 vertically adjacent to each other may be aligned with and connected to the second through-electrodes FV of the lower one of the semiconductor packages 200 vertically adjacent to each other.
  • the semiconductor device 10 described with reference to FIG. 1 may be manufactured as described above.
  • the same semiconductor packages 200 may be stacked to manufacture the semiconductor device having a wide bandwidth, and the processes of manufacturing the semiconductor device may be simplified.
  • the package stack PS may be stacked on a package substrate 100 .
  • the singulation process may be performed on the resultant structure obtained by the processes described with reference to FIGS. 15 to 18 .
  • the semiconductor chips 210 may be separated from each other to manufacture the semiconductor packages 200 .
  • the package substrate 100 may be provided.
  • the package substrate 100 may be a printed circuit board (PCB).
  • the package substrate 100 may have a top surface and a bottom surface.
  • First pads 102 may be provided on the top surface of the package substrate 100
  • second pads 104 may be provided on the bottom surface of the package substrate 100 .
  • the semiconductor packages 200 may be stacked on the package substrate 100 to form the package stack PS.
  • one of the semiconductor packages 200 may be mounted on the package substrate 100 in such a way that the connection terminals 202 of the one semiconductor package 200 are connected to the first pads 102 of the package substrate 100 , and then, other semiconductor packages 200 may be stacked on the one semiconductor package 200 in such a way that the connection terminals 202 of the other semiconductor package 200 are connected to the through-electrodes SV and FV of the one semiconductor package 200 .
  • a package molding layer 300 may be formed on the package substrate 100 .
  • a molding member may be deposited to cover the package stack PS on the package substrate 100 , and then, the molding member may be hardened to form the package molding layer 300 .
  • external terminals 106 may be provided on the bottom surface of the package substrate 100 .
  • the external terminals 106 may be formed on the second pads 104 of the package substrate 100 .
  • the semiconductor device 10 ′ described with reference to FIG. 4 may be manufactured as described above.
  • the semiconductor chips of the semiconductor packages may be respectively connected to the redistribution patterns electrically insulated from each other.
  • the bandwidth of the semiconductor device may be increased.
  • the same semiconductor packages may be stacked to manufacture the semiconductor device having a wide bandwidth, and the processes of manufacturing the semiconductor device may be simplified.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This U.S. non-provisional patent application is a continuation of U.S. application Ser. No. 17/018,324, filed on Sep. 11, 2020, which is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0009017, filed on Jan. 23, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated by reference in its entirety.
BACKGROUND
Some example embodiments of the inventive concepts relate to semiconductor devices and, more particularly, to semiconductor devices including a wafer-level semiconductor package.
With the development of an electronic industry, semiconductor packages have been variously developed to reduce their sizes, weights and/or manufacturing costs. In addition, various kinds of semiconductor packages have been developed to be applied to various fields such as digital imaging devices, MP3 players, mobile phones, and large-capacity storage means. For example, a ball grid array (BGA) package and/or a wafer-level package have been suggested.
In the wafer-level package, a redistribution pattern may be formed on a semiconductor chip without a molding process, and a solder ball may be adhered directly to the redistribution pattern. In other words, the molding process and a printed circuit board may not be required in the wafer-level package. Thus, processes of manufacturing the wafer-level package may be simplified and a thickness of the wafer-level package may be reduced.
SUMMARY
Some example embodiments of the inventive concepts may provide semiconductor devices with improved electrical characteristics and/or method for manufacturing the same.
In an example embodiment of the inventive concepts, a semiconductor device may include a first package, and a second package stacked on the first package. Each of the first and second packages may include a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package may be electrically connected to the second through-electrode of the first package.
In an example embodiment of the inventive concepts, a semiconductor device may include semiconductor packages sequentially stacked. Each of the semiconductor packages may include a redistribution substrate having a first redistribution pattern and a second redistribution pattern, the first and second redistribution patterns being insulated from each other, a semiconductor chip on the redistribution substrate, a first molding layer surrounding the semiconductor chip, and through-electrodes penetrating the first molding layer. The through-electrodes may include a first through-electrode on a first sidewall of the semiconductor chip and connected to the first redistribution pattern, and a second through-electrode spaced apart from the first through-electrode and connected to the second redistribution pattern. The first through-electrode of one semiconductor package of the semiconductor packages may be vertically aligned with the second through-electrode of another semiconductor package of the semiconductor packages thereunder.
In an example embodiment of the inventive concepts, a semiconductor device may include a first package and a second package stacked on the first package. The first package may include a first semiconductor chip, a first molding layer surrounding the first semiconductor chip, a first through-electrode penetrating the first molding layer and connected to the first semiconductor chip through a first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The second package may include a second semiconductor chip, a second molding layer surrounding the second semiconductor chip, a third through-electrode penetrating the second molding layer and connected to the second semiconductor chip through a second redistribution pattern, and a fourth through-electrode penetrating the second molding layer and not connected to the second redistribution pattern. The third through-electrode of the second package may be connected to the second through-electrode of the first package.
BRIEF DESCRIPTION OF THE DRAWINGS
The inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
FIG. 2 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
FIG. 3 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
FIGS. 4 and 5 are cross-sectional views illustrating semiconductor devices according to an example embodiment of the inventive concepts.
FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
FIG. 7 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
FIG. 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
FIG. 9 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
FIG. 10 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
FIG. 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
FIGS. 12 and 13 are schematic plan views illustrating arrangements of through-electrodes of semiconductor packages.
FIG. 14 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concepts.
 DETAILED DESCRIPTION
Semiconductor devices according to some example embodiments of the inventive concepts will be described hereinafter with reference to the accompanying drawings.
While the term “same” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts. FIG. 2 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages. FIG. 3 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
Referring to FIG. 1 , a semiconductor device 10 may include a package stack PS.
The package stack PS may include first semiconductor packages 200 stacked in a first direction D1. The first semiconductor packages 200 may have the same or substantially similar components and shape. Hereinafter, the components of the first semiconductor packages 200 will be described in detail.
Referring to FIGS. 1 and 2 , each of the first semiconductor packages 200 may include a first redistribution substrate 220, a first semiconductor chip 210, a first molding layer 230, and through-electrodes SV, FV and PGV.
The first redistribution substrate 220 may include a plurality of redistribution patterns. The redistribution patterns may include a first redistribution pattern 222, a second redistribution pattern 224, and a first insulating pattern 226. The first insulating pattern 226 may include stacked insulating layers. The number of the stacked insulating layers is 2 in FIG. 1 . However, the number of the stacked insulating layers may be variously changed. The first redistribution pattern 222 and the second redistribution pattern 224 may be buried by the stacked insulating layers. The first redistribution pattern 222 and the second redistribution pattern 224 may be electrically insulated from each other. Here, the first redistribution pattern 222 may include a signal transmission pattern connected to the first semiconductor chip 210, and the second redistribution pattern 224 may include floating patterns electrically isolated from the first semiconductor chip 210. A portion of the first redistribution pattern 222 and a portion of the second redistribution pattern 224 may be exposed through a bottom surface of the first insulating pattern 226, and the exposed portions of the first and second redistribution patterns 222 and 224 may function as conductive pads. For example, first connection terminals 202 may be provided on the exposed portions of the first and second redistribution patterns 222 and 224. The first connection terminals 202 may be connected to the first and second redistribution patterns 222 and 224.
The first semiconductor chip 210 may be mounted on the first redistribution substrate 220. The first semiconductor chip 210 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and first chip pads 212 connected to the interconnection lines. The integrated circuits of the first semiconductor chip 210 may include transistors. The first chip pads 212 may be provided on a bottom surface of the first semiconductor chip 210. The first chip pads 212 may include metal (e.g., copper (Cu) or aluminum (Al)). The first chip pads 212 may be electrically connected to the integrated circuits of the first semiconductor chip 210 through the interconnection lines. In the present specification, it will be understood that when a component is referred to as being “electrically connected” to another component, it may be connected directly to the other component or intervening components may be present. The first semiconductor chip 210 may have a polygonal shape when viewed in a plan view. In FIGS. 1 to 3 , the first semiconductor chip 210 having a square shape in a plan view is illustrated as an example. The first semiconductor chip 210 may include first to fourth sidewalls 210 a, 210 b, 210 c and 210 d. The first to fourth sidewalls 210 a, 210 b, 210 c and 210 d may be sequentially arranged in a second direction D2 corresponding to a counter-clockwise direction around the first direction D1. The first to fourth sidewalls 210 a, 210 b, 210 c and 210 d may be disposed adjacent to each other. The first to fourth sidewalls 210 a, 210 b, 210 c and 210 d of the first semiconductor chip 210 may have the same width. The first semiconductor chip 210 may have a thickness of 20 μm to 40 μm.
The first semiconductor chip 210 may be disposed on the first redistribution substrate 220 in such a way that the first chip pads 212 of the first semiconductor chip 210 face the first redistribution substrate 220. The first chip pads 212 may be connected to the first redistribution pattern 222 of the first redistribution substrate 220. The first chip pads 212 may not be connected to the second redistribution pattern 224. In other words, the first semiconductor chip 210 may be electrically insulated from the second redistribution pattern 224 of the first redistribution substrate 220. In FIG. 1 , the first chip pads 212 of the first semiconductor chip 210 are connected directly to the first redistribution pattern 222 of the first redistribution substrate 220. However, embodiments of the inventive concepts are not limited thereto. Unlike FIG. 1 , the first semiconductor chip 210 may be mounted on the first redistribution substrate 220 through chip terminals. For example, the chip terminals may be formed between the first redistribution pattern 222 and the first chip pads 212 to electrically connect the first chip pads 212 to the first redistribution pattern 222. In other words, the first semiconductor chip 210 may be electrically connected to the first redistribution substrate 220 through the chip terminals. Each of the chip terminals may include at least one of a solder, a pillar, or a bump. The chip terminals may include a conductive material (e.g., metal).
The first molding layer 230 may be provided on the first redistribution substrate 220. The first molding layer 230 may cover the first redistribution substrate 220. The first semiconductor chip 210 may be buried in the first molding layer 230. For example, the first molding layer 230 may cover the sidewalls of the first semiconductor chip 210 and a top surface of the first semiconductor chip 210. Unlike FIG. 1 , the first molding layer 230 may expose the top surface of the first semiconductor chip 210. In other words, the first molding layer 230 may surround the first semiconductor chip 210 on the first redistribution substrate 220. For example, the first molding layer 230 may cover the sidewalls of the first semiconductor chip 210 but may expose the top surface of the first semiconductor chip 210. When the first semiconductor chip 210 is mounted on the first redistribution substrate 220 through the chip terminals, the first molding layer 230 may extend into a gap region between the first semiconductor chip 210 and the first redistribution substrate 220 to seal the chip terminals. The first molding layer 230 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
The through-electrodes SV, FV and PGV may be provided in the first molding layer 230 on the first redistribution substrate 220. The through-electrodes SV, FV and PGV may be laterally spaced apart from the first semiconductor chip 210. The through-electrodes SV, FV and PGV may penetrate the first molding layer 230 in the first direction D1. Each of the through-electrodes SV, FV and PGV may be connected to one of the first redistribution pattern 222 and the second redistribution pattern 224 of the first redistribution substrate 220. Each of the through-electrodes SV, FV and PGV may be electrically connected to the first connection terminal 202 or the first semiconductor chip 210 through one of the first and second redistribution patterns 222 and 224. The through-electrodes SV, FV and PGV may be exposed at a top surface of the first molding layer 230. The through-electrodes SV, FV and PGV may include a conductive material (e.g., metal).
Referring to FIGS. 1 and 2 , the through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV. The first through-electrodes SV may be signal through-electrodes. Here, the signal through-electrode may mean a through-electrode which is used to transmit/receive an electrical signal to/from the first semiconductor chip 210 in the first semiconductor package 200. The second through-electrodes FV may be floating through-electrodes. Here, the floating through-electrode may mean a through-electrode which is electrically isolated from the first semiconductor chip 210 in the first semiconductor package 200. The third through-electrodes PGV may be power/ground through-electrodes. Here, the power/ground through-electrode may mean a through-electrode for supplying a ground voltage or a power voltage to the first semiconductor chip 210.
The first through-electrodes SV may be provided in a signal region SR located on the first sidewall 210 a of the first semiconductor chip 210. The first through-electrodes SV may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220. Unlike FIG. 2 , the first through-electrodes SV may be arranged in a zigzag form. The first through-electrodes SV may be connected to the first redistribution pattern 222 and may be connected to the first semiconductor chip 210 through the first redistribution pattern 222.
The second through-electrodes FV may be provided in floating regions FR1, FR2 and FR3 located on the second sidewall 210 b, the third sidewall 210 c and the fourth sidewall 210 d of the first semiconductor chip 210. In some example embodiments, the second through-electrodes FV may include first sub-through-electrodes FV1, second sub-through-electrodes FV2, and third sub-through-electrodes FV3. The first sub-through-electrodes FV1 may be provided in a first floating region FR1 located on the second sidewall 210 b of the first semiconductor chip 210. The second sub-through-electrodes FV2 may be provided in a second floating region FR2 located on the third sidewall 210 c of the first semiconductor chip 210. The third sub-through-electrodes FV3 may be provided in a third floating region FR3 located on the fourth sidewall 210 d of the first semiconductor chip 210. The first sub-through-electrodes FV1 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220. The second sub-through-electrodes FV2 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220. The third sub-through-electrodes FV3 may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220. Unlike FIG. 2 , the first sub-through-electrodes FV1 may be arranged in a zigzag form, the second sub-through-electrodes FV2 may be arranged in a zigzag form, and the third sub-through-electrodes FV3 may be arranged in a zigzag form. The first to third sub-through-electrodes FV1, FV2 and FV3 may be connected to the second redistribution pattern 224 and may be electrically insulated from the first semiconductor chip 210. Here, the first to third sub-through-electrodes FV1, FV2 and FV3 may be respectively connected to the floating patterns electrically isolated from each other in the second redistribution pattern 224. In other words, the first to third sub-through-electrodes FV1, FV2 and FV3 may be electrically insulated from each other.
The third through-electrodes PGV may be provided in a power/ground region PGR. The power/ground region PGR may be spaced apart from the signal region SR and the floating regions FR1, FR2 and FR3. For example, the power/ground region PGR may be disposed adjacent to each of corners of the first semiconductor chip 210. Here, each of the corners of the first semiconductor chip 210 may mean a portion at which two of the sidewalls 210 a, 210 b, 210 c and 210 d of the first semiconductor chip 210 are in contact with (e.g., meet) each other. The third through-electrodes PGV may be arranged to constitute rows and columns which are parallel to the top surface of the first redistribution substrate 220. The third through-electrodes PGV may be connected to the first semiconductor chip 210 through a redistribution pattern of the first redistribution substrate 220.
The first semiconductor package 200 may be provided as described above. A thickness of the first semiconductor package 200 including the first redistribution substrate 220, the first semiconductor chip 210 and the first molding layer 230 may range from 30 μm to 50 μm.
Referring to FIGS. 1 to 3 , the first semiconductor packages 200 may be stacked. For example, four first semiconductor packages 200 may be stacked. In FIGS. 1 and 3 , the four first semiconductor packages 200 are stacked. However, embodiments of the inventive concepts are not limited thereto. In certain example embodiments, two or more first semiconductor packages 200 may be stacked. Hereinafter, the embodiments of FIGS. 1 and 3 in which the four first semiconductor packages 200 are stacked will be mainly described.
The first semiconductor packages 200 may be stacked. Hereinafter, the four first semiconductor packages 200 will be referred to as first to fourth sub-semiconductor packages 200-1, 200-2, 200-3 and 200-4 for the purpose of ease and convenience in explanation. Each of the first to fourth sub-semiconductor packages 200-1, 200-2, 200-3 and 200-4 may be the same as the first semiconductor package 200 described above, and the components of the first to fourth sub-semiconductor packages 200-1, 200-2, 200-3 and 200-4 may be the same as each other.
The second sub-semiconductor package 200-2 may be mounted on the first sub-semiconductor package 200-1. The second sub-semiconductor package 200-2 may not be aligned with the first sub-semiconductor package 200-1. For example, the second sub-semiconductor package 200-2 and the first sub-semiconductor package 200-1 may be twist-shifted from each other. In the present specification, it may be understood that when one component is ‘twist-shifted’ from (or with respect to) another component, the one component may be rotated (or twisted) around one axis with respect to the other component in a state in which the one and other components overlap with each other along the one axis. The second sub-semiconductor package 200-2 may be twist-shifted with respect to the first sub-semiconductor package 200-1 in the second direction D2 corresponding to the counter-clockwise direction rotating around the first direction D1. For example, the first sub-semiconductor package 200-1 and the second sub-semiconductor package 200-2 may overlap with each other in the first direction D1, and the first sidewall 210 a of the first semiconductor chip 210 of the second sub-semiconductor package 200-2 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D1) as the second sidewall 210 b of the first semiconductor chip 210 of the first sub-semiconductor package 200-1. In other words, the second sub-semiconductor package 200-2 may be twist-shifted 90 degrees with respect to the first sub-semiconductor package 200-1. Thus, the first through-electrodes SV of the second sub-semiconductor package 200-2 may be aligned with the first sub-through-electrodes FV1 of the first sub-semiconductor package 200-1.
The first sub-through-electrodes FV1, the second sub-through-electrodes FV2 and the third sub-through-electrodes FV3 of the second sub-semiconductor package 200-2 may be aligned with the second sub-through-electrodes FV2, the third sub-through-electrodes FV3 and the first through-electrodes SV of the first sub-semiconductor package 200-1, respectively. The third through-electrodes PGV of the second sub-semiconductor package 200-2 may be aligned with and electrically connected to the third through-electrodes PGV of the first sub-semiconductor package 200-1.
The first connection terminals 202 of the second sub-semiconductor package 200-2 may be connected to the through-electrodes SV, FV1, FV2, FV3 and PGV of the first sub-semiconductor package 200-1. The first semiconductor chip 210 of the second sub-semiconductor package 200-2 may be connected to the first sub-through-electrodes FV1 of the first sub-semiconductor package 200-1 through the first redistribution pattern 222 and the first connection terminals 202 of the second sub-semiconductor package 200-2. The first semiconductor chip 210 of the first sub-semiconductor package 200-1 and the first semiconductor chip 210 of the second sub-semiconductor package 200-2 may be respectively connected to the first redistribution pattern 222 and the second redistribution pattern 224 of the first sub-semiconductor package 200-1 which are electrically insulated from each other, and thus a bandwidth of the semiconductor device 10 may be increased.
The third sub-semiconductor package 200-3 may be mounted on the second sub-semiconductor package 200-2. The third sub-semiconductor package 200-3 may not be aligned with the second sub-semiconductor package 200-2. For example, the third sub-semiconductor package 200-3 and the second sub-semiconductor package 200-2 may be twist-shifted from each other. The third sub-semiconductor package 200-3 may be twist-shifted with respect to the second sub-semiconductor package 200-2 in the second direction D2. For example, the second sub-semiconductor package 200-2 and the third sub-semiconductor package 200-3 may overlap with each other in the first direction D1, and the first sidewall 210 a of the first semiconductor chip 210 of the third sub-semiconductor package 200-3 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D1) as the second sidewall 210 b of the first semiconductor chip 210 of the second sub-semiconductor package 200-2. In other words, the third sub-semiconductor package 200-3 may be twist-shifted 90 degrees with respect to the second sub-semiconductor package 200-2. Thus, the first through-electrodes SV of the third sub-semiconductor package 200-3 may be aligned with the first sub-through-electrodes FV1 of the second sub-semiconductor package 200-2.
The first sub-through-electrodes FV1, the second sub-through-electrodes FV2 and the third sub-through-electrodes FV3 of the third sub-semiconductor package 200-3 may be aligned with the second sub-through-electrodes FV2, the third sub-through-electrodes FV3 and the first through-electrodes SV of the second sub-semiconductor package 200-2, respectively. The third through-electrodes PGV of the third sub-semiconductor package 200-3 may be aligned with and electrically connected to the third through-electrodes PGV of the second sub-semiconductor package 200-2.
The first connection terminals 202 of the third sub-semiconductor package 200-3 may be connected to the through-electrodes SV, FV1, FV2, FV3 and PGV of the second sub-semiconductor package 200-2. The first semiconductor chip 210 of the third sub-semiconductor package 200-3 may be connected to the second sub-through-electrodes FV2 of the first sub-semiconductor package 200-1 through the first redistribution pattern 222 and the first connection terminals 202 of the third sub-semiconductor package 200-3 and the first sub-through-electrodes FV1 of the second sub-semiconductor package 200-2. The first semiconductor chip 210 of the first sub-semiconductor package 200-1, the first semiconductor chip 210 of the second sub-semiconductor package 200-2 and the first semiconductor chip 210 of the third sub-semiconductor package 200-3 may be respectively connected to the first redistribution pattern 222 and the second redistribution patterns 224 of the first sub-semiconductor package 200-1 which are electrically insulated from each other, and thus the bandwidth of the semiconductor device 10 may be increased.
The fourth sub-semiconductor package 200-4 may be mounted on the third sub-semiconductor package 200-3. The fourth sub-semiconductor package 200-4 may not be aligned with the third sub-semiconductor package 200-3. For example, the fourth sub-semiconductor package 200-4 and the third sub-semiconductor package 200-3 may be twist-shifted from each other. The fourth sub-semiconductor package 200-4 may be twist-shifted with respect to the third sub-semiconductor package 200-3 in the second direction D2. For example, the third sub-semiconductor package 200-3 and the fourth sub-semiconductor package 200-4 may overlap with each other in the first direction D1, and the first sidewall 210 a of the first semiconductor chip 210 of the fourth sub-semiconductor package 200-4 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D1) as the second sidewall 210 b of the first semiconductor chip 210 of the third sub-semiconductor package 200-3. In other words, the fourth sub-semiconductor package 200-4 may be twist-shifted 90 degrees with respect to the third sub-semiconductor package 200-3. Thus, the first through-electrodes SV of the fourth sub-semiconductor package 200-4 may be aligned with the first sub-through-electrodes FV1 of the third sub-semiconductor package 200-3.
The first sub-through-electrodes FV1, the second sub-through-electrodes FV2 and the third sub-through-electrodes FV3 of the fourth sub-semiconductor package 200-4 may be aligned with the second sub-through-electrodes FV2, the third sub-through-electrodes FV3 and the first through-electrodes SV of the third sub-semiconductor package 200-3, respectively. The third through-electrodes PGV of the fourth sub-semiconductor package 200-4 may be aligned with and electrically connected to the third through-electrodes PGV of the third sub-semiconductor package 200-3.
The first connection terminals 202 of the fourth sub-semiconductor package 200-4 may be connected to the through-electrodes SV, FV1, FV2, FV3 and PGV of the third sub-semiconductor package 200-3. The first semiconductor chip 210 of the fourth sub-semiconductor package 200-4 may be connected to the third sub-through-electrodes FV3 of the first sub-semiconductor package 200-1 through the first redistribution pattern 222 and the first connection terminals 202 of the fourth sub-semiconductor package 200-4, the first sub-through-electrodes FV1 of the third sub-semiconductor package 200-3, and the second sub-through-electrodes FV2 of the second sub-semiconductor package 200-2. The first semiconductor chip 210 of the first sub-semiconductor package 200-1, the first semiconductor chip 210 of the second sub-semiconductor package 200-2, the first semiconductor chip 210 of the third sub-semiconductor package 200-3 and the first semiconductor chip 210 of the fourth sub-semiconductor package 200-4 may be respectively connected to the first redistribution pattern 222 and the second redistribution patterns 224 of the first sub-semiconductor package 200-1 which are electrically insulated from each other, and thus the bandwidth of the semiconductor device 10 may be increased. The package stack PS may be provided as described above.
In certain example embodiments, a semiconductor device 10′ may further include a package substrate 100 and a package molding layer 300. Referring to FIG. 4 , the package substrate 100 may be provided. The package substrate 100 may be a printed circuit board (PCB). The package substrate 100 may have a top surface and a bottom surface. First pads 102 may be provided on the top surface of the package substrate 100, and second pads 104 may be provided on the bottom surface of the package substrate 100. The first pads 102 may be pads on which the package stack PS is mounted. External terminals 106 may be disposed on the second pads 104, respectively. The external terminals 106 may electrically connect the semiconductor device 10′ to an external device.
The package stack PS may be mounted on the package substrate 100. For example, the first semiconductor packages 200 may be stacked on the package substrate 100.
The first sub-semiconductor package 200-1 disposed at a lowermost end of the package stack PS may be mounted on the package substrate 100. The first connection terminals 202 of the first sub-semiconductor package 200-1 may be connected to the first pads 102 of the package substrate 100. The first semiconductor chip 210 of the first sub-semiconductor package 200-1 may be connected to the package substrate 100 through the first redistribution pattern 222. The second through-electrodes FV1, FV2 and FV3 of the first sub-semiconductor package 200-1 may be connected to the package substrate 100 through the second redistribution pattern 224. The third through-electrodes PGV of the first sub-semiconductor package 200-1 may be connected to a ground circuit or a power circuit of the package substrate 100.
The package molding layer 300 may be provided on the package substrate 100. The package molding layer 300 may cover the package stack PS on the package substrate 100. The package molding layer 300 may cover sidewalls of the first semiconductor packages 200 and may fill spaces between the first semiconductor packages 200. Thus, the package molding layer 300 may protect the package stack PS. The package molding layer 300 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
In certain example embodiments, a semiconductor device 10″ may not include the package substrate 100. Referring to FIG. 5 , the package substrate 100 may not be provided. The first connection terminals 202 of the first sub-semiconductor package 200-1 disposed at the lowermost end of the package stack PS may electrically connect the semiconductor device 10″ to an external device.
The package molding layer 300 may be provided. The package molding layer 300 may cover the package stack PS. The package molding layer 300 may cover the sidewalls of the first semiconductor packages 200 and may fill the spaces between the first semiconductor packages 200. Thus, the package molding layer 300 may protect the package stack PS. In addition, the package molding layer 300 may cover the redistribution substrate 220 of the first sub-semiconductor package 200-1. Thus, the package molding layer 300 may protect the redistribution substrate 220 of the first sub-semiconductor package 200-1. The first connection terminals 202 of the first sub-semiconductor package 200-1 may penetrate the package molding layer 300 so as to be exposed to the outside. The package molding layer 300 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts. FIG. 7 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages.
Referring to FIGS. 6 and 7 , a semiconductor device 20 may include a package stack PS.
The package stack PS may include second semiconductor packages 400 stacked in the first direction D1. The second semiconductor packages 400 may be sequentially stacked. For example, two second semiconductor packages 400 may be sequentially stacked. The second semiconductor packages 400 may have the same or substantially similar components and shape.
The second semiconductor package 400 may include a second redistribution substrate 420, a second semiconductor chip 410, a second molding layer 430, and through-electrodes SV, FV and PGV.
The second redistribution substrate 420 may include a plurality of redistribution patterns. The redistribution patterns may include a third redistribution pattern 422, a fourth redistribution pattern 424, and a second insulating pattern 426. The third redistribution pattern 422 and the fourth redistribution pattern 424 may be buried in the second insulating pattern 426. The third redistribution pattern 422 and the fourth redistribution pattern 424 may be electrically insulated from each other. Here, the third redistribution pattern 422 may include a signal transmission pattern connected to the second semiconductor chip 410, and the fourth redistribution pattern 424 may include a floating pattern electrically isolated from the second semiconductor chip 410. A portion of the third redistribution pattern 422 and a portion of the fourth redistribution pattern 424 may be exposed through a bottom surface of the second insulating pattern 426, and second connection terminals 402 may be provided on the exposed portions of the third and fourth redistribution patterns 422 and 424.
The second semiconductor chip 410 may be mounted on the second redistribution substrate 420. The second semiconductor chip 410 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and second chip pads 412 connected to the interconnection lines. The second chip pads 412 may be electrically connected to the integrated circuits of the second semiconductor chip 410 through the interconnection lines. The second semiconductor chip 410 may have a square shape when viewed in a plan view.
The second semiconductor chip 410 may be disposed on the second redistribution substrate 420 in such a way that the second chip pads 412 of the second semiconductor chip 410 face the second redistribution substrate 420. The second chip pads 412 may be connected to the third redistribution pattern 422 of the second redistribution substrate 420. The second chip pads 412 may not be connected to the fourth redistribution pattern 424.
The second molding layer 430 may be provided on the second redistribution substrate 420. The second molding layer 430 may cover the second redistribution substrate 420. The second molding layer 430 may cover the second semiconductor chip 410.
The through-electrodes SV, FV and PGV may be provided in the second molding layer 430 on the second redistribution substrate 420. The through-electrodes SV, FV and PGV may be laterally spaced apart from the second semiconductor chip 410. The through-electrodes SV, FV and PGV may penetrate the second molding layer 430 in the first direction D1. Each of the through-electrodes SV, FV and PGV may be connected to one of the third redistribution pattern 422 and the fourth redistribution pattern 424 of the second redistribution substrate 420. Each of the through-electrodes SV, FV and PGV may be electrically connected to the second connection terminal 402 or the second semiconductor chip 410 through one of the third and fourth redistribution patterns 422 and 424.
The through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV. The first through-electrodes SV may be signal through-electrodes. The second through-electrodes FV may be floating through-electrodes. The third through-electrodes PGV may be power/ground through-electrodes.
The first through-electrodes SV may be provided on two sidewalls of the second semiconductor chip 410. The first through-electrodes SV may be connected to the third redistribution pattern 422 and may be connected to the second semiconductor chip 410 through the third redistribution pattern 422.
The second through-electrodes FV may be provided on two sidewalls of the second semiconductor chip 410. Here, the sidewalls of the second semiconductor chip 410 which are adjacent to the first through-electrodes SV may be different from the sidewalls of the second semiconductor chip 410 which are adjacent to the second through-electrodes FV. The second through-electrodes FV may be connected to the fourth redistribution pattern 424 and may be electrically insulated from the second semiconductor chip 410.
The third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV and FV. For example, the third through-electrodes PGV may be disposed adjacent to a corner of the second semiconductor chip 410. The third through-electrodes PGV may be connected to the second semiconductor chip 410 through a redistribution pattern of the second redistribution substrate 420.
The second semiconductor packages 400 may be stacked. The second semiconductor packages 400 may not be aligned with each other. For example, the second semiconductor packages 400 may be twist-shifted from each other. An upper one of the second semiconductor packages 400 may be twist-shifted with respect to a lower one of the second semiconductor packages 400 in the second direction D2. For example, the second semiconductor packages 400 may overlap with each other in the first direction D1, and the upper one of the second semiconductor packages 400 may be twist-shifted 180 degrees with respect to the lower one of the second semiconductor packages 400. Thus, the first through-electrodes SV of the upper one of the second semiconductor packages 400 may be aligned with the second through-electrodes FV of the lower one of the second semiconductor packages 400.
The second connection terminals 402 of the upper one of the second semiconductor packages 400 may be connected to the through-electrodes SV, FV and PGV of the lower one of the second semiconductor packages 400. The second semiconductor chip 410 of the upper one of the second semiconductor packages 400 may be connected to the second through-electrodes FV of the lower one of the second semiconductor packages 400. The second semiconductor chips 410 of the second semiconductor packages 400 may be respectively connected to the redistribution patterns electrically insulated from each other, and thus a bandwidth of the semiconductor device 20 may be increased.
FIG. 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts. FIG. 9 is a schematic plan view illustrating arrangement of through-electrodes of semiconductor packages. FIG. 10 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
Referring to FIGS. 8 to 10 , a semiconductor device 30 may include a package stack PS.
The package stack PS may include third semiconductor packages 500 stacked in the first direction D1. The third semiconductor packages 500 may be sequentially stacked. For example, six third semiconductor packages 500 may be sequentially stacked. The third semiconductor packages 500 may have the same or substantially similar components and shape.
The third semiconductor package 500 may include a third redistribution substrate 520, a third semiconductor chip 510, a third molding layer 530, and through-electrodes SV, FV and PGV.
The third redistribution substrate 520 may include a plurality of redistribution patterns. The redistribution patterns may include a fifth redistribution pattern 522, a sixth redistribution pattern 524, and a third insulating pattern 526. The fifth redistribution pattern 522 and the sixth redistribution pattern 524 may be buried in the third insulating pattern 526. The fifth redistribution pattern 522 and the sixth redistribution pattern 524 may be electrically insulated from each other. Here, the fifth redistribution pattern 522 may include a signal transmission pattern connected to the third semiconductor chip 510, and the sixth redistribution pattern 524 may include a floating pattern electrically isolated from the third semiconductor chip 510. A portion of the fifth redistribution pattern 522 and a portion of the sixth redistribution pattern 524 may be exposed through a bottom surface of the third insulating pattern 526, and third connection terminals 502 may be provided on the exposed portions of the fifth and sixth redistribution patterns 522 and 524.
The third semiconductor chip 510 may be mounted on the third redistribution substrate 520. The third semiconductor chip 510 may include a semiconductor substrate, integrated circuits on the semiconductor substrate, interconnection lines connected to the integrated circuits, and third chip pads 512 connected to the interconnection lines. The third chip pads 512 may be electrically connected to the integrated circuits of the third semiconductor chip 510 through the interconnection lines. The third semiconductor chip 510 may have a regular hexagon shape when viewed in a plan view. The third semiconductor chip 510 may include first to sixth sidewalls 510 a, 510 b, 510 c, 510 d, 510 e and 510 f.
The third semiconductor chip 510 may be disposed on the third redistribution substrate 520 in such a way that the third chip pads 512 of the third semiconductor chip 510 face the third redistribution substrate 520. The third chip pads 512 may be connected to the fifth redistribution pattern 522 of the third redistribution substrate 520. The third chip pads 512 may not be connected to the sixth redistribution pattern 524.
The third molding layer 530 may be provided on the third redistribution substrate 520. The third molding layer 530 may cover the third redistribution substrate 520. The third molding layer 530 may cover the third semiconductor chip 510.
The through-electrodes SV, FV and PGV may be provided in the third molding layer 530 on the third redistribution substrate 520. The through-electrodes SV, FV and PGV may be laterally spaced apart from the third semiconductor chip 510. Each of the through-electrodes SV, FV and PGV may be connected to one of the fifth redistribution pattern 522 and the sixth redistribution pattern 524 of the third redistribution substrate 520. Each of the through-electrodes SV, FV and PGV may be electrically connected to the third connection terminal 502 or the third semiconductor chip 510 through one of the fifth and sixth redistribution patterns 522 and 524.
The through-electrodes SV, FV and PGV may include first through-electrodes SV, second through-electrodes FV, and third through-electrodes PGV. The first through-electrodes SV may be signal through-electrodes. The second through-electrodes FV may be floating through-electrodes. The third through-electrodes PGV may be power/ground through-electrodes.
The first through-electrodes SV may be provided on the first sidewall 510 a of the third semiconductor chip 510. The first through-electrodes SV may be connected to the fifth redistribution pattern 522 and may be connected to the third semiconductor chip 510 through the fifth redistribution pattern 522.
The second through-electrodes FV may be provided on the second to sixth sidewalls 510 b, 510 c, 510 d, 510 e and 510 f of the third semiconductor chip 510. The second through-electrodes FV may be connected to the sixth redistribution pattern 524 and may be electrically insulated from the third semiconductor chip 510.
The third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV and FV. For example, the third through-electrodes PGV may be disposed adjacent to a corner of the third semiconductor chip 510. The third through-electrodes PGV may be connected to the third semiconductor chip 510 through a redistribution pattern of the third redistribution substrate 520.
The third semiconductor packages 500 may be stacked. The third semiconductor packages 500 may not be aligned with each other. For example, the third semiconductor packages 500 may be twist-shifted from each other. An upper one of the third semiconductor packages 500 vertically adjacent to each other may be twist-shifted in the second direction D2 with respect to a lower one of the third semiconductor packages 500 vertically adjacent to each other. For example, the third semiconductor packages 500 may overlap with each other in the first direction D1, and the upper one of the third semiconductor packages 500 vertically adjacent to each other may be twist-shifted 60 degrees with respect to the lower one of the third semiconductor packages 500 vertically adjacent to each other. Thus, the first through-electrodes SV of the upper one of the third semiconductor packages 500 may be aligned with the second through-electrodes FV of the lower one of the third semiconductor packages 500. In particular, the first through-electrodes SV of the upper one of the third semiconductor packages 500 may be aligned with the second through-electrodes FV located on the second sidewall 510 b of the third semiconductor chip 510 of the lower one of the third semiconductor packages 500.
The third connection terminals 502 of the upper one of the third semiconductor packages 500 may be connected to the through-electrodes SV, FV and PGV of the lower one of the third semiconductor packages 500. The third semiconductor chip 510 of the upper one of the third semiconductor packages 500 may be connected to the second through-electrodes FV of the lower one of the third semiconductor packages 500. The third semiconductor chips 510 of the third semiconductor packages 500 may be respectively connected to the redistribution patterns electrically insulated from each other, and thus a bandwidth of the semiconductor device 30 may be increased.
FIG. 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts. FIGS. 12 and 13 are schematic plan views illustrating arrangements of through-electrodes of semiconductor packages. FIG. 14 is a schematic exploded perspective view illustrating configurations of semiconductor packages.
Referring to FIGS. 11 to 13 , a semiconductor device may include a package stack PS.
The package stack PS may include fourth semiconductor packages 600 and fifth semiconductor packages 700, which are stacked in the first direction D1. The fourth semiconductor packages 600 and the fifth semiconductor packages 700 may be alternately stacked. For example, the fourth semiconductor package 600 and the fifth semiconductor package 700 which are sequentially stacked may constitute a sub-stack SS, and the package stack PS may include four sub-stacks SS sequentially stacked. The fourth semiconductor packages 600 may have the same or substantially similar components and shape. The fifth semiconductor packages 700 may have the same or substantially similar components and shape. Hereinafter, components of the sub-stack SS will be described in detail.
The fourth semiconductor package 600 may include a fourth redistribution substrate 620, a fourth semiconductor chip 610, a fourth molding layer 630, and through-electrodes SV1, FV and PGV.
The fourth redistribution substrate 620 may include a plurality of redistribution patterns. The redistribution patterns may include a seventh redistribution pattern 622, an eighth redistribution pattern 624, and a fourth insulating pattern 626. The seventh and eighth redistribution patterns 622 and 624 may be electrically insulated from each other.
The fourth semiconductor chip 610 may be mounted on the fourth redistribution substrate 620. The fourth semiconductor chip 610 may be connected to the fourth redistribution substrate 620 through fourth chip pads 612 electrically connected to integrated circuits of the fourth semiconductor chip 610. The fourth chip pads 612 may be connected to the seventh redistribution pattern 622 of the fourth redistribution substrate 620. The fourth chip pads 612 may not be connected to the eighth redistribution pattern 624. The fourth semiconductor chip 610 may have a square shape when viewed in a plan view. The fourth semiconductor chip 610 may include first to fourth sidewalls 610 a, 610 b, 610 c and 610 d.
The fourth molding layer 630 may cover the fourth semiconductor chip 610 on the fourth redistribution substrate 620.
First through-electrodes SV1, second through-electrodes FV and third through-electrodes PGV of the fourth semiconductor package 600 may be provided in the fourth molding layer 630. The first through-electrodes SV1 may be signal through-electrodes. The second through-electrodes FV may be floating through-electrodes. The third through-electrodes PGV may be power/ground through-electrodes.
The first through-electrodes SV1 may be provided in a signal region SR1 located on the first sidewall 610 a of the fourth semiconductor chip 610. The first through-electrodes SV1 may be connected to the fourth semiconductor chip 610 through the seventh redistribution pattern 622.
The second through-electrodes FV may be provided on the second sidewall 610 b, the third sidewall 610 c and the fourth sidewall 610 d of the fourth semiconductor chip 610. In addition, some FV4 of the second through-electrodes FV may be provided in a fourth floating region FR4 provided on the first sidewall 610 a of the fourth semiconductor chip 610. Here, the fourth floating region FR4 may be spaced apart from the signal region SR1 on the first sidewall 610 a of the fourth semiconductor chip 610. The second through-electrodes FV may be connected to the eighth redistribution pattern 624 and may be electrically insulated from the fourth semiconductor chip 610.
The third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV1 and FV. For example, the third through-electrodes PGV may be disposed adjacent to a corner of the fourth semiconductor chip 610.
The fifth semiconductor package 700 may include a fifth redistribution substrate 720, a fifth semiconductor chip 710, a fifth molding layer 730, and through-electrodes SV2, FV and PGV.
The fifth redistribution substrate 720 may include a plurality of redistribution patterns. The redistribution patterns may include a ninth redistribution pattern 722, a tenth redistribution pattern 724, and a fifth insulating pattern 726. The ninth and tenth redistribution patterns 722 and 724 may be electrically insulated from each other.
The fifth semiconductor chip 710 may be mounted on the fifth redistribution substrate 720. The fifth semiconductor chip 710 may be connected to the fifth redistribution substrate 720 through fifth chip pads 712 electrically connected to integrated circuits of the fifth semiconductor chip 710. The fifth chip pads 712 may be connected to the ninth redistribution pattern 722 of the fifth redistribution substrate 720. The fifth chip pads 712 may not be connected to the tenth redistribution pattern 724. The fifth semiconductor chip 710 may have a square shape when viewed in a plan view. The fifth semiconductor chip 710 may include first to fourth sidewalls 710 a, 710 b, 710 c and 710 d.
The fifth molding layer 730 may cover the fifth semiconductor chip 710 on the fifth redistribution substrate 720.
First through-electrodes SV2, second through-electrodes FV and third through-electrodes PGV of the fifth semiconductor package 700 may be provided in the fifth molding layer 730. The first through-electrodes SV2 may be signal through-electrodes. The second through-electrodes FV may be floating through-electrodes. The third through-electrodes PGV may be power/ground through-electrodes.
The first through-electrodes SV2 may be provided in a signal region SR2 located on the first sidewall 710 a of the fifth semiconductor chip 710. The first through-electrodes SV2 may be connected to the fifth semiconductor chip 710 through the ninth redistribution pattern 722.
The second through-electrodes FV may be provided on the second sidewall 710 b, the third sidewall 710 c and the fourth sidewall 710 d of the fifth semiconductor chip 710. In addition, some FV5 of the second through-electrodes FV may be provided in a fifth floating region FR5 provided on the first sidewall 710 a of the fifth semiconductor chip 710. Here, the fifth floating region FR5 may be spaced apart from the signal region SR5 on the first sidewall 710 a of the fifth semiconductor chip 710. The second through-electrodes FV may be connected to the tenth redistribution pattern 724 and may be electrically insulated from the fifth semiconductor chip 710.
The third through-electrodes PGV may be spaced apart from the first and second through-electrodes SV2 and FV. For example, the third through-electrodes PGV may be disposed adjacent to a corner of the fifth semiconductor chip 710.
The fifth semiconductor package 700 may be mounted on the fourth semiconductor package 600. The fourth semiconductor package 600 and the fifth semiconductor package 700 may have the same planar shape and may be aligned with each other in the first direction D1. For example, the first sidewall 610 a of the fourth semiconductor chip 610 may be located in the same plane (e.g., the same vertical plane or a plane in the first direction D1) as the first sidewall 710 a of the fifth semiconductor chip 710. Here, the signal region SR5 and the fifth floating region FR5 of the fifth semiconductor package 700 may overlap with the fourth floating region FR4 and the signal region SR4 of the fourth semiconductor package 600, respectively. Thus, the first through-electrodes SV2 of the fifth semiconductor package 700 may be aligned with the some FV4 of the second through-electrodes FV of the fourth semiconductor package 600 in the first direction D1, and the some FV5 of the second through-electrodes FV of the fifth semiconductor package 700 may be aligned with the first through-electrodes SV1 of the fourth semiconductor package 600 in the first direction D1.
The fourth semiconductor chip 610 of the fourth semiconductor package 600 may be connected to the seventh redistribution pattern 622, and the fifth semiconductor chip 710 of the fifth semiconductor package 700 may be connected to the eighth redistribution pattern 624 of the fourth semiconductor package 600 through the ninth redistribution pattern 722 of the fifth semiconductor package 700 and the some FV4 of the second through-electrodes FV of the fourth semiconductor package 600. In other words, the fourth semiconductor chip 610 and the fifth semiconductor chip 710 may be respectively connected to the seventh redistribution pattern 622 and the eighth redistribution pattern 624 which are electrically insulated from each other, and thus a bandwidth of the semiconductor device may be increased.
The sub-stacks SS may be stacked. The sub-stacks SS may not be aligned with each other. For example, the sub-stacks SS may be twist-shifted from each other. An upper one of the sub-stacks SS vertically adjacent to each other may be twist-shifted 90 degrees in the second direction D2 with respect to a lower one of the sub-stacks SS vertically adjacent to each other. The first through-electrodes SV1 and SV2 of the upper one of the sub-stacks SS may be aligned with and connected to the second through-electrodes FV of the lower one of the sub-stacks SS. As a result, the sub-stacks SS may be connected to the redistribution patterns electrically insulated from each other, and thus the bandwidth of the semiconductor device may be increased.
FIGS. 15 to 19 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concepts.
Referring to FIG. 15 , a support substrate 800 may be prepared. The support substrate 800 may be a carrier or may be an auxiliary member disposed on the carrier. The support substrate 800 may be formed of at least one of various materials such as glass, plastic, and metal. A separation layer 810 may be conformally formed on the support substrate 800. The separation layer 810 may be a double-sided adhesive tape or an adhesive layer. When the separation layer 810 is the double-sided adhesive tape, the separation layer 810 may be adhered onto the support substrate 800 by a lamination process using a vacuum. When the separation layer 810 is the adhesive layer, the separation layer 810 may be formed by coating the support substrate 800 with an adhesive material.
Semiconductor chips 210 may be disposed on the support substrate 800. The semiconductor chips 210 may be horizontally spaced apart from each other on the separation layer 810. Bottom surfaces of the semiconductor chips 210 may be adhered to the separation layer 810. Chip pads 212 may be disposed on the bottom surface of each of the semiconductor chips 210.
Referring to FIG. 16 , a molding layer 1230 may be formed on the support substrate 800. The molding layer 1230 may be formed to cover the semiconductor chips 210 on the support substrate 800. The molding layer 1230 may cover top surfaces and sidewalls of the semiconductor chips 210. The molding layer 1230 may include an insulating polymer (e.g., an epoxy molding compound (EMC)).
First through-electrodes SV and second through-electrodes FV may be formed in the molding layer 1230. For example, holes may be formed to penetrate the molding layer 1230, and then, the first and second through-electrodes SV and FV may be formed by filling the holes with a conductive material. As described with reference to FIG. 2 , the first through-electrodes SV may be formed on one sidewall of the semiconductor chip 210, and the second through-electrodes FV may be formed on the other sidewalls of the semiconductor chip 210.
Referring to FIG. 17 , the support substrate 800 may be separated from the semiconductor chips 210 by selectively removing the support substrate 800. For example, when the separation layer 810 is the double-sided adhesive tape, the adhesive tape may be weakened by applying heat of 170 degrees Celsius or more, and thus the separation layer 810 may be detached from the semiconductor chips 210. When the support substrate 800 is formed of glass, ultraviolet light may be irradiated to the adhesive tape through a back surface of the support substrate 800, and thus an adhesive of the adhesive tape may be hardened to weaken adhesive strength of the adhesive tape. Alternatively, the separation layer 810 may be melted using chemicals and thus may be removed. Thus, the bottom surfaces of the semiconductor chips 210 and a bottom surface of the molding layer 1230 may be exposed.
A redistribution layer 1220 may be formed on the bottom surface of the molding layer 1230. For example, an insulating layer 1226 may be formed on the bottom surface of the molding layer 1230. For example, the insulating layer 1226 may be formed by a spin-coating method, a physical vapor deposition (PVD) method (e.g., a sputtering method), a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a printing method. For example, the insulating layer 1226 may be formed of an inorganic insulating layer (e.g., a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer) or an organic polymer insulating layer (e.g., polyimide). In some example embodiments, the insulating layer 1226 may include photosensitive polyimide. Thereafter, the insulating layer 1226 (e.g., a lower portion of the insulating layer 1226) may be patterned to form via holes. The via holes may expose the chip pads 212 of the semiconductor chips 210, the first through-electrodes SV, and the second through-electrodes FV. The via holes may be formed by a laser drilling process, a photolithography process, or an etching process. Redistribution patterns 222 and 224 may be formed on the insulating layer 1226. For example, a conductive layer may be formed on the insulating layer 1226, and the conductive layer may be patterned to form the redistribution patterns 222 and 224. The redistribution patterns 222 and 224 may include a conductive material (e.g., copper (Cu)). The redistribution patterns 222 and 224 may include a first redistribution pattern 222 connected to the chip pads 212 and the first through-electrodes SV, and a second redistribution pattern 224 connected to the second through-electrodes FV. An insulating layer 1226 (e.g., an upper portion of the insulating layer 1226) covering the redistribution patterns 222 and 224 may be formed by depositing an insulating material on the insulating layer 1226 (e.g., the lower portion of the insulating layer 1226).
Referring to FIG. 18 , the insulating layer 1226 may be etched to form recesses exposing portions of the redistribution patterns 222 and 224, and connection terminals 202 may be formed on the portions of the redistribution patterns 222 and 224, which are exposed by the recesses. For example, the recesses may be formed by a laser drilling process, a photolithography process, or an etching process. The recesses may be formed over the first through-electrodes SV and the second through-electrodes FV to overlap with the first through-electrodes SV and the second through-electrodes FV. Thus, the connection terminals 202 may be formed over the first through-electrodes SV and the second through-electrodes FV to overlap with the first through-electrodes SV and the second through-electrodes FV.
Next, the molding layer 1230 may be cut to separate semiconductor packages 200 from each other. For example, a singulation process may be performed on the molding layer 1230 and the insulating layer 1226 along a sawing line SL of FIG. 18 . In other words, since the molding layer 1230 and the insulating layer 1226 are sawed, the semiconductor chips 210 may be separated from each other to manufacture the semiconductor packages 200.
Referring again to FIG. 1 , the semiconductor packages 200 may be stacked to form a package stack PS. For example, one of the semiconductor packages 200 may be located at a predetermined position, and then, other semiconductor packages 200 may be stacked on the one semiconductor package 200 to connect the connection terminals 202 to the through-electrodes SV and FV of the one semiconductor package 200. At this time, the semiconductor packages 200 may not be aligned with each other, as described with reference to FIG. 3 . For example, the semiconductor packages 200 may be twist-shifted from each other. An upper one of the semiconductor packages 200 vertically adjacent to each other may be twist-shifted 90 degrees with respect to a lower one of the semiconductor packages 200 vertically adjacent to each other. The first through-electrodes SV of the upper one of the semiconductor packages 200 vertically adjacent to each other may be aligned with and connected to the second through-electrodes FV of the lower one of the semiconductor packages 200 vertically adjacent to each other. The semiconductor device 10 described with reference to FIG. 1 may be manufactured as described above.
According to the embodiments of the inventive concepts, the same semiconductor packages 200 may be stacked to manufacture the semiconductor device having a wide bandwidth, and the processes of manufacturing the semiconductor device may be simplified.
In certain example embodiments, the package stack PS may be stacked on a package substrate 100.
The singulation process may be performed on the resultant structure obtained by the processes described with reference to FIGS. 15 to 18 . In other words, since the molding layer 1230 and the insulating layer 1226 are sawed, the semiconductor chips 210 may be separated from each other to manufacture the semiconductor packages 200.
Referring to FIG. 19 , the package substrate 100 may be provided. The package substrate 100 may be a printed circuit board (PCB). The package substrate 100 may have a top surface and a bottom surface. First pads 102 may be provided on the top surface of the package substrate 100, and second pads 104 may be provided on the bottom surface of the package substrate 100.
Referring again to FIG. 4 , the semiconductor packages 200 may be stacked on the package substrate 100 to form the package stack PS. For example, one of the semiconductor packages 200 may be mounted on the package substrate 100 in such a way that the connection terminals 202 of the one semiconductor package 200 are connected to the first pads 102 of the package substrate 100, and then, other semiconductor packages 200 may be stacked on the one semiconductor package 200 in such a way that the connection terminals 202 of the other semiconductor package 200 are connected to the through-electrodes SV and FV of the one semiconductor package 200.
A package molding layer 300 may be formed on the package substrate 100. For example, a molding member may be deposited to cover the package stack PS on the package substrate 100, and then, the molding member may be hardened to form the package molding layer 300.
Thereafter, external terminals 106 may be provided on the bottom surface of the package substrate 100. The external terminals 106 may be formed on the second pads 104 of the package substrate 100. The semiconductor device 10′ described with reference to FIG. 4 may be manufactured as described above.
In the semiconductor device according to the embodiments of the inventive concepts, the semiconductor chips of the semiconductor packages may be respectively connected to the redistribution patterns electrically insulated from each other. Thus, the bandwidth of the semiconductor device may be increased.
According to the embodiments of the inventive concepts, the same semiconductor packages may be stacked to manufacture the semiconductor device having a wide bandwidth, and the processes of manufacturing the semiconductor device may be simplified.
While the inventive concepts have been described with reference to some example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above example embodiments are not limiting, but illustrative. Thus, the scope of the inventive concepts is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.

Claims (20)

What is claimed is:
1. A semiconductor device, comprising:
semiconductor packages sequentially stacked,
wherein each of the semiconductor packages includes,
a redistribution substrate having a first redistribution pattern and a second redistribution pattern, the first and second redistribution pattern being insulated from each other,
a semiconductor chip on the redistribution substrate, the semiconductor chip electrically connected to the first redistribution pattern and not electrically connected to the second redistribution pattern,
a first molding layer surrounding the semiconductor chip,
a first through-electrode penetrating the first molding layer on a first sidewall of the semiconductor chip and connected to the first redistribution pattern, and
a second through-electrode penetrating the first molding layer on a second sidewall of the semiconductor chip and connected to the second redistribution pattern, the second sidewall being different from the first sidewall, and
wherein the first sidewall of the semiconductor chip of one semiconductor package is in a same vertical plane as the second sidewall of the semiconductor chip of another semiconductor.
2. The semiconductor device of claim 1, wherein the first through-electrode of the one semiconductor package of the semiconductor packages is vertically aligned with the second through-electrode of another semiconductor package of the semiconductor packages thereunder.
3. The semiconductor device of claim 1, wherein the first redistribution pattern of the one semiconductor package is connected to the second through-electrode of another semiconductor package.
4. The semiconductor device of claim 1, wherein the first sidewall and the second sidewall meet each other.
5. The semiconductor device of claim 1, wherein the one semiconductor package is twist-shifted with respect to another semiconductor package when viewed in a plan view.
6. The semiconductor device of claim 5, wherein the one semiconductor package is twist-shifted 90 degrees or 180 degrees with respect to the another semiconductor package.
7. The semiconductor device of claim 1, wherein the semiconductor chip has a polygonal shape including a tetragonal shape or a hexagonal shape when viewed in a plan view.
8. The semiconductor device of claim 1, wherein
the semiconductor packages further comprises third through-electrodes penetrating the first molding layer so as to be connected to a ground circuit or a power circuit of the redistribution substrate, respectively, and
the third through-electrodes of the semiconductor packages are electrically connected to each other.
9. The semiconductor device of claim 8, wherein the third through-electrodes of the semiconductor packages are vertically aligned with each other.
10. The semiconductor device of claim 1, further comprising:
a package substrate on which the semiconductor packages are stacked; and
a second molding layer covering the semiconductor packages on the package substrate.
11. A semiconductor device comprising:
a first package; and
a second package stacked on the first package,
wherein each of the first and second packages comprises,
a first redistribution substrate having a first redistribution pattern and a second redistribution pattern that are electrically insulated from each other,
a first semiconductor chip on the first redistribution substrate, the first semiconductor chip connected to the first redistribution pattern,
a first molding layer covering the first semiconductor chip on the first redistribution substrate,
a first through-electrode penetrating the first molding layer and connected to the first redistribution pattern, and
a second through-electrode penetrating the first molding layer and connected to the second redistribution pattern,
wherein the first package and the second package have a same planar shape, and
wherein the second package is twist-shifted 90 degrees or 180 degrees with respect to the first package when viewed in a plan view.
12. The semiconductor device of claim 11, wherein
the second through-electrode is not connected to the first redistribution pattern,
the first semiconductor chip is electrically connected to the second redistribution pattern, and
the first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.
13. The semiconductor device of claim 11, wherein the first through-electrode of the second package is vertically aligned with the second through-electrode of the first package.
14. The semiconductor device of claim 11, wherein
the first through-electrode is on a first sidewall of the first semiconductor chip, the first sidewall extending in a first direction,
the second through-electrode is on a second sidewall of the first semiconductor chip, the second sidewall extending in a second direction.
15. The semiconductor device of claim 14, wherein the first sidewall and the second sidewall of the first semiconductor chip meet each other.
16. The semiconductor device of claim 14, wherein the first sidewall of the first semiconductor chip of the second package is in a same vertical plane as the second sidewall of the first semiconductor chip of the first package.
17. The semiconductor device of claim 14, wherein the first semiconductor chip has a square shape when viewed in a plan view.
18. The semiconductor device of claim 11, wherein the first semiconductor chip of the second package is electrically connected to the second redistribution pattern of the first package through the first redistribution pattern of the second package and the second through-electrode of the first package.
19. The semiconductor device of claim 18, further comprising:
a third package stacked on the second package,
wherein the third package comprises,
a second redistribution substrate having a third redistribution pattern,
a second semiconductor chip on the second redistribution substrate and connected to the third redistribution pattern,
a second molding layer covering the second semiconductor chip on the second redistribution substrate, and
a third through-electrode penetrating the second molding layer so as to be connected to the third redistribution pattern, and
wherein the third redistribution pattern of the third package is electrically connected to the second through-electrode of the second package.
20. The semiconductor device of claim 11, further comprising:
a package substrate on which the first package is stacked; and
a package molding layer covering the first and second packages on the package substrate.
US17/696,157 2020-01-23 2022-03-16 Semiconductor device Active US11784171B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/696,157 US11784171B2 (en) 2020-01-23 2022-03-16 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020200009017A KR20210095754A (en) 2020-01-23 2020-01-23 Semiconductor device
KR10-2020-0009017 2020-01-23
US17/018,324 US11329032B2 (en) 2020-01-23 2020-09-11 Semiconductor device
US17/696,157 US11784171B2 (en) 2020-01-23 2022-03-16 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US17/018,324 Continuation US11329032B2 (en) 2020-01-23 2020-09-11 Semiconductor device

Publications (2)

Publication Number Publication Date
US20220208743A1 US20220208743A1 (en) 2022-06-30
US11784171B2 true US11784171B2 (en) 2023-10-10

Family

ID=76971200

Family Applications (2)

Application Number Title Priority Date Filing Date
US17/018,324 Active US11329032B2 (en) 2020-01-23 2020-09-11 Semiconductor device
US17/696,157 Active US11784171B2 (en) 2020-01-23 2022-03-16 Semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US17/018,324 Active US11329032B2 (en) 2020-01-23 2020-09-11 Semiconductor device

Country Status (2)

Country Link
US (2) US11329032B2 (en)
KR (1) KR20210095754A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210095754A (en) * 2020-01-23 2021-08-03 삼성전자주식회사 Semiconductor device
US12033947B2 (en) * 2021-04-15 2024-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078541B2 (en) 2002-02-07 2006-07-18 Galileo Pharmaceuticals, Inc. Benzofuran derivatives
US7098541B2 (en) 2003-05-19 2006-08-29 Hewlett-Packard Development Company, L.P. Interconnect method for directly connected stacked integrated circuits
US20110309468A1 (en) 2010-06-17 2011-12-22 Samsung Electronics Co., Ltd. Semiconductor chip package and method of manufacturing the same
US20130214855A1 (en) 2009-11-11 2013-08-22 International Business Machines Corporation Integrated Circuit Die Stacks With Rotationally Symmetric VIAS
US8546946B2 (en) 2011-04-20 2013-10-01 Nanya Technology Corp. Chip stack package having spiral interconnection strands
US9108841B1 (en) 2014-03-05 2015-08-18 Freescale Semiconductor, Inc. Microelectronic packages having stacked accelerometer and magnetometer die and methods for the production thereof
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US9177892B2 (en) 2011-03-31 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for increasing bandwidths of stacked dies
US9379063B2 (en) 2011-08-31 2016-06-28 Ps4 Luxco S.A.R.L. Semiconductor device and semiconductor chip
US9595485B2 (en) 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US20180130782A1 (en) 2016-11-10 2018-05-10 Samsung Electronics Co., Ltd. Stacked semiconductor package
US10103124B2 (en) 2015-08-17 2018-10-16 Fujitsu Limited Semiconductor device
US20190333894A1 (en) 2018-04-30 2019-10-31 SK Hynix Inc. Stack packages including through mold vias
US11329032B2 (en) * 2020-01-23 2022-05-10 Samsung Electronics Co., Ltd. Semiconductor device

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078541B2 (en) 2002-02-07 2006-07-18 Galileo Pharmaceuticals, Inc. Benzofuran derivatives
US7098541B2 (en) 2003-05-19 2006-08-29 Hewlett-Packard Development Company, L.P. Interconnect method for directly connected stacked integrated circuits
US20130214855A1 (en) 2009-11-11 2013-08-22 International Business Machines Corporation Integrated Circuit Die Stacks With Rotationally Symmetric VIAS
US8816490B2 (en) 2009-11-11 2014-08-26 International Business Machines Corporation Integrated circuit die stacks with rotationally symmetric VIAS
US20110309468A1 (en) 2010-06-17 2011-12-22 Samsung Electronics Co., Ltd. Semiconductor chip package and method of manufacturing the same
US9177892B2 (en) 2011-03-31 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for increasing bandwidths of stacked dies
US8546946B2 (en) 2011-04-20 2013-10-01 Nanya Technology Corp. Chip stack package having spiral interconnection strands
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US9379063B2 (en) 2011-08-31 2016-06-28 Ps4 Luxco S.A.R.L. Semiconductor device and semiconductor chip
US9108841B1 (en) 2014-03-05 2015-08-18 Freescale Semiconductor, Inc. Microelectronic packages having stacked accelerometer and magnetometer die and methods for the production thereof
US9595485B2 (en) 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US9761565B2 (en) 2014-06-26 2017-09-12 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US10103124B2 (en) 2015-08-17 2018-10-16 Fujitsu Limited Semiconductor device
US20180130782A1 (en) 2016-11-10 2018-05-10 Samsung Electronics Co., Ltd. Stacked semiconductor package
US20190333894A1 (en) 2018-04-30 2019-10-31 SK Hynix Inc. Stack packages including through mold vias
US11329032B2 (en) * 2020-01-23 2022-05-10 Samsung Electronics Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US20210233897A1 (en) 2021-07-29
US20220208743A1 (en) 2022-06-30
US11329032B2 (en) 2022-05-10
KR20210095754A (en) 2021-08-03

Similar Documents

Publication Publication Date Title
US9911688B2 (en) Semiconductor chip, semiconductor package including the same, and method of fabricating the same
US7602047B2 (en) Semiconductor device having through vias
US8373278B2 (en) Semiconductor device having stacked dice disposed on base substrate
US8338289B2 (en) Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
US8043895B2 (en) Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US11784171B2 (en) Semiconductor device
US7948089B2 (en) Chip stack package and method of fabricating the same
US9881859B2 (en) Substrate block for PoP package
US20170098619A1 (en) Semiconductor chip, semiconductor package including the same, and method of fabricating the same
KR20140083657A (en) Circuit board having embedded interposer, electronic module using the device, and method for manufacturing the same
US20210375810A1 (en) Semiconductor package
US11532551B2 (en) Semiconductor package with chamfered semiconductor device
US11676927B2 (en) Semiconductor package device
US20110233795A1 (en) Stacked wafer level package having a reduced size
US20170062363A1 (en) Semiconductor device, and method of fabricating the same
CN115708200A (en) Semiconductor package
US11495507B2 (en) Manufacturing method of a semiconductor package
US20170062387A1 (en) Semiconductor chip, semiconductor package including the same, and method of fabricating the same
CN112397462B (en) Semiconductor packaging structure and manufacturing method thereof
TW202046456A (en) Electronic package and manufacturing method thereof
US20230035026A1 (en) Semiconductor package
US20230011778A1 (en) Semiconductor package
TWI784285B (en) Semiconductor devices and methods for manufacturing the same
US10020288B2 (en) Semiconductor chips including redistribution interconnections and related semiconductor packages
US20230121888A1 (en) Semiconductor package

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: AWAITING TC RESP., ISSUE FEE NOT PAID

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE