US11569444B2 - Three-dimensional confined memory cell with decoupled read-write - Google Patents
Three-dimensional confined memory cell with decoupled read-write Download PDFInfo
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- US11569444B2 US11569444B2 US17/217,788 US202117217788A US11569444B2 US 11569444 B2 US11569444 B2 US 11569444B2 US 202117217788 A US202117217788 A US 202117217788A US 11569444 B2 US11569444 B2 US 11569444B2
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- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
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Definitions
- the present invention relates to memory devices, and more specifically, to resistive analog memory devices.
- ANNs artificial neural networks
- DNNs deep neural networks
- CNNs convolutional neural networks
- Crossbar arrays are high density, low cost circuit architectures used to form a variety of electronic circuits and devices, including ANN architectures, neuromorphic microchips and ultra-high density nonvolatile memory.
- a basic crossbar array configuration includes a set of conductive row wires and a set of conductive column wires formed to intersect the set of conductive row wires.
- the intersections between the two sets of wires are separated by so-called cross-point devices.
- Such cross-point devices may be analog memory devices capable of storing a weighted value (e.g., 0-1 instead of the binary 0 or 1), and may be capable of use in analog computing devices.
- Cross-point devices can be implemented as so-called resistive memory (colloquially, memristive) devices.
- Characteristics of a memristive device may include non-volatility, the ability to store a variable analog resistance value, the ability to determine the analog resistance value without disturbing the state of the memristive device, and the ability to tune up or tune down a resistance using current or voltage pulses.
- These memristive devices can be used in hardware to simulate the artificial synapses of an ANN.
- An embodiment of the invention may include a memory structure.
- the structure may include a multi-level nonvolatile electrochemical cell having an inner conductive core surrounded by a programming gate.
- the inner conductive core may be in contact with a first contact.
- the outer portion of the cell may comprise a channel.
- the channel may be in contact with a second contact.
- An embodiment of the invention may include a first electrode, a second electrode, and a multi-level nonvolatile electrochemical cell located between the first electrode and second electrode.
- the multi-level nonvolatile electrochemical cell may have a read path and a write path through the cell, where the read path and the write path are different.
- An embodiment of the invention may include a method of writing to the memory structure.
- the method may include creating a voltage between the first contact and the second contact.
- the voltage may cause electrons to move through a variable resistance channel of the multi-level nonvolatile electrochemical cell.
- the voltage may create an electric field across a charge-exchange layer, which may cause ions to move along the electric field.
- the method may include the direction of ion movement being different than the direction of electron movement.
- FIG. 1 depicts a cross-sectional view of a bottom contact located in an insulating layer, according to an example embodiment
- FIG. 2 depicts a cross-sectional view following deposition of a channel material layer; according to an example embodiment
- FIG. 3 depicts a cross-sectional view following deposition of a ion exchange layer; according to an example embodiment
- FIG. 4 depicts a cross-sectional view following deposition of a conductive core; according to an example embodiment
- FIG. 5 depicts a cross-sectional view following deposition of a dielectric layer, according to an example embodiment
- FIG. 6 depicts an electrical wiring diagram describing the operation of the memory cell, according to an example embodiment
- FIG. 7 depicts a movement of charged elements through the memory cell during a write operation, according to an example embodiment
- FIG. 8 depicts a movement of charged elements through the memory cell causing a read operation, according to an example embodiment
- FIG. 9 depicts possible tuning parameters of the device design, according to an example embodiment.
- FIG. 10 depicts a plurality of memory cells arranged in a cross-point array, according to an example embodiment.
- terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures.
- Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element.
- the term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
- Analog resistive memory devices may use mechanisms of ion transfer during write operations to impact the resistance of the overall memory device during read operations. Such devices may enable migration of conductive ions into a dielectric region, thereby increasing the conductivity through the dielectric, or alternatively may enable migration of ions containing holes into a conductive region, thereby reducing the conductivity of the conductive region.
- read and write paths of these devices overlap, leading to breakdown of the dielectric. By decoupling the read path and write path during operations, such breakdown may be reduced, as the flow of current through the devices is not required to move through a dielectric layer of the device.
- decoupling of read and write paths would typically require additional wiring to the device, as well as additional transistors to signal the device, thereby increasing the footprint of structures needed to operate the device.
- the footprint of the structures may be reduced, while maintaining decoupled read and write paths for the resistive analog memory device.
- the M x dielectric 100 may be formed on a sub structure (not shown) and may be formed using any suitable dielectric deposition techniques.
- the M x dielectric 100 may be silicon nitride, silicon oxide, silicon oxynitride, or any other suitable low-k dielectrics.
- the deposited dielectric can be etched to form the regions that contain the bottom electrode 110 any appropriate lithographic process.
- the bottom electrode 110 can be formed from metal or a metal nitride.
- the sense electrodes are made using titanium at a thickness of about 5 nm or platinum at a thickness of about 50 nm, but it should be understood that any appropriate material and thickness can be used, including for example tungsten, nickel, molybdenum, tantalum, copper, silver, gold, ruthenium, iridium, rhenium, rhodium, and alloys thereof.
- the bottom electrode 110 can be formed by an appropriate physical vapor deposition (PVD) process, whereby a sputtering apparatus can include electron-beam evaporation, thermal evaporation, direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering.
- PVD physical vapor deposition
- CMP chemical mechanical polishing
- the channel material layer 120 is formed from a variable-resistance material that changes resistance based on its oxygen content and is composed of metal-oxides such as WOx, TiOx, VOx, TaOx, HfOx.
- the variable-resistance material can be WO3, TiO2, HfO2, Ta2O5, VxOy, and their sub-oxides.
- the channel material layer 120 can be formed by any appropriate deposition process such as, for example, PVD, ALD, and CVD.
- a metal-oxide layer about 50 nm thick can be formed by sputtering, or a layer of about 40 nm thick can be formed by electron beam evaporation.
- the channel can be made 1-50 nm in thickness in some examples.
- an ion exchange material layer 130 is depicted, and optionally a metal-oxide reservoir layer may be formed with the ion exchange material layer.
- the ion exchange material layer 130 may be formed on the channel material layer 120 .
- the ion exchange material layer 130 may be formed using a dielectric material composed of a metal-oxide such as HfOx or TaOx in their sub-oxide or stoichiometric form, for example, HfO 2 , Ta 2 O 5 , and their sub-oxides.
- the ion exchange material layer 130 can be of a thickness between 1-50 nm.
- the ion exchange material layer 130 can be formed using chemical vapor deposition (CVD), PVD, or atomic layer deposition (ALD).
- the optional metal-oxide reservoir layer that is formed from any appropriate oxygen-containing material where oxygen ions readily dissociate under an applied voltage.
- One exemplary material for the metal-oxide reservoir layer is cerium oxide (CeO 2 ), which reversibly converts to a nonstoichiometric oxide by emitting oxygen ions when subjected to an appropriate voltage.
- the metal-oxide reservoir layer can be formed from cerium oxide at a thickness of less than 100 nm by a thermal evaporation process. The thickness of the metal-oxide reservoir layer can be in a predetermined range.
- metal-oxide reservoir can be used for metal-oxide reservoir.
- the metal-oxide reservoir can also be formed using ALD, PVD, CVD, diffusion, or any other process.
- the metal-oxide reservoir can be a hydrogen reservoir in other examples and is composed of suitable material.
- the charge exchange can include non-metallic ions (oxygen, hydrogen) modifying the resistivity of the channel material layer 120 .
- the charge exchange in one or more examples, can include electron/holes building up static charge in ion exchange material 125 and affecting carrier dynamic in the channel.
- the channel material layer 120 accepts additional oxygen ions by intercalation, where the oxide material creates a crystalline structure and additional oxygen ions (e.g., O 2 ⁇ ) fit into gaps in that crystalline structure under an appropriate voltage. The voltage overcomes the repulsive force created by any electrical charge already present in the channel material layer 120 , forcing more charged ions to occupy that layer.
- an conductive core 140 is formed on the optional metal-oxide reservoir layer or ion exchange material layer 130 .
- the conductive core 140 can be formed from metal or a metal nitride.
- the conductive core 140 are made using titanium or platinum, but it should be understood that any appropriate material and thickness can be used, including for example tungsten, nickel, molybdenum, tantalum, copper, silver, gold, ruthenium, iridium, rhenium, rhodium, and alloys thereof.
- the conductive core 140 can be formed by an appropriate physical vapor deposition (PVD) process, whereby a sputtering apparatus can include electron-beam evaporation, thermal evaporation, direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering.
- PVD physical vapor deposition
- CMP chemical mechanical polishing
- wiring above the memory cell may be formed.
- An M x+1 dielectric (not shown) may be formed and patterned to create a trench for the top electrode 150 .
- the M x+1 dielectric layer may be formed using any suitable dielectric deposition techniques.
- the M x+1 dielectric may be silicon nitride, silicon oxide, silicon oxynitride, or any other suitable low-k dielectrics.
- the top electrode 150 may be formed within a M x+1 dielectric layer (not shown), using similar materials and techniques as the formation of the bottom electrode 110 and the conductive pedestal 115 in the M x dielectric 100 .
- the top electrode 150 may be part of a wordline. Additionally, as illustrated in FIG. 6 and overlaid onto FIG.
- the structure may include a first programming gate 10 , a first variable resistor 20 , a fixed channel resistor 22 , a fixed conductive core resistor 12 , a second programming gate 15 , and a second variable resistor 20 .
- a programming gate 10 may be the portion of the ion exchange layer 135 capable of transferring ions into the channel 125 , having an electrode that includes either conductive core 140 .
- a variable resistor 20 may be a portion of the channel 125 , and location of the variable resistor may be based on the location where ions may be transferred from the ion exchange layer 135 .
- the tuning of the characteristics of the elements of the memory cell may be done through adjusting the thicknesses of the channel 125 and ion exchange layer 135 .
- first voltage is applied across the top electrode 150 and bottom electrode 110 .
- the first voltage is selected so that a sufficient potential is created between the conductive core 140 and the channel 125 , which may cause non-metal ions, for example oxygen ions, to migrate between the channel 125 and the ion exchange layer 135 .
- first voltage may be about 1V to about 5V.
- Such migration of ions allows the memory device to produce a movement of ions that is not in the direction of current flow during a read operation.
- the top electrode 150 is in direct contact with the channel 125 , current will flow between the top electrode 150 and bottom electrode 110 along the channel as well.
- the arrows depicted in FIG. 10 show the movement of ions from ion exchange layer 135 , as well as the flow of current along channel 125 .
- a second voltage may be used which is substantially less than the first voltage.
- second voltage may be about 50 mV to about 250 mV.
- the resulting change of resistance of the channel 125 may be measured based on the flow of current between the bottom electrode 110 and the top electrode 150 . It should be noted that voltage for measurement may be substantially less than the write conditions, such that the movement of ions described with respect to FIG. 7 does not occur.
- tuning parameters of the memory cell are depicted with associated electrical structures overlaid on the cell.
- realization of more ion mobility through the programming gate 10 , and less through the programming gate 15 may enable more precise control of the dynamic range of resistances through the variable resistor 20 .
- Ion flow through programming gate 10 may be tuned using fixed channel resistor 22 and fixed inner resistor 12 .
- the resistance through the fixed channel resistor 22 may be based on the cell height H, the height of the core H C , and the thickness of the ion exchange layer T EL .
- the resistance through the fixed inner resistor 12 may be based on the height of the core H C and the width W IC of the conductive core 140 .
- the capacitance of the programming gate 10 may be dependent on the material, the thickness of the ion exchange layer T EL and the area of the capacitive element, which may be related to the length of the variable resistors L V1 and L V2 .
- the capacitance, and structure, of the programming gate 10 and 15 may impact the rate of ion mobility into the variable resistor 20 and 25 during write operations, as well as the voltage across the programming gate 10 required to perform write operations.
- the resistance of the variable resistor 20 is dependent on the fixed parameters of the material, length L V1 or L V2 and thickness T C of the channel layer 125 , as well as a dynamic concentration of mobile ions from the ion exchange layer 135 .
- the length of the variable resistor 20 , L V1 or L V2 may be dependent on the height H of the cell, thickness T C of the channel layer 125 , and thickness of the ion exchange layer T EL .
- the dynamic concentration is based on programming of the unit cell, as depicted in FIG. 10 .
- the electrical parameters may be tuned according to the principles set forth above. Additionally, in some embodiments, variations in geometry may be used as well (e.g., change contact angle between the read channel and the bottom electrode).
- the memory cell of FIG. 5 is depicted as part of a cross-point array, as may be used in analog computing.
- the top electrode 150 may be a part of a word line 150 A/B/C
- the bottom electrode 110 may be a part of a bit line 110 AB/C.
- Each junction of a word line 150 A/B/C and bit line 110 A/B/C may include a memory cell as depicted in FIG. 5 .
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