US11450387B2 - Method of controlling internal address for a serial nor flash memory - Google Patents

Method of controlling internal address for a serial nor flash memory Download PDF

Info

Publication number
US11450387B2
US11450387B2 US17/211,060 US202117211060A US11450387B2 US 11450387 B2 US11450387 B2 US 11450387B2 US 202117211060 A US202117211060 A US 202117211060A US 11450387 B2 US11450387 B2 US 11450387B2
Authority
US
United States
Prior art keywords
address
spi
row
flash memory
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US17/211,060
Other versions
US20210407580A1 (en
Inventor
Guangjun YANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Assigned to Shanghai Huahong Grace Semiconductor Manufacturing Corporation reassignment Shanghai Huahong Grace Semiconductor Manufacturing Corporation ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YANG, GUANGJUN
Publication of US20210407580A1 publication Critical patent/US20210407580A1/en
Application granted granted Critical
Publication of US11450387B2 publication Critical patent/US11450387B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present application relates to the field of semiconductor integrated circuit manufacturing, in particular to a serial flash memory.
  • the present application further relates to an address control method of a serial flash memory.
  • FIG. 1 is a structural diagram of a memory cell of an existing serial flash memory
  • FIG. 2 is a diagram of a memory array of the existing serial flash memory
  • FIG. 3 is a schematic structural diagram of the existing serial flash memory
  • FIG. 4 is a timing diagram of address transmission during a read operation on the existing serial flash memory.
  • the existing serial flash memory 201 includes: a memory array 102 , a row decoder 204 , a column decoder 205 , a control module 203 , and a serial peripheral interface (SPI), i.e., an SPI interface 202 .
  • SPI serial peripheral interface
  • an arrangement structure of the memory cells 101 of the memory array 102 is a NOR type.
  • Each of the memory cells 101 includes a gate structure, a source region 6 , a drain region 7 , and a channel region.
  • the channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
  • the gate structure includes a stack structure which is composed of a first gate dielectric layer 2 , a floating gate 3 , a second gate dielectric layer 4 , and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1 .
  • a sidewall 8 is formed at the side of the gate structure.
  • the floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection.
  • the first gate dielectric layer 2 is usually an oxide layer.
  • the second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer.
  • the semiconductor substrate 1 is usually a silicon substrate.
  • the material of the sidewall 8 is an oxide layer or a nitride layer.
  • the polysilicon control gates 5 of the memory cells 101 in the same row are all connected to a word line (WL) of the same row, and the drain regions 7 of the memory cells 101 in the same column are all connected to a bit line (BL) of the same column.
  • the source region 6 of each memory cell 101 is connected to a source line (SL).
  • FIG. 2 shows j word lines respectively represented by WL 1 , WL 2 , . . . , and WLj and shows i bit lines respectively represented by BL 1 , BL 2 , . . . , and BLi.
  • the memory array 102 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
  • the serial flash memory 201 further includes a row drive circuit 207 , and the row drive circuit 207 drives a row signal during a row decoding process.
  • the control module 203 includes a read enable signal REN.
  • the control module 203 enables the read enable signal REN, such that the internal address is valid and reading starts.
  • the internal address is separately transmitted to the row decoder 204 for row decoding and to the column decoder 205 for column decoding via the control module 203 .
  • the word length includes 16 bits ( ⁇ 16), 32 bits ( ⁇ 16), 64 bits ( ⁇ 16), or 128 bits ( ⁇ 128).
  • a bit corresponding to the word-length address of the SPI address signal is A n .
  • the serial flash memory 201 further includes a readout circuit 206 , and the readout circuit 206 includes a sense amplifier (SA) used for amplifying a signal read from the bit line.
  • SA sense amplifier
  • control module 203 controls a corresponding operation according to the code and transmits the address to the row decoder 204 and the column decoder 205 to implement row address decoding and column address decoding respectively, and finally, an operation such as erasing, writing, or reading on a memory cell corresponding to the decoded address is implemented.
  • the control module 203 also controls the row drive circuit 207 .
  • the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address.
  • the most significant bit (MSB) of the SPI address signal is the most significant bit of the SPI sector address
  • the least significant bit (LSB) of the SPI address signal is the least significant bit of the SPI column address
  • the SPI row address is between the SPI sector address and the SPI column address.
  • the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 4 , wherein MSB corresponds to A m , and a bit corresponding to LSB is A 0 (not shown).
  • a bit following behind A m is A m-1
  • the subscript values of following bits are decreased by one successively, and each bit is represented by two dots, until it reaches A n and A n-1 , or until it reaches A 0 .
  • the SPI interface 202 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO.
  • the SPI address signal is input into the serial flash memory 201 via the input signal pin SI.
  • the SPI interface 202 is connected to an SPI interface controller, and the SPI interface controller is connected to a processor.
  • a connection wire between the SPI interface 202 and the SPI interface controller is an SPI wire; and the SPI interface controller and the processor are connected to each other via parallel connection wires.
  • the processor selects the corresponding serial flash memory 201 via the selection signal pin CE, then inputs a clock signal to the clock signal pin SCLK of the serial flash memory 201 , and then inputs corresponding code, address, or data to the input signal pin SI of the serial flash memory 201 . If there is data in the serial flash memory 201 to be output, the data is output via the output signal pin SO. Connection wires of the serial flash memory 201 and power consumption can be reduced by means of the SPI interface 202 .
  • the internal address is valid only when a word-length address of the SPI address signal is read. If the internal address is valid, row decoding and column decoding are performed at the same time, only then can operations such as reading be performed on the memory cell 101 corresponding to the address. In this case, requirements on row decoding and driving are relatively high, and a relatively large area is occupied.
  • the technical problem to be solved by the present application is to provide a serial flash memory, to relax the timing requirement on a row address, reduce the area of a row decoder, and reduce the area of a row drive circuit. To this end, the present application further provides an address control method of a serial flash memory.
  • the serial flash memory provided in the present application comprises: a memory array, a row decoder, a column decoder, a control module, and an SPI interface.
  • the control module comprises a row enable signal.
  • the control module When the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address.
  • the serial flash memory further comprises a row drive circuit, and when the row enable signal is enabled, the row drive circuit operates.
  • control module further comprises a read enable signal.
  • the control module enables the read enable signal, such that the internal address is valid and reading starts, the time for selecting the internal row address is before the moment at which the reading starts, and when the internal address is valid, the column decoder starts to decode an internal column address of the internal address.
  • the word length comprises 16 bits, 32 bits, 64 bits, or 128 bits.
  • an arrangement structure of memory cells of the memory array is a NOR type.
  • Each of the memory cells comprises a gate structure, a source region, a drain region, and a channel region.
  • the gate structure comprises a stack structure which is composed of a first gate dielectric layer, a floating gate, a second gate dielectric layer, and a polysilicon control gate and formed on the surface of a semiconductor substrate.
  • the polysilicon control gates of the memory cells in the same row are all connected to a word line of the same row, and the drain regions of the memory cells in the same column are all connected to a bit line of the same column.
  • the memory array is divided into a plurality of sectors, and an address of the memory cell is determined by a sector address, a row address, and a column address.
  • the SPI address signal comprises an SPI transmission sector address, an SPI row address, and an SPI column address, in the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
  • the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process.
  • the last bit of the SPI row address is the least significant bit of the SPI row address.
  • the SPI interface comprises a selection signal pin, a clock signal pin, an input signal pin, and an output signal pin, and the SPI address signal is input into the serial flash memory via the input signal pin.
  • the serial flash memory comprises: a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein operation steps of the serial flash memory comprise the following address control steps.
  • the control module inputs an SPI address signal via the SPI interface, and when the last bit of an SPI row address in the SPI address signal is to be read, the control module enables a row enable signal.
  • the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address.
  • the serial flash memory further comprises a row drive circuit, and when the row enable signal is enabled, the row drive circuit operates.
  • the control module when the operation step is a read step, during a read process, when a word-length address of the SPI address signal is to be read, the control module enables a read enable signal, such that the internal address is valid and reading starts, the time for selecting the internal row address is before the moment at which the reading starts, and when the internal address is valid, the column decoder starts to decode an internal column address of the internal address.
  • the word length comprises 16 bits, 32 bits, 64 bits, or 128 bits.
  • an arrangement structure of memory cells of the memory array is a NOR type.
  • Each of the memory cells comprises a gate structure, a source region, a drain region, and a channel region.
  • the gate structure comprises a stack structure which is composed of a first gate dielectric layer, a floating gate, a second gate dielectric layer, and a polysilicon control gate and formed on the surface of a semiconductor substrate.
  • the polysilicon control gates of the memory cells in the same row are all connected to a word line of the same row, and the drain regions of the memory cells in the same column are all connected to a bit line of the same column.
  • the memory array is divided into a plurality of sectors, and an address of the memory cell is determined by a sector address, a row address, and a column address.
  • the SPI address signal comprises an SPI transmission sector address, an SPI row address, and an SPI column address, in the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
  • the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process; and the last bit of the SPI row address is the least significant bit of the SPI row address.
  • the row enable signal is added to the control module, and detection of the last bit of the SPI row address is added during reading of the SPI address signal.
  • the control module enables the row enable signal
  • the row enable signal enables the internal row address of the internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. Therefore, the present application can overcome the defect in the prior art that the row decoder is enabled together with the column decoder after the SPI address signal of a word length is read.
  • enablement of the row decoder can be advanced by at least one cycle, relaxing the timing requirement on the row address, thereby lowering the performance requirement on the row decoder, thus reducing the area of the row decoder.
  • the present application can also lower the performance requirement on the row drive circuit, thereby reducing the area of the row drive circuit.
  • FIG. 1 is a structural diagram of a memory cell of an existing serial flash memory.
  • FIG. 2 is a diagram of a memory array of the existing serial flash memory.
  • FIG. 3 is a schematic structural diagram of the existing serial flash memory.
  • FIG. 4 is a timing diagram of address transmission during a read operation on the existing serial flash memory.
  • FIG. 5 is a schematic structural diagram of a serial flash memory in an embodiment of the present application.
  • FIG. 6 is a timing diagram of address transmission during a read operation on a serial flash memory in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a serial flash memory 301 in an embodiment of the present application
  • FIG. 6 is a timing diagram of address transmission during a read operation on the serial flash memory 301 in the embodiment of the present application.
  • the serial flash memory 301 in the embodiment of the present application includes: a memory array 308 , a row decoder 304 , a column decoder 305 , a control module 303 , and an SPI interface 302 .
  • an arrangement structure of memory cells 101 of the memory array 308 is a NOR type.
  • Each of the memory cells 101 includes a gate structure, a source region 6 , a drain region 7 , and a channel region.
  • the channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
  • the gate structure includes a stack structure which is composed of a first gate dielectric layer 2 , a floating gate 3 , a second gate dielectric layer 4 , and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1 .
  • a sidewall 8 is formed at the side of the gate structure.
  • the floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection.
  • the first gate dielectric layer 2 is usually an oxide layer.
  • the second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer.
  • the semiconductor substrate 1 is usually a silicon substrate.
  • the material of the sidewall 8 is an oxide layer or a nitride layer.
  • FIG. 2 shows j word lines respectively represented by WL 1 , WL 2 , . . . , and WLj and shows i bit lines respectively represented by BL 1 , BL 2 , . . . , and BLi.
  • the memory array 308 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
  • the control module 303 includes a row enable signal RowEN.
  • the control module 303 enables the row enable signal RowEN, and the row enable signal RowEN enables an internal row address of an internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address.
  • the SPI address signal is represented by SPI ADDR
  • the last bit of the SPI row address is A k
  • the internal address is represented by Internal ADDR
  • the internal row address is represented by Internal Row ADDR.
  • the serial flash memory 301 further includes a row drive circuit 307 , and when the row enable signal RowEN is enabled, the row drive circuit 307 operates.
  • the control module 303 further includes a read enable signal REN.
  • the control module 303 enables the read enable signal REN, such that the internal address is valid and reading starts.
  • the time for selecting the internal row address is before the moment at which the reading starts.
  • the column decoder 305 starts to decode an internal column address of the internal address.
  • the word length includes 16 bits, 32 bits, 64 bits, or 128 bits.
  • a bit corresponding to the word-length address of the SPI address signal is A n .
  • the serial flash memory 301 further includes a readout circuit 306 , and the readout circuit 306 includes a sense amplifier used for amplifying a signal of a read bit line.
  • read data is transmitted to the control module 303 , and then the control module 303 transmits the data to the SPI interface 302 .
  • control module 303 controls a corresponding operation according to the code and transmits the address to the row decoder 304 and the column decoder 305 to implement row address decoding and column address decoding respectively, and finally, an operation such as erasing, writing, or reading on a memory cell corresponding to the decoded address is implemented.
  • the control module 303 also controls the row drive circuit 307 .
  • the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address.
  • the most significant bit of the SPI address signal is the most significant bit of the SPI sector address
  • the least significant bit of the SPI address signal is the least significant bit of the SPI column address
  • the SPI row address is between the SPI sector address and the SPI column address.
  • the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 6 , wherein MSB corresponds to A m , and a bit corresponding to LSB is A 0 (not shown).
  • a bit following behind A m is A m-1
  • the subscript values of following bits are decreased by one successively, each bit is represented by two dots, until it reaches A k
  • bits distant from A k for more than one bit are A n and A n-1 , until it reaches A 0 .
  • the last bit of the SPI row address is the least significant bit of the SPI row address, that is, A k is the least significant bit of the SPI row address.
  • the SPI interface 302 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO.
  • the SPI address signal is input into the serial flash memory 301 via the input signal pin SI.
  • the SPI interface 302 is connected to an SPI interface controller, and the SPI interface controller is connected to a processor.
  • a connection wire between the SPI interface 302 and the SPI interface controller is an SPI wire; and the SPI interface controller and the processor are connected to each other via parallel connection wires.
  • the processor selects the corresponding serial flash memory 301 via the selection signal pin CE, then inputs a clock signal to the clock signal pin SCLK of the serial flash memory 301 , and then inputs corresponding code, address, or data to the input signal pin SI of the serial flash memory 301 . If there is data in the serial flash memory 301 to be output, the data is output via the output signal pin SO. Connection wires of the serial flash memory 301 and power consumption can be reduced by means of the SPI interface 302 .
  • the row enable signal RowEN is added to the control module 303 , and detection of the last bit of the SPI row address is added during reading of the SPI address signal.
  • the control module 303 enables the row enable signal RowEN, and the row enable signal RowEN enables the internal row address of the internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address. Therefore, the embodiment of the present application can overcome the defect in the prior art that the row decoder 304 is enabled together with the column decoder 305 after the SPI address signal of a word length is read.
  • enablement of the row decoder 304 can be advanced by at least one cycle, relaxing the timing requirement on the row address, thereby lowering the performance requirement on the row decoder 304 , thus reducing the area of the row decoder 304 .
  • the embodiment of the present application can also lower the performance requirement on the row drive circuit 307 , thereby reducing the area of the row drive circuit 307 .
  • the serial flash memory 301 includes: a memory array 308 , a row decoder 304 , a column decoder 305 , a control module 303 , and an SPI interface 302 .
  • an arrangement structure of memory cells 101 of the memory array 308 is a NOR type.
  • Each of the memory cells 101 includes a gate structure, a source region 6 , a drain region 7 , and a channel region.
  • the channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
  • the gate structure includes a stack structure which is composed of a first gate dielectric layer 2 , a floating gate 3 , a second gate dielectric layer 4 , and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1 .
  • a sidewall 8 is formed at the side of the gate structure.
  • the floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection.
  • the first gate dielectric layer 2 is usually an oxide layer.
  • the second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer.
  • the semiconductor substrate 1 is usually a silicon substrate.
  • the material of the sidewall 8 is an oxide layer or a nitride layer.
  • FIG. 2 shows j word lines respectively represented by WL 1 , WL 2 , . . . , and WLj and shows i bit lines respectively represented by BL 1 , BL 2 , . . . , and BLi.
  • the memory array 308 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
  • the control module 303 includes a row enable signal RowEN.
  • Operation steps of the serial flash memory 301 include the following address control steps.
  • the control module 303 inputs an SPI address signal via the SPI interface 302 , and when the last bit of an SPI row address in the SPI address signal is to be read, the control module 303 enables the row enable signal RowEN.
  • the row enable signal RowEN enables an internal row address of an internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address.
  • the SPI address signal is represented by SPI ADDR
  • the last bit of the SPI row address is A k
  • the internal address is represented by Internal ADDR
  • Internal Row ADDR Internal Row ADDR
  • the serial flash memory 301 further includes a row drive circuit 307 , and when the row enable signal RowEN is enabled, the row drive circuit 307 operates.
  • the control module 303 when the operation step is a read step, during a read process, when a word-length address of the SPI address signal is to be read, the control module 303 enables a read enable signal REN, such that the internal address is valid and reading starts.
  • the time for selecting the internal row address is before the moment at which the reading starts.
  • the column decoder 305 starts to decode an internal column address of the internal address.
  • the word length includes 16 bits, 32 bits, 64 bits, or 128 bits.
  • a bit corresponding to the word-length address of the SPI address signal is A n .
  • the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address.
  • the most significant bit of the SPI address signal is the most significant bit of the SPI sector address
  • the least significant bit of the SPI address signal is the least significant bit of the SPI column address
  • the SPI row address is between the SPI sector address and the SPI column address.
  • the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 6 , wherein MSB corresponds to A m , and a bit corresponding to LSB is A 0 (not shown).
  • a bit following behind A m is A m-1
  • the subscript values of following bits are decreased by one successively, each bit is represented by two dots, until it reaches A k
  • bits distant from A k for more than one bit are A n and A n-1 , until it reaches A 0 .
  • the last bit of the SPI row address is the least significant bit of the SPI row address, that is, A k is the least significant bit of the SPI row address.
  • the SPI interface 302 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO.
  • the SPI address signal is input into the serial flash memory 301 via the input signal pin SI.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)

Abstract

The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

Description

CROSS-REFERENCES TO RELATED APPLICATION
This application claims the priority to Chinese patent application No. CN 202010594516.9 filed at CNIPA on Jun. 28, 2020, and entitled “SERIAL FLASH MEMORY AND ADDRESS CONTROL METHOD THEREOF”, the disclosure of which is incorporated herein by reference in entirety.
TECHNICAL FIELD
The present application relates to the field of semiconductor integrated circuit manufacturing, in particular to a serial flash memory. The present application further relates to an address control method of a serial flash memory.
BACKGROUND
FIG. 1 is a structural diagram of a memory cell of an existing serial flash memory; FIG. 2 is a diagram of a memory array of the existing serial flash memory; FIG. 3, is a schematic structural diagram of the existing serial flash memory; and FIG. 4 is a timing diagram of address transmission during a read operation on the existing serial flash memory. The existing serial flash memory 201 includes: a memory array 102, a row decoder 204, a column decoder 205, a control module 203, and a serial peripheral interface (SPI), i.e., an SPI interface 202.
Generally, an arrangement structure of the memory cells 101 of the memory array 102 is a NOR type.
Each of the memory cells 101 includes a gate structure, a source region 6, a drain region 7, and a channel region. The channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
The gate structure includes a stack structure which is composed of a first gate dielectric layer 2, a floating gate 3, a second gate dielectric layer 4, and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1. Generally, a sidewall 8 is formed at the side of the gate structure. The floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection. When there is no electron stored in the polysilicon floating gate, the threshold voltage of the memory cell 101 is decreased, and the memory cell 101 is enabled during reading, such that the corresponding bit line is at a low level, in which case the stored information is 0, and the information 0 is a corresponding post-erasing state. The first gate dielectric layer 2 is usually an oxide layer. The second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer. The semiconductor substrate 1 is usually a silicon substrate. The material of the sidewall 8 is an oxide layer or a nitride layer.
The polysilicon control gates 5 of the memory cells 101 in the same row are all connected to a word line (WL) of the same row, and the drain regions 7 of the memory cells 101 in the same column are all connected to a bit line (BL) of the same column. The source region 6 of each memory cell 101 is connected to a source line (SL). FIG. 2 shows j word lines respectively represented by WL1, WL2, . . . , and WLj and shows i bit lines respectively represented by BL1, BL2, . . . , and BLi.
The memory array 102 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
The serial flash memory 201 further includes a row drive circuit 207, and the row drive circuit 207 drives a row signal during a row decoding process.
The control module 203 includes a read enable signal REN. During a read process, when a word-length address of an SPI address signal is to be read, the control module 203 enables the read enable signal REN, such that the internal address is valid and reading starts. When the internal address is valid, the internal address is separately transmitted to the row decoder 204 for row decoding and to the column decoder 205 for column decoding via the control module 203. Generally, the word length includes 16 bits (×16), 32 bits (×16), 64 bits (×16), or 128 bits (×128). In FIG. 4, a bit corresponding to the word-length address of the SPI address signal is An. It can be seen that when transmission is to be performed at An, the level of the read enable signal REN rises to a high level, and at a rising edge of the read enable signal REN, the invalid internal address becomes valid. In FIG. 4, the invalid internal address is represented by a cross, and the valid internal address is represented by Valid.
Referring to in FIG. 3, the serial flash memory 201 further includes a readout circuit 206, and the readout circuit 206 includes a sense amplifier (SA) used for amplifying a signal read from the bit line. Finally, read data is transmitted to the control module 203, and then the control module 203 transmits the data to the SPI interface 202.
After an code or address input by the SPI interface 202 is transmitted to the control module 203, the control module 203 controls a corresponding operation according to the code and transmits the address to the row decoder 204 and the column decoder 205 to implement row address decoding and column address decoding respectively, and finally, an operation such as erasing, writing, or reading on a memory cell corresponding to the decoded address is implemented. The control module 203 also controls the row drive circuit 207.
Generally, the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address. In the SPI address signal, the most significant bit (MSB) of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit (LSB) of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
The SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 4, wherein MSB corresponds to Am, and a bit corresponding to LSB is A0 (not shown). In FIG. 4, a bit following behind Am is Am-1, the subscript values of following bits are decreased by one successively, and each bit is represented by two dots, until it reaches An and An-1, or until it reaches A0.
The SPI interface 202 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO. The SPI address signal is input into the serial flash memory 201 via the input signal pin SI.
Generally, the SPI interface 202 is connected to an SPI interface controller, and the SPI interface controller is connected to a processor. A connection wire between the SPI interface 202 and the SPI interface controller is an SPI wire; and the SPI interface controller and the processor are connected to each other via parallel connection wires. The processor selects the corresponding serial flash memory 201 via the selection signal pin CE, then inputs a clock signal to the clock signal pin SCLK of the serial flash memory 201, and then inputs corresponding code, address, or data to the input signal pin SI of the serial flash memory 201. If there is data in the serial flash memory 201 to be output, the data is output via the output signal pin SO. Connection wires of the serial flash memory 201 and power consumption can be reduced by means of the SPI interface 202.
It can be seen from FIG. 4 that, in the prior art, the internal address is valid only when a word-length address of the SPI address signal is read. If the internal address is valid, row decoding and column decoding are performed at the same time, only then can operations such as reading be performed on the memory cell 101 corresponding to the address. In this case, requirements on row decoding and driving are relatively high, and a relatively large area is occupied.
BRIEF SUMMARY
The technical problem to be solved by the present application is to provide a serial flash memory, to relax the timing requirement on a row address, reduce the area of a row decoder, and reduce the area of a row drive circuit. To this end, the present application further provides an address control method of a serial flash memory.
In order to solve the above technical problem, the serial flash memory provided in the present application comprises: a memory array, a row decoder, a column decoder, a control module, and an SPI interface.
The control module comprises a row enable signal.
When the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address.
In an improvement, the serial flash memory further comprises a row drive circuit, and when the row enable signal is enabled, the row drive circuit operates.
In an improvement, the control module further comprises a read enable signal.
During a read process, when a word-length address of the SPI address signal is to be read, the control module enables the read enable signal, such that the internal address is valid and reading starts, the time for selecting the internal row address is before the moment at which the reading starts, and when the internal address is valid, the column decoder starts to decode an internal column address of the internal address.
In an improvement, the word length comprises 16 bits, 32 bits, 64 bits, or 128 bits.
In an improvement, an arrangement structure of memory cells of the memory array is a NOR type.
Each of the memory cells comprises a gate structure, a source region, a drain region, and a channel region.
The gate structure comprises a stack structure which is composed of a first gate dielectric layer, a floating gate, a second gate dielectric layer, and a polysilicon control gate and formed on the surface of a semiconductor substrate.
The polysilicon control gates of the memory cells in the same row are all connected to a word line of the same row, and the drain regions of the memory cells in the same column are all connected to a bit line of the same column.
In an improvement, the memory array is divided into a plurality of sectors, and an address of the memory cell is determined by a sector address, a row address, and a column address.
The SPI address signal comprises an SPI transmission sector address, an SPI row address, and an SPI column address, in the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
The SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process.
The last bit of the SPI row address is the least significant bit of the SPI row address.
The SPI interface comprises a selection signal pin, a clock signal pin, an input signal pin, and an output signal pin, and the SPI address signal is input into the serial flash memory via the input signal pin.
In order to solve the above technical problem, in the address control method of a serial flash memory provided in the present application, the serial flash memory comprises: a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein operation steps of the serial flash memory comprise the following address control steps.
The control module inputs an SPI address signal via the SPI interface, and when the last bit of an SPI row address in the SPI address signal is to be read, the control module enables a row enable signal.
The row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address.
In an improvement, the serial flash memory further comprises a row drive circuit, and when the row enable signal is enabled, the row drive circuit operates.
In an improvement, when the operation step is a read step, during a read process, when a word-length address of the SPI address signal is to be read, the control module enables a read enable signal, such that the internal address is valid and reading starts, the time for selecting the internal row address is before the moment at which the reading starts, and when the internal address is valid, the column decoder starts to decode an internal column address of the internal address.
In an improvement, the word length comprises 16 bits, 32 bits, 64 bits, or 128 bits.
In an improvement, an arrangement structure of memory cells of the memory array is a NOR type.
Each of the memory cells comprises a gate structure, a source region, a drain region, and a channel region.
The gate structure comprises a stack structure which is composed of a first gate dielectric layer, a floating gate, a second gate dielectric layer, and a polysilicon control gate and formed on the surface of a semiconductor substrate.
The polysilicon control gates of the memory cells in the same row are all connected to a word line of the same row, and the drain regions of the memory cells in the same column are all connected to a bit line of the same column.
In an improvement, the memory array is divided into a plurality of sectors, and an address of the memory cell is determined by a sector address, a row address, and a column address.
The SPI address signal comprises an SPI transmission sector address, an SPI row address, and an SPI column address, in the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
In an improvement, the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process; and the last bit of the SPI row address is the least significant bit of the SPI row address.
In the present application, the row enable signal is added to the control module, and detection of the last bit of the SPI row address is added during reading of the SPI address signal. When the last bit of the SPI row address in the SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables the internal row address of the internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. Therefore, the present application can overcome the defect in the prior art that the row decoder is enabled together with the column decoder after the SPI address signal of a word length is read. In the present application, enablement of the row decoder can be advanced by at least one cycle, relaxing the timing requirement on the row address, thereby lowering the performance requirement on the row decoder, thus reducing the area of the row decoder.
In addition, since the row address is usually driven by the row drive circuit, the present application can also lower the performance requirement on the row drive circuit, thereby reducing the area of the row drive circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
The present application will be further described in detail below with reference to the drawings and specific implementations.
FIG. 1 is a structural diagram of a memory cell of an existing serial flash memory.
FIG. 2 is a diagram of a memory array of the existing serial flash memory.
FIG. 3 is a schematic structural diagram of the existing serial flash memory.
FIG. 4 is a timing diagram of address transmission during a read operation on the existing serial flash memory.
FIG. 5 is a schematic structural diagram of a serial flash memory in an embodiment of the present application.
FIG. 6 is a timing diagram of address transmission during a read operation on a serial flash memory in an embodiment of the present application.
 DETAILED DESCRIPTION OF THE DISCLOSURE
FIG. 5 is a schematic structural diagram of a serial flash memory 301 in an embodiment of the present application; and FIG. 6 is a timing diagram of address transmission during a read operation on the serial flash memory 301 in the embodiment of the present application. The serial flash memory 301 in the embodiment of the present application includes: a memory array 308, a row decoder 304, a column decoder 305, a control module 303, and an SPI interface 302.
In the embodiment of the present application, an arrangement structure of memory cells 101 of the memory array 308 is a NOR type. For the structure of the memory array 308, reference may be made to the existing memory array 102 shown in FIG. 2. For the memory cell 101 of the memory array 308, reference may be made to FIG. 1.
Each of the memory cells 101 includes a gate structure, a source region 6, a drain region 7, and a channel region. The channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
The gate structure includes a stack structure which is composed of a first gate dielectric layer 2, a floating gate 3, a second gate dielectric layer 4, and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1. Generally, a sidewall 8 is formed at the side of the gate structure. The floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection. When there is no electron stored in the polysilicon floating gate, the threshold voltage of the memory cell 101 is decreased, and the memory cell 101 is enabled during reading, such that the corresponding bit line is at a low level, in which case the stored information is 0, and the information 0 is a corresponding post-erasing state. The first gate dielectric layer 2 is usually an oxide layer. The second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer. The semiconductor substrate 1 is usually a silicon substrate. The material of the sidewall 8 is an oxide layer or a nitride layer.
The polysilicon control gates 5 of the memory cells 101 in the same row are all connected to a word line of the same row, and the drain regions 7 of the memory cells 101 in the same column are all connected to a bit line of the same column. The source region 6 of each memory cell 101 is connected to a source line. FIG. 2 shows j word lines respectively represented by WL1, WL2, . . . , and WLj and shows i bit lines respectively represented by BL1, BL2, . . . , and BLi.
The memory array 308 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
The control module 303 includes a row enable signal RowEN.
Referring to in FIG. 6, when the last bit of an SPI row address in an SPI address signal is to be read, the control module 303 enables the row enable signal RowEN, and the row enable signal RowEN enables an internal row address of an internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address. In FIG. 6, the SPI address signal is represented by SPI ADDR, the last bit of the SPI row address is Ak, the internal address is represented by Internal ADDR, and the internal row address is represented by Internal Row ADDR. It can be seen that when transmission is to be performed at Ak, the level of the row enable signal RowEN rises to a high level, and at a rising edge of the row enable signal RowEN, the invalid internal address becomes valid. In FIG. 6, the invalid internal address is represented by a cross, and the valid internal address is represented by Valid.
Referring to in FIG. 5, the serial flash memory 301 further includes a row drive circuit 307, and when the row enable signal RowEN is enabled, the row drive circuit 307 operates.
The control module 303 further includes a read enable signal REN.
During a read process, when a word-length address of the SPI address signal is to be read, the control module 303 enables the read enable signal REN, such that the internal address is valid and reading starts. The time for selecting the internal row address is before the moment at which the reading starts. When the internal address is valid, the column decoder 305 starts to decode an internal column address of the internal address. In the embodiment of the present application, the word length includes 16 bits, 32 bits, 64 bits, or 128 bits. In FIG. 6, a bit corresponding to the word-length address of the SPI address signal is An. It can be seen that when transmission is to be performed at An, the level of the read enable signal REN rises to a high level, and at a rising edge of the read enable signal REN, the invalid internal address becomes valid. In FIG. 6, the invalid internal address is represented by a cross, and the valid internal address is represented by Valid.
Referring to in FIG. 5, the serial flash memory 301 further includes a readout circuit 306, and the readout circuit 306 includes a sense amplifier used for amplifying a signal of a read bit line. Finally, read data is transmitted to the control module 303, and then the control module 303 transmits the data to the SPI interface 302.
After an code or address input by the SPI interface 302 is transmitted to the control module 303, the control module 303 controls a corresponding operation according to the code and transmits the address to the row decoder 304 and the column decoder 305 to implement row address decoding and column address decoding respectively, and finally, an operation such as erasing, writing, or reading on a memory cell corresponding to the decoded address is implemented. The control module 303 also controls the row drive circuit 307.
In the embodiment of the present application, the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address. In the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
The SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 6, wherein MSB corresponds to Am, and a bit corresponding to LSB is A0 (not shown). In FIG. 6, a bit following behind Am is Am-1, the subscript values of following bits are decreased by one successively, each bit is represented by two dots, until it reaches Ak, and bits distant from Ak for more than one bit are An and An-1, until it reaches A0.
The last bit of the SPI row address is the least significant bit of the SPI row address, that is, Ak is the least significant bit of the SPI row address.
The SPI interface 302 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO. The SPI address signal is input into the serial flash memory 301 via the input signal pin SI.
Generally, the SPI interface 302 is connected to an SPI interface controller, and the SPI interface controller is connected to a processor. A connection wire between the SPI interface 302 and the SPI interface controller is an SPI wire; and the SPI interface controller and the processor are connected to each other via parallel connection wires. The processor selects the corresponding serial flash memory 301 via the selection signal pin CE, then inputs a clock signal to the clock signal pin SCLK of the serial flash memory 301, and then inputs corresponding code, address, or data to the input signal pin SI of the serial flash memory 301. If there is data in the serial flash memory 301 to be output, the data is output via the output signal pin SO. Connection wires of the serial flash memory 301 and power consumption can be reduced by means of the SPI interface 302.
In the embodiment of the present application, the row enable signal RowEN is added to the control module 303, and detection of the last bit of the SPI row address is added during reading of the SPI address signal. When the last bit of the SPI row address in the SPI address signal is to be read, the control module 303 enables the row enable signal RowEN, and the row enable signal RowEN enables the internal row address of the internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address. Therefore, the embodiment of the present application can overcome the defect in the prior art that the row decoder 304 is enabled together with the column decoder 305 after the SPI address signal of a word length is read. In the embodiment of the present application, enablement of the row decoder 304 can be advanced by at least one cycle, relaxing the timing requirement on the row address, thereby lowering the performance requirement on the row decoder 304, thus reducing the area of the row decoder 304.
In addition, since the row address is usually driven by the row drive circuit 307, the embodiment of the present application can also lower the performance requirement on the row drive circuit 307, thereby reducing the area of the row drive circuit 307.
In an address control method of a serial flash memory 301 in an embodiment of the present application, the serial flash memory 301 includes: a memory array 308, a row decoder 304, a column decoder 305, a control module 303, and an SPI interface 302.
In the method of the embodiment of the present application, an arrangement structure of memory cells 101 of the memory array 308 is a NOR type. For the structure of the memory array 308, reference may be made to the existing memory array 102 shown in FIG. 2. For the memory cell 101 of the memory array 308, reference may be made to FIG. 1.
Each of the memory cells 101 includes a gate structure, a source region 6, a drain region 7, and a channel region. The channel region is located between the source region 6 and the drain region 7 and is covered by the gate structure.
The gate structure includes a stack structure which is composed of a first gate dielectric layer 2, a floating gate 3, a second gate dielectric layer 4, and a polysilicon control gate 5 and formed on the surface of a semiconductor substrate 1. Generally, a sidewall 8 is formed at the side of the gate structure. The floating gate 3 is usually a polysilicon floating gate used for storing information. When there are electrons stored in the polysilicon floating gate, a threshold voltage of the memory cell 101 is increased, and the memory cell 101 is disabled during reading, such that a corresponding bit line is at a high level, in which case the stored information is 1, and the information 1 can be achieved by means of programming electron injection. When there is no electron stored in the polysilicon floating gate, the threshold voltage of the memory cell 101 is decreased, and the memory cell 101 is enabled during reading, such that the corresponding bit line is at a low level, in which case the stored information is 0, and the information 0 is a corresponding post-erasing state. The first gate dielectric layer 2 is usually an oxide layer. The second gate dielectric layer 4 is an oxide layer or a stack layer composed of an oxide layer, a nitride layer, and an oxide layer, i.e., an ONO layer. The semiconductor substrate 1 is usually a silicon substrate. The material of the sidewall 8 is an oxide layer or a nitride layer.
The polysilicon control gates 5 of the memory cells 101 in the same row are all connected to a word line of the same row, and the drain regions 7 of the memory cells 101 in the same column are all connected to a bit line of the same column. The source region 6 of each memory cell 101 is connected to a source line. FIG. 2 shows j word lines respectively represented by WL1, WL2, . . . , and WLj and shows i bit lines respectively represented by BL1, BL2, . . . , and BLi.
The memory array 308 is divided into a plurality of sectors, and an address of the memory cell 101 is determined by a sector address, a row address, and a column address.
The control module 303 includes a row enable signal RowEN.
Operation steps of the serial flash memory 301 include the following address control steps.
The control module 303 inputs an SPI address signal via the SPI interface 302, and when the last bit of an SPI row address in the SPI address signal is to be read, the control module 303 enables the row enable signal RowEN.
The row enable signal RowEN enables an internal row address of an internal address of the serial flash memory 301 to be valid and enables the row decoder 304 to perform decoding and select the internal row address.
In FIG. 6, the SPI address signal is represented by SPI ADDR, the last bit of the SPI row address is Ak, the internal address is represented by Internal ADDR, and the internal row address is represented by Internal Row ADDR. It can be seen that when transmission is to be performed at Ak, the level of the row enable signal RowEN rises to a high level, and at a rising edge of the row enable signal RowEN, the invalid internal address becomes valid. In FIG. 6, the invalid internal address is represented by a cross, and the valid internal address is represented by Valid.
Referring to in FIG. 5, the serial flash memory 301 further includes a row drive circuit 307, and when the row enable signal RowEN is enabled, the row drive circuit 307 operates.
In the method of the embodiment of the present application, when the operation step is a read step, during a read process, when a word-length address of the SPI address signal is to be read, the control module 303 enables a read enable signal REN, such that the internal address is valid and reading starts. The time for selecting the internal row address is before the moment at which the reading starts. When the internal address is valid, the column decoder 305 starts to decode an internal column address of the internal address. In the embodiment of the present application, the word length includes 16 bits, 32 bits, 64 bits, or 128 bits. In FIG. 6, a bit corresponding to the word-length address of the SPI address signal is An. It can be seen that when transmission is to be performed at An, the level of the read enable signal REN rises to a high level, and at a rising edge of the read enable signal REN, the invalid internal address becomes valid. In FIG. 6, the invalid internal address is represented by a cross, and the valid internal address is represented by Valid.
In the embodiment of the present application, the SPI address signal includes an SPI transmission sector address, an SPI row address, and an SPI column address. In the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
The SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process, that is, transmission is performed from MSB to LSB in FIG. 6, wherein MSB corresponds to Am, and a bit corresponding to LSB is A0 (not shown). In FIG. 6, a bit following behind Am is Am-1, the subscript values of following bits are decreased by one successively, each bit is represented by two dots, until it reaches Ak, and bits distant from Ak for more than one bit are An and An-1, until it reaches A0.
The last bit of the SPI row address is the least significant bit of the SPI row address, that is, Ak is the least significant bit of the SPI row address.
The SPI interface 302 includes a selection signal pin CE, a clock signal pin SCLK, an input signal pin SI, and an output signal pin SO. The SPI address signal is input into the serial flash memory 301 via the input signal pin SI.
The present application is described in detail above via specific embodiments, but these embodiments are not intended to limit the present application. Without departing from the principle of the present application, those skilled in the art can still make many variations and improvements, which should also be considered to fall into the protection scope of the present application.

Claims (5)

What is claimed is:
1. A method of controlling internal address for a serial NOR flash memory, the serial NOR flash memory comprising: a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein operation steps of the serial NOR flash memory comprise the following address control steps:
the control module inputs an SPI address signal via the SPI interface, and when the last bit of an SPI row address in the SPI address signal is to be read, the control module enables a row enable signal; and
the row enable signal enables an internal row address of an internal address of the serial NOR flash memory to be valid and enables the row decoder to perform decoding and select the internal row address, the row enable signal is a pulse signal,
wherein the serial NOR flash memory further comprises a row drive circuit, and when the row enable signal is enabled, the row drive circuit operates,
wherein when the operation step is read step, during a read process, when a word-length address of the SPI address signal is to be read, the control module enables a read enable signal, such that the internal address is valid and reading starts, the time for selecting the internal row address is before the moment at which the reading starts, and when the internal address is valid, the column decoder starts to decode an internal column address of the internal address, the read enable signal is a pulse signal.
2. The method of controlling internal address for a serial NOR flash memory according to claim 1, wherein the word length comprises 16 bits, 32 bits, 64 bits, or 128 bits.
3. The method of controlling internal address for a serial NOR flash memory according to claim 1, wherein an arrangement structure of memory cells of the memory array is a NOR type;
each of the memory cells comprises a gate structure, a source region, a drain region, and a channel region;
the gate structure comprises a stack structure which is composed of a first gate dielectric layer, a floating gate, a second gate dielectric layer, and a polysilicon control gate and formed on the surface of a semiconductor substrate; and
the polysilicon control gates of the memory cells in the same row are all connected to a word line of the same row, and the drain regions of the memory cells in the same column are all connected to a bit line of the same column.
4. The method of controlling internal address for a serial NOR flash memory according to claim 3, wherein the memory array is divided into a plurality of sectors, and an address of the memory cell is determined by a sector address, a row address, and a column address; and
the SPI address signal comprises an SPI transmission sector address, an SPI row address, and an SPI column address, in the SPI address signal, the most significant bit of the SPI address signal is the most significant bit of the SPI sector address, the least significant bit of the SPI address signal is the least significant bit of the SPI column address, and the SPI row address is between the SPI sector address and the SPI column address.
5. The method of controlling internal address for a serial NOR flash memory according to claim 4, wherein the SPI address signal is input bit by bit from the most significant bit to the least significant bit during an input process; and the last bit of the SPI row address is the least significant bit of the SPI row address.
US17/211,060 2020-06-28 2021-03-24 Method of controlling internal address for a serial nor flash memory Active US11450387B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010594516.9A CN111813705B (en) 2020-06-28 2020-06-28 Serial flash memory and address control method thereof
CN202010594516.9 2020-06-28

Publications (2)

Publication Number Publication Date
US20210407580A1 US20210407580A1 (en) 2021-12-30
US11450387B2 true US11450387B2 (en) 2022-09-20

Family

ID=72855471

Family Applications (1)

Application Number Title Priority Date Filing Date
US17/211,060 Active US11450387B2 (en) 2020-06-28 2021-03-24 Method of controlling internal address for a serial nor flash memory

Country Status (2)

Country Link
US (1) US11450387B2 (en)
CN (1) CN111813705B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12380932B2 (en) * 2023-04-06 2025-08-05 Silicon Storage Technology, Inc. Row decoder and row address scheme in a memory system

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050213421A1 (en) * 2002-11-28 2005-09-29 Salvatore Polizzi Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface
US20080304321A1 (en) * 2005-09-09 2008-12-11 Excel Semiconductor Inc. Serial Flash Memory Device and Precharging Method Thereof
US8102710B2 (en) * 2007-10-17 2012-01-24 Micron Technology, Inc. System and method for setting access and modification for synchronous serial interface NAND
US20150318049A1 (en) * 2014-04-30 2015-11-05 Stmicroelectronics (Grenoble 2) Sas Tag-based implementations enabling high speed data capture and transparent pre-fetch from a nor flash
US20160034352A1 (en) * 2014-07-31 2016-02-04 Winbond Electronics Corporation NAND Flash Memory Having an Enhanced Buffer Read Capability and Method of Operation Thereof
US20180151232A1 (en) * 2016-11-30 2018-05-31 Realtek Semiconductor Corporation Memory control circuit and method thereof
US20210280222A1 (en) * 2020-03-06 2021-09-09 Macronix International Co., Ltd. Method and system for enhanced read performance in low pin count interface

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018711A (en) * 1999-08-21 2001-03-15 윤종용 Nor-flash memory apparatus and control method for programming thereof
US8120959B2 (en) * 2008-05-30 2012-02-21 Aplus Flash Technology, Inc. NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
CN103106918B (en) * 2012-12-24 2015-12-02 西安华芯半导体有限公司 A kind of two-port static RAM using single-port memory cell
CN103811065B (en) * 2014-03-07 2017-12-08 上海华虹宏力半导体制造有限公司 Nonvolatile memory system
CN105609142B (en) * 2016-03-10 2018-07-31 上海华虹宏力半导体制造有限公司 The detection circuit and method for trimming of embedded flash memory, embedded flash memory
CN110111833B (en) * 2019-04-03 2021-07-13 中国科学院微电子研究所 Memory verification circuit and verification method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050213421A1 (en) * 2002-11-28 2005-09-29 Salvatore Polizzi Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface
US20080304321A1 (en) * 2005-09-09 2008-12-11 Excel Semiconductor Inc. Serial Flash Memory Device and Precharging Method Thereof
US8102710B2 (en) * 2007-10-17 2012-01-24 Micron Technology, Inc. System and method for setting access and modification for synchronous serial interface NAND
US20150318049A1 (en) * 2014-04-30 2015-11-05 Stmicroelectronics (Grenoble 2) Sas Tag-based implementations enabling high speed data capture and transparent pre-fetch from a nor flash
US20160034352A1 (en) * 2014-07-31 2016-02-04 Winbond Electronics Corporation NAND Flash Memory Having an Enhanced Buffer Read Capability and Method of Operation Thereof
US20180151232A1 (en) * 2016-11-30 2018-05-31 Realtek Semiconductor Corporation Memory control circuit and method thereof
US20210280222A1 (en) * 2020-03-06 2021-09-09 Macronix International Co., Ltd. Method and system for enhanced read performance in low pin count interface

Also Published As

Publication number Publication date
US20210407580A1 (en) 2021-12-30
CN111813705B (en) 2024-06-14
CN111813705A (en) 2020-10-23

Similar Documents

Publication Publication Date Title
US7391655B2 (en) Data processing system and nonvolatile memory
US8139407B2 (en) Nonvolatile semiconductor memory device including NAND-type flash memory and the like
US7630236B2 (en) Flash memory programming to reduce program disturb
US20010005330A1 (en) Nand-type flash memory device and method of operating the same
US6937513B1 (en) Integrated NAND and nor-type flash memory device and method of using the same
JP4554616B2 (en) Semiconductor integrated circuit
JP2006504218A (en) Flash memory architecture with page mode erase using NMOS and PMOS row decode mechanisms
US20250273576A1 (en) Memory device including staircase structure having conductive pads
JP2004071012A (en) Semiconductor storage device
US12087396B2 (en) Memory system
US6404681B1 (en) Method for erasing data from a non-volatile semiconductor memory device
JP7589087B2 (en) Semiconductor memory device
US11450387B2 (en) Method of controlling internal address for a serial nor flash memory
US6941411B2 (en) Non-contiguous address erasable blocks and command in flash memory
CN1551226A (en) Flash memory device with burst read mode of operation
JP2590764B2 (en) Nonvolatile semiconductor memory device
US20220383919A1 (en) Semiconductor storage device
US11942180B2 (en) Memory system
US6954376B2 (en) Non-volatile semiconductor memory array structure and operations
US6987695B2 (en) Writing data to nonvolatile memory
US6747911B2 (en) Synchronous memory with open page
US12394480B2 (en) Flash memory
US6970368B1 (en) CAM (content addressable memory) cells as part of core array in flash memory device
US20250021431A1 (en) Memory controller for performing efficient error correction code (ecc) decoding and a storage device including the same
WO2006035502A1 (en) Semiconductor device and data reading method

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE